-- -------------------------------------------------------------------- 
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 
-- -------------------------------------------------------------------- 
-- Copyright (c) 2001 by Lattice Semiconductor Corporation 
-- -------------------------------------------------------------------- 
-- 
-- 
--                     Lattice Semiconductor Corporation 
--                     5555 NE Moore Court 
--                     Hillsboro, OR 97214 
--                     U.S.A 
-- 
--                     TEL: 1-800-Lattice (USA and Canada) 
--                          408-826-6000 (other locations) 
-- 
--                     web: http://www.latticesemi.com/ 
--                     email: techsupport@latticesemi.com 
-- 
-- -------------------------------------------------------------------- 
-- Revision History:

--$Header: R:/src/mod_kits/Mach/vital/rcs/LC5KMX.vhd 1.58 2004/03/12 22:37:22Z jli Exp $

----------------------------------------------------------------
-- 
-- FILE CONTENTS:    LC5KMX VITAL Library 
-- DATE CREATED :    Wen Sept  15 1998
-- 
-- LIBRARY      :    LC5KMX
-- REVISION     :    1.2 
-- TIME SCALE   :    1 ns
-- LOGIC SYSTEM :    IEEE-1164
-- NOTES        :    
-- HISTORY      :
-- 
-- version 1.0, Initial beta version for beta testing 
-- version 1.1, Change the array size to pass model tech.
-- version 1.2, Change the default for setup and hold for DFF/TFF/DLAT
--              Modified the index range to pass Modelsim EE 5.2e warnings
-- version 1.3, Change the default pw, period for FF and LATCH.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.VITAL_timing.all;
USE IEEE.VITAL_primitives.all;
 
 
package VLOGTOVITAL_TABLES is
 
---------------------------------------------------------------------------------
-- Local type declaration
---------------------------------------------------------------------------------

    TYPE edge_table IS ARRAY (std_ulogic, std_ulogic) OF boolean ;

---------------------------------------------------------------------------------
-- Contants Specifications
-- posedge, negedge
---------------------------------------------------------------------------------
    CONSTANT POSEDGE : edge_table := (
    --      ---------------------------------------------------------
    --      |  U      X      0      1      Z      W      L      H      - |   |
    --      ---------------------------------------------------------
            ( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
            ( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
            ( FALSE, TRUE,  FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 0 |
            ( FALSE, FALSE, FALSE, FALSE,FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 1 |
            ( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
            ( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
            ( FALSE, TRUE,  FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | L |
            ( FALSE, FALSE, FALSE, FALSE,FALSE, FALSE, FALSE, FALSE, FALSE ), -- | H |
            ( FALSE, FALSE, FALSE, FALSE,FALSE, FALSE, FALSE, FALSE, FALSE )  -- | - |
        );

    CONSTANT NEGEDGE : edge_table := (
    --      ---------------------------------------------------- -----
    --      |  U    X    0    1    Z    W    L    H    - |   |
    --      ---------------------------------------------------- -----
            ( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
            ( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
            ( FALSE, FALSE, FALSE,FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 0 |
            ( FALSE, TRUE,  TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 1 |
            ( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
            ( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
            ( FALSE, FALSE, FALSE,FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | L |
            ( FALSE, TRUE,  TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | H |
            ( FALSE, FALSE, FALSE,FALSE, FALSE, FALSE, FALSE, FALSE, FALSE )  -- | - |
        );

        -------------------------------------------------------------------------------
        --State Table Declaration
        -------------------------------------------------------------------------------

	CONSTANT dfftab : VitalStateTableType := (
	-- D CLK R S lstSt Q
	( '-', '-', '0', '1', '-', '0' ),
	( '-', '-', '1', '0', '-', '1' ),
	( '1', '/', '1', '-', '-', '1' ),
	( '0', '/', '-', '1', '-', '0' ),
	( '1', '-', '1', '*', '1', '1' ),
	( '-', '0', '1', '*', '1', '1' ),
	( '-', '1', '1', '*', '1', '1' ),
	( '1', '-', '0', '\', '0', 'X' ),---
	( '-', '0', '0', '\', '0', 'X' ),---
	( '-', '1', '0', '\', '0', 'X' ),---
	( '0', '-', '*', '1', '0', '0' ),
	( '-', '0', '*', '1', '0', '0' ),
	( '-', '1', '*', '1', '0', '0' ),
	( '0', '-', '\', '0', '1', 'X' ),--
	( '-', '0', '\', '0', '1', 'X' ),--
	( '-', '1', '\', '0', '1', 'X' ),--
	( '1', 'R', '1', '1', '1', '1' ),
	( '0', 'R', '1', '1', '0', '0' ),
	( '-', '\', '-', '-', '-', 'S' ),
	( '-', 'v', '-', '-', '-', 'S' ),
	( '0', 'r', '-', '-', '0', 'S' ),
	( '0', 'f', '-', '-', '0', 'S' ),
	( '1', 'r', '-', '-', '1', 'S' ),
	( '1', 'f', '-', '-', '1', 'S' ),
	( '*', '1', '-', '-', '-', 'S' ),
	( '*', '0', '-', '-', '-', 'S' ),
	( 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'S', '-', 'S' ),
	( 'S', 'S', 'S', 'r', '-', 'X' ),
	( 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'f', '-', 'X' ),
	( 'X', 'X', 'X', 'X', '-', 'S' ) );


	-------------------------------------------------------------------------------
	--State Table Declaration
	-------------------------------------------------------------------------------
	CONSTANT latchtab : VitalStateTableType := (
	-- D LAT R S lstSt Q
	( '-', '-', '0', '1', '-', '0' ),
	( '-', '-', '1', '0', '-', '1' ),
	( '*', '0', '1', '1', '-', 'S' ),
	( '-', '\', '1', '1', '-', 'S' ),
	( '-', 'v', '1', '1', '-', 'S' ),
	( '-', 'f', '1', '1', '-', 'S' ),
	( '0', '^', '-', '1', '-', '0' ),
	( '1', '^', '1', '-', '-', '1' ),
	( '0', 'r', '1', '1', '0', '0' ),
	( '1', 'r', '1', '1', '1', '1' ),
	( '\', '1', '-', '1', '-', '0' ),
	( 'v', '1', '-', '1', '-', '0' ),
	( '/', '1', '1', '-', '-', '1' ),
	( '^', '1', '1', '-', '-', '1' ),
	( '0', '/', '-', '1', '-', '0' ),
	( '1', '/', '1', '-', '-', '1' ),
	( '-', '0', '1', '/', '-', 'S' ),
	( '-', '0', '1', '^', '-', 'S' ),
	( '-', '0', '/', '1', '-', 'S' ),
	( '-', '0', '^', '1', '-', 'S' ),
	( '0', '1', '-', '/', '-', '0' ),
	( '0', '1', '-', '^', '-', '0' ),
	( '1', '1', '/', '-', '-', '1' ),
	( '1', '1', '^', '-', '-', '1' ),
	( '1', '1', '1', '/', '-', '1' ),
	( '1', '1', '1', '^', '-', '1' ),
	( '0', '1', '/', '1', '-', '0' ),
	( '0', '1', '^', '1', '-', '0' ),
	( '/', 'X', '1', '-', '1', '1' ),
	( '^', 'X', '1', '-', '1', '1' ),
	( '\', 'X', '-', '1', '0', '0' ),
	( 'v', 'X', '-', '1', '0', '0' ),
	( 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'S', '-', 'S' ),
	( 'S', 'S', 'S', 'r', '-', 'X' ),
	( 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'f', '-', 'X' ),
	( 'X', 'X', 'X', 'X', '-', 'S' ) );


	-------------------------------------------------------------------------------
	--State Table Declaration
	-------------------------------------------------------------------------------
	CONSTANT jkfftab : VitalStateTableType := (
	-- CLK J K S R lstSt Q
	( '-', '-', '-', '0', '1', '-', '1' ),
	( '-', '-', '-', '1', '0', '-', '0' ),
	( '-', '-', '-', '*', '1', '1', '1' ),
	( '-', '-', '-', '1', '*', '0', '0' ),
	( '/', '0', '0', '1', '1', '-', 'S' ),
	( '/', '0', '1', '1', '1', '-', '0' ),
	( '/', '1', '0', '1', '1', '-', '1' ),
	( '/', '1', '1', '1', '1', '1', '0' ),
	( '/', '1', '1', '1', '1', '0', '1' ),
	( '\', '-', '-', '-', '-', '-', 'S' ),
	( 'B', '*', '-', '-', '-', '-', 'S' ),
	( 'B', '-', '*', '-', '-', '-', 'S' ),
	( 'R', '0', '0', '1', '1', '-', 'S' ),
	( 'R', '0', '-', '1', '-', '0', 'S' ),
	( 'R', '-', '0', '-', '1', '1', 'S' ),
	( 'v', '-', '-', '-', '-', '-', 'S' ),
	( 'f', '0', '0', '1', '1', '-', 'S' ),
	( 'f', '0', '-', '1', '-', '0', 'S' ),
	( 'f', '-', '0', '-', '1', '1', 'S' ),
	( 'X', '*', '0', '-', '1', '1', 'S' ),
	( 'X', '0', '*', '1', '-', '0', 'S' ),
	( 'S', 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'S', '-', 'S' ),
	( 'S', 'S', 'S', 'S', 'r', '-', 'X' ),
	( 'S', 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'f', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'X', '-', 'S' ) );


	-------------------------------------------------------------------------------
	--State Table Declaration
	-------------------------------------------------------------------------------
	CONSTANT rsfftab : VitalStateTableType := (
	-- CLK RE SE S R lstSt Q
	( '-', '-', '-', '0', '1', '-', '1' ),
	( '-', '-', '-', '1', '0', '-', '0' ),
	( '-', '1', '1', '/', '1', '-', 'S' ),
	( '-', '1', '1', '^', '1', '-', 'S' ),
	( '-', '1', '1', '1', '/', '-', 'S' ),
	( '-', '1', '1', '1', '^', '-', 'S' ),
	( '/', '0', '0', '1', '1', '-', 'S' ),
	( '/', '0', '1', '1', '1', '-', '1' ),
	( '/', '1', '0', '1', '1', '-', '0' ),
	( '\', '-', '-', '-', '-', '-', 'S' ),
	( 'R', '0', '0', '1', '1', '-', 'S' ),
	( 'R', '0', '-', '1', '-', '0', 'S' ),
	( 'R', '-', '0', '-', '1', '1', 'S' ),
	( 'v', '-', '-', '-', '-', '-', 'S' ),
	( 'f', '0', '0', '1', '1', '-', 'S' ),
	( 'f', '0', '-', '1', '-', '0', 'S' ),
	( 'f', '-', '0', '-', '1', '1', 'S' ),
	( 'X', '*', '0', '-', '1', '1', 'S' ),
	( 'X', '0', '*', '1', '-', '0', 'S' ),
	( 'S', 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'S', '-', 'S' ),
	( 'S', 'S', 'S', 'S', '/', '-', 'S' ),----
	( 'S', 'S', 'S', '/', 'S', '-', 'S' ),----
	( 'S', 'S', 'S', 'S', 'r', '-', 'X' ),----
	( 'S', 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'f', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'X', '-', 'S' ),
	( '-', '*', '-', '1', '1', '-', 'S' ),
	( '-', '-', '*', '1', '1', '-', 'S' ));


	-------------------------------------------------------------------------------
	--State Table Declaration
	-------------------------------------------------------------------------------
	CONSTANT tfftab : VitalStateTableType := (
	-- CLK T S R lstSt Q
	( '-', '-', '0', '1', '-', '1' ),
	( '-', '-', '1', '0', '-', '0' ),
	( 'X', '0', '1', '-', '0', 'S' ),
	( '-', '-', '*', '1', '1', '1' ),
	( '-', '-', '1', '*', '0', '0' ),
	( '/', '0', '1', '1', '-', 'S' ),
	( '/', '1', '1', '1', '1', '0' ),
	( '/', '1', '1', '1', '0', '1' ),
	( '\', '-', '-', '-', '-', 'S' ),
	( 'B', '*', '-', '-', '-', 'S' ),
	( 'R', '0', '1', '1', '-', 'S' ),
	( 'R', '0', '1', '-', '0', 'S' ),
	( 'R', '0', '-', '1', '1', 'S' ),
	( 'v', '-', '-', '-', '-', 'S' ),
	( 'f', '0', '1', '1', '-', 'S' ),
	( 'f', '-', '-', '1', '1', 'S' ),
	( 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'S', '-', 'S' ),
	( 'S', 'S', 'S', 'r', '-', 'X' ),
	( 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'f', '-', 'X' ),
	( 'X', 'X', 'X', 'X', '-', 'S' ) );


	-------------------------------------------------------------------------------
	--State Table Declaration
	-------------------------------------------------------------------------------
	CONSTANT dffcetab : VitalStateTableType := (
	-- D CLK R S CE lstSt Q
	( '-', '-', '0', '1', '-', '-', '0' ),
	( '-', '-', '1', '0', '-', '-', '1' ),
	( '-', '-', '1', '1', '0', '-', 'S' ),
	( '1', '/', '1', '-', '1', '-', '1' ),
	( '0', '/', '-', '1', '1', '-', '0' ),
	( '1', '-', '1', '*', '1', '1', '1' ),
	( '-', '0', '1', '*', '1', '1', '1' ),
	( '-', '1', '1', '*', '1', '1', '1' ),
	( '0', '-', '*', '1', '1', '0', '0' ),
	( '-', '0', '*', '1', '1', '0', '0' ),
	( '-', '1', '*', '1', '1', '0', '0' ),
	( '1', 'R', '1', '1', '1', '1', '1' ),
	( '0', 'R', '1', '1', '1', '0', '0' ),
	( '-', '\', '-', '-', '1', '-', 'S' ),
	( '-', 'v', '-', '-', '1', '-', 'S' ),
	( '0', 'r', '-', '-', '1', '0', 'S' ),
	( '0', 'f', '-', '-', '1', '0', 'S' ),
	( '1', 'r', '-', '-', '1', '1', 'S' ),
	( '1', 'f', '-', '-', '1', '1', 'S' ),
	( '*', '1', '-', '-', '1', '-', 'S' ),
	( '*', '0', '-', '-', '1', '-', 'S' ),
	( 'S', 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'S', '-', 'S' ),
	( 'S', 'S', 'S', 'S', 'r', '-', 'X' ),
	( 'S', 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'f', '-', 'X' ),
	( '-', '-', '1', '1', '*', '-', 'S' ),
	( 'X', 'X', 'X', 'X', 'X', '-', 'S' ) );


end VLOGTOVITAL_TABLES;
 
----- VITAL model for cell AND2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity AND2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of AND2 : entity is TRUE;
end AND2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of AND2 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := (I1_ipd) AND (I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_AND2_VITAL of AND2 is 
        for VITAL
        end for; 
end CFG_AND2_VITAL;
----- VITAL model for cell AND3 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity AND3 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of AND3 : entity is TRUE;
end AND3;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of AND3 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := (I1_ipd) AND (I0_ipd) AND (I2_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_AND3_VITAL of AND3 is 
        for VITAL
        end for; 
end CFG_AND3_VITAL;
----- VITAL model for cell AND4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity AND4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of AND4 : entity is TRUE;
end AND4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of AND4 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := (I1_ipd) AND (I0_ipd) AND (I2_ipd) AND (I3_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_AND4_VITAL of AND4 is 
        for VITAL
        end for; 
end CFG_AND4_VITAL;
----- VITAL model for cell AND5 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity AND5 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of AND5 : entity is TRUE;
end AND5;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
 
library LC5KMX;
architecture VITAL of AND5 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       (I1_ipd) AND (I0_ipd) AND (I2_ipd) AND (I3_ipd) AND (I4_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;
 
configuration CFG_AND5_VITAL of AND5 is 
        for VITAL
        end for; 
end CFG_AND5_VITAL;
----- VITAL model for cell AND6 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity AND6 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I5_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      I5                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of AND6 : entity is TRUE;
end AND6;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
 
library LC5KMX;
architecture VITAL of AND6 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I5_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   VitalWireDelay (I5_ipd, I5, tipd_I5);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd, I5_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       (I1_ipd) AND (I0_ipd) AND (I2_ipd) AND (I3_ipd) AND (I4_ipd) AND
         (I5_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE),
                 5 => (I5_ipd'last_event, tpd_I5_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;
 
configuration CFG_AND6_VITAL of AND6 is 
        for VITAL
        end for; 
end CFG_AND6_VITAL;
----- VITAL model for cell AND7 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity AND7 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I5_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I6_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      I5                             :	in    STD_ULOGIC;
      I6                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of AND7 : entity is TRUE;
end AND7;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
 
library LC5KMX;
architecture VITAL of AND7 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I5_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I6_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   VitalWireDelay (I5_ipd, I5, tipd_I5);
   VitalWireDelay (I6_ipd, I6, tipd_I6);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd, I5_ipd, I6_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       (I1_ipd) AND (I0_ipd) AND (I2_ipd) AND (I3_ipd) AND (I4_ipd) AND
         (I5_ipd) AND (I6_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE),
                 5 => (I5_ipd'last_event, tpd_I5_O, TRUE),
                 6 => (I6_ipd'last_event, tpd_I6_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;
 
configuration CFG_AND7_VITAL of AND7 is 
        for VITAL
        end for; 
end CFG_AND7_VITAL;
----- VITAL model for cell AND8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity AND8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I5_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I6_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I7_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      I5                             :	in    STD_ULOGIC;
      I6                             :	in    STD_ULOGIC;
      I7                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of AND8 : entity is TRUE;
end AND8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
 
library LC5KMX;
architecture VITAL of AND8 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I5_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I6_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I7_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   VitalWireDelay (I5_ipd, I5, tipd_I5);
   VitalWireDelay (I6_ipd, I6, tipd_I6);
   VitalWireDelay (I7_ipd, I7, tipd_I7);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd, I5_ipd, I6_ipd, I7_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       (I1_ipd) AND (I0_ipd) AND (I2_ipd) AND (I3_ipd) AND (I4_ipd) AND
         (I5_ipd) AND (I6_ipd) AND (I7_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE),
                 5 => (I5_ipd'last_event, tpd_I5_O, TRUE),
                 6 => (I6_ipd'last_event, tpd_I6_O, TRUE),
                 7 => (I7_ipd'last_event, tpd_I7_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;
 
configuration CFG_AND8_VITAL of AND8 is 
        for VITAL
        end for; 
end CFG_AND8_VITAL;


----- CELL MUX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity MUX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      S0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of MUX2 : entity is TRUE;
end MUX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of MUX2 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (S0_ipd, S0, tipd_S0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, S0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalMUX
                 (data => (I1_ipd, I0_ipd),
                  dselect => (0 => S0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (S0_ipd'last_event, tpd_S0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_MUX2_VITAL of MUX2 is
   for VITAL
   end for;
end CFG_MUX2_VITAL;


----- CELL MUX4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity MUX4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      S0                             :	in    STD_ULOGIC;
      S1                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of MUX4 : entity is TRUE;
end MUX4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of MUX4 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S1_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (S0_ipd, S0, tipd_S0);
   VitalWireDelay (S1_ipd, S1, tipd_S1);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, S0_ipd, S1_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalMUX
                 (data => (I3_ipd, I2_ipd, I1_ipd, I0_ipd),
                  dselect => (S1_ipd, S0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (S0_ipd'last_event, tpd_S0_O, TRUE),
                 5 => (S1_ipd'last_event, tpd_S1_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_MUX4_VITAL of MUX4 is
   for VITAL
   end for;
end CFG_MUX4_VITAL;
 
----- VITAL model for cell BI_DIR -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity BI_DIR is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      OUTOPEN        : string  := "Off";
      PULL           : string  := "Off";
      tpd_OE_IO                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_I0_IO                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_IO_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_OE                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_IO                        :	VitalDelayType01 := (0.0 ns, 0.0 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      OE                             :	in    STD_ULOGIC;
      IO                             :	inout STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BI_DIR : entity is TRUE;
end BI_DIR;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of BI_DIR is
   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL IO_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   VitalWireDelay (IO_ipd, IO, tipd_IO);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------

   VITALBehavior : process (OE_ipd, I0_ipd, IO_ipd)


   -- functionality results
     VARIABLE O_zd : std_ulogic ;

   -- output glitch detection variables
     VARIABLE IO_GlitchData	: VitalGlitchDataType;
     VARIABLE O_GlitchData	: VitalGlitchDataType;
     VARIABLE IO_zd : std_ulogic ;

   begin
      -------------------------
      --  Functionality Section
      -------------------------

      if (OE_ipd = '0') then
         IO_zd := 'Z';
      elsif (OE_ipd = '1') then
         if (OUTOPEN = "Off") then
             IO_zd := TO_X01(I0_ipd);
         elsif (OUTOPEN = "Drain" or OUTOPEN = "Collect") then
             if (I0_ipd = '0') then
                IO_zd := '0';
             elsif (I0_ipd = '1') then
                IO_zd := 'Z';
             else
                IO_zd := 'X';
             end if;
         end if;
      end if;


      if (PULL = "Off") then
           O_zd := TO_X01(IO_ipd);
      elsif (PULL = "Up") then
           CASE TO_X01Z(IO_ipd) IS
              WHEN '0'  =>  O_zd := '0';
              WHEN '1'  =>  O_zd := '1';
              WHEN 'Z'  =>  O_zd := '1';
              WHEN others => O_zd := 'X';
           END CASE;
      elsif (PULL = "Down") then
           CASE TO_X01Z(IO_ipd) IS
              WHEN '0'  =>  O_zd := '0';
              WHEN '1'  =>  O_zd := '1';
              WHEN 'Z'  =>  O_zd := '0';
              WHEN others => O_zd := 'X';
           END CASE;
      elsif (PULL = "Hold") then
           CASE TO_X01Z(IO_ipd) IS
              WHEN '0'  =>  O_zd := '0';
              WHEN '1'  =>  O_zd := '1';
              WHEN 'Z'  =>  O_zd := O_zd;
              WHEN others => O_zd := 'X';
           END CASE;
      end if;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => IO,
       GlitchData => IO_GlitchData,
       OutSignalName => "IO",
       OutTemp => IO_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_IO), TRUE),
                 1 => (I0_ipd'last_event, VitalExtendToFillDelay(tpd_I0_IO), TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");

      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (IO_ipd'last_event, tpd_IO_O, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_BI_DIR_VITAL of BI_DIR is 
        for VITAL
        end for; 
end CFG_BI_DIR_VITAL;

----- VITAL model for cell BUFF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity BUFF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BUFF : entity is TRUE;
end BUFF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of BUFF is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_BUFF_VITAL of BUFF is 
        for VITAL
        end for; 
end CFG_BUFF_VITAL;

----- VITAL model for cell BUFTH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity BUFTH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      OUTOPEN        : string := "Off";
      tpd_OE_O                       :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_OE                        :	VitalDelayType01 := (0.0 ns, 0.0 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      OE                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BUFTH : entity is TRUE;
end BUFTH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of BUFTH is
   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, OE_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------

       if (OE = '0') then
          O_zd := 'Z';
       elsif (OE = '1') then
         if (OUTOPEN = "Off") then
              O_zd := TO_X01(I0_ipd);
         elsif (OUTOPEN = "Drain" or OUTOPEN = "Collect") then
           if (I0_ipd = '0') then
              O_zd := '0';
           elsif (I0_ipd = '1') then
              O_zd := 'Z';
           else
              O_zd := 'X';
           end if;
         end if;
       end if;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_O), TRUE),
                 1 => (I0_ipd'last_event, VitalExtendToFillDelay(tpd_I0_O), TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");

end process;
end VITAL;

configuration CFG_BUFTH_VITAL of BUFTH is 
        for VITAL
        end for; 
end CFG_BUFTH_VITAL;

----- VITAL model for cell BUFTL -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity BUFTL is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      OUTOPEN       : string := "Off";
      tpd_OE_O                       :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_OE                        :	VitalDelayType01 := (0.0 ns, 0.0 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      OE                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BUFTL : entity is TRUE;
end BUFTL;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of BUFTL is
   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, OE_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
       if (OE = '1') then
          O_zd := 'Z';
       elsif (OE = '0') then
         if (OUTOPEN = "Off") then
              O_zd := TO_X01(I0_ipd);
         elsif (OUTOPEN = "Drain" or OUTOPEN = "Collect") then
           if (I0_ipd = '0') then
              O_zd := '0';
           elsif (I0_ipd = '1') then
              O_zd := 'Z';
           else
              O_zd := 'X';
           end if;
         end if;
       end if;
      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_O), TRUE),
                 1 => (I0_ipd'last_event, VitalExtendToFillDelay(tpd_I0_O), TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");

end process;
end VITAL;

configuration CFG_BUFTL_VITAL of BUFTL is 
        for VITAL
        end for; 
end CFG_BUFTL_VITAL;

----- VITAL model for cell CLKI -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CLKI is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_PAD_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_PAD                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      PAD                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CLKI : entity is TRUE;
end CLKI;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of CLKI is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL PAD_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (PAD_ipd, PAD, tipd_PAD);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (PAD_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(PAD_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (PAD_ipd'last_event, tpd_PAD_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_CLKI_VITAL of CLKI is 
        for VITAL
        end for; 
end CFG_CLKI_VITAL;

----- VITAL model for cell DFF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;

-- entity declaration --
entity DFF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      R_DELAY : TIME := 2 ns;
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge    :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge     :	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge            :	VitalDelayType := 1.000 ns;
      tpw_CLK_posedge                :	VitalDelayType := 1.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFF : entity is TRUE;
end DFF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DFF is
   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R              : STD_ULOGIC := '0';

begin

   R <= '1' after R_DELAY; 

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_posedge,
          TimingData              => Tmkr_D_CLK_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/DFF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_posedge or Pviol_CLK;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_CLK_dly, CLK_dly, R ,'1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFF_VITAL of DFF is 
        for VITAL
        end for; 
end CFG_DFF_VITAL;

----- VITAL model for cell DFFC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFC is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      R_DELAY : TIME := 2 ns;
      tpd_CLK_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_CE_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge        :	VitalDelayType := 1.000 ns;
      tperiod_CLK_posedge            :	VitalDelayType := 1.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFC : entity is TRUE;
end DFFC;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DFFC is
   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R              : STD_ULOGIC := '0';

begin

   R <= '1' after R_DELAY; 

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_posedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TO_X01(CE_ipd) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFC",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_posedge,
          TimingData              => Tmkr_CE_CLK_posedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_noedge_posedge,
          SetupLow                => tsetup_CE_CLK_noedge_posedge,
          HoldHigh                => thold_CE_CLK_noedge_posedge,
          HoldLow                 => thold_CE_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFC",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1,
          PeriodData              => PInfo_CLK_CE_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(CE_ipd) = '1',
          HeaderMsg               => InstancePath & "/DFFC",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_CE_EQ_1_posedge or Tviol_CE_CLK_posedge or Pviol_CLK_CE_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcetab,
        DataIn => (
               D_CLK_dly, CLK_dly, R ,'1', CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFC_VITAL of DFFC is 
        for VITAL
        end for; 
end CFG_DFFC_VITAL;

----- VITAL model for cell DFFCR -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFCR is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_R_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_CE_CLK_posedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge :	VitalDelayType := 1.000 ns;
      tperiod_CLK_posedge :	VitalDelayType := 1.000 ns;
      trecovery_R_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_R_CLK_posedge_posedge :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCR : entity is TRUE;
end DFFCR;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DFFCR is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (R_ipd, R, tipd_R);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, R_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_ANB_R_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_R_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_R_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_CE_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_CE_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1_ANB_R_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1_ANB_R_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_1_posedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_ANB_R_EQ_1_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => 
                           TO_X01((R_CLK_dly) AND (CE_ipd)) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_R_EQ_1_posedge,
          TimingData              => Tmkr_CE_CLK_R_EQ_1_posedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_posedge_posedge,
          SetupLow                => tsetup_CE_CLK_posedge_posedge,
          HoldHigh                => thold_CE_CLK_posedge_posedge,
          HoldLow                 => thold_CE_CLK_posedge_posedge,
          CheckEnabled            => TO_X01(R_CLK_dly) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_CE_EQ_1_posedge,
          TimingData              => Tmkr_R_CLK_CE_EQ_1_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_posedge_posedge,
          Removal                 => thold_R_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => 
                           TO_X01(CE_ipd) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1_ANB_R_EQ_1,
          PeriodData              => PInfo_CLK_CE_EQ_1_ANB_R_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01((R_CLK_dly) AND (CE_ipd)) = '1',
          HeaderMsg               => InstancePath & "/DFFCR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_1_posedge or Tviol_CE_CLK_R_EQ_1_posedge or Tviol_R_CLK_CE_EQ_1_posedge or Pviol_CLK_CE_EQ_1_ANB_R_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcetab,
        DataIn => (
               D_CLK_dly, CLK_dly,R_CLK_dly,'1', CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCR_VITAL of DFFCR is 
        for VITAL
        end for; 
end CFG_DFFCR_VITAL;
----- VITAL model for cell DFFCRH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFCRH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_R_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_CE_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge 		:	VitalDelayType := 1.000 ns;
      tpw_R_posedge 		:	VitalDelayType := 1.000 ns;
      tperiod_CLK_posedge :	VitalDelayType := 1.000 ns;
      trecovery_R_CLK_negedge_posedge :	VitalDelayType := 0.100 ns;
      thold_R_CLK_negedge_posedge :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCRH : entity is TRUE;
end DFFCRH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DFFCRH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (R_ipd, R, tipd_R);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, R_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_ANB_R_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_R_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_R_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_CE_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_CE_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1_ANB_R_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_R				: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1_ANB_R_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_R				: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE R_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_0_posedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_ANB_R_EQ_0_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => 
                           TO_X01(((NOT R_CLK_dly)) AND (CE_ipd)) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_R_EQ_0_posedge,
          TimingData              => Tmkr_CE_CLK_R_EQ_0_posedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_noedge_posedge,
          SetupLow                => tsetup_CE_CLK_noedge_posedge,
          HoldHigh                => thold_CE_CLK_noedge_posedge,
          HoldLow                 => thold_CE_CLK_noedge_posedge,
          CheckEnabled            => TO_X01(NOT R_CLK_dly)= '1', 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_CE_EQ_1_posedge,
          TimingData              => Tmkr_R_CLK_CE_EQ_1_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_negedge_posedge,
          Removal                 => thold_R_CLK_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => 
                           TO_X01(CE_ipd) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_R,
          PeriodData              => PInfo_R,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_R_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/DFFCRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1_ANB_R_EQ_0,
          PeriodData              => PInfo_CLK_CE_EQ_1_ANB_R_EQ_0,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01(((NOT R_CLK_dly)) AND (CE_ipd)) = '1',
          HeaderMsg               => InstancePath & "/DFFCRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_0_posedge or Tviol_CE_CLK_R_EQ_0_posedge or Tviol_R_CLK_CE_EQ_1_posedge or Pviol_CLK_CE_EQ_1_ANB_R_EQ_0 or Pviol_R;
      R_inverted := (NOT R_CLK_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcetab,
        DataIn => (
               D_CLK_dly, CLK_dly,R_inverted,'1', CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCRH_VITAL of DFFCRH is 
        for VITAL
        end for; 
end CFG_DFFCRH_VITAL;

----- VITAL model for cell DFFCS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFCS is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_S_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_CE_CLK_posedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge :	VitalDelayType := 1.000 ns;
      tperiod_CLK_posedge :	VitalDelayType := 1.000 ns;
      trecovery_S_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_S_CLK_posedge_posedge :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCS : entity is TRUE;
end DFFCS;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DFFCS is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, S_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_ANB_S_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_ANB_S_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_S_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_S_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_CE_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_CE_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1_ANB_S_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1_ANB_S_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_ANB_S_EQ_1_posedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_ANB_S_EQ_1_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => 
                           TO_X01((S_CLK_dly) AND (CE_ipd)) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_S_EQ_1_posedge,
          TimingData              => Tmkr_CE_CLK_S_EQ_1_posedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_posedge_posedge,
          SetupLow                => tsetup_CE_CLK_posedge_posedge,
          HoldHigh                => thold_CE_CLK_posedge_posedge,
          HoldLow                 => thold_CE_CLK_posedge_posedge,
          CheckEnabled            => TO_X01(S_CLK_dly) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_CE_EQ_1_posedge,
          TimingData              => Tmkr_S_CLK_CE_EQ_1_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_posedge_posedge,
          Removal                 => thold_S_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => 
                           TO_X01(CE_ipd) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1_ANB_S_EQ_1,
          PeriodData              => PInfo_CLK_CE_EQ_1_ANB_S_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                          TO_X01((S_CLK_dly) AND (CE_ipd)) = '1',
          HeaderMsg               => InstancePath & "/DFFCS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_CE_EQ_1_ANB_S_EQ_1_posedge or Tviol_CE_CLK_S_EQ_1_posedge or Tviol_S_CLK_CE_EQ_1_posedge or Pviol_CLK_CE_EQ_1_ANB_S_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcetab,
        DataIn => (
               D_CLK_dly, CLK_dly,'1',S_CLK_dly, CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCS_VITAL of DFFCS is 
        for VITAL
        end for; 
end CFG_DFFCS_VITAL;
----- VITAL model for cell DFFCSH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFCSH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_S_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_CE_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge :	VitalDelayType := 1.000 ns;
      tpw_S_posedge :	VitalDelayType := 1.000 ns;
      tperiod_CLK_posedge :	VitalDelayType := 1.000 ns;
      trecovery_S_CLK_negedge_posedge :	VitalDelayType := 0.100 ns;
      thold_S_CLK_negedge_posedge :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCSH : entity is TRUE;
end DFFCSH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DFFCSH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, S_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_ANB_S_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_ANB_S_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_S_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_S_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_CE_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_CE_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1_ANB_S_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_S	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1_ANB_S_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_S	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE S_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_ANB_S_EQ_0_posedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_ANB_S_EQ_0_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => 
                           TO_X01(((NOT S_CLK_dly)) AND (CE_ipd)) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_S_EQ_0_posedge,
          TimingData              => Tmkr_CE_CLK_S_EQ_0_posedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_noedge_posedge,
          SetupLow                => tsetup_CE_CLK_noedge_posedge,
          HoldHigh                => thold_CE_CLK_noedge_posedge,
          HoldLow                 => thold_CE_CLK_noedge_posedge,
          CheckEnabled            => TO_X01(NOT S_CLK_dly) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_CE_EQ_1_posedge,
          TimingData              => Tmkr_S_CLK_CE_EQ_1_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_negedge_posedge,
          Removal                 => thold_S_CLK_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => 
                           TO_X01(CE_ipd) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_S,
          PeriodData              => PInfo_S,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_S_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DFFCSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1_ANB_S_EQ_0,
          PeriodData              => PInfo_CLK_CE_EQ_1_ANB_S_EQ_0,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01(((NOT S_CLK_dly)) AND (CE_ipd)) = '1',
          HeaderMsg               => InstancePath & "/DFFCSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_CE_EQ_1_ANB_S_EQ_0_posedge or Tviol_CE_CLK_S_EQ_0_posedge or Tviol_S_CLK_CE_EQ_1_posedge or Pviol_CLK_CE_EQ_1_ANB_S_EQ_0 or Pviol_S;
      S_inverted := (NOT S_CLK_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcetab,
        DataIn => (
               D_CLK_dly, CLK_dly,'1', S_inverted, CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCSH_VITAL of DFFCSH is 
        for VITAL
        end for; 
end CFG_DFFCSH_VITAL;

----- VITAL model for cell DFFCRS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;

-- entity declaration --
entity DFFCRS is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_S_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_R_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      tsetup_CE_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      thold_CE_CLK_posedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge :	VitalDelayType := 1.000 ns;
      tperiod_CLK_posedge :	VitalDelayType := 1.000 ns;
      trecovery_R_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_R_CLK_posedge_posedge :	VitalDelayType := 0.000 ns;
      trecovery_S_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_S_CLK_posedge_posedge :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCRS : entity is TRUE;
end DFFCRS;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DFFCRS is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (R_ipd, R, tipd_R);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_CLK_dly, CLK_dly, D_CLK_dly, R_CLK_dly, S_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_AN_R_EQ_1_AN_S_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_AN_R_EQ_1_AN_S_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_R_EQ_1_AN_S_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_R_EQ_1_AN_S_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_CE_EQ_1_AN_S_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_CE_EQ_1_AN_S_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_CE_EQ_1_AN_R_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_CE_EQ_1_AN_R_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1_AN_R_EQ_1_AN_S_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1_AN_R_EQ_1_AN_S_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE CE_delayed : STD_ULOGIC := 'X';
   VARIABLE D_delayed : STD_ULOGIC := 'X';
   VARIABLE CLK_delayed : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_AN_R_EQ_1_AN_S_EQ_1_posedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_AN_R_EQ_1_AN_S_EQ_1_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => 
                           TO_X01((R_CLK_dly) AND (CE_CLK_dly) AND (S_CLK_dly))
                            /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_R_EQ_1_AN_S_EQ_1_posedge,
          TimingData              => Tmkr_CE_CLK_R_EQ_1_AN_S_EQ_1_posedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_posedge_posedge,
          SetupLow                => tsetup_CE_CLK_posedge_posedge,
          HoldHigh                => thold_CE_CLK_posedge_posedge,
          HoldLow                 => thold_CE_CLK_posedge_posedge,
          CheckEnabled            => TO_X01(R_CLK_dly AND S_CLK_dly) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_CE_EQ_1_AN_S_EQ_1_posedge,
          TimingData              => Tmkr_R_CLK_CE_EQ_1_AN_S_EQ_1_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_posedge_posedge,
          Removal                 => thold_R_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => 
                           TO_X01((S_CLK_dly) AND (CE_CLK_dly)) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_CE_EQ_1_AN_R_EQ_1_posedge,
          TimingData              => Tmkr_S_CLK_CE_EQ_1_AN_R_EQ_1_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_posedge_posedge,
          Removal                 => thold_S_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => 
                           TO_X01((R_CLK_dly) AND (CE_CLK_dly)) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1_AN_R_EQ_1_AN_S_EQ_1,
          PeriodData              => PInfo_CLK_CE_EQ_1_AN_R_EQ_1_AN_S_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01(( (NOT S_CLK_dly) ) OR ( (NOT R_CLK_dly) )
                            ) /= '1',
          HeaderMsg               => InstancePath & "/DFFCRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_CE_EQ_1_AN_R_EQ_1_AN_S_EQ_1_posedge or Tviol_CE_CLK_R_EQ_1_AN_S_EQ_1_posedge or Tviol_R_CLK_CE_EQ_1_AN_S_EQ_1_posedge or Pviol_CLK_CE_EQ_1_AN_R_EQ_1_AN_S_EQ_1 or Tviol_S_CLK_CE_EQ_1_AN_R_EQ_1_posedge;
      CE_delayed := CE_CLK_dly;
      D_delayed := D_CLK_dly;
      CLK_delayed := CLK_dly;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcetab,
        DataIn => (
               D_delayed, CLK_delayed, R_CLK_dly, S_CLK_dly,CE_delayed ));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 1 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 2 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCRS_VITAL of DFFCRS is 
        for VITAL
        end for; 
end CFG_DFFCRS_VITAL;
----- VITAL model for cell DFFCRSH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;


-- entity declaration --
entity DFFCRSH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_S_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_R_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_CE_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge :	VitalDelayType := 1.000 ns;
      tpw_R_posedge :	VitalDelayType := 1.000 ns;
      tpw_S_posedge :	VitalDelayType := 1.000 ns;
      tperiod_CLK_posedge :	VitalDelayType := 1.000 ns;
      trecovery_R_CLK_negedge_posedge :	VitalDelayType := 0.100 ns;
      thold_R_CLK_negedge_posedge :	VitalDelayType := 0.000 ns;
      trecovery_S_CLK_negedge_posedge :	VitalDelayType := 0.100 ns;
      thold_S_CLK_negedge_posedge :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCRSH : entity is TRUE;
end DFFCRSH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DFFCRSH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';


begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (R_ipd, R, tipd_R);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_CLK_dly, CLK_dly, D_CLK_dly, R_CLK_dly, S_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_AN_R_EQ_0_AN_S_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_AN_R_EQ_0_AN_S_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_R_EQ_0_AN_S_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_R_EQ_0_AN_S_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_CE_EQ_1_AN_S_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_CE_EQ_1_AN_S_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_CE_EQ_1_AN_R_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_CE_EQ_1_AN_R_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1_AN_R_EQ_0_AN_S_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_R	: STD_ULOGIC := '0';
   VARIABLE Pviol_S	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1_AN_R_EQ_0_AN_S_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_R	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_S	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE CE_delayed : STD_ULOGIC := 'X';
   VARIABLE D_delayed : STD_ULOGIC := 'X';
   VARIABLE R_inverted : STD_ULOGIC := 'X';
   VARIABLE S_inverted : STD_ULOGIC := 'X';
   VARIABLE CLK_delayed : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_AN_R_EQ_0_AN_S_EQ_0_posedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_AN_R_EQ_0_AN_S_EQ_0_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => 
                           TO_X01(((NOT R_CLK_dly)) AND (CE_CLK_dly) AND ((NOT
                            S_CLK_dly))) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_R_EQ_0_AN_S_EQ_0_posedge,
          TimingData              => Tmkr_CE_CLK_R_EQ_0_AN_S_EQ_0_posedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_noedge_posedge,
          SetupLow                => tsetup_CE_CLK_noedge_posedge,
          HoldHigh                => thold_CE_CLK_noedge_posedge,
          HoldLow                 => thold_CE_CLK_noedge_posedge,
          CheckEnabled            => TO_X01((NOT R_CLK_dly) AND (NOT S_CLK_dly)) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_CE_EQ_1_AN_S_EQ_0_posedge,
          TimingData              => Tmkr_R_CLK_CE_EQ_1_AN_S_EQ_0_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_negedge_posedge,
          Removal                 => thold_R_CLK_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => 
                           TO_X01(((NOT S_CLK_dly)) AND (CE_CLK_dly)) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_CE_EQ_1_AN_R_EQ_0_posedge,
          TimingData              => Tmkr_S_CLK_CE_EQ_1_AN_R_EQ_0_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_negedge_posedge,
          Removal                 => thold_S_CLK_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => 
                           TO_X01(((NOT R_CLK_dly)) AND (CE_CLK_dly)) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_S,
          PeriodData              => PInfo_S,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_S_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DFFCRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_R,
          PeriodData              => PInfo_R,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_R_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DFFCRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1_AN_R_EQ_0_AN_S_EQ_0,
          PeriodData              => PInfo_CLK_CE_EQ_1_AN_R_EQ_0_AN_S_EQ_0,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01(( S_CLK_dly ) OR ( R_CLK_dly ) ) /= '1',
          HeaderMsg               => InstancePath & "/DFFCRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_CE_EQ_1_AN_R_EQ_0_AN_S_EQ_0_posedge or Tviol_CE_CLK_R_EQ_0_AN_S_EQ_0_posedge or Tviol_R_CLK_CE_EQ_1_AN_S_EQ_0_posedge or Tviol_S_CLK_CE_EQ_1_AN_R_EQ_0_posedge or Pviol_CLK_CE_EQ_1_AN_R_EQ_0_AN_S_EQ_0 or Pviol_R or Pviol_S;
      CE_delayed := CE_CLK_dly;
      D_delayed := D_CLK_dly;
      CLK_delayed := CLK_dly;
      R_inverted := (NOT R_CLK_dly);
      S_inverted := (NOT S_CLK_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcetab,
        DataIn => (
               D_delayed, CLK_delayed,R_inverted,S_inverted,CE_delayed));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 1 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 2 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCRSH_VITAL of DFFCRSH is 
        for VITAL
        end for; 
end CFG_DFFCRSH_VITAL;

----- VITAL model for cell DFFR -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFR is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_R_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge         :	VitalDelayType := 1.000 ns;
      tperiod_CLK_posedge             :	VitalDelayType := 1.000 ns;
      trecovery_R_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_R_CLK_posedge_posedge    :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFR : entity is TRUE;
end DFFR;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DFFR is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (R_ipd, R, tipd_R);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, R_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_R_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_R_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_R_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_R_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_R_EQ_1_posedge,
          TimingData              => Tmkr_D_CLK_R_EQ_1_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => 
                           TO_X01(R_CLK_dly) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_posedge,
          TimingData              => Tmkr_R_CLK_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_posedge_posedge,
          Removal                 => thold_R_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_R_EQ_1,
          PeriodData              => PInfo_CLK_R_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01((R_CLK_dly) ) = '1',
          HeaderMsg               => InstancePath & "/DFFR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_R_EQ_1_posedge or Tviol_R_CLK_posedge or Pviol_CLK_R_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
              D_CLK_dly, CLK_dly, R_CLK_dly, '1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFR_VITAL of DFFR is 
        for VITAL
        end for; 
end CFG_DFFR_VITAL;
----- VITAL model for cell DFFRH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFRH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_R_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge         :	VitalDelayType := 1.000 ns;
      tpw_R_posedge         :	VitalDelayType := 1.000 ns;
      tperiod_CLK_posedge             :	VitalDelayType := 1.000 ns;
      trecovery_R_CLK_negedge_posedge :	VitalDelayType := 0.100 ns;
      thold_R_CLK_negedge_posedge    :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFRH : entity is TRUE;
end DFFRH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DFFRH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (R_ipd, R, tipd_R);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, R_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_R_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_R_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_R_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_R	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_R_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_R	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE R_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_R_EQ_0_posedge,
          TimingData              => Tmkr_D_CLK_R_EQ_0_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => 
                           TO_X01((R_CLK_dly)) = '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_posedge,
          TimingData              => Tmkr_R_CLK_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_negedge_posedge,
          Removal                 => thold_R_CLK_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_R,
          PeriodData              => PInfo_R,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_R_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DFFRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_R_EQ_0,
          PeriodData              => PInfo_CLK_R_EQ_0,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01(R_CLK_dly ) = '0',
          HeaderMsg               => InstancePath & "/DFFRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_R_EQ_0_posedge or Tviol_R_CLK_posedge or Pviol_CLK_R_EQ_0 or Pviol_R;
      R_inverted := (NOT R_CLK_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_CLK_dly, CLK_dly, R_inverted, '1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFRH_VITAL of DFFRH is 
        for VITAL
        end for; 
end CFG_DFFRH_VITAL;
----- VITAL model for cell DFFRS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;

-- entity declaration --
entity DFFRS is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_R_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_S_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge :	VitalDelayType := 1.000 ns;
      tpw_R_negedge :	VitalDelayType := 1.000 ns;
      tpw_S_negedge :	VitalDelayType := 1.000 ns;
      tperiod_CLK_posedge   :	VitalDelayType := 1.000 ns;
      trecovery_R_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_R_CLK_posedge_posedge :	VitalDelayType := 0.000 ns;
      trecovery_S_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_S_CLK_posedge_posedge :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFRS : entity is TRUE;
end DFFRS;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DFFRS is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (R_ipd, R, tipd_R);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, R_CLK_dly, S_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_R_EQ_1_AN_S_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_R_EQ_1_AN_S_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_S_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_S_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_R_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_R_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_R_EQ_1_AN_S_EQ_1	: STD_ULOGIC := '0';
   VARIABLE Pviol_R			: STD_ULOGIC := '0';
   VARIABLE Pviol_S			: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_R_EQ_1_AN_S_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_R			: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_S			: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE D_delayed : STD_ULOGIC := 'X';
   VARIABLE CLK_delayed : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_R_EQ_1_AN_S_EQ_1_posedge,
          TimingData              => Tmkr_D_CLK_R_EQ_1_AN_S_EQ_1_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => 
                           TO_X01((S_CLK_dly) AND (R_CLK_dly)) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_S_EQ_1_posedge,
          TimingData              => Tmkr_R_CLK_S_EQ_1_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_posedge_posedge,
          Removal                 => thold_R_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => 
                           TO_X01(S_CLK_dly) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_R_EQ_1_posedge,
          TimingData              => Tmkr_S_CLK_R_EQ_1_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_posedge_posedge,
          Removal                 => thold_S_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => 
                           TO_X01(R_CLK_dly) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_S,
          PeriodData              => PInfo_S,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_S_negedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/DFFRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_R,
          PeriodData              => PInfo_R,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_R_negedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DFFRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_R_EQ_1_AN_S_EQ_1,
          PeriodData              => PInfo_CLK_R_EQ_1_AN_S_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01(( (NOT S_CLK_dly) ) OR ( (NOT R_CLK_dly) )
                            ) /= '1',
          HeaderMsg               => InstancePath & "/DFFRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      D_delayed := D_CLK_dly;
      CLK_delayed := CLK_dly;
      Violation := Tviol_D_CLK_R_EQ_1_AN_S_EQ_1_posedge or Tviol_R_CLK_S_EQ_1_posedge or Tviol_S_CLK_R_EQ_1_posedge or Pviol_CLK_R_EQ_1_AN_S_EQ_1 or Pviol_R or Pviol_S;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_delayed, CLK_delayed, R_CLK_dly, S_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 1 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 2 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFRS_VITAL of DFFRS is 
        for VITAL
        end for; 
end CFG_DFFRS_VITAL;
----- VITAL model for cell DFFRSH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;

-- entity declaration --
entity DFFRSH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_R_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_S_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_D_CLK_noedge_posedge    :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge     :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge 		     :	VitalDelayType := 1.000 ns;
      tpw_R_posedge 		     :	VitalDelayType := 1.000 ns;
      tpw_S_posedge 		     :	VitalDelayType := 1.000 ns;
      tperiod_CLK_posedge   	     :	VitalDelayType := 1.000 ns;
      trecovery_R_CLK_negedge_posedge :	VitalDelayType := 0.100 ns;
      thold_R_CLK_negedge_posedge     :	VitalDelayType := 0.000 ns;
      trecovery_S_CLK_negedge_posedge :	VitalDelayType := 0.100 ns;
      thold_S_CLK_negedge_posedge     :	VitalDelayType := 0.000 ns;
      ticd_CLK                        :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                      :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                      :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                      :	VitalDelayType := 0.000 ns;
      tipd_D                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFRSH : entity is TRUE;
end DFFRSH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DFFRSH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (R_ipd, R, tipd_R);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, R_CLK_dly, S_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_R_EQ_0_AN_S_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_R_EQ_0_AN_S_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_S_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_S_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_R_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_R_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_R_EQ_0_AN_S_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_R			: STD_ULOGIC := '0';
   VARIABLE Pviol_S			: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_R_EQ_0_AN_S_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_R			: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_S			: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE D_delayed : STD_ULOGIC := 'X';
   VARIABLE CLK_delayed : STD_ULOGIC := 'X';
   VARIABLE R_inverted: STD_ULOGIC := 'X';
   VARIABLE S_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_R_EQ_0_AN_S_EQ_0_posedge,
          TimingData              => Tmkr_D_CLK_R_EQ_0_AN_S_EQ_0_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => 
                           TO_X01(((NOT S_CLK_dly)) AND ((NOT R_CLK_dly))) /=
                            '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_S_EQ_0_posedge,
          TimingData              => Tmkr_R_CLK_S_EQ_0_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_negedge_posedge,
          Removal                 => thold_R_CLK_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => 
                           TO_X01((NOT S_CLK_dly)) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_R_EQ_0_posedge,
          TimingData              => Tmkr_S_CLK_R_EQ_0_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_negedge_posedge,
          Removal                 => thold_S_CLK_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => 
                           TO_X01((NOT R_CLK_dly)) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_S,
          PeriodData              => PInfo_S,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_S_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_S_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DFFRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_R,
          PeriodData              => PInfo_R,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_R_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DFFRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_R_EQ_0_AN_S_EQ_0,
          PeriodData              => PInfo_CLK_R_EQ_0_AN_S_EQ_0,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01(( S_CLK_dly ) OR ( R_CLK_dly ) ) /= '1',
          HeaderMsg               => InstancePath & "/DFFRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      D_delayed := D_CLK_dly;
      CLK_delayed := CLK_dly;
      R_inverted := NOT R_CLK_dly;
      S_inverted := NOT S_CLK_dly;
      Violation := Tviol_D_CLK_R_EQ_0_AN_S_EQ_0_posedge or Tviol_R_CLK_S_EQ_0_posedge or Tviol_S_CLK_R_EQ_0_posedge or Pviol_CLK_R_EQ_0_AN_S_EQ_0 or Pviol_R or Pviol_S;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_delayed, CLK_delayed, R_inverted, S_inverted));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 1 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 2 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFRSH_VITAL of DFFRSH is 
        for VITAL
        end for; 
end CFG_DFFRSH_VITAL;

----- VITAL model for cell DFFS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFS is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_S_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge         :	VitalDelayType := 1.000 ns;
      tperiod_CLK_posedge             :	VitalDelayType := 1.000 ns;
      trecovery_S_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_S_CLK_posedge_posedge    :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFS : entity is TRUE;
end DFFS;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DFFS is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, S_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_S_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_S_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_S_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_S_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_S_EQ_1_posedge,
          TimingData              => Tmkr_D_CLK_S_EQ_1_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => 
                           TO_X01(S_CLK_dly) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_posedge,
          TimingData              => Tmkr_S_CLK_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_posedge_posedge,
          Removal                 => thold_S_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_S_EQ_1,
          PeriodData              => PInfo_CLK_S_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01((S_CLK_dly) ) = '1',
          HeaderMsg               => InstancePath & "/DFFS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_S_EQ_1_posedge or Tviol_S_CLK_posedge or Pviol_CLK_S_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_CLK_dly, CLK_dly, '1', S_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFS_VITAL of DFFS is 
        for VITAL
        end for; 
end CFG_DFFS_VITAL;
----- VITAL model for cell DFFSH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFSH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_S_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge         :	VitalDelayType := 1.000 ns;
      tpw_S_posedge         :	VitalDelayType := 1.000 ns;
      tperiod_CLK_posedge             :	VitalDelayType := 1.000 ns;
      trecovery_S_CLK_negedge_posedge :	VitalDelayType := 0.100 ns;
      thold_S_CLK_negedge_posedge    :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFSH : entity is TRUE;
end DFFSH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DFFSH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, S_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_S_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_S_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_S_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_S	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_S_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_S	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE S_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_S_EQ_0_posedge,
          TimingData              => Tmkr_D_CLK_S_EQ_0_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => 
                           TO_X01((S_CLK_dly)) = '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_posedge,
          TimingData              => Tmkr_S_CLK_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_negedge_posedge,
          Removal                 => thold_S_CLK_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_S,
          PeriodData              => PInfo_S,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_S_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DFFSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_S_EQ_0,
          PeriodData              => PInfo_CLK_S_EQ_0,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01(S_CLK_dly ) = '0',
          HeaderMsg               => InstancePath & "/DFFSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_S_EQ_0_posedge or Tviol_S_CLK_posedge or Pviol_CLK_S_EQ_0;
      S_inverted := (NOT S_CLK_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_CLK_dly, CLK_dly, '1', S_inverted));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFSH_VITAL of DFFSH is 
        for VITAL
        end for; 
end CFG_DFFSH_VITAL;
----- VITAL model for cell DLAT -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DLAT is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_LAT_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_D_LAT_noedge_negedge    :	VitalDelayType := 0.100 ns;
      thold_D_LAT_noedge_negedge     :	VitalDelayType := 0.000 ns;
      tperiod_LAT_posedge            :	VitalDelayType := 1.000 ns;
      tpw_LAT_posedge                :	VitalDelayType := 1.000 ns;
      ticd_LAT                       :	VitalDelayType := 0.000 ns;
      tisd_D_LAT                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LAT                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      LAT                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DLAT : entity is TRUE;
end DLAT;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DLAT is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_LAT_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (LAT_ipd, LAT, tipd_LAT);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (LAT_dly, LAT_ipd, ticd_LAT);
   VitalSignalDelay (D_LAT_dly, D_ipd, tisd_D_LAT);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (LAT_dly, D_LAT_dly)

   -- timing check results
   VARIABLE Tviol_D_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_LAT	: STD_ULOGIC := '0';
   VARIABLE PInfo_LAT	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_LAT_negedge,
          TimingData              => Tmkr_D_LAT_negedge,
          TestSignal              => D_LAT_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_D_LAT_noedge_negedge,
          SetupLow                => tsetup_D_LAT_noedge_negedge,
          HoldHigh                => thold_D_LAT_noedge_negedge,
          HoldLow                 => thold_D_LAT_noedge_negedge,
          CheckEnabled            => 
                           TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLAT",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_LAT,
          PeriodData              => PInfo_LAT,
          TestSignal              => LAT_dly,
          TestSignalName          => "LAT",
          TestDelay               => ticd_LAT,
          Period                  => tperiod_LAT_posedge,
          PulseWidthHigh          => tpw_LAT_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TRUE,
          HeaderMsg               => InstancePath &"/DLAT",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_LAT_negedge or Pviol_LAT;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => latchtab,
        DataIn => (
               D_LAT_dly, LAT_dly,'1','1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_LAT_dly'last_event, tpd_D_Q, TRUE),
                 1 => (LAT_dly'last_event, tpd_LAT_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DLAT_VITAL of DLAT is 
        for VITAL
        end for; 
end CFG_DLAT_VITAL;
----- VITAL model for cell DLATR -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DLATR is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_LAT_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_R_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_D_LAT_noedge_negedge :	VitalDelayType := 0.100 ns;
      thold_D_LAT_noedge_negedge :	VitalDelayType := 0.000 ns;
      tpw_LAT_posedge         :	VitalDelayType := 1.0 ns;
      tperiod_LAT_posedge             :	VitalDelayType := 1.0 ns;
      trecovery_R_LAT_posedge_negedge :	VitalDelayType := 0.1 ns;
      thold_R_LAT_posedge_negedge    :	VitalDelayType := 0.0 ns;
      ticd_LAT                       :	VitalDelayType := 0.0 ns;
      tisd_D_LAT                     :	VitalDelayType := 0.0 ns;
      tisd_R_LAT                     :	VitalDelayType := 0.0 ns;
      tipd_D                         :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_LAT                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_R                         :	VitalDelayType01 := (0.0 ns, 0.0 ns));

   port(
      D                              :	in    STD_ULOGIC;
      LAT                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DLATR : entity is TRUE;
end DLATR;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DLATR is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_LAT_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (LAT_ipd, LAT, tipd_LAT);
   VitalWireDelay (R_ipd, R, tipd_R);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (LAT_dly, LAT_ipd, ticd_LAT);
   VitalSignalDelay (D_LAT_dly, D_ipd, tisd_D_LAT);
   VitalSignalDelay (R_LAT_dly, R_ipd, tisd_R_LAT);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (LAT_dly, D_LAT_dly, R_LAT_dly)

   -- timing check results
   VARIABLE Tviol_D_LAT_R_EQ_1_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_LAT_R_EQ_1_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_LAT_R_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_LAT_R_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_LAT_R_EQ_1_negedge,
          TimingData              => Tmkr_D_LAT_R_EQ_1_negedge,
          TestSignal              => D_LAT_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_D_LAT_noedge_negedge,
          SetupLow                => tsetup_D_LAT_noedge_negedge,
          HoldHigh                => thold_D_LAT_noedge_negedge,
          HoldLow                 => thold_D_LAT_noedge_negedge,
          CheckEnabled            => 
                           TO_X01(R_LAT_dly) = '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_LAT_negedge,
          TimingData              => Tmkr_R_LAT_negedge,
          TestSignal              => R_LAT_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          Recovery                => trecovery_R_LAT_posedge_negedge,
          Removal                 => thold_R_LAT_posedge_negedge,
          ActiveLow               => TRUE,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_LAT_R_EQ_1,
          PeriodData              => PInfo_LAT_R_EQ_1,
          TestSignal              => LAT_dly,
          TestSignalName          => "LAT",
          TestDelay               => ticd_LAT,
          Period                  => tperiod_LAT_posedge,
          PulseWidthHigh          => tpw_LAT_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01(R_LAT_dly ) = '1',
          HeaderMsg               => InstancePath & "/DLATR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_LAT_R_EQ_1_negedge or Tviol_R_LAT_negedge or Pviol_LAT_R_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => latchtab,
        DataIn => (
               D_LAT_dly, LAT_dly, R_LAT_dly,'1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_LAT_dly'last_event, tpd_D_Q, TRUE),
                 1 => (LAT_dly'last_event, tpd_LAT_Q, TRUE),
                 2 => (R_LAT_dly'last_event, tpd_R_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DLATR_VITAL of DLATR is 
        for VITAL
        end for; 
end CFG_DLATR_VITAL;
----- VITAL model for cell DLATRH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DLATRH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_LAT_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_R_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_D_LAT_noedge_negedge :	VitalDelayType := 0.1 ns;
      thold_D_LAT_noedge_negedge :	VitalDelayType := 0.0 ns;
      tpw_LAT_posedge         :	VitalDelayType := 1.000 ns;
      tperiod_LAT_posedge             :	VitalDelayType := 1.000 ns;
      trecovery_R_LAT_negedge_negedge :	VitalDelayType := 0.100 ns;
      thold_R_LAT_negedge_negedge    :	VitalDelayType := 0.000 ns;
      ticd_LAT                       :	VitalDelayType := 0.000 ns;
      tisd_D_LAT                     :	VitalDelayType := 0.000 ns;
      tisd_R_LAT                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LAT                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      LAT                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DLATRH : entity is TRUE;
end DLATRH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DLATRH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_LAT_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (LAT_ipd, LAT, tipd_LAT);
   VitalWireDelay (R_ipd, R, tipd_R);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (LAT_dly, LAT_ipd, ticd_LAT);
   VitalSignalDelay (D_LAT_dly, D_ipd, tisd_D_LAT);
   VitalSignalDelay (R_LAT_dly, R_ipd, tisd_R_LAT);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (LAT_dly, D_LAT_dly, R_LAT_dly)

   -- timing check results
   VARIABLE Tviol_D_LAT_R_EQ_0_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_LAT_R_EQ_0_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_LAT_R_EQ_0	: STD_ULOGIC := '0';
   VARIABLE PInfo_LAT_R_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE R_inverted : STD_ULOGIC := 'X';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_LAT_R_EQ_0_negedge,
          TimingData              => Tmkr_D_LAT_R_EQ_0_negedge,
          TestSignal              => D_LAT_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_D_LAT_noedge_negedge,
          SetupLow                => tsetup_D_LAT_noedge_negedge,
          HoldHigh                => thold_D_LAT_noedge_negedge,
          HoldLow                 => thold_D_LAT_noedge_negedge,
          CheckEnabled            => 
                           TO_X01((R_LAT_dly)) = '0',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_LAT_negedge,
          TimingData              => Tmkr_R_LAT_negedge,
          TestSignal              => R_LAT_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          Recovery                => trecovery_R_LAT_negedge_negedge,
          Removal                 => thold_R_LAT_negedge_negedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_LAT_R_EQ_0,
          PeriodData              => PInfo_LAT_R_EQ_0,
          TestSignal              => LAT_dly,
          TestSignalName          => "LAT",
          TestDelay               => ticd_LAT,
          Period                  => tperiod_LAT_posedge,
          PulseWidthHigh          => tpw_LAT_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01((R_LAT_dly) ) = '0',
          HeaderMsg               => InstancePath & "/DLATRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_LAT_R_EQ_0_negedge or Tviol_R_LAT_negedge or Pviol_LAT_R_EQ_0;
      R_inverted := (NOT R_LAT_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => latchtab,
        DataIn => (
               D_LAT_dly, LAT_dly,R_inverted,'1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_LAT_dly'last_event, tpd_D_Q, TRUE),
                 1 => (LAT_dly'last_event, tpd_LAT_Q, TRUE),
                 2 => (R_LAT_dly'last_event, tpd_R_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DLATRH_VITAL of DLATRH is 
        for VITAL
        end for; 
end CFG_DLATRH_VITAL;
----- VITAL model for cell DLATRS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DLATRS is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_LAT_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_R_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_S_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_D_LAT_noedge_negedge :	VitalDelayType := 0.100 ns;
      thold_D_LAT_noedge_negedge :	VitalDelayType := 0.000 ns;
      tpw_LAT_posedge :	VitalDelayType := 1.000 ns;
      tpw_R_negedge :	VitalDelayType := 1.000 ns;
      tpw_S_negedge :	VitalDelayType := 1.000 ns;
      tperiod_LAT_posedge  :	VitalDelayType := 1.000 ns;
      trecovery_R_LAT_posedge_negedge :	VitalDelayType := 0.100 ns;
      thold_R_LAT_posedge_negedge :	VitalDelayType := 0.000 ns;
      trecovery_S_LAT_posedge_negedge :	VitalDelayType := 0.100 ns;
      thold_S_LAT_posedge_negedge :	VitalDelayType := 0.000 ns;
      ticd_LAT                       :	VitalDelayType := 0.000 ns;
      tisd_D_LAT                     :	VitalDelayType := 0.000 ns;
      tisd_R_LAT                     :	VitalDelayType := 0.000 ns;
      tisd_S_LAT                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LAT                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      LAT                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DLATRS : entity is TRUE;
end DLATRS;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DLATRS is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_LAT_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (LAT_ipd, LAT, tipd_LAT);
   VitalWireDelay (R_ipd, R, tipd_R);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (LAT_dly, LAT_ipd, ticd_LAT);
   VitalSignalDelay (D_LAT_dly, D_ipd, tisd_D_LAT);
   VitalSignalDelay (R_LAT_dly, R_ipd, tisd_R_LAT);
   VitalSignalDelay (S_LAT_dly, S_ipd, tisd_S_LAT);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (LAT_dly, D_LAT_dly, R_LAT_dly, S_LAT_dly)

   -- timing check results
   VARIABLE Tviol_D_LAT_R_EQ_1_ANB_S_EQ_1_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_LAT_R_EQ_1_ANB_S_EQ_1_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_LAT_S_EQ_1_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_LAT_S_EQ_1_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_LAT_R_EQ_1_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_LAT_R_EQ_1_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_LAT_R_EQ_1_ANB_S_EQ_1	: STD_ULOGIC := '0';
   VARIABLE Pviol_R	: STD_ULOGIC := '0';
   VARIABLE Pviol_S	: STD_ULOGIC := '0';
   VARIABLE PInfo_LAT_R_EQ_1_ANB_S_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_R	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_S	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   VARIABLE D_in_zd : STD_ULOGIC := '0';
   VARIABLE NOT_S_zd : STD_ULOGIC := '0';

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_LAT_R_EQ_1_ANB_S_EQ_1_negedge,
          TimingData              => Tmkr_D_LAT_R_EQ_1_ANB_S_EQ_1_negedge,
          TestSignal              => D_LAT_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_D_LAT_noedge_negedge,
          SetupLow                => tsetup_D_LAT_noedge_negedge,
          HoldHigh                => thold_D_LAT_noedge_negedge,
          HoldLow                 => thold_D_LAT_noedge_negedge,
          CheckEnabled            => 
                           TO_X01((S_LAT_dly) AND (R_LAT_dly)) = '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_LAT_S_EQ_1_negedge,
          TimingData              => Tmkr_R_LAT_S_EQ_1_negedge,
          TestSignal              => R_LAT_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          Recovery                => trecovery_R_LAT_posedge_negedge,
          Removal                 => thold_R_LAT_posedge_negedge,
          ActiveLow               => TRUE,
          CheckEnabled            => 
                           TO_X01(S_LAT_dly) = '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_LAT_R_EQ_1_negedge,
          TimingData              => Tmkr_S_LAT_R_EQ_1_negedge,
          TestSignal              => S_LAT_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          Recovery                => trecovery_S_LAT_posedge_negedge,
          Removal                 => thold_S_LAT_posedge_negedge,
          ActiveLow               => TRUE,
          CheckEnabled            => 
                           TO_X01(R_LAT_dly) = '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_S,
          PeriodData              => PInfo_S,
          TestSignal              => S_LAT_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_LAT,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_S_negedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DLATRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_R,
          PeriodData              => PInfo_R,
          TestSignal              => R_LAT_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_LAT,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_R_negedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DLATRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_LAT_R_EQ_1_ANB_S_EQ_1,
          PeriodData              => PInfo_LAT_R_EQ_1_ANB_S_EQ_1,
          TestSignal              => LAT_dly,
          TestSignalName          => "LAT",
          TestDelay               => ticd_LAT,
          Period                  => tperiod_LAT_posedge,
          PulseWidthHigh          => tpw_LAT_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01(( S_LAT_dly ) AND ( R_LAT_dly ) ) = '1',
          HeaderMsg               => InstancePath & "/DLATRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------

        NOT_S_zd := VitalINV (S_LAT_dly);
        D_in_zd := VitalOR2 (NOT_S_zd , D_LAT_dly);

      Violation := Tviol_D_LAT_R_EQ_1_ANB_S_EQ_1_negedge or Tviol_S_LAT_R_EQ_1_negedge or Pviol_LAT_R_EQ_1_ANB_S_EQ_1 or Tviol_R_LAT_S_EQ_1_negedge;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => latchtab,
        DataIn => (
               D_LAT_dly, LAT_dly, R_LAT_dly, S_LAT_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_LAT_dly'last_event, tpd_D_Q, TRUE),
                 1 => (LAT_dly'last_event, tpd_LAT_Q, TRUE),
                 2 => (R_LAT_dly'last_event, tpd_R_Q, TRUE),
                 3 => (S_LAT_dly'last_event, tpd_S_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DLATRS_VITAL of DLATRS is 
        for VITAL
        end for; 
end CFG_DLATRS_VITAL;
----- VITAL model for cell DLATRSH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DLATRSH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_LAT_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_R_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_S_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_D_LAT_noedge_negedge :	VitalDelayType := 0.100 ns;
      thold_D_LAT_noedge_negedge :	VitalDelayType := 0.000 ns;
      tpw_LAT_posedge :	VitalDelayType := 1.000 ns;
      tpw_R_posedge :	VitalDelayType := 1.000 ns;
      tpw_S_posedge :	VitalDelayType := 1.000 ns;
      tperiod_LAT_posedge  :	VitalDelayType := 1.000 ns;
      trecovery_R_LAT_negedge_negedge :	VitalDelayType := 0.100 ns;
      thold_R_LAT_negedge_negedge     :	VitalDelayType := 0.000 ns;
      trecovery_S_LAT_negedge_negedge :	VitalDelayType := 0.100 ns;
      thold_S_LAT_negedge_negedge     :	VitalDelayType := 0.000 ns;
      ticd_LAT                       :	VitalDelayType := 0.000 ns;
      tisd_D_LAT                     :	VitalDelayType := 0.000 ns;
      tisd_R_LAT                     :	VitalDelayType := 0.000 ns;
      tisd_S_LAT                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LAT                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      LAT                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DLATRSH : entity is TRUE;
end DLATRSH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DLATRSH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_LAT_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (LAT_ipd, LAT, tipd_LAT);
   VitalWireDelay (R_ipd, R, tipd_R);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (LAT_dly, LAT_ipd, ticd_LAT);
   VitalSignalDelay (D_LAT_dly, D_ipd, tisd_D_LAT);
   VitalSignalDelay (R_LAT_dly, R_ipd, tisd_R_LAT);
   VitalSignalDelay (S_LAT_dly, S_ipd, tisd_S_LAT);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (LAT_dly, D_LAT_dly, R_LAT_dly, S_LAT_dly)

   -- timing check results
   VARIABLE Tviol_D_LAT_R_EQ_0_ANB_S_EQ_0_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_LAT_R_EQ_0_ANB_S_EQ_0_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_LAT_S_EQ_0_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_LAT_S_EQ_0_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_LAT_R_EQ_0_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_LAT_R_EQ_0_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_LAT_R_EQ_0_ANB_S_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_R : STD_ULOGIC := '0';
   VARIABLE Pviol_S : STD_ULOGIC := '0';
   VARIABLE PInfo_LAT_R_EQ_0_ANB_S_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_R	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_S	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE R_inverted : STD_ULOGIC := 'X';
   VARIABLE S_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   VARIABLE D_in_zd : STD_ULOGIC := '0';

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_LAT_R_EQ_0_ANB_S_EQ_0_negedge,
          TimingData              => Tmkr_D_LAT_R_EQ_0_ANB_S_EQ_0_negedge,
          TestSignal              => D_LAT_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_D_LAT_noedge_negedge,
          SetupLow                => tsetup_D_LAT_noedge_negedge,
          HoldHigh                => thold_D_LAT_noedge_negedge,
          HoldLow                 => thold_D_LAT_noedge_negedge,
          CheckEnabled            => 
                           TO_X01(((NOT S_LAT_dly)) AND ((NOT R_LAT_dly))) = '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_LAT_S_EQ_0_negedge,
          TimingData              => Tmkr_R_LAT_S_EQ_0_negedge,
          TestSignal              => R_LAT_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          Recovery                => trecovery_R_LAT_negedge_negedge,
          Removal                 => thold_R_LAT_negedge_negedge,
          ActiveLow               => FALSE,
          CheckEnabled            => 
                           TO_X01(S_LAT_dly) = '0',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_LAT_R_EQ_0_negedge,
          TimingData              => Tmkr_S_LAT_R_EQ_0_negedge,
          TestSignal              => S_LAT_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          Recovery                => trecovery_S_LAT_negedge_negedge,
          Removal                 => thold_S_LAT_negedge_negedge,
          ActiveLow               => FALSE,
          CheckEnabled            => 
                           TO_X01(R_LAT_dly) = '0',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_S,
          PeriodData              => PInfo_S,
          TestSignal              => S_LAT_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_LAT,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_S_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DLATRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_R,
          PeriodData              => PInfo_R,
          TestSignal              => R_LAT_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_LAT,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_R_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DLATRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_LAT_R_EQ_0_ANB_S_EQ_0,
          PeriodData              => PInfo_LAT_R_EQ_0_ANB_S_EQ_0,
          TestSignal              => LAT_dly,
          TestSignalName          => "LAT",
          TestDelay               => ticd_LAT,
          Period                  => tperiod_LAT_posedge,
          PulseWidthHigh          => tpw_LAT_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01(((NOT S_LAT_dly)) AND ((NOT R_LAT_dly))) = '1',
          HeaderMsg               => InstancePath & "/DLATRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------

        D_in_zd := VitalOR2 (S_LAT_dly , D_LAT_dly);

      Violation := Tviol_D_LAT_R_EQ_0_ANB_S_EQ_0_negedge or Tviol_R_LAT_S_EQ_0_negedge or Tviol_S_LAT_R_EQ_0_negedge or Pviol_LAT_R_EQ_0_ANB_S_EQ_0 or Pviol_R or Pviol_S;
      S_inverted := (NOT S_LAT_dly);
      R_inverted := (NOT R_LAT_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => latchtab,
        DataIn => (
               D_LAT_dly, LAT_dly, R_inverted, S_inverted));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_LAT_dly'last_event, tpd_D_Q, TRUE),
                 1 => (LAT_dly'last_event, tpd_LAT_Q, TRUE),
                 2 => (R_LAT_dly'last_event, tpd_R_Q, TRUE),
                 3 => (S_LAT_dly'last_event, tpd_S_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DLATRSH_VITAL of DLATRSH is 
        for VITAL
        end for; 
end CFG_DLATRSH_VITAL;
----- VITAL model for cell DLATS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DLATS is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_LAT_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_S_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_D_LAT_noedge_negedge :	VitalDelayType := 0.100 ns;
      thold_D_LAT_noedge_negedge :	VitalDelayType := 0.000 ns;
      tpw_LAT_posedge         :	VitalDelayType := 1.0 ns;
      tperiod_LAT_posedge             :	VitalDelayType := 1.0 ns;
      trecovery_S_LAT_posedge_negedge :	VitalDelayType := 0.1 ns;
      thold_S_LAT_posedge_negedge    :	VitalDelayType := 0.0 ns;
      ticd_LAT                       :	VitalDelayType := 0.0 ns;
      tisd_D_LAT                     :	VitalDelayType := 0.0 ns;
      tisd_S_LAT                     :	VitalDelayType := 0.0 ns;
      tipd_D                         :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_LAT                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_S                         :	VitalDelayType01 := (0.0 ns, 0.0 ns));

   port(
      D                              :	in    STD_ULOGIC;
      LAT                            :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DLATS : entity is TRUE;
end DLATS;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DLATS is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_LAT_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (LAT_ipd, LAT, tipd_LAT);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (LAT_dly, LAT_ipd, ticd_LAT);
   VitalSignalDelay (D_LAT_dly, D_ipd, tisd_D_LAT);
   VitalSignalDelay (S_LAT_dly, S_ipd, tisd_S_LAT);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (LAT_dly, D_LAT_dly, S_LAT_dly)

   -- timing check results
   VARIABLE Tviol_D_LAT_S_EQ_1_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_LAT_S_EQ_1_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_LAT_S_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_LAT_S_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_LAT_S_EQ_1_negedge,
          TimingData              => Tmkr_D_LAT_S_EQ_1_negedge,
          TestSignal              => D_LAT_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_D_LAT_noedge_negedge,
          SetupLow                => tsetup_D_LAT_noedge_negedge,
          HoldHigh                => thold_D_LAT_noedge_negedge,
          HoldLow                 => thold_D_LAT_noedge_negedge,
          CheckEnabled            => 
                           TO_X01(S_LAT_dly) = '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_LAT_negedge,
          TimingData              => Tmkr_S_LAT_negedge,
          TestSignal              => S_LAT_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          Recovery                => trecovery_S_LAT_posedge_negedge,
          Removal                 => thold_S_LAT_posedge_negedge,
          ActiveLow               => TRUE,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_LAT_S_EQ_1,
          PeriodData              => PInfo_LAT_S_EQ_1,
          TestSignal              => LAT_dly,
          TestSignalName          => "LAT",
          TestDelay               => ticd_LAT,
          Period                  => tperiod_LAT_posedge,
          PulseWidthHigh          => tpw_LAT_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01(S_LAT_dly ) = '1',
          HeaderMsg               => InstancePath & "/DLATS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_LAT_S_EQ_1_negedge or Tviol_S_LAT_negedge or Pviol_LAT_S_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => latchtab,
        DataIn => (
               D_LAT_dly, LAT_dly,'1', S_LAT_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_LAT_dly'last_event, tpd_D_Q, TRUE),
                 1 => (LAT_dly'last_event, tpd_LAT_Q, TRUE),
                 2 => (S_LAT_dly'last_event, tpd_S_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DLATS_VITAL of DLATS is 
        for VITAL
        end for; 
end CFG_DLATS_VITAL;
----- VITAL model for cell DLATSH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DLATSH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_LAT_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_S_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_D_LAT_noedge_negedge :	VitalDelayType := 0.1 ns;
      thold_D_LAT_noedge_negedge :	VitalDelayType := 0.0 ns;
      tpw_LAT_posedge         :	VitalDelayType := 1.000 ns;
      tpw_S_posedge         :	VitalDelayType := 1.000 ns;
      tperiod_LAT_posedge             :	VitalDelayType := 1.000 ns;
      trecovery_S_LAT_negedge_negedge :	VitalDelayType := 0.100 ns;
      thold_S_LAT_negedge_negedge    :	VitalDelayType := 0.000 ns;
      ticd_LAT                       :	VitalDelayType := 0.000 ns;
      tisd_D_LAT                     :	VitalDelayType := 0.000 ns;
      tisd_S_LAT                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LAT                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      LAT                            :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DLATSH : entity is TRUE;
end DLATSH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of DLATSH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_LAT_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (LAT_ipd, LAT, tipd_LAT);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (LAT_dly, LAT_ipd, ticd_LAT);
   VitalSignalDelay (D_LAT_dly, D_ipd, tisd_D_LAT);
   VitalSignalDelay (S_LAT_dly, S_ipd, tisd_S_LAT);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (LAT_dly, D_LAT_dly, S_LAT_dly)

   -- timing check results
   VARIABLE Tviol_D_LAT_S_EQ_0_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_LAT_S_EQ_0_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_LAT_S_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_S	: STD_ULOGIC := '0';
   VARIABLE PInfo_LAT_S_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_S	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE S_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_LAT_S_EQ_0_negedge,
          TimingData              => Tmkr_D_LAT_S_EQ_0_negedge,
          TestSignal              => D_LAT_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_D_LAT_noedge_negedge,
          SetupLow                => tsetup_D_LAT_noedge_negedge,
          HoldHigh                => thold_D_LAT_noedge_negedge,
          HoldLow                 => thold_D_LAT_noedge_negedge,
          CheckEnabled            => 
                           TO_X01((S_LAT_dly)) = '0',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_LAT_negedge,
          TimingData              => Tmkr_S_LAT_negedge,
          TestSignal              => S_LAT_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          Recovery                => trecovery_S_LAT_negedge_negedge,
          Removal                 => thold_S_LAT_negedge_negedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_S,
          PeriodData              => PInfo_S,
          TestSignal              => S_LAT_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_LAT,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_S_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DLATSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_LAT_S_EQ_0,
          PeriodData              => PInfo_LAT_S_EQ_0,
          TestSignal              => LAT_dly,
          TestSignalName          => "LAT",
          TestDelay               => ticd_LAT,
          Period                  => tperiod_LAT_posedge,
          PulseWidthHigh          => tpw_LAT_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01((S_LAT_dly) ) = '0',
          HeaderMsg               => InstancePath & "/DLATSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_LAT_S_EQ_0_negedge or Tviol_S_LAT_negedge or Pviol_LAT_S_EQ_0 or Pviol_S;
      S_inverted := (NOT S_LAT_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => latchtab,
        DataIn => (
               D_LAT_dly, LAT_dly, '1',S_inverted));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_LAT_dly'last_event, tpd_D_Q, TRUE),
                 1 => (LAT_dly'last_event, tpd_LAT_Q, TRUE),
                 2 => (S_LAT_dly'last_event, tpd_S_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DLATSH_VITAL of DLATSH is 
        for VITAL
        end for; 
end CFG_DLATSH_VITAL;
----- VITAL model for cell GND -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity GND is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True);

   port(
      X                              :	out   STD_ULOGIC := '0');
attribute VITAL_LEVEL0 of GND : entity is TRUE;
end GND;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of GND is
   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

	SIGNAL SUPPLY0    :   STD_ULOGIC := '0';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   --  empty
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------

Inst1 : VitalBUF (X,SUPPLY0);

end VITAL;

configuration CFG_GND_VITAL of GND is 
        for VITAL
        end for; 
end CFG_GND_VITAL;
----- VITAL model for cell GSRBUF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity GSRBUF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_SRI_O                       :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tipd_SRI                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      SRI                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of GSRBUF : entity is TRUE;
end GSRBUF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of GSRBUF is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL SRI_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (SRI_ipd, SRI, tipd_SRI);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (SRI_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(SRI_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (SRI_ipd'last_event, tpd_SRI_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_GSRBUF_VITAL of GSRBUF is 
        for VITAL
        end for; 
end CFG_GSRBUF_VITAL;

----- VITAL model for cell IBUF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity IBUF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      PULL           : string  := "Off";
      tpd_I0_O                       :	VitalDelayType01 := ( 0.00 ns, 0.00 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of IBUF : entity is TRUE;
end IBUF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of IBUF is
   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd)


   -- functionality results
   VARIABLE Results : STD_ULOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_ULOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
        if (PULL = "Off") then
           O_zd := TO_X01(I0_ipd);
        elsif (PULL = "Up") then
           CASE TO_X01Z(I0_ipd) IS
              WHEN '0'  =>  O_zd := '0';
              WHEN '1'  =>  O_zd := '1';
              WHEN 'Z'  =>  O_zd := '1';
              WHEN others => O_zd := 'X';
           END CASE;
        elsif (PULL = "Down") then
           CASE TO_X01Z(I0_ipd) IS
              WHEN '0'  =>  O_zd := '0';
              WHEN '1'  =>  O_zd := '1';
              WHEN 'Z'  =>  O_zd := '0';
              WHEN others => O_zd := 'X';
           END CASE;
        elsif (PULL = "Hold") then
           CASE TO_X01Z(I0_ipd) IS
              WHEN '0'  =>  O_zd := '0';
              WHEN '1'  =>  O_zd := '1';
              WHEN 'Z'  =>  O_zd := O_zd;
              WHEN others => O_zd := 'X';
           END CASE;
        end if;
      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_IBUF_VITAL of IBUF is 
        for VITAL
        end for; 
end CFG_IBUF_VITAL;

----- VITAL model for cell INV -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity INV is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of INV : entity is TRUE;
end INV;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of INV is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := (NOT I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_INV_VITAL of INV is 
        for VITAL
        end for; 
end CFG_INV_VITAL;

----- VITAL model for cell INVTH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity INVTH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      OUTOPEN        : string := "Off";
      tpd_OE_O                       :	VitalDelayType01z := (0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns);
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      OE                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of INVTH : entity is TRUE;
end INVTH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of INVTH is
   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, OE_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);
   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;
   VARIABLE I0_inv          : STD_ULOGIC := 'X';

   begin

      -------------------------
      --  Functionality Section
      -------------------------
       I0_inv := not I0_ipd;

       if (OE = '0') then
          O_zd := 'Z';
       elsif (OE = '1') then
         if (OUTOPEN = "Off") then
              O_zd := TO_X01(I0_inv);
         elsif (OUTOPEN = "Drain" or OUTOPEN = "Collect") then
           if (I0_inv = '0') then
              O_zd := '0';
           elsif (I0_inv = '1') then
              O_zd := 'Z';
           else
              O_zd := 'X';
           end if;
         end if;
       end if;


      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_O), TRUE),
                 1 => (I0_ipd'last_event, VitalExtendToFillDelay(tpd_I0_O), TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");

end process;
end VITAL;

configuration CFG_INVTH_VITAL of INVTH is 
        for VITAL
        end for; 
end CFG_INVTH_VITAL;

----- VITAL model for cell INVTL -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity INVTL is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      OUTOPEN        : string := "Off";
      tpd_OE_O                       :	VitalDelayType01z := (0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns);
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      OE                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of INVTL : entity is TRUE;
end INVTL;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of INVTL is
   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, OE_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;
   VARIABLE I0_inv          : STD_ULOGIC := 'X';

   begin

      -------------------------
      --  Functionality Section
      -------------------------
       I0_inv := not I0_ipd;

       if (OE = '1') then
          O_zd := 'Z';
       elsif (OE = '0') then
         if (OUTOPEN = "Off") then
              O_zd := TO_X01(I0_inv);
         elsif (OUTOPEN = "Drain" or OUTOPEN = "Collect") then
           if (I0_inv = '0') then
              O_zd := '0';
           elsif (I0_inv = '1') then
              O_zd := 'Z';
           else
              O_zd := 'X';
           end if;
         end if;
       end if;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_O), TRUE),
                 1 => (I0_ipd'last_event, VitalExtendToFillDelay(tpd_I0_O), TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");

end process;
end VITAL;

configuration CFG_INVTL_VITAL of INVTL is 
        for VITAL
        end for; 
end CFG_INVTL_VITAL;

----- VITAL model for cell NAN2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NAN2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NAN2 : entity is TRUE;
end NAN2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of NAN2 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := ((NOT I1_ipd)) OR ((NOT I0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_NAN2_VITAL of NAN2 is 
        for VITAL
        end for; 
end CFG_NAN2_VITAL;
----- VITAL model for cell NAN3 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NAN3 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I1                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I2                        :	VitalDelayType01 := (0.0 ns, 0.0 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NAN3 : entity is TRUE;
end NAN3;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of NAN3 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := ((NOT I1_ipd)) OR ((NOT I0_ipd)) OR ((NOT I2_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_NAN3_VITAL of NAN3 is 
        for VITAL
        end for; 
end CFG_NAN3_VITAL;
----- VITAL model for cell NAN4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NAN4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NAN4 : entity is TRUE;
end NAN4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of NAN4 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       ((NOT I1_ipd)) OR ((NOT I0_ipd)) OR ((NOT I2_ipd)) OR ((NOT I3_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_NAN4_VITAL of NAN4 is 
        for VITAL
        end for; 
end CFG_NAN4_VITAL;
----- VITAL model for cell NAN5 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NAN5 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NAN5 : entity is TRUE;
end NAN5;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of NAN5 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       ((NOT I1_ipd)) OR ((NOT I0_ipd)) OR ((NOT I2_ipd)) OR ((NOT I3_ipd))
         OR ((NOT I4_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_NAN5_VITAL of NAN5 is 
        for VITAL
        end for; 
end CFG_NAN5_VITAL;
----- VITAL model for cell NAN6 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NAN6 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I5_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      I5                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NAN6 : entity is TRUE;
end NAN6;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
 
library LC5KMX;
architecture VITAL of NAN6 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I5_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   VitalWireDelay (I5_ipd, I5, tipd_I5);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd, I5_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       ((NOT I1_ipd)) OR ((NOT I0_ipd)) OR ((NOT I2_ipd)) OR ((NOT I3_ipd))
         OR ((NOT I4_ipd)) OR ((NOT I5_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE),
                 5 => (I5_ipd'last_event, tpd_I5_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;
 
configuration CFG_NAN6_VITAL of NAN6 is 
        for VITAL
        end for; 
end CFG_NAN6_VITAL;
----- VITAL model for cell NAN7 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NAN7 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I5_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I6_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      I5                             :	in    STD_ULOGIC;
      I6                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NAN7 : entity is TRUE;
end NAN7;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
 
library LC5KMX;
architecture VITAL of NAN7 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I5_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I6_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   VitalWireDelay (I5_ipd, I5, tipd_I5);
   VitalWireDelay (I6_ipd, I6, tipd_I6);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd, I5_ipd, I6_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       ((NOT I1_ipd)) OR ((NOT I0_ipd)) OR ((NOT I2_ipd)) OR ((NOT I3_ipd))
         OR ((NOT I4_ipd)) OR ((NOT I5_ipd)) OR ((NOT I6_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE),
                 5 => (I5_ipd'last_event, tpd_I5_O, TRUE),
                 6 => (I6_ipd'last_event, tpd_I6_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;
 
configuration CFG_NAN7_VITAL of NAN7 is 
        for VITAL
        end for; 
end CFG_NAN7_VITAL;
----- VITAL model for cell NAN8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NAN8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I5_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I6_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I7_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      I5                             :	in    STD_ULOGIC;
      I6                             :	in    STD_ULOGIC;
      I7                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NAN8 : entity is TRUE;
end NAN8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
 
library LC5KMX;
architecture VITAL of NAN8 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I5_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I6_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I7_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   VitalWireDelay (I5_ipd, I5, tipd_I5);
   VitalWireDelay (I6_ipd, I6, tipd_I6);
   VitalWireDelay (I7_ipd, I7, tipd_I7);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd, I5_ipd, I6_ipd, I7_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       ((NOT I1_ipd)) OR ((NOT I0_ipd)) OR ((NOT I2_ipd)) OR ((NOT I3_ipd))
         OR ((NOT I4_ipd)) OR ((NOT I5_ipd)) OR ((NOT I6_ipd)) OR ((NOT
         I7_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE),
                 5 => (I5_ipd'last_event, tpd_I5_O, TRUE),
                 6 => (I6_ipd'last_event, tpd_I6_O, TRUE),
                 7 => (I7_ipd'last_event, tpd_I7_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;
 
configuration CFG_NAN8_VITAL of NAN8 is 
        for VITAL
        end for; 
end CFG_NAN8_VITAL;

----- VITAL model for cell NOR2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NOR2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I1                        :	VitalDelayType01 := (0.0 ns, 0.0 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NOR2 : entity is TRUE;
end NOR2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of NOR2 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := ((NOT I1_ipd)) AND ((NOT I0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_NOR2_VITAL of NOR2 is 
        for VITAL
        end for; 
end CFG_NOR2_VITAL;
----- VITAL model for cell NOR3 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NOR3 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NOR3 : entity is TRUE;
end NOR3;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of NOR3 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := ((NOT I1_ipd)) AND ((NOT I0_ipd)) AND ((NOT I2_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_NOR3_VITAL of NOR3 is 
        for VITAL
        end for; 
end CFG_NOR3_VITAL;
----- VITAL model for cell NOR4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NOR4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NOR4 : entity is TRUE;
end NOR4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of NOR4 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       ((NOT I1_ipd)) AND ((NOT I0_ipd)) AND ((NOT I2_ipd)) AND ((NOT
         I3_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_NOR4_VITAL of NOR4 is 
        for VITAL
        end for; 
end CFG_NOR4_VITAL;
----- VITAL model for cell NOR5 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NOR5 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NOR5 : entity is TRUE;
end NOR5;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
 
library LC5KMX;
architecture VITAL of NOR5 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       ((NOT I1_ipd)) AND ((NOT I0_ipd)) AND ((NOT I2_ipd)) AND ((NOT
         I3_ipd)) AND ((NOT I4_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;
 
configuration CFG_NOR5_VITAL of NOR5 is 
        for VITAL
        end for; 
end CFG_NOR5_VITAL;
----- VITAL model for cell NOR6 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NOR6 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I5_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      I5                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NOR6 : entity is TRUE;
end NOR6;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
 
library LC5KMX;
architecture VITAL of NOR6 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I5_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   VitalWireDelay (I5_ipd, I5, tipd_I5);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd, I5_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       ((NOT I1_ipd)) AND ((NOT I0_ipd)) AND ((NOT I2_ipd)) AND ((NOT
         I3_ipd)) AND ((NOT I4_ipd)) AND ((NOT I5_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE),
                 5 => (I5_ipd'last_event, tpd_I5_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;
 
configuration CFG_NOR6_VITAL of NOR6 is 
        for VITAL
        end for; 
end CFG_NOR6_VITAL;
----- VITAL model for cell NOR7 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NOR7 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I5_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I6_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      I5                             :	in    STD_ULOGIC;
      I6                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NOR7 : entity is TRUE;
end NOR7;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
 
library LC5KMX;
architecture VITAL of NOR7 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I5_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I6_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   VitalWireDelay (I5_ipd, I5, tipd_I5);
   VitalWireDelay (I6_ipd, I6, tipd_I6);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd, I5_ipd, I6_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       ((NOT I1_ipd)) AND ((NOT I0_ipd)) AND ((NOT I2_ipd)) AND ((NOT
         I3_ipd)) AND ((NOT I4_ipd)) AND ((NOT I5_ipd)) AND ((NOT I6_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE),
                 5 => (I5_ipd'last_event, tpd_I5_O, TRUE),
                 6 => (I6_ipd'last_event, tpd_I6_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;
 
configuration CFG_NOR7_VITAL of NOR7 is 
        for VITAL
        end for; 
end CFG_NOR7_VITAL;
----- VITAL model for cell NOR8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NOR8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I5_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I6_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I7_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      I5                             :	in    STD_ULOGIC;
      I6                             :	in    STD_ULOGIC;
      I7                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NOR8 : entity is TRUE;
end NOR8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
 
library LC5KMX;
architecture VITAL of NOR8 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I5_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I6_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I7_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   VitalWireDelay (I5_ipd, I5, tipd_I5);
   VitalWireDelay (I6_ipd, I6, tipd_I6);
   VitalWireDelay (I7_ipd, I7, tipd_I7);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd, I5_ipd, I6_ipd, I7_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       ((NOT I1_ipd)) AND ((NOT I0_ipd)) AND ((NOT I2_ipd)) AND ((NOT
         I3_ipd)) AND ((NOT I4_ipd)) AND ((NOT I5_ipd)) AND ((NOT I6_ipd))
         AND ((NOT I7_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE),
                 5 => (I5_ipd'last_event, tpd_I5_O, TRUE),
                 6 => (I6_ipd'last_event, tpd_I6_O, TRUE),
                 7 => (I7_ipd'last_event, tpd_I7_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;
 
configuration CFG_NOR8_VITAL of NOR8 is 
        for VITAL
        end for; 
end CFG_NOR8_VITAL;

----- VITAL model for cell OBUF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity OBUF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      OUTOPEN          : string  := "Off";
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of OBUF : entity is TRUE;
end OBUF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of OBUF is
   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
       if (OUTOPEN = "Off") then
              O_zd := TO_X01(I0_ipd);
       elsif (OUTOPEN = "Drain" or OUTOPEN = "Collect") then
           if (I0_ipd = '0') then
              O_zd := '0';
           elsif (I0_ipd = '1') then
              O_zd := 'Z';
           else
              O_zd := 'X';
           end if;
       end if;
          

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_OBUF_VITAL of OBUF is 
        for VITAL
        end for; 
end CFG_OBUF_VITAL;

----- VITAL model for cell OR2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity OR2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of OR2 : entity is TRUE;
end OR2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of OR2 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := (I1_ipd) OR (I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_OR2_VITAL of OR2 is 
        for VITAL
        end for; 
end CFG_OR2_VITAL;
----- VITAL model for cell OR3 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity OR3 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of OR3 : entity is TRUE;
end OR3;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of OR3 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := (I1_ipd) OR (I0_ipd) OR (I2_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_OR3_VITAL of OR3 is 
        for VITAL
        end for; 
end CFG_OR3_VITAL;
----- VITAL model for cell OR4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity OR4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of OR4 : entity is TRUE;
end OR4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of OR4 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := (I1_ipd) OR (I0_ipd) OR (I2_ipd) OR (I3_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_OR4_VITAL of OR4 is 
        for VITAL
        end for; 
end CFG_OR4_VITAL;
----- VITAL model for cell OR5 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity OR5 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of OR5 : entity is TRUE;
end OR5;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
 
library LC5KMX;
architecture VITAL of OR5 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := (I1_ipd) OR (I0_ipd) OR (I2_ipd) OR (I3_ipd) OR (I4_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;
 
configuration CFG_OR5_VITAL of OR5 is 
        for VITAL
        end for; 
end CFG_OR5_VITAL;
----- VITAL model for cell OR6 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity OR6 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I5_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      I5                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of OR6 : entity is TRUE;
end OR6;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
 
library LC5KMX;
architecture VITAL of OR6 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I5_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   VitalWireDelay (I5_ipd, I5, tipd_I5);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd, I5_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       (I1_ipd) OR (I0_ipd) OR (I2_ipd) OR (I3_ipd) OR (I4_ipd) OR (I5_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE),
                 5 => (I5_ipd'last_event, tpd_I5_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;
 
configuration CFG_OR6_VITAL of OR6 is 
        for VITAL
        end for; 
end CFG_OR6_VITAL;
----- VITAL model for cell OR7 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity OR7 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I5_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I6_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      I5                             :	in    STD_ULOGIC;
      I6                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of OR7 : entity is TRUE;
end OR7;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
 
library LC5KMX;
architecture VITAL of OR7 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I5_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I6_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   VitalWireDelay (I5_ipd, I5, tipd_I5);
   VitalWireDelay (I6_ipd, I6, tipd_I6);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd, I5_ipd, I6_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       (I1_ipd) OR (I0_ipd) OR (I2_ipd) OR (I3_ipd) OR (I4_ipd) OR (I5_ipd)
         OR (I6_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE),
                 5 => (I5_ipd'last_event, tpd_I5_O, TRUE),
                 6 => (I6_ipd'last_event, tpd_I6_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;
 
configuration CFG_OR7_VITAL of OR7 is 
        for VITAL
        end for; 
end CFG_OR7_VITAL;
----- VITAL model for cell OR8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity OR8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I5_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I6_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I7_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      I5                             :	in    STD_ULOGIC;
      I6                             :	in    STD_ULOGIC;
      I7                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of OR8 : entity is TRUE;
end OR8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
 
library LC5KMX;
architecture VITAL of OR8 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I5_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I6_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I7_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   VitalWireDelay (I5_ipd, I5, tipd_I5);
   VitalWireDelay (I6_ipd, I6, tipd_I6);
   VitalWireDelay (I7_ipd, I7, tipd_I7);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd, I5_ipd, I6_ipd, I7_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       (I1_ipd) OR (I0_ipd) OR (I2_ipd) OR (I3_ipd) OR (I4_ipd) OR (I5_ipd)
         OR (I6_ipd) OR (I7_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE),
                 5 => (I5_ipd'last_event, tpd_I5_O, TRUE),
                 6 => (I6_ipd'last_event, tpd_I6_O, TRUE),
                 7 => (I7_ipd'last_event, tpd_I7_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;
 
configuration CFG_OR8_VITAL of OR8 is 
        for VITAL
        end for; 
end CFG_OR8_VITAL;

----- VITAL model for cell TFF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity TFF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_CLK_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_T_CLK_noedge_posedge    :	VitalDelayType := 0.1 ns;
      thold_T_CLK_noedge_posedge     :	VitalDelayType := 0.0 ns;
      tperiod_CLK_posedge            :	VitalDelayType := 1.0 ns;
      tpw_CLK_posedge                :	VitalDelayType := 1.0 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_T_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_T                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      T                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of TFF : entity is TRUE;
end TFF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of TFF is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL T_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL T_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (T_ipd, T, tipd_T);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (T_CLK_dly, T_ipd, tisd_T_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, T_CLK_dly)

   -- timing check results
   VARIABLE Tviol_T_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_T_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => '0');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_T_CLK_posedge,
          TimingData              => Tmkr_T_CLK_posedge,
          TestSignal              => T_CLK_dly,
          TestSignalName          => "T",
          TestDelay               => tisd_T_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_T_CLK_noedge_posedge,
          SetupLow                => tsetup_T_CLK_noedge_posedge,
          HoldHigh                => thold_T_CLK_noedge_posedge,
          HoldLow                 => thold_T_CLK_noedge_posedge,
          CheckEnabled            => 
                           TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TFF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TRUE,
          HeaderMsg               => InstancePath &"/TFF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_T_CLK_posedge or Pviol_CLK;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => tfftab,
        DataIn => (
               CLK_dly, T_CLK_dly, '1', '1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_TFF_VITAL of TFF is 
        for VITAL
        end for; 
end CFG_TFF_VITAL;
----- VITAL model for cell TFFR -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity TFFR is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_R_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_T_CLK_noedge_posedge :	VitalDelayType := 0.1 ns;
      thold_T_CLK_noedge_posedge :	VitalDelayType := 0.0 ns;
      trecovery_R_CLK_posedge_posedge :	VitalDelayType := 0.1 ns;
      thold_R_CLK_posedge_posedge    :	VitalDelayType := 0.0 ns;
      tpw_CLK_posedge         :	VitalDelayType := 1.0 ns;
      tperiod_CLK_posedge             :	VitalDelayType := 1.0 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_T_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_T                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      T                              :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of TFFR : entity is TRUE;
end TFFR;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of TFFR is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL T_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL T_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (T_ipd, T, tipd_T);
   VitalWireDelay (R_ipd, R, tipd_R);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (T_CLK_dly, T_ipd, tisd_T_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, T_CLK_dly, R_CLK_dly)

   -- timing check results
   VARIABLE Tviol_T_CLK_R_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_T_CLK_R_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_R_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_R_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_T_CLK_R_EQ_1_posedge,
          TimingData              => Tmkr_T_CLK_R_EQ_1_posedge,
          TestSignal              => T_CLK_dly,
          TestSignalName          => "T",
          TestDelay               => tisd_T_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_T_CLK_noedge_posedge,
          SetupLow                => tsetup_T_CLK_noedge_posedge,
          HoldHigh                => thold_T_CLK_noedge_posedge,
          HoldLow                 => thold_T_CLK_noedge_posedge,
          CheckEnabled            => 
                           TO_X01(R_CLK_dly) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TFFR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_posedge,
          TimingData              => Tmkr_R_CLK_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_posedge_posedge,
          Removal                 => thold_R_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TFFR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_R_EQ_1,
          PeriodData              => PInfo_CLK_R_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01((R_CLK_dly) ) = '1',
          HeaderMsg               => InstancePath & "/TFFR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_T_CLK_R_EQ_1_posedge or Pviol_CLK_R_EQ_1 or Tviol_R_CLK_posedge;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => tfftab,
        DataIn => (
               CLK_dly, T_CLK_dly, '1', R_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_TFFR_VITAL of TFFR is 
        for VITAL
        end for; 
end CFG_TFFR_VITAL;
----- VITAL model for cell TFFRH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity TFFRH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_R_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_T_CLK_noedge_posedge :	VitalDelayType := 0.1 ns;
      thold_T_CLK_noedge_posedge :	VitalDelayType := 0.0 ns;
      trecovery_R_CLK_negedge_posedge :	VitalDelayType := 0.1 ns;
      thold_R_CLK_negedge_posedge    :	VitalDelayType := 0.0 ns;
      tpw_CLK_posedge         :	VitalDelayType := 1.0 ns;
      tpw_R_posedge         :	VitalDelayType := 1.0 ns;
      tperiod_CLK_posedge             :	VitalDelayType := 1.0 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_T_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_T                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      T                              :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of TFFRH : entity is TRUE;
end TFFRH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of TFFRH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL T_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL T_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (T_ipd, T, tipd_T);
   VitalWireDelay (R_ipd, R, tipd_R);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (T_CLK_dly, T_ipd, tisd_T_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, T_CLK_dly, R_CLK_dly)

   -- timing check results
   VARIABLE Tviol_T_CLK_R_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_T_CLK_R_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_R_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_R	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_R_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_R	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE R_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_T_CLK_R_EQ_0_posedge,
          TimingData              => Tmkr_T_CLK_R_EQ_0_posedge,
          TestSignal              => T_CLK_dly,
          TestSignalName          => "T",
          TestDelay               => tisd_T_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_T_CLK_noedge_posedge,
          SetupLow                => tsetup_T_CLK_noedge_posedge,
          HoldHigh                => thold_T_CLK_noedge_posedge,
          HoldLow                 => thold_T_CLK_noedge_posedge,
          CheckEnabled            => 
                           TO_X01((R_CLK_dly)) = '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TFFRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_posedge,
          TimingData              => Tmkr_R_CLK_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_negedge_posedge,
          Removal                 => thold_R_CLK_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TFFRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_R,
          PeriodData              => PInfo_R,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_R_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/TFFRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_R_EQ_0,
          PeriodData              => PInfo_CLK_R_EQ_0,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01(R_CLK_dly ) = '0',
          HeaderMsg               => InstancePath & "/TFFRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_T_CLK_R_EQ_0_posedge or Tviol_R_CLK_posedge or Pviol_CLK_R_EQ_0;
      R_inverted := (NOT R_CLK_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => tfftab,
        DataIn => (
               CLK_dly, T_CLK_dly, '1', R_inverted));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_TFFRH_VITAL of TFFRH is 
        for VITAL
        end for; 
end CFG_TFFRH_VITAL;
----- VITAL model for cell TFFRS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;


-- entity declaration --
entity TFFRS is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_S_Q             :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_R_Q             :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_Q           :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_T_CLK_noedge_posedge :	VitalDelayType := 0.1 ns;
      thold_T_CLK_noedge_posedge :	VitalDelayType := 0.0 ns;
      trecovery_R_CLK_posedge_posedge :	VitalDelayType := 0.1 ns;
      thold_R_CLK_posedge_posedge :	VitalDelayType := 0.0 ns;
      trecovery_S_CLK_posedge_posedge :	VitalDelayType := 0.1 ns;
      thold_S_CLK_posedge_posedge :	VitalDelayType := 0.0 ns;
      tpw_CLK_posedge :	VitalDelayType := 1.0 ns;
      tpw_R_negedge :	VitalDelayType := 1.0 ns;
      tpw_S_negedge :	VitalDelayType := 1.0 ns;
      tperiod_CLK_posedge   :	VitalDelayType := 1.0 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_T_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_T                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      T                              :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of TFFRS : entity is TRUE;
end TFFRS;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of TFFRS is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL T_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL T_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (T_ipd, T, tipd_T);
   VitalWireDelay (R_ipd, R, tipd_R);
   VitalWireDelay (S_ipd, S, tipd_S);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (T_CLK_dly, T_ipd, tisd_T_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, T_CLK_dly, R_CLK_dly, S_CLK_dly)

   -- timing check results
   VARIABLE Tviol_T_CLK_R_EQ_1_AN_S_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_T_CLK_R_EQ_1_AN_S_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_S_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_S_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_R_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_R_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_R_EQ_1_AN_S_EQ_1	: STD_ULOGIC := '0';
   VARIABLE Pviol_R	: STD_ULOGIC := '0';
   VARIABLE Pviol_S	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_R_EQ_1_AN_S_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_R	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_S	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE T_delayed : STD_ULOGIC := 'X';
   VARIABLE CLK_delayed : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_T_CLK_R_EQ_1_AN_S_EQ_1_posedge,
          TimingData              => Tmkr_T_CLK_R_EQ_1_AN_S_EQ_1_posedge,
          TestSignal              => T_CLK_dly,
          TestSignalName          => "T",
          TestDelay               => tisd_T_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_T_CLK_noedge_posedge,
          SetupLow                => tsetup_T_CLK_noedge_posedge,
          HoldHigh                => thold_T_CLK_noedge_posedge,
          HoldLow                 => thold_T_CLK_noedge_posedge,
          CheckEnabled            => 
                           TO_X01((S_CLK_dly) AND (R_CLK_dly)) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TFFRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_S_EQ_1_posedge,
          TimingData              => Tmkr_R_CLK_S_EQ_1_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_posedge_posedge,
          Removal                 => thold_R_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => 
                           TO_X01(S_CLK_dly) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TFFRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_R_EQ_1_posedge,
          TimingData              => Tmkr_S_CLK_R_EQ_1_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_posedge_posedge,
          Removal                 => thold_S_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => 
                           TO_X01(R_CLK_dly) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TFFRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_S,
          PeriodData              => PInfo_S,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_S_negedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/TFFRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_R,
          PeriodData              => PInfo_R,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_R_negedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/TFFRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_R_EQ_1_AN_S_EQ_1,
          PeriodData              => PInfo_CLK_R_EQ_1_AN_S_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01(( (NOT S_CLK_dly) ) OR ( (NOT R_CLK_dly) )
                            ) /= '1',
          HeaderMsg               => InstancePath & "/TFFRS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_T_CLK_R_EQ_1_AN_S_EQ_1_posedge or Tviol_R_CLK_S_EQ_1_posedge or Tviol_S_CLK_R_EQ_1_posedge or Pviol_CLK_R_EQ_1_AN_S_EQ_1 or Pviol_R or Pviol_s;
      T_delayed := T_CLK_dly;
      CLK_delayed := CLK_dly;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => tfftab,
        DataIn => (
               CLK_dly, T_CLK_dly,S_CLK_dly, R_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 1 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 2 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_TFFRS_VITAL of TFFRS is 
        for VITAL
        end for; 
end CFG_TFFRS_VITAL;
----- VITAL model for cell TFFRSH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;

-- entity declaration --
entity TFFRSH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_S_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_R_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_T_CLK_noedge_posedge :	VitalDelayType := 0.1 ns;
      thold_T_CLK_noedge_posedge :	VitalDelayType := 0.0 ns;
      trecovery_R_CLK_negedge_posedge :	VitalDelayType := 0.1 ns;
      thold_R_CLK_negedge_posedge :	VitalDelayType := 0.0 ns;
      trecovery_S_CLK_negedge_posedge :	VitalDelayType := 0.1 ns;
      thold_S_CLK_negedge_posedge :	VitalDelayType := 0.0 ns;
      tpw_CLK_posedge :	VitalDelayType := 1.0 ns;
      tpw_R_posedge :	VitalDelayType := 1.0 ns;
      tpw_S_posedge :	VitalDelayType := 1.0 ns;
      tperiod_CLK_posedge   :	VitalDelayType := 1.0 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_T_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_T                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      T                              :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of TFFRSH : entity is TRUE;
end TFFRSH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of TFFRSH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL T_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL T_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (T_ipd, T, tipd_T);
   VitalWireDelay (R_ipd, R, tipd_R);
   VitalWireDelay (S_ipd, S, tipd_S);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (T_CLK_dly, T_ipd, tisd_T_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, T_CLK_dly, R_CLK_dly, S_CLK_dly)

   -- timing check results
   VARIABLE Tviol_T_CLK_R_EQ_0_AN_S_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_T_CLK_R_EQ_0_AN_S_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_S_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_S_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_R_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_R_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_R_EQ_0_AN_S_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_R	: STD_ULOGIC := '0';
   VARIABLE Pviol_S	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_R_EQ_0_AN_S_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_R	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_S	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE T_delayed : STD_ULOGIC := 'X';
   VARIABLE CLK_delayed : STD_ULOGIC := 'X';
   VARIABLE S_inverted : STD_ULOGIC := 'X';
   VARIABLE R_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_T_CLK_R_EQ_0_AN_S_EQ_0_posedge,
          TimingData              => Tmkr_T_CLK_R_EQ_0_AN_S_EQ_0_posedge,
          TestSignal              => T_CLK_dly,
          TestSignalName          => "T",
          TestDelay               => tisd_T_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_T_CLK_noedge_posedge,
          SetupLow                => tsetup_T_CLK_noedge_posedge,
          HoldHigh                => thold_T_CLK_noedge_posedge,
          HoldLow                 => thold_T_CLK_noedge_posedge,
          CheckEnabled            => 
                           TO_X01(((NOT S_CLK_dly)) AND ((NOT R_CLK_dly))) /=
                            '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TFFRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_S_EQ_0_posedge,
          TimingData              => Tmkr_R_CLK_S_EQ_0_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_negedge_posedge,
          Removal                 => thold_R_CLK_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => 
                           TO_X01((NOT S_CLK_dly)) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TFFRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_R_EQ_0_posedge,
          TimingData              => Tmkr_S_CLK_R_EQ_0_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_negedge_posedge,
          Removal                 => thold_S_CLK_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => 
                           TO_X01((NOT R_CLK_dly)) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TFFRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_S,
          PeriodData              => PInfo_S,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_S_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/TFFRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_R,
          PeriodData              => PInfo_R,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_R_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/TFFRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_R_EQ_0_AN_S_EQ_0,
          PeriodData              => PInfo_CLK_R_EQ_0_AN_S_EQ_0,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01(( S_CLK_dly ) OR ( R_CLK_dly ) ) /= '1',
          HeaderMsg               => InstancePath & "/TFFRSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_T_CLK_R_EQ_0_AN_S_EQ_0_posedge or Tviol_S_CLK_R_EQ_0_posedge or Pviol_CLK_R_EQ_0_AN_S_EQ_0 or Tviol_R_CLK_S_EQ_0_posedge or Pviol_R or Pviol_S;
      T_delayed := T_CLK_dly;
      CLK_delayed := CLK_dly;
      S_inverted := NOT S_CLK_dly;
      R_inverted := NOT R_CLK_dly;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => tfftab,
        DataIn => (
               CLK_dly, T_CLK_dly,S_inverted, R_inverted));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 1 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 2 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_TFFRSH_VITAL of TFFRSH is 
        for VITAL
        end for; 
end CFG_TFFRSH_VITAL;
----- VITAL model for cell TFFS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity TFFS is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_S_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_T_CLK_noedge_posedge :	VitalDelayType := 0.1 ns;
      thold_T_CLK_noedge_posedge :	VitalDelayType := 0.0 ns;
      trecovery_S_CLK_posedge_posedge :	VitalDelayType := 0.1 ns;
      thold_S_CLK_posedge_posedge    :	VitalDelayType := 0.0 ns;
      tpw_CLK_posedge         :	VitalDelayType := 1.0 ns;
      tperiod_CLK_posedge             :	VitalDelayType := 1.0 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_T_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_T                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      T                              :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of TFFS : entity is TRUE;
end TFFS;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of TFFS is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL T_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL T_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (T_ipd, T, tipd_T);
   VitalWireDelay (S_ipd, S, tipd_S);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (T_CLK_dly, T_ipd, tisd_T_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, T_CLK_dly, S_CLK_dly)

   -- timing check results
   VARIABLE Tviol_T_CLK_S_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_T_CLK_S_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_S_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_S_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_T_CLK_S_EQ_1_posedge,
          TimingData              => Tmkr_T_CLK_S_EQ_1_posedge,
          TestSignal              => T_CLK_dly,
          TestSignalName          => "T",
          TestDelay               => tisd_T_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_T_CLK_noedge_posedge,
          SetupLow                => tsetup_T_CLK_noedge_posedge,
          HoldHigh                => thold_T_CLK_noedge_posedge,
          HoldLow                 => thold_T_CLK_noedge_posedge,
          CheckEnabled            => 
                           TO_X01(S_CLK_dly) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TFFS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_posedge,
          TimingData              => Tmkr_S_CLK_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_posedge_posedge,
          Removal                 => thold_S_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TFFS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_S_EQ_1,
          PeriodData              => PInfo_CLK_S_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01((S_CLK_dly) ) = '1',
          HeaderMsg               => InstancePath & "/TFFS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_T_CLK_S_EQ_1_posedge or Tviol_S_CLK_posedge or Pviol_CLK_S_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => tfftab,
        DataIn => (
               CLK_dly, T_CLK_dly, S_CLK_dly, '1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_TFFS_VITAL of TFFS is 
        for VITAL
        end for; 
end CFG_TFFS_VITAL;
----- VITAL model for cell TFFSH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity TFFSH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_S_Q                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_T_CLK_noedge_posedge :	VitalDelayType := 0.1 ns;
      thold_T_CLK_noedge_posedge :	VitalDelayType := 0.0 ns;
      trecovery_S_CLK_negedge_posedge :	VitalDelayType := 0.1 ns;
      thold_S_CLK_negedge_posedge    :	VitalDelayType := 0.0 ns;
      tpw_CLK_posedge         :	VitalDelayType := 1.0 ns;
      tpw_S_posedge         :	VitalDelayType := 1.0 ns;
      tperiod_CLK_posedge             :	VitalDelayType := 1.0 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_T_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_T                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      T                              :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of TFFSH : entity is TRUE;
end TFFSH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of TFFSH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL T_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL T_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (T_ipd, T, tipd_T);
   VitalWireDelay (S_ipd, S, tipd_S);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (T_CLK_dly, T_ipd, tisd_T_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, T_CLK_dly, S_CLK_dly)

   -- timing check results
   VARIABLE Tviol_T_CLK_S_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_T_CLK_S_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_S_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_S	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_S_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_S	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE S_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_T_CLK_S_EQ_0_posedge,
          TimingData              => Tmkr_T_CLK_S_EQ_0_posedge,
          TestSignal              => T_CLK_dly,
          TestSignalName          => "T",
          TestDelay               => tisd_T_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_T_CLK_noedge_posedge,
          SetupLow                => tsetup_T_CLK_noedge_posedge,
          HoldHigh                => thold_T_CLK_noedge_posedge,
          HoldLow                 => thold_T_CLK_noedge_posedge,
          CheckEnabled            => 
                           TO_X01((S_CLK_dly)) = '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TFFSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_posedge,
          TimingData              => Tmkr_S_CLK_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_negedge_posedge,
          Removal                 => thold_S_CLK_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TFFSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_S,
          PeriodData              => PInfo_S,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_S_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/TFFSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_S_EQ_0,
          PeriodData              => PInfo_CLK_S_EQ_0,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => 
                           TO_X01(S_CLK_dly ) = '0',
          HeaderMsg               => InstancePath & "/TFFSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_T_CLK_S_EQ_0_posedge or Tviol_S_CLK_posedge or Pviol_CLK_S_EQ_0 or Pviol_S;
      S_inverted := (NOT S_CLK_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => tfftab,
        DataIn => (
               CLK_dly, T_CLK_dly, S_inverted, '1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_TFFSH_VITAL of TFFSH is 
        for VITAL
        end for; 
end CFG_TFFSH_VITAL;
----- VITAL model for cell VCC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity VCC is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True);

   port(
      X                              :	out   STD_ULOGIC := '1');
attribute VITAL_LEVEL0 of VCC : entity is TRUE;
end VCC;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of VCC is
   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;
   
   SIGNAL SUPPLY1  : STD_ULOGIC := '1'; 

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   --  empty
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------

Inst1: VitalBUF (X,SUPPLY1);

end VITAL;

configuration CFG_VCC_VITAL of VCC is 
        for VITAL
        end for; 
end CFG_VCC_VITAL;

----- VITAL model for cell XOR2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity XOR2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of XOR2 : entity is TRUE;

   -- real names
   -- REAL_NAME of XOR2 is "XOR2"
end XOR2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of XOR2 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       (((NOT I0_ipd)) AND (I1_ipd)) OR (((NOT I1_ipd)) AND (I0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_XOR2_VITAL of XOR2 is 
        for VITAL
        end for; 
end CFG_XOR2_VITAL;

----- VITAL model for cell XORSOFT -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity XORSOFT is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of XORSOFT : entity is TRUE;
end XORSOFT;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of XORSOFT is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       (((NOT I0_ipd)) AND (I1_ipd)) OR (((NOT I1_ipd)) AND (I0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_XORSOFT_VITAL of XORSOFT is 
        for VITAL
        end for; 
end CFG_XORSOFT_VITAL;



library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity SPLL is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      IN_FREQ: STRING := "100.0";
      CLK_OUT_TO_PIN: STRING := "OFF";
      WAKE_ON_LOCK: STRING := "OFF";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_CLK_IN_CLK_OUT             :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tipd_CLK_IN                    :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CLK_IN                         :	in    STD_ULOGIC;
      CLK_OUT                        :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of SPLL : entity is FALSE;
end SPLL;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
architecture VITAL of SPLL is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL CLK_IN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CLK_IN_ipd, CLK_IN, tipd_CLK_IN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_IN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(CLK_IN_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => CLK_OUT,
       GlitchData => O_GlitchData,
       OutSignalName => "CLK_OUT",
       OutTemp => O_zd,
       Paths => (0 => (CLK_IN_ipd'last_event, tpd_CLK_IN_CLK_OUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_SPLL_VITAL of SPLL is 
        for VITAL
        end for; 
end CFG_SPLL_VITAL;

----- VITAL model for cell STDPLL -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library LC5KMX;
use LC5KMX.components.all;

-- entity declaration --
entity STDPLL is
   generic(
      IN_FREQ  : string  := "100.0";
      CLK_OUT_TO_PIN: STRING := "OFF";
      WAKE_ON_LOCK: STRING := "OFF";
      MULT     : string  := "1";
      DIV      : string  := "1";
      POST     : string  := "1";
      SECDIV   : string  := "2";
      lock_cyc : integer := 2;
      PLL_DLY  : string  := "0.0";
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_CLK_IN_CLK_OUT             :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tpd_CLK_IN_PLL_LOCK             :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tipd_CLK_IN             :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      CLK_IN                         :	in    STD_ULOGIC;
      CLK_OUT                        :	out   STD_ULOGIC;
      PLL_LOCK                       :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of STDPLL : entity is FALSE;
end STDPLL;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
use LC5KMX.components.all;
architecture VITAL of STDPLL is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL CLK_IN_ipd	 : STD_ULOGIC := 'X';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL clklock_half_period1 : TIME :=100 ns;
  SIGNAL clklock_half_period0 : TIME :=100 ns;
  SIGNAL clklock_half_period_minus_dly1 : TIME :=100 ns;
  SIGNAL clklock_half_period_minus_dly0 : TIME :=100 ns;
  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_falling_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;

  SIGNAL clock_count : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;
  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_start  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_sig1 : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';
  CONSTANT clockboost: integer := str2int(mult) / str2int(div);
  CONSTANT tpd: time := 1.0 ns * str2real(pll_dly);

BEGIN

   WireDelay : block
   begin
   VitalWireDelay (CLK_IN_ipd, CLK_IN, tipd_CLK_IN);
   end block;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN
     clklock_half_period <= (clklock_half_period0 + clklock_half_period1)/2;

  WAIT UNTIL (CLK_IN_ipd'EVENT AND CLK_IN_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     IF clklock_rising_edge_count = 0 THEN
        clklock_last_rising_edge <= NOW;	
	start_inclk <= CLK_IN_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
       clklock_half_period0 <= (NOW - clklock_last_falling_edge)* real(str2int(div))/real(str2int(mult));
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
       clklock_half_period_minus_dly0 <= (NOW - clklock_last_falling_edge) + tpd;
     END IF;
     END IF;
 
  WAIT UNTIL (CLK_IN_ipd'EVENT AND CLK_IN_ipd='0');
     clklock_falling_edge_count <= clklock_falling_edge_count +1;	  	
     IF clklock_falling_edge_count = 0 THEN	
	clklock_last_falling_edge <= NOW;
	clklock_half_period1 <= (NOW - clklock_last_rising_edge)* real(str2int(div))/real(str2int(mult)); 
     ELSIF clklock_falling_edge_count = 1 THEN
        clklock_half_period_minus_dly1 <= (NOW - clklock_last_rising_edge) + tpd;
     END IF;
END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc + 1 THEN
        if(clockboost >1) then
	   FOR i IN 1 TO (2*clockboost) LOOP 	         
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	END LOOP;
      else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
      end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
end process;

process
begin
   wait until CLK_OUT_sig_d_start = '1'; LOOP
     wait for clklock_half_period1;
   CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not;
     wait for clklock_half_period0;
   CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not ;
   END LOOP;
end process;

process(clklock_falling_edge_count)
begin
   if (clklock_falling_edge_count >= lock_cyc + 1) then
       CLK_OUT_start <= '1' after clklock_half_period_minus_dly0;
   end if;
end process;

process
begin
   wait until  CLK_OUT_start = '1'; LOOP
      CLK_OUT_sig_3d <= not CLK_OUT_sig_3d;
     wait for clklock_half_period1;
      CLK_OUT_sig_3d <= not CLK_OUT_sig_3d ;
     wait for clklock_half_period0;
     END LOOP;
end process;


    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    CLK_OUT <= CLK_OUT_plus_delay;

    PLL_LOCK <= PLL_LOCK_plus when tpd >= 0 ns else
                PLL_LOCK_minus;
               

end VITAL;

configuration CFG_STDPLL_VITAL of STDPLL is 
        for VITAL
        end for; 
end CFG_STDPLL_VITAL;


----- VITAL model for cell STDPLLX -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library LC5KMX;
use LC5KMX.components.all;

-- entity declaration --
entity STDPLLX is
   generic(
      IN_FREQ  : string  := "100.0";
      CLK_OUT_TO_PIN: STRING := "OFF";
      WAKE_ON_LOCK: STRING := "OFF";
      MULT     : string  := "1";
      DIV      : string  := "1";
      POST     : string  := "1";
      LOCK_CYC : integer := 2;
      SECDIV   : string   := "2";
      PLL_DLY  : string  := "0.0";
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_PLL_RST_PLL_LOCK :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_IN_CLK_OUT             :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tpd_CLK_IN_PLL_LOCK             :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tpd_CLK_IN_SEC_OUT             :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tipd_CLK_IN             :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_PLL_FBK   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_PLL_RST   :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      CLK_IN            : in    STD_ULOGIC;
      PLL_FBK           : in    STD_ULOGIC;
      PLL_RST           : in    STD_ULOGIC;
      CLK_OUT           : out   STD_ULOGIC;
      SEC_OUT           : out   STD_ULOGIC;
      PLL_LOCK          : out   STD_ULOGIC);
attribute VITAL_LEVEL0 of STDPLLX : entity is FALSE;
end STDPLLX;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
use LC5KMX.components.all;


architecture VITAL of STDPLLX is
  attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

  SIGNAL CLK_IN_ipd	 : STD_ULOGIC := 'X';
  SIGNAL PLL_RST_ipd	 : STD_ULOGIC := 'X';
  SIGNAL PLL_RST_sig_ipd : STD_ULOGIC := 'X';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL clklock_half_period1 : TIME :=100 ns;
  SIGNAL clklock_half_period0 : TIME :=100 ns;
  SIGNAL clklock_half_period_minus_dly1 : TIME :=100 ns;
  SIGNAL clklock_half_period_minus_dly0 : TIME :=100 ns;
  SIGNAL secd_delay_minus1 : TIME :=100 ns;
  SIGNAL secd_delay_minus0 : TIME :=100 ns;
  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_falling_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;

  SIGNAL clock_count : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;
  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';

  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL SEC_OUT_sig_d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_not  : std_logic := '0';

  SIGNAL SEC_OUT_sig_3d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_start  : std_logic := '0';
  SIGNAL SEC_OUT_start  : std_logic := '0';
  SIGNAL SEC_OUT_plus_delay : std_logic := '0';
  SIGNAL CLK_OUT_sig1 : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';

  CONSTANT secdiv_p: integer := str2int(secdiv);
  CONSTANT clockboost: integer := str2int(mult) / str2int(div);
  CONSTANT tpd: time := 1.0 ns * str2real(pll_dly);

BEGIN
   WireDelay : block
   begin
   VitalWireDelay (CLK_IN_ipd, CLK_IN, tipd_CLK_IN);
   VitalWireDelay (PLL_RST_sig_ipd, PLL_RST, tipd_PLL_RST);
   end block;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN
      clklock_half_period <= (clklock_half_period0 + clklock_half_period1)/2;

   PLL_RST_ipd <= PLL_RST_sig_ipd after 1 ns;

  WAIT UNTIL (CLK_IN_ipd'EVENT AND CLK_IN_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     IF clklock_rising_edge_count = 0 THEN
        clklock_last_rising_edge <= NOW;	
	start_inclk <= CLK_IN_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
       clklock_half_period0 <= (NOW - clklock_last_falling_edge)* real(str2int(div))/real(str2int(mult));
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
       clklock_half_period_minus_dly0 <= (NOW - clklock_last_falling_edge) + tpd;
        secd_delay_minus0 <= clklock_half_period0 * secdiv_p + tpd;
     END IF;
     END IF;
 
  WAIT UNTIL (CLK_IN_ipd'EVENT AND CLK_IN_ipd='0');
     clklock_falling_edge_count <= clklock_falling_edge_count +1;	  	
     IF clklock_falling_edge_count = 0 THEN	
	clklock_last_falling_edge <= NOW;
	clklock_half_period1 <= (NOW - clklock_last_rising_edge)* real(str2int(div))/real(str2int(mult)); 
     ELSIF clklock_falling_edge_count = 1 THEN
        clklock_half_period_minus_dly1 <= (NOW - clklock_last_rising_edge) + tpd;
        secd_delay_minus1 <= clklock_half_period1 * secdiv_p + tpd;
     END IF;
END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc + 1 and PLL_RST_ipd ='0' THEN
        if(clockboost >1) then
	   FOR i IN 1 TO (2*clockboost) LOOP 	       
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	   END LOOP;
        else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
        end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
    SEC_OUT_sig_d_start <='1';
end process;

process
begin
   wait until CLK_OUT_sig_d_start = '1'; LOOP
     wait for clklock_half_period1;
   CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not;
     wait for clklock_half_period0;
   CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not ;
   END LOOP;
end process;

process(clklock_falling_edge_count)
begin
   if (clklock_falling_edge_count >= lock_cyc + 1 and PLL_RST_ipd = '0') then
       CLK_OUT_start <= '1' after clklock_half_period_minus_dly0;
   end if;
end process;

process
begin
   wait until  CLK_OUT_start = '1'; LOOP
      CLK_OUT_sig_3d <= not CLK_OUT_sig_3d;
     wait for clklock_half_period1;
      CLK_OUT_sig_3d <= not CLK_OUT_sig_3d ;
     wait for clklock_half_period0;
     END LOOP;
end process;

process
begin
   wait until SEC_OUT_sig_d_start = '1'; LOOP
     wait for clklock_half_period1 * secdiv_p;
   SEC_OUT_sig_d_not <= not SEC_OUT_sig_d_not;
     wait for clklock_half_period0 * secdiv_p;
   SEC_OUT_sig_d_not <= not SEC_OUT_sig_d_not ;
   END LOOP;
end process;

process(clklock_falling_edge_count)
begin
   if(clklock_falling_edge_count >= lock_cyc + 1 and PLL_RST_ipd = '0') then
        SEC_OUT_start <= '1' after clklock_half_period_minus_dly0;
   end if;
end process;

process
begin
   wait until  SEC_OUT_start = '1'; LOOP
      SEC_OUT_sig_3d <= not SEC_OUT_sig_3d;
     wait for clklock_half_period1 * secdiv_p;
      SEC_OUT_sig_3d <= not SEC_OUT_sig_3d ;
     wait for clklock_half_period0 * secdiv_p;
     END LOOP;
end process;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    CLK_OUT <= CLK_OUT_plus_delay and not PLL_RST_ipd;

    PLL_LOCK <= PLL_LOCK_plus and not PLL_RST_ipd when tpd >= 0 ns else
                PLL_LOCK_minus and  not PLL_RST_ipd;

    SEC_OUT_sig_d <=  SEC_OUT_sig_d_start and not SEC_OUT_sig_d_not; 

    SEC_OUT_plus_delay <= SEC_OUT_sig_d after tpd when tpd >= 0 ns else
                          SEC_OUT_sig_3d; 

    SEC_OUT <= SEC_OUT_plus_delay and not PLL_RST_ipd;

end VITAL;

configuration CFG_STDPLLX_VITAL of STDPLLX is 
        for VITAL
        end for; 
end CFG_STDPLLX_VITAL;


----- VITAL model for cell LVDSIN -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity LVDSIN is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_P_IN_O                      :	VitalDelayType01 := ( 0.00 ns, 0.00 ns);
      tpd_N_IN_O                      :	VitalDelayType01 := ( 0.00 ns, 0.00 ns);
      tipd_N_IN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_P_IN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      N_IN                            :	in    STD_ULOGIC;
      P_IN                            :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of LVDSIN : entity is FALSE;
end LVDSIN;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
-- -- use LC5KMX.VTABLES.all;
architecture VITAL of LVDSIN is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL P_IN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (P_IN_ipd, P_IN, tipd_P_IN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (P_IN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(P_IN_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (P_IN_ipd'last_event, tpd_P_IN_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_LVDSIN_VITAL of LVDSIN is 
        for VITAL
        end for; 
end CFG_LVDSIN_VITAL;

----- VITAL model for cell LVDSOUT -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;

-- entity declaration --
entity LVDSOUT is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I_P_OUT                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I_N_OUT                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I                             :	in    STD_ULOGIC;
      P_OUT                             :	out   STD_ULOGIC;
      N_OUT                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of LVDSOUT : entity is FALSE;
end LVDSOUT;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
-- use LC5KMX.VTABLES.all;
architecture VITAL of LVDSOUT is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL I_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I_ipd, I, tipd_I);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(I_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => P_OUT,
       GlitchData => O_GlitchData,
       OutSignalName => "P_OUT",
       OutTemp => O_zd,
       Paths => (0 => (I_ipd'last_event, tpd_I_P_OUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_LVDSOUT_VITAL of LVDSOUT is 
        for VITAL
        end for; 
end CFG_LVDSOUT_VITAL;

----- VITAL model for cell LVDSTRI -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity LVDSTRI is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_OE_P_OUT                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_N_OUT                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_I_P_OUT                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I_N_OUT                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_OE                        :	VitalDelayType01 := (0.0 ns, 0.0 ns));

   port(
      I                             :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      P_OUT                          :	out   STD_ULOGIC;
      N_OUT                          :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of LVDSTRI : entity is FALSE;
end LVDSTRI;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
--use LC5KMX.VTABLES.all;
architecture VITAL of LVDSTRI is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL I_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I_ipd, I, tipd_I);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I_ipd, OE_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalBUFIF0 (data => I_ipd,
              enable => (NOT OE_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => P_OUT,
       GlitchData => O_GlitchData,
       OutSignalName => "P_OUT",
       OutTemp => O_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_P_OUT), TRUE),
                 1 => (I_ipd'last_event, VitalExtendToFillDelay(tpd_I_P_OUT), TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");

end process;
end VITAL;

configuration CFG_LVDSTRI_VITAL of LVDSTRI is 
        for VITAL
        end for; 
end CFG_LVDSTRI_VITAL;
----- VITAL model for cell LVDSIO -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity LVDSIO is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_OE_P_IO                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_N_IO                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_I_P_IO                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I_N_IO                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_P_IO_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_N_IO_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_OE                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_P_IO                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_N_IO                        :	VitalDelayType01 := (0.0 ns, 0.0 ns));

   port(
      I                             :	in    STD_ULOGIC;
      OE                             :	in    STD_ULOGIC;
      P_IO                             :	inout STD_ULOGIC;
      N_IO                             :	inout STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of LVDSIO : entity is FALSE ;
end LVDSIO;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
--use LC5KMX.VTABLES.all;
architecture VITAL of LVDSIO is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL I_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL P_IO_ipd	 : STD_ULOGIC := 'X';
   SIGNAL N_IO_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I_ipd, I, tipd_I);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   VitalWireDelay (P_IO_ipd, P_IO, tipd_P_IO);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I_ipd, OE_ipd, P_IO_ipd)


   -- functionality results
--   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
     VARIABLE IO_zd : std_ulogic ;
     VARIABLE O_zd : std_ulogic ;

   -- output glitch detection variables
   VARIABLE IO_GlitchData	: VitalGlitchDataType;
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      IO_zd := VitalBUFIF1 (I_ipd, OE_ipd);
      O_zd := VitalBUF(P_IO_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => P_IO,
       GlitchData => IO_GlitchData,
       OutSignalName => "P_IO",
       OutTemp => IO_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_P_IO), TRUE),
                 1 => (I_ipd'last_event, VitalExtendToFillDelay(tpd_I_P_IO), TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (P_IO_ipd'last_event, tpd_P_IO_O, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_LVDSIO_VITAL of LVDSIO is 
        for VITAL
        end for; 
end CFG_LVDSIO_VITAL;


----- VITAL model for cell BLVDSIN -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity BLVDSIN is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_P_IN_O                      :	VitalDelayType01 := ( 0.00 ns, 0.00 ns);
      tpd_N_IN_O                      :	VitalDelayType01 := ( 0.00 ns, 0.00 ns);
      tipd_N_IN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_P_IN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      N_IN                            :	in    STD_ULOGIC;
      P_IN                            :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BLVDSIN : entity is FALSE;
end BLVDSIN;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
-- -- use LC5KMX.VTABLES.all;
architecture VITAL of BLVDSIN is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL P_IN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (P_IN_ipd, P_IN, tipd_P_IN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (P_IN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(P_IN_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (P_IN_ipd'last_event, tpd_P_IN_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_BLVDSIN_VITAL of BLVDSIN is 
        for VITAL
        end for; 
end CFG_BLVDSIN_VITAL;

----- VITAL model for cell BLVDSOUT -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LC5KMX ;
use LC5KMX.VLOGTOVITAL_TABLES.all;

-- entity declaration --
entity BLVDSOUT is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I_P_OUT                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I_N_OUT                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I                 :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I                             :	in    STD_ULOGIC;
      P_OUT                             :	out   STD_ULOGIC;
      N_OUT                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BLVDSOUT : entity is FALSE;
end BLVDSOUT;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
-- use LC5KMX.VTABLES.all;
architecture VITAL of BLVDSOUT is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL I_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I_ipd, I, tipd_I);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(I_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => P_OUT,
       GlitchData => O_GlitchData,
       OutSignalName => "P_OUT",
       OutTemp => O_zd,
       Paths => (0 => (I_ipd'last_event, tpd_I_P_OUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_BLVDSOUT_VITAL of BLVDSOUT is 
        for VITAL
        end for; 
end CFG_BLVDSOUT_VITAL;

----- VITAL model for cell BLVDSTRI -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity BLVDSTRI is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_OE_P_OUT                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_N_OUT                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_I_P_OUT                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I_N_OUT                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_OE                        :	VitalDelayType01 := (0.0 ns, 0.0 ns));

   port(
      I                             :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      P_OUT                          :	out   STD_ULOGIC;
      N_OUT                          :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BLVDSTRI : entity is FALSE;
end BLVDSTRI;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
--use LC5KMX.VTABLES.all;
architecture VITAL of BLVDSTRI is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL I_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I_ipd, I, tipd_I);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I_ipd, OE_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalBUFIF0 (data => I_ipd,
              enable => (NOT OE_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => P_OUT,
       GlitchData => O_GlitchData,
       OutSignalName => "P_OUT",
       OutTemp => O_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_P_OUT), TRUE),
                 1 => (I_ipd'last_event, VitalExtendToFillDelay(tpd_I_P_OUT), TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");

end process;
end VITAL;

configuration CFG_BLVDSTRI_VITAL of BLVDSTRI is 
        for VITAL
        end for; 
end CFG_BLVDSTRI_VITAL;

----- VITAL model for cell BLVDSIO -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity BLVDSIO is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_OE_P_IO                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_N_IO                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_I_P_IO                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I_N_IO                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_P_IO_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_N_IO_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_OE                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_P_IO                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_N_IO                        :	VitalDelayType01 := (0.0 ns, 0.0 ns));

   port(
      I                             :	in    STD_ULOGIC;
      OE                             :	in    STD_ULOGIC;
      P_IO                             :	inout STD_ULOGIC;
      N_IO                             :	inout STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BLVDSIO : entity is FALSE;
end BLVDSIO;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LC5KMX;
--use LC5KMX.VTABLES.all;
architecture VITAL of BLVDSIO is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL I_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL P_IO_ipd	 : STD_ULOGIC := 'X';
   SIGNAL NTRUE_IO_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I_ipd, I, tipd_I);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   VitalWireDelay (P_IO_ipd, P_IO, tipd_P_IO);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I_ipd, OE_ipd, P_IO_ipd)


   -- functionality results
--   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
     VARIABLE IO_zd : std_ulogic ;
     VARIABLE O_zd : std_ulogic ;

   -- output glitch detection variables
   VARIABLE IO_GlitchData	: VitalGlitchDataType;
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      IO_zd := VitalBUFIF1 (I_ipd, OE_ipd);
      O_zd := VitalBUF(P_IO_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => P_IO,
       GlitchData => IO_GlitchData,
       OutSignalName => "P_IO",
       OutTemp => IO_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_P_IO), TRUE),
                 1 => (I_ipd'last_event, VitalExtendToFillDelay(tpd_I_P_IO), TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (P_IO_ipd'last_event, tpd_P_IO_O, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_BLVDSIO_VITAL of BLVDSIO is 
        for VITAL
        end for; 
end CFG_BLVDSIO_VITAL;

----- CELL CCU_AGB -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_AGB is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      B0                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_AGB : entity is TRUE;
end CCU_AGB;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_AGB is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (B0_ipd, B0, tipd_B0);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, B0_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS COUT_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      COUT_zd :=
       ((CIN_ipd) AND ((NOT ((B0_ipd) XOR (A0_ipd))))) OR (((NOT B0_ipd))
         AND (A0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE),
                 2 => (B0_ipd'last_event, tpd_B0_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_AGB_VITAL of CCU_AGB is
   for VITAL
   end for;
end CFG_CCU_AGB_VITAL;

----- CELL CCU_AS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_AS is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_AS_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_AS_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AS                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      B0                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      AS                             :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_AS : entity is TRUE;
end CCU_AS;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_AS is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';
   SIGNAL AS_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (B0_ipd, B0, tipd_B0);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   VitalWireDelay (AS_ipd, AS, tipd_AS);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, B0_ipd, CIN_ipd, AS_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd :=
       ((((NOT AS_ipd)) AND ((NOT B0_ipd))) OR ((AS_ipd) AND (B0_ipd))) XOR
         (A0_ipd) XOR (CIN_ipd);
      COUT_zd :=
       (((((NOT AS_ipd)) AND ((NOT B0_ipd))) OR ((AS_ipd) AND (B0_ipd))) AND
         ((CIN_ipd) OR (A0_ipd))) OR ((CIN_ipd) AND (A0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_S0, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_S0, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE),
                 3 => (AS_ipd'last_event, tpd_AS_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_COUT, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE),
                 3 => (AS_ipd'last_event, tpd_AS_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_AS_VITAL of CCU_AS is
   for VITAL
   end for;
end CFG_CCU_AS_VITAL;

----- CELL CCU_ADD -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_ADD is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      B0                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_ADD : entity is TRUE;
end CCU_ADD;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_ADD is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (B0_ipd, B0, tipd_B0);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, B0_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := (B0_ipd) XOR (A0_ipd) XOR (CIN_ipd);
      COUT_zd :=
       ((CIN_ipd) AND (A0_ipd)) OR ((B0_ipd) AND (A0_ipd)) OR ((CIN_ipd) AND
         (B0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_S0, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_S0, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_COUT, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_ADD_VITAL of CCU_ADD is
   for VITAL
   end for;
end CFG_CCU_ADD_VITAL;

----- CELL CCU_SUB -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_SUB is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      B0                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_SUB : entity is TRUE;
end CCU_SUB;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_SUB is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (B0_ipd, B0, tipd_B0);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, B0_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := (NOT(B0_ipd)) XOR (A0_ipd) XOR (CIN_ipd);
      COUT_zd :=
       ((CIN_ipd) AND (A0_ipd)) OR ((NOT(B0_ipd)) AND (A0_ipd)) OR ((CIN_ipd) AND
         (NOT(B0_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_S0, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_S0, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_COUT, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_SUB_VITAL of CCU_SUB is
   for VITAL
   end for;
end CFG_CCU_SUB_VITAL;

----- CELL CCU_UDCP -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_UDCP is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_D_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LOAD_S0                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_UD_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_SD_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LOAD_COUT                  :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_UD_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SD                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LOAD                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_UD                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      SD                             :	in    STD_ULOGIC;
      LOAD                           :	in    STD_ULOGIC;
      UD                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_UDCP : entity is TRUE;
end CCU_UDCP;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_UDCP is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL SD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LOAD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL UD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SD_ipd, SD, tipd_SD);
   VitalWireDelay (LOAD_ipd, LOAD, tipd_LOAD);
   VitalWireDelay (UD_ipd, UD, tipd_UD);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, SD_ipd, LOAD_ipd, UD_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd :=
       (((CIN_ipd) XOR (NOT (UD_ipd)) XOR (D_ipd)) AND (NOT (LOAD_ipd))) OR
         ((SD_ipd) AND (LOAD_ipd));
      COUT_zd :=
       (((CIN_ipd) AND (D_ipd)) OR (((NOT UD_ipd)) AND (D_ipd)) OR (((NOT
         UD_ipd)) AND (CIN_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_S0, TRUE),
                 1 => (LOAD_ipd'last_event, tpd_LOAD_S0, TRUE),
                 2 => (UD_ipd'last_event, tpd_UD_S0, TRUE),
                 3 => (SD_ipd'last_event, tpd_SD_S0, TRUE),
                 4 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_COUT, TRUE),
                 1 => (LOAD_ipd'last_event, tpd_LOAD_COUT, TRUE),
                 2 => (UD_ipd'last_event, tpd_UD_COUT, TRUE),
                 3 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_UDCP_VITAL of CCU_UDCP is
   for VITAL
   end for;
end CFG_CCU_UDCP_VITAL;

----- CELL CCU_UDC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_UDC is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_D_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_UD_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_UD_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_UD                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      UD                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_UDC : entity is TRUE;
end CCU_UDC;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_UDC is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL UD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (UD_ipd, UD, tipd_UD);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, UD_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := ((NOT UD_ipd)) XOR (D_ipd) XOR (CIN_ipd);
      COUT_zd :=
       ((CIN_ipd) AND (D_ipd)) OR (((NOT UD_ipd)) AND (D_ipd)) OR ((CIN_ipd)
         AND ((NOT UD_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_S0, TRUE),
                 1 => (UD_ipd'last_event, tpd_UD_S0, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_COUT, TRUE),
                 1 => (UD_ipd'last_event, tpd_UD_COUT, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_UDC_VITAL of CCU_UDC is
   for VITAL
   end for;
end CFG_CCU_UDC_VITAL;

----- CELL CCU_DC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_DC is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_D_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_DC : entity is TRUE;
end CCU_DC;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_DC is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := (NOT((CIN_ipd) XOR (D_ipd)));
      COUT_zd := (CIN_ipd) OR (D_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_S0, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_COUT, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_DC_VITAL of CCU_DC is
   for VITAL
   end for;
end CFG_CCU_DC_VITAL;

----- CELL CCU_UC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_UC is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_D_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_UC : entity is TRUE;
end CCU_UC;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_UC is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := ((CIN_ipd) XOR (D_ipd));
      COUT_zd := (CIN_ipd) AND (D_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_S0, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_COUT, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_UC_VITAL of CCU_UC is
   for VITAL
   end for;
end CFG_CCU_UC_VITAL;

----- CELL DC_LSB -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity DC_LSB is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_D_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                  :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                    :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CIN                         :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DC_LSB : entity is TRUE;
end DC_LSB;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of DC_LSB is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := (CIN_ipd) XOR (D_ipd);
      COUT_zd := (CIN_ipd) AND (D_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_S0, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_COUT, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_DC_LSB_VITAL of DC_LSB is
   for VITAL
   end for;
end CFG_DC_LSB_VITAL;

----- CELL UC_LSB -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity UC_LSB is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_D_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                  :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                    :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CIN                         :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of UC_LSB : entity is TRUE;
end UC_LSB;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of UC_LSB is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := (CIN_ipd) XOR (D_ipd);
      COUT_zd := (CIN_ipd) AND (D_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_S0, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_COUT, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_UC_LSB_VITAL of UC_LSB is
   for VITAL
   end for;
end CFG_UC_LSB_VITAL;

----- CELL CCU_UCP -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_UCP is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_SD_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_SD_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LOAD_S0                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LOAD_COUT                  :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SD                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LOAD                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      SD                             :	in    STD_ULOGIC;
      LOAD                           :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_UCP : entity is TRUE;
end CCU_UCP;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_UCP is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL SD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LOAD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SD_ipd, SD, tipd_SD);
   VitalWireDelay (LOAD_ipd, LOAD, tipd_LOAD);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, SD_ipd, LOAD_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd :=
       (CIN_ipd) XOR ((((NOT LOAD_ipd)) AND (D_ipd)) OR ((LOAD_ipd) AND
         (SD_ipd)));
      COUT_zd := ((((NOT LOAD_ipd)) AND (D_ipd)) OR ((LOAD_ipd) AND
         (SD_ipd))) AND (CIN_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (SD_ipd'last_event, tpd_SD_S0, TRUE),
                 1 => (LOAD_ipd'last_event, tpd_LOAD_S0, TRUE),
                 2 => (D_ipd'last_event, tpd_D_S0, TRUE),
                 3 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (LOAD_ipd'last_event, tpd_LOAD_COUT, TRUE),
                 1 => (D_ipd'last_event, tpd_D_COUT, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE),
       		 3 => (SD_ipd'last_event, tpd_SD_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_UCP_VITAL of CCU_UCP is
   for VITAL
   end for;
end CFG_CCU_UCP_VITAL;

----- CELL CCU_DCP -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_DCP is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_SD_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LOAD_S0                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LOAD_COUT                  :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SD                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LOAD                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      SD                             :	in    STD_ULOGIC;
      LOAD                           :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_DCP : entity is TRUE;
end CCU_DCP;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_DCP is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL SD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LOAD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SD_ipd, SD, tipd_SD);
   VitalWireDelay (LOAD_ipd, LOAD, tipd_LOAD);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, SD_ipd, LOAD_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd :=
       (NOT((CIN_ipd) XOR  (((NOT LOAD_ipd) AND (D_ipd)) OR ((LOAD_ipd)
         AND (SD_ipd)))));
      COUT_zd :=((CIN_ipd) OR (((NOT LOAD_ipd) AND (D_ipd)) OR ((LOAD_ipd)
         AND (SD_ipd))));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (SD_ipd'last_event, tpd_SD_S0, TRUE),
                 1 => (LOAD_ipd'last_event, tpd_LOAD_S0, TRUE),
                 2 => (D_ipd'last_event, tpd_D_S0, TRUE),
                 3 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (LOAD_ipd'last_event, tpd_LOAD_COUT, TRUE),
                 1 => (D_ipd'last_event, tpd_D_COUT, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_DCP_VITAL of CCU_DCP is
   for VITAL
   end for;
end CFG_CCU_DCP_VITAL;

-- ************************************************************************
--
--  Block Memory: Behavioral Model
--  The kernel of other RAM applications  
--
-- ************************************************************************
--
--  Init: Sep. 10, 2001
--  Written by: Zhou Xiao-qiu
--  Email: xqzhou@lscsh.latticesemi.com
--  Tel: 86-21-64852865 ext. 224/226
--
-- ************************************************************************
--
--  Filename:  SC_BLOCK_RAM.vhd
--  Description: 16K X 1  BRAM behavioral model. 
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
library std;
use std.textio.all;

library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;


-- ************************************************************************
-- Entity definition  
-- "generic" members 
-- ************************************************************************

entity SC_BRAM_16K is

  generic (

	 DEVICE_FAMILY : string  := "SuperCool";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 262144;       
	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := ""

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 

end SC_BRAM_16K;

-- ************************************************************************
-- Architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_BRAM_16K is

procedure READ_MEM_INIT_FILE(
                              f_name : IN    STRING;
                              v_MEM  : OUT   STD_LOGIC_VECTOR
                             ) IS

    file     f_INIT_FILE   : TEXT is MEM_INIT_FILE;
    variable v_WORD        : line;
    variable v_GOODFLAG    : boolean;
    variable v_WORD_BIT    : string (WDATA_WIDTH_A downto 1) ;
    variable v_CHAR        : character;
    variable v_OFFSET      : integer := 0;
    variable v_LINE        : integer := 0;

    begin      
      
      while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop

      readline(f_INIT_FILE, v_WORD);
      read(v_WORD, v_WORD_BIT, v_GOODFLAG);

      for k in 0 to WDATA_WIDTH_A - 1 loop
        v_CHAR := v_WORD_BIT (k + 1);
        if (v_CHAR = '1') then
          v_MEM(v_OFFSET + k) := '1';

	elsif (v_CHAR = '0') then
          v_MEM(v_OFFSET + k) := '0';

--	else 
--          v_MEM(v_OFFSET + k) := 'X';

	end if;
      end loop;

      v_LINE := v_LINE + 1;
      v_OFFSET := v_OFFSET + WDATA_WIDTH_A;

    end loop;

  end READ_MEM_INIT_FILE;



--------------------------------------------------------------------------
-- Function: Valid_Address 
-- Description: 
--------------------------------------------------------------------------
function Valid_Address (
    IN_ADDR : in std_logic_vector
 ) return boolean is

    variable v_Valid_Flag : boolean := TRUE;
 
begin

    for i in IN_ADDR'high downto IN_ADDR'low loop
        if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
            v_Valid_Flag := FALSE;
        end if;
    end loop;

    return v_Valid_Flag;
end Valid_Address;

--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------

--------- Local signals used to propagate input wire delay ---------------

signal WADA_node   : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node    : std_logic := 'X';
signal WDA_node    : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node   : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node    : std_logic := 'X';
signal RDA_node    : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');

signal WADB_node   : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node    : std_logic := 'X';
signal WDB_node    : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node   : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node    : std_logic := 'X';
signal RDB_node    : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');

-- architecture
begin 

 WADA_node <= WADA;
 WEA_node  <= WEA;
 WDA_node  <= WDA;
 RADA_node <= RADA;
 REA_node  <= REA;
 RDA       <= RDA_node;
 
 WADB_node <= WADB;
 WEB_node  <= WEB;
 WDB_node  <= WDB;
 RADB_node <= RADB;
 REB_node  <= REB;
 RDB       <= RDB_node;

-----------------------------------------
--------- Behavior process  -------------
-----------------------------------------


  KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)


--TSPEC: A note about sram initial values and rom mode: 
--       If the user does not provide any values, ... default 0 
--       for all ram locations in JECED
    variable v_MEM         : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' ); 
    variable v_INI_DONE    : boolean := FALSE;
    variable v_WADDR_A     : integer;
    variable v_RADDR_A     : integer;
    variable v_WADDR_B     : integer;
    variable v_RADDR_B     : integer;

    variable v_WADDRA_Valid_Flag : boolean := TRUE;
    variable v_WADDRB_Valid_Flag : boolean := TRUE;
    variable v_RADDRA_Valid_Flag : boolean := TRUE;
    variable v_RADDRB_Valid_Flag : boolean := TRUE;

  begin -- Process
   
    if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
	READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
	v_INI_DONE := TRUE;
    end if;

  -- Address Check    
    v_WADDRA_Valid_Flag := Valid_Address(WADA_node);	
    v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
    v_RADDRA_Valid_Flag := Valid_Address(RADA_node);	
    v_RADDRB_Valid_Flag := Valid_Address(RADB_node);

    if ( v_WADDRA_Valid_Flag = TRUE ) then
 	v_WADDR_A := CONV_INTEGER(WADA_node);
--    else	
--      assert (Now = 0 ps) 
--        report "Write AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_WADDRB_Valid_Flag = TRUE ) then
      v_WADDR_B := CONV_INTEGER(WADB_node);
    else
--      assert (Now = 0 ps)
--        report "Write AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRA_Valid_Flag = TRUE ) then
      v_RADDR_A := CONV_INTEGER(RADA_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRB_Valid_Flag = TRUE ) then
      v_RADDR_B := CONV_INTEGER(RADB_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

  -- CHECK Operation
    if (WEA = '1' and WEB = '1' and 
       (v_WADDR_A*WDATA_WIDTH_A = v_WADDR_B*WDATA_WIDTH_B
              or
           (WDATA_WIDTH_A > WDATA_WIDTH_B and 
           (v_WADDR_A+1)*WDATA_WIDTH_A > v_WADDR_B*WDATA_WIDTH_B and
           v_WADDR_A*WDATA_WIDTH_A <= v_WADDR_B*WDATA_WIDTH_B)
              or
           (WDATA_WIDTH_B > WDATA_WIDTH_A and 
           (v_WADDR_B+1)*WDATA_WIDTH_B > v_WADDR_B*WDATA_WIDTH_A and
           v_WADDR_B*WDATA_WIDTH_B <= v_WADDR_A*WDATA_WIDTH_A)
          )) then
      assert false
        report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
        severity warning;
    end if;  

  -- MEM Operation	
    if (WEA_node = '1') then
        v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
    end if;

    if (WEB_node = '1') then
        v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
    end if;

    if (REA_node = '1') then
       RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
--    else
--       RDA_node <= ( others => 'X');
    end if;
    
    if (REB_node = '1') then
       RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
--    else
--       RDB_node <= ( others => 'X');
    end if;
    
  end process KERNEL_BEHAV;
    
end LATTICE_BEHAV;


-- ************************************************************************
--
--  Block Memory: Behavioral Model
--  The kernel of other RAM applications  
--
-- ************************************************************************
--
--  Init: Sep. 10, 2001
--  Written by: Zhou Xiao-qiu
--  Email: xqzhou@lscsh.latticesemi.com
--  Tel: 86-21-64852865 ext. 224/226
--
-- ************************************************************************
--
--  Filename:  SC_BLOCK_RAM.vhd
--  Description: 16K X 1  BRAM behavioral model. 
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
library std;
use std.textio.all;

library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;


-- ************************************************************************
-- Entity definition  
-- "generic" members 
-- ************************************************************************

entity SC_BRAM_16K_SYNC is

  generic (

	 DEVICE_FAMILY : string  := "SuperCool";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 262144;       
	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := ""

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
         WCLK : in  STD_LOGIC;
         RCLK : in  STD_LOGIC
	); 

end SC_BRAM_16K_SYNC;

-- ************************************************************************
-- Architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_BRAM_16K_SYNC is


procedure READ_MEM_INIT_FILE(
                              f_name : IN    STRING;
                              v_MEM  : OUT   STD_LOGIC_VECTOR
                             ) IS

    file     f_INIT_FILE   : TEXT is MEM_INIT_FILE;
    variable v_WORD        : line;
    variable v_GOODFLAG    : boolean;
    variable v_WORD_BIT    : string (WDATA_WIDTH_A downto 1) ;
    variable v_CHAR        : character;
    variable v_OFFSET      : integer := 0;
    variable v_LINE        : integer := 0;

    begin      
      
      while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop

      readline(f_INIT_FILE, v_WORD);
      read(v_WORD, v_WORD_BIT, v_GOODFLAG);

      for k in 0 to WDATA_WIDTH_A - 1 loop
        v_CHAR := v_WORD_BIT (k + 1);
        if (v_CHAR = '1') then
          v_MEM(v_OFFSET + k) := '1';

	elsif (v_CHAR = '0') then
          v_MEM(v_OFFSET + k) := '0';

--	else 
--          v_MEM(v_OFFSET + k) := 'X';

	end if;
      end loop;

      v_LINE := v_LINE + 1;
      v_OFFSET := v_OFFSET + WDATA_WIDTH_A;

    end loop;

  end READ_MEM_INIT_FILE;

--------------------------------------------------------------------------
-- Function: Valid_Address 
-- Description: 
--------------------------------------------------------------------------
function Valid_Address (
    IN_ADDR : in std_logic_vector
 ) return boolean is

    variable v_Valid_Flag : boolean := TRUE;
 
begin

    for i in IN_ADDR'high downto IN_ADDR'low loop
        if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
            v_Valid_Flag := FALSE;
        end if;
    end loop;

    return v_Valid_Flag;
end Valid_Address;

--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------

--------- Local signals used to propagate input wire delay ---------------

signal WADA_node   : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node    : std_logic := 'X';
signal WDA_node    : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node   : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node    : std_logic := 'X';
signal RDA_node    : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');

signal WADB_node   : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node    : std_logic := 'X';
signal WDB_node    : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node   : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node    : std_logic := 'X';
signal RDB_node    : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal WCLK_node   : std_logic := 'X';
signal RCLK_node   : std_logic := 'X';
-- architecture
begin 

 WADA_node <= WADA;
 WEA_node  <= WEA;
 WDA_node  <= WDA;
 RADA_node <= RADA;
 REA_node  <= REA;
 RDA       <= RDA_node;
 
 WADB_node <= WADB;
 WEB_node  <= WEB;
 WDB_node  <= WDB;
 RADB_node <= RADB;
 REB_node  <= REB;
 RDB       <= RDB_node;

 WCLK_node <= WCLK;
 RCLK_node <= RCLK;

-----------------------------------------
--------- Behavior process  -------------
-----------------------------------------


  --KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
KERNEL_BEHAV : process( WCLK_node, RCLK_node)

--TSPEC: A note about sram initial values and rom mode: 
--       If the user does not provide any values, ... default 0 
--       for all ram locations in JECED
    variable v_MEM         : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' ); 
    variable v_INI_DONE    : boolean := FALSE;
    variable v_WADDR_A     : integer;
    variable v_RADDR_A     : integer;
    variable v_WADDR_B     : integer;
    variable v_RADDR_B     : integer;

    variable v_WADDRA_Valid_Flag : boolean := TRUE;
    variable v_WADDRB_Valid_Flag : boolean := TRUE;
    variable v_RADDRA_Valid_Flag : boolean := TRUE;
    variable v_RADDRB_Valid_Flag : boolean := TRUE;

  begin -- Process
   
    if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
	READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
	v_INI_DONE := TRUE;
    end if;

  -- Address Check    
    v_WADDRA_Valid_Flag := Valid_Address(WADA_node);	
    v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
    v_RADDRA_Valid_Flag := Valid_Address(RADA_node);	
    v_RADDRB_Valid_Flag := Valid_Address(RADB_node);

    if ( v_WADDRA_Valid_Flag = TRUE ) then
 	v_WADDR_A := CONV_INTEGER(WADA_node);
--    else	
--      assert (Now = 0 ps) 
--        report "Write AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_WADDRB_Valid_Flag = TRUE ) then
      v_WADDR_B := CONV_INTEGER(WADB_node);
    else
--      assert (Now = 0 ps)
--        report "Write AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRA_Valid_Flag = TRUE ) then
      v_RADDR_A := CONV_INTEGER(RADA_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRB_Valid_Flag = TRUE ) then
      v_RADDR_B := CONV_INTEGER(RADB_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

  -- CHECK Operation
    if (WEA = '1' and WEB = '1' and 
         not( 
          (v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B) 
                         or
          (v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
         )
        ) then
      assert false
        report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
        severity warning;
    end if;  

  -- MEM Operation	
    if (WEA_node = '1' and WCLK_node'event and WCLK_node = '1' ) then
        v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
    end if;

    if (WEB_node = '1' and WCLK_node'event and WCLK_node = '1') then
        v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
    end if;

    if (REA_node = '1' and RCLK_node'event and RCLK_node = '1') then
       RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
--    else
--       RDA_node <= ( others => 'X');
    end if;
    
    if (REB_node = '1' and RCLK_node'event and RCLK_node = '1') then
       RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
--    else
--       RDB_node <= ( others => 'X');
    end if;
    
  end process KERNEL_BEHAV;
    
end LATTICE_BEHAV;


-- ************************************************************************
--
--  Block Memory: Behavioral Model
--  The kernel of other RAM applications  
--
-- ************************************************************************
--
--  Init: Sep. 10, 2001
--  Written by: Zhou Xiao-qiu
--  Email: xqzhou@lscsh.latticesemi.com
--  Tel: 86-21-64852865 ext. 224/226
--
-- ************************************************************************
--
--  Filename:  SC_BLOCK_RAM_L.vhd
--  Description: BRAM behavioral model. 
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
library std;
use std.textio.all;

library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;


-- ************************************************************************
-- Entity definition  
-- "generic" members 
-- ************************************************************************

entity SC_BRAM_16K_L_SYNC is

  generic (

	 DEVICE_FAMILY : string  := "SuperCool";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 262144;       
	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := ""

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
         WCLK : in  STD_LOGIC;
         RCLK : in  STD_LOGIC
	); 

end SC_BRAM_16K_L_SYNC;

-- ************************************************************************
-- Architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_BRAM_16K_L_SYNC is

procedure READ_MEM_INIT_FILE(
                              f_name : IN    STRING;
                              v_MEM  : OUT   STD_LOGIC_VECTOR
                             ) IS

    file     f_INIT_FILE   : TEXT is MEM_INIT_FILE;
    variable v_WORD        : line;
    variable v_GOODFLAG    : boolean;
    variable v_WORD_BIT    : string (WDATA_WIDTH_A downto 1) ;
    variable v_CHAR        : character;
    variable v_OFFSET      : integer := 0;
    variable v_LINE        : integer := 0;

    begin      
      
      while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop

      readline(f_INIT_FILE, v_WORD);
      read(v_WORD, v_WORD_BIT, v_GOODFLAG);

      for k in 0 to WDATA_WIDTH_A - 1 loop
        v_CHAR := v_WORD_BIT (k + 1);
        if (v_CHAR = '1') then
          v_MEM(v_OFFSET + k) := '1';

	elsif (v_CHAR = '0') then
          v_MEM(v_OFFSET + k) := '0';

--	else 
--          v_MEM(v_OFFSET + k) := 'X';

	end if;
      end loop;

      v_LINE := v_LINE + 1;
      v_OFFSET := v_OFFSET + WDATA_WIDTH_A;

    end loop;

  end READ_MEM_INIT_FILE;

--------------------------------------------------------------------------
-- Function: Valid_Address 
-- Description: 
--------------------------------------------------------------------------
function Valid_Address (
    IN_ADDR : in std_logic_vector
 ) return boolean is

    variable v_Valid_Flag : boolean := TRUE;
 
begin

    for i in IN_ADDR'high downto IN_ADDR'low loop
        if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
            v_Valid_Flag := FALSE;
        end if;
    end loop;

    return v_Valid_Flag;
end Valid_Address;

--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------

--------- Local signals used to propagate input wire delay ---------------

signal WADA_node   : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node    : std_logic := 'X';
signal WDA_node    : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node   : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node    : std_logic := 'X';
signal RDA_node    : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');

signal WADB_node   : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node    : std_logic := 'X';
signal WDB_node    : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node   : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node    : std_logic := 'X';
signal RDB_node    : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal WCLK_node   : std_logic := 'X';
signal RCLK_node   : std_logic := 'X';
-- architecture
begin 

 WADA_node <= WADA;
 WEA_node  <= WEA;
 WDA_node  <= WDA;
 RADA_node <= RADA;
 REA_node  <= REA;
 RDA       <= RDA_node;
 
 WADB_node <= WADB;
 WEB_node  <= WEB;
 WDB_node  <= WDB;
 RADB_node <= RADB;
 REB_node  <= REB;
 RDB       <= RDB_node;

 WCLK_node <= WCLK;
 RCLK_node <= RCLK;

-----------------------------------------
--------- Behavior process  -------------
-----------------------------------------


  --KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
KERNEL_BEHAV : process( WCLK_node, RCLK_node)

--TSPEC: A note about sram initial values and rom mode: 
--       If the user does not provide any values, ... default 0 
--       for all ram locations in JECED
    variable v_MEM         : std_logic_vector(ARRAY_SIZE*WDATA_WIDTH_A - 1 downto 0) := ( others => '0' ); 
    variable v_INI_DONE    : boolean := FALSE;
    variable v_WADDR_A     : integer;
    variable v_RADDR_A     : integer;
    variable v_WADDR_B     : integer;
    variable v_RADDR_B     : integer;

    variable v_WADDRA_Valid_Flag : boolean := TRUE;
    variable v_WADDRB_Valid_Flag : boolean := TRUE;
    variable v_RADDRA_Valid_Flag : boolean := TRUE;
    variable v_RADDRB_Valid_Flag : boolean := TRUE;

  begin -- Process
   
    if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
	READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
	v_INI_DONE := TRUE;
    end if;

  -- Address Check    
    v_WADDRA_Valid_Flag := Valid_Address(WADA_node);	
    v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
    v_RADDRA_Valid_Flag := Valid_Address(RADA_node);	
    v_RADDRB_Valid_Flag := Valid_Address(RADB_node);

    if ( v_WADDRA_Valid_Flag = TRUE ) then
 	v_WADDR_A := CONV_INTEGER(WADA_node);
--    else	
--      assert (Now = 0 ps) 
--        report "Write AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_WADDRB_Valid_Flag = TRUE ) then
      v_WADDR_B := CONV_INTEGER(WADB_node);
    else
--      assert (Now = 0 ps)
--        report "Write AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRA_Valid_Flag = TRUE ) then
      v_RADDR_A := CONV_INTEGER(RADA_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRB_Valid_Flag = TRUE ) then
      v_RADDR_B := CONV_INTEGER(RADB_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

  -- CHECK Operation
    if (WEA = '1' and WEB = '1' and 
         not( 
          (v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B) 
                         or
          (v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
         )
        ) then
      assert false
        report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
        severity warning;
    end if;  

  -- MEM Operation	
    if (WEA_node = '1' and WCLK_node'event and WCLK_node = '1' ) then
        v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
    end if;

    if (WEB_node = '1' and WCLK_node'event and WCLK_node = '1') then
        v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
    end if;

    if (REA_node = '1' and RCLK_node'event and RCLK_node = '1') then
       RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
--    else
--       RDA_node <= ( others => 'X');
    end if;
    
    if (REB_node = '1' and RCLK_node'event and RCLK_node = '1') then
       RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
--    else
--       RDB_node <= ( others => 'X');
    end if;
    
  end process KERNEL_BEHAV;
    
end LATTICE_BEHAV;


-- ************************************************************************
--
--  Block Memory: Behavioral Model
--  The kernel of other RAM applications  
--
-- ************************************************************************
--
--  Init: Sep. 10, 2001
--  Written by: Zhou Xiao-qiu
--  Email: xqzhou@lscsh.latticesemi.com
--  Tel: 86-21-64852865 ext. 224/226
--
-- ************************************************************************
--
--  Filename:  SC_BLOCK_RAM.vhd
--  Description: 16K X 1  BRAM behavioral model. 
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
library std;
use std.textio.all;

library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;


-- ************************************************************************
-- Entity definition  
-- "generic" members 
-- ************************************************************************

entity SC_BRAM_PDP_16K is

  generic (

	 DEVICE_FAMILY : string  := "SuperCool";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 262144;       
	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := ""

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 

end SC_BRAM_PDP_16K;

-- ************************************************************************
-- Architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_BRAM_PDP_16K is

procedure READ_MEM_INIT_FILE(
                              f_name : IN    STRING;
                              v_MEM  : OUT   STD_LOGIC_VECTOR
                             ) IS

    file     f_INIT_FILE   : TEXT is MEM_INIT_FILE;
    variable v_WORD        : line;
    variable v_GOODFLAG    : boolean;
    variable v_WORD_BIT    : string (WDATA_WIDTH_A downto 1) ;
    variable v_CHAR        : character;
    variable v_OFFSET      : integer := 0;
    variable v_LINE        : integer := 0;

    begin      
      
      while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop

      readline(f_INIT_FILE, v_WORD);
      read(v_WORD, v_WORD_BIT, v_GOODFLAG);

      for k in 0 to WDATA_WIDTH_A - 1 loop
        v_CHAR := v_WORD_BIT (k + 1);
        if (v_CHAR = '1') then
          v_MEM(v_OFFSET + k) := '1';

	elsif (v_CHAR = '0') then
          v_MEM(v_OFFSET + k) := '0';

--	else 
--          v_MEM(v_OFFSET + k) := 'X';

	end if;
      end loop;

      v_LINE := v_LINE + 1;
      v_OFFSET := v_OFFSET + WDATA_WIDTH_A;

    end loop;

  end READ_MEM_INIT_FILE;

--------------------------------------------------------------------------
-- Function: Valid_Address 
-- Description: 
--------------------------------------------------------------------------
function Valid_Address (
    IN_ADDR : in std_logic_vector
 ) return boolean is

    variable v_Valid_Flag : boolean := TRUE;
 
begin

    for i in IN_ADDR'high downto IN_ADDR'low loop
        if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
            v_Valid_Flag := FALSE;
        end if;
    end loop;

    return v_Valid_Flag;
end Valid_Address;

--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------

--------- Local signals used to propagate input wire delay ---------------

signal WADA_node   : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node    : std_logic := 'X';
signal WDA_node    : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node   : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node    : std_logic := 'X';
signal RDA_node    : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');

signal WADB_node   : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node    : std_logic := 'X';
signal WDB_node    : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node   : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node    : std_logic := 'X';
signal RDB_node    : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');

-- architecture
begin 

 WADA_node <= WADA;
 WEA_node  <= WEA;
 WDA_node  <= WDA;
 RADA_node <= RADA;
 REA_node  <= REA;
 RDA       <= RDA_node;
 
 WADB_node <= WADB;
 WEB_node  <= WEB;
 WDB_node  <= WDB;
 RADB_node <= RADB;
 REB_node  <= REB;
 RDB       <= RDB_node;

-----------------------------------------
--------- Behavior process  -------------
-----------------------------------------


  KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)


--TSPEC: A note about sram initial values and rom mode: 
--       If the user does not provide any values, ... default 0 
--       for all ram locations in JECED
    variable v_MEM         : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' ); 
    variable v_INI_DONE    : boolean := FALSE;
    variable v_WADDR_A     : integer ;
    variable v_RADDR_A     : integer ;
    variable v_WADDR_B     : integer ;
    variable v_RADDR_B     : integer ;

    variable v_WADDRA_Valid_Flag : boolean := TRUE;
    variable v_WADDRB_Valid_Flag : boolean := TRUE;
    variable v_RADDRA_Valid_Flag : boolean := TRUE;
    variable v_RADDRB_Valid_Flag : boolean := TRUE;

  begin -- Process
   
    if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
	READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
	v_INI_DONE := TRUE;
    end if;

  -- Address Check    
    v_WADDRA_Valid_Flag := Valid_Address(WADA_node);	
    v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
    v_RADDRA_Valid_Flag := Valid_Address(RADA_node);	
    v_RADDRB_Valid_Flag := Valid_Address(RADB_node);

    if ( v_WADDRA_Valid_Flag = TRUE ) then
 	v_WADDR_A := CONV_INTEGER(WADA_node);
--    else	
--      assert (Now = 0 ps) 
--        report "Write AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_WADDRB_Valid_Flag = TRUE ) then
      v_WADDR_B := CONV_INTEGER(WADB_node);
    else
--      assert (Now = 0 ps)
--        report "Write AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRA_Valid_Flag = TRUE ) then
      v_RADDR_A := CONV_INTEGER(RADA_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRB_Valid_Flag = TRUE ) then
      v_RADDR_B := CONV_INTEGER(RADB_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

  -- CHECK Operation
    if (WEA = '1' and WEB = '1' and 
         not( 
          (v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B) 
                         or
          (v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
         )
        ) then
      assert false
        report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
        severity warning;
    end if;  

  -- MEM Operation	
    if (WEA_node = '1') then
        v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
    end if;

    if (WEB_node = '1') then
        v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
    end if;

    if (REA_node = '1') then
       RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
--    else
--       RDA_node <= ( others => 'X');
    end if;
    
    if (REB_node = '1') then
       RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
--    else
--       RDB_node <= ( others => 'X');
    end if;
    
  end process KERNEL_BEHAV;
    
end LATTICE_BEHAV;


-- ************************************************************************
--
--  Block Memory: Behavioral Model
--  The kernel of other RAM applications  
--
-- ************************************************************************
--
--  Init: Sep. 10, 2001
--  Written by: Zhou Xiao-qiu
--  Email: xqzhou@lscsh.latticesemi.com
--  Tel: 86-21-64852865 ext. 224/226
--
-- ************************************************************************
--
--  Filename:  SC_BLOCK_RAM.vhd
--  Description: 16K X 1  BRAM behavioral model. 
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
library std;
use std.textio.all;

library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;


-- ************************************************************************
-- Entity definition  
-- "generic" members 
-- ************************************************************************

entity SC_BRAM_16K_L is

  generic (

	 DEVICE_FAMILY : string  := "SuperCool";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 262144;       
	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := ""

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 

end SC_BRAM_16K_L;

-- ************************************************************************
-- Architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_BRAM_16K_L is

procedure READ_MEM_INIT_FILE(
                              f_name : IN    STRING;
                              v_MEM  : OUT   STD_LOGIC_VECTOR
                             ) IS

    file     f_INIT_FILE   : TEXT is MEM_INIT_FILE;
    variable v_WORD        : line;
    variable v_GOODFLAG    : boolean;
    variable v_WORD_BIT    : string (WDATA_WIDTH_A downto 1) ;
    variable v_CHAR        : character;
    variable v_OFFSET      : integer := 0;
    variable v_LINE        : integer := 0;

    begin      
      
      while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop

      readline(f_INIT_FILE, v_WORD);
      read(v_WORD, v_WORD_BIT, v_GOODFLAG);

      for k in 0 to WDATA_WIDTH_A - 1 loop
        v_CHAR := v_WORD_BIT (k + 1);
        if (v_CHAR = '1') then
          v_MEM(v_OFFSET + k) := '1';

	elsif (v_CHAR = '0') then
          v_MEM(v_OFFSET + k) := '0';

--	else 
--          v_MEM(v_OFFSET + k) := 'X';

	end if;
      end loop;

      v_LINE := v_LINE + 1;
      v_OFFSET := v_OFFSET + WDATA_WIDTH_A;

    end loop;

  end READ_MEM_INIT_FILE;
--------------------------------------------------------------------------
-- Function: Valid_Address 
-- Description: 
--------------------------------------------------------------------------
function Valid_Address (
    IN_ADDR : in std_logic_vector
 ) return boolean is

    variable v_Valid_Flag : boolean := TRUE;
 
begin

    for i in IN_ADDR'high downto IN_ADDR'low loop
        if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
            v_Valid_Flag := FALSE;
        end if;
    end loop;

    return v_Valid_Flag;
end Valid_Address;

--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------

--------- Local signals used to propagate input wire delay ---------------

signal WADA_node   : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node    : std_logic := 'X';
signal WDA_node    : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node   : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node    : std_logic := 'X';
signal RDA_node    : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');

signal WADB_node   : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node    : std_logic := 'X';
signal WDB_node    : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node   : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node    : std_logic := 'X';
signal RDB_node    : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');

-- architecture
begin 

 WADA_node <= WADA;
 WEA_node  <= WEA;
 WDA_node  <= WDA;
 RADA_node <= RADA;
 REA_node  <= REA;
 RDA       <= RDA_node;
 
 WADB_node <= WADB;
 WEB_node  <= WEB;
 WDB_node  <= WDB;
 RADB_node <= RADB;
 REB_node  <= REB;
 RDB       <= RDB_node;

-----------------------------------------
--------- Behavior process  -------------
-----------------------------------------

  KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)


--TSPEC: A note about sram initial values and rom mode: 
--       If the user does not provide any values, ... default 0 
--       for all ram locations in JECED
--QQ 7_17 variable v_MEM         : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' ); 

    variable v_MEM         : std_logic_vector(ARRAY_SIZE*WDATA_WIDTH_A + WDATA_WIDTH_A - 1 downto 0) := ( others => '0' ); 
    variable v_INI_DONE    : boolean := FALSE;
    variable v_WADDR_A     : integer;
    variable v_RADDR_A     : integer;
    variable v_WADDR_B     : integer;
    variable v_RADDR_B     : integer;

    variable v_WADDRA_Valid_Flag : boolean := TRUE;
    variable v_WADDRB_Valid_Flag : boolean := TRUE;
    variable v_RADDRA_Valid_Flag : boolean := TRUE;
    variable v_RADDRB_Valid_Flag : boolean := TRUE;

  begin -- Process
   
    if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
	READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
	v_INI_DONE := TRUE;
    end if;

  -- Address Check    
    v_WADDRA_Valid_Flag := Valid_Address(WADA_node);	
    v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
    v_RADDRA_Valid_Flag := Valid_Address(RADA_node);	
    v_RADDRB_Valid_Flag := Valid_Address(RADB_node);

    if ( v_WADDRA_Valid_Flag = TRUE ) then
 	v_WADDR_A := CONV_INTEGER(WADA_node);
--    else	
--      assert (Now = 0 ps) 
--        report "Write AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_WADDRB_Valid_Flag = TRUE ) then
      v_WADDR_B := CONV_INTEGER(WADB_node);
--    else
--      assert (Now = 0 ps)
--        report "Write AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRA_Valid_Flag = TRUE ) then
      v_RADDR_A := CONV_INTEGER(RADA_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRB_Valid_Flag = TRUE ) then
      v_RADDR_B := CONV_INTEGER(RADB_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

  -- CHECK Operation
    if (WEA = '1' and WEB = '1' and 
       (v_WADDR_A*WDATA_WIDTH_A = v_WADDR_B*WDATA_WIDTH_B
              or
           (WDATA_WIDTH_A > WDATA_WIDTH_B and 
           (v_WADDR_A+1)*WDATA_WIDTH_A > v_WADDR_B*WDATA_WIDTH_B and
           v_WADDR_A*WDATA_WIDTH_A <= v_WADDR_B*WDATA_WIDTH_B)
              or
           (WDATA_WIDTH_B > WDATA_WIDTH_A and 
           (v_WADDR_B+1)*WDATA_WIDTH_B > v_WADDR_B*WDATA_WIDTH_A and
           v_WADDR_B*WDATA_WIDTH_B <= v_WADDR_A*WDATA_WIDTH_A)
          )) then
      assert false
        report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
        severity warning;
    end if;  

  -- MEM Operation	
    if (WEA_node = '1') then
        v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
    end if;

    if (WEB_node = '1') then
        v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
    end if;

    if (REA_node = '1') then
       RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
--    else
--       RDA_node <= ( others => 'X');
    end if;
    
    if (REB_node = '1') then
       RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
--    else
--       RDB_node <= ( others => 'X');
    end if;
    
  end process KERNEL_BEHAV;
    
end LATTICE_BEHAV;




library std;
use std.textio.all;

library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;


-- ************************************************************************
-- Entity definition  
-- "generic" members 
-- ************************************************************************

entity SC_BRAM_PDP_16K_L is

  generic (

	 DEVICE_FAMILY : string  := "SuperCool";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 262144;       
	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := ""

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 

end SC_BRAM_PDP_16K_L;

-- ************************************************************************
-- Architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_BRAM_PDP_16K_L is

procedure READ_MEM_INIT_FILE(
                              f_name : IN    STRING;
                              v_MEM  : OUT   STD_LOGIC_VECTOR
                             ) IS

    file     f_INIT_FILE   : TEXT is MEM_INIT_FILE;
    variable v_WORD        : line;
    variable v_GOODFLAG    : boolean;
    variable v_WORD_BIT    : string (WDATA_WIDTH_A downto 1) ;
    variable v_CHAR        : character;
    variable v_OFFSET      : integer := 0;
    variable v_LINE        : integer := 0;

    begin      
      
      while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop

      readline(f_INIT_FILE, v_WORD);
      read(v_WORD, v_WORD_BIT, v_GOODFLAG);

      for k in 0 to WDATA_WIDTH_A - 1 loop
        v_CHAR := v_WORD_BIT (k + 1);
        if (v_CHAR = '1') then
          v_MEM(v_OFFSET + k) := '1';

	elsif (v_CHAR = '0') then
          v_MEM(v_OFFSET + k) := '0';

--	else 
--          v_MEM(v_OFFSET + k) := 'X';

	end if;
      end loop;

      v_LINE := v_LINE + 1;
      v_OFFSET := v_OFFSET + WDATA_WIDTH_A;

    end loop;

  end READ_MEM_INIT_FILE;

--------------------------------------------------------------------------
-- Function: Valid_Address 
-- Description: 
--------------------------------------------------------------------------
function Valid_Address (
    IN_ADDR : in std_logic_vector
 ) return boolean is

    variable v_Valid_Flag : boolean := TRUE;
 
begin

    for i in IN_ADDR'high downto IN_ADDR'low loop
        if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
            v_Valid_Flag := FALSE;
        end if;
    end loop;

    return v_Valid_Flag;
end Valid_Address;

--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------

--------- Local signals used to propagate input wire delay ---------------

signal WADA_node   : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node    : std_logic := 'X';
signal WDA_node    : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node   : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node    : std_logic := 'X';
signal RDA_node    : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');

signal WADB_node   : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node    : std_logic := 'X';
signal WDB_node    : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node   : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node    : std_logic := 'X';
signal RDB_node    : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');

-- architecture
begin 

 WADA_node <= WADA;
 WEA_node  <= WEA;
 WDA_node  <= WDA;
 RADA_node <= RADA;
 REA_node  <= REA;
 RDA       <= RDA_node;
 
 WADB_node <= WADB;
 WEB_node  <= WEB;
 WDB_node  <= WDB;
 RADB_node <= RADB;
 REB_node  <= REB;
 RDB       <= RDB_node;

-----------------------------------------
--------- Behavior process  -------------
-----------------------------------------

  KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)


--TSPEC: A note about sram initial values and rom mode: 
--       If the user does not provide any values, ... default 0 
--       for all ram locations in JECED

          variable v_MEM         : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );  

    variable v_INI_DONE    : boolean := FALSE;
    variable v_WADDR_A     : integer;
    variable v_RADDR_A     : integer;
    variable v_WADDR_B     : integer;
    variable v_RADDR_B     : integer;

    variable v_WADDRA_Valid_Flag : boolean := TRUE;
    variable v_WADDRB_Valid_Flag : boolean := TRUE;
    variable v_RADDRA_Valid_Flag : boolean := TRUE;
    variable v_RADDRB_Valid_Flag : boolean := TRUE;

  begin -- Process
   
    if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
	READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
	v_INI_DONE := TRUE;
    end if;

  -- Address Check    
    v_WADDRA_Valid_Flag := Valid_Address(WADA_node);	
    v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
    v_RADDRA_Valid_Flag := Valid_Address(RADA_node);	
    v_RADDRB_Valid_Flag := Valid_Address(RADB_node);

    if ( v_WADDRA_Valid_Flag = TRUE ) then
 	v_WADDR_A := CONV_INTEGER(WADA_node);
--    else	
--      assert (Now = 0 ps) 
--        report "Write AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_WADDRB_Valid_Flag = TRUE ) then
      v_WADDR_B := CONV_INTEGER(WADB_node);
--    else
--      assert (Now = 0 ps)
--        report "Write AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRA_Valid_Flag = TRUE ) then
      v_RADDR_A := CONV_INTEGER(RADA_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRB_Valid_Flag = TRUE ) then
      v_RADDR_B := CONV_INTEGER(RADB_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

  -- CHECK Operation
    if (WEA = '1' and WEB = '1' and 
         not( 
          (v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B) 
                         or
          (v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
         )
        ) then
      assert false
        report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
        severity warning;
    end if;  

  -- MEM Operation	
    if (WEA_node = '1') then
        v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
    end if;

    if (WEB_node = '1') then
        v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
    end if;

    if (REA_node = '1') then
       RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
--    else
--       RDA_node <= ( others => 'X');
    end if;
    
    if (REB_node = '1') then
       RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
--    else
--       RDB_node <= ( others => 'X');
    end if;
    
  end process KERNEL_BEHAV;
    
end LATTICE_BEHAV;



---------------------------------------------------------
--
--  CAM (Content Addressable Memory)
--  Behavioral Model
--  VHDL
--
---------------------------------------------------------
--
-- Init: Nov. 2001
-- Written by: Zhou Xiao-qiu (Sean ZHOU)
-- Email: xqzhou@lscsh.latticesemi.com
-- Tel: 86-21-64852865 ext. 226
--
---------------------------------------------------------
-- 
-- Filename: SC_CAM.vhd
-- Description: CAM behavioral model.
--
---------------------------------------------------------
--
--
-- Main Body of CAM Description
-- 
--
--
---------------------------------------------------------
-- History
--1. 12.5 Support "Z" as never match;
--
---------------------------------------------------------
-- Library Declarations
---------------------------------------------------------

library ieee;
use  ieee.std_logic_1164.all;
use  ieee.std_logic_unsigned.all;
use  ieee.std_logic_arith.all;
use  std.textio.all;

---------------------------------------------------------
-- Main Entity SC_CAM_16K
-- Description: 
---------------------------------------------------------

entity SC_CAM_16K is

	generic (
		DEVICE_FAMILY : string  := "SuperCool";
		ADDR_WIDTH    : integer :=  7;
		DATA_WIDTH    : integer := 48;
                MEM_INIT_FLAG : integer :=  0;  
	        MEM_INIT_FILE : string  := ""
		);
	port (
		CE        :  in  STD_LOGIC ;
		WE        :  in  STD_LOGIC ;
		CLK       :  in  STD_LOGIC ;
		EN_MASK   :  in  STD_LOGIC ;
		WR_MASK   :  in  STD_LOGIC ;
		WR_DC     :  in  STD_LOGIC ;
		RST       :  in  STD_LOGIC ;
		CS        :  in  STD_LOGIC_VECTOR ( 1 downto 0) ;
		WAD       :  in  STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0);
		WD        :  in  STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0);
		CO        :  out STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0);
		MATCH     :  out STD_LOGIC;
		MUL_MATCH :  out STD_LOGIC
		);

end SC_CAM_16K ;

---------------------------------------------------------
-- Architecture LATTICE_BEHAV for Entity SC_CAM_16K
---------------------------------------------------------

architecture LATTICE_BEHAV of SC_CAM_16K is

---------------------------------------------------------
-- Procedure: READ_CAM_INIT_FILE
-- Return: 
---------------------------------------------------------
procedure READ_CAM_INIT_FILE(
                              f_name : IN    STRING;
                              v_MEM  : OUT   STD_LOGIC_VECTOR
                             ) IS

    file     f_INIT_FILE   : TEXT is MEM_INIT_FILE;
    variable v_WORD        : line;
    variable v_GOODFLAG    : boolean;
    variable v_WORD_BIT    : string (DATA_WIDTH downto 1) ;
    variable v_CHAR        : character;
    variable v_OFFSET      : integer := 0;
    variable v_LINE        : integer := 0;

    begin      
      
      while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**ADDR_WIDTH)) loop

      readline(f_INIT_FILE, v_WORD);
      read(v_WORD, v_WORD_BIT, v_GOODFLAG);

      for k in 0 to DATA_WIDTH - 1 loop
        v_CHAR := v_WORD_BIT (k + 1);
        if (v_CHAR = '1') then
          v_MEM(v_OFFSET + k) := '1';

	elsif (v_CHAR = '0') then
          v_MEM(v_OFFSET + k) := '0';

	elsif (v_CHAR = 'X') then
          v_MEM(v_OFFSET + k) := 'X';

--Support Never Match<
	elsif (v_CHAR = 'Z') then
          v_MEM(v_OFFSET + k) := 'Z';
	end if;
--Support Never Match>
      end loop;

      v_LINE := v_LINE + 1;
      v_OFFSET := v_OFFSET + DATA_WIDTH;

    end loop;

  end READ_CAM_INIT_FILE;


---------------------------------------------------------
-- Function: TO_STRING
-- Return: STD_LOGIC_VECTOR TO STRING
---------------------------------------------------------
 function TO_STRING ( INPUT_VECTOR : std_logic_vector; INPUT_LENGTH: integer)
 return string is

   variable vDATA_STRI: string(INPUT_LENGTH downto 1);
   variable vTRANS: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
 
 begin 
    vTRANS := INPUT_VECTOR;

    for i in INPUT_LENGTH downto 1 loop
      if (vTRANS(i-1) = '1') then
        vDATA_STRI(i) := '1';
      elsif ( vTRANS(i-1) ='0') then
        vDATA_STRI(i) := '0';
      end if;  
    end loop;

  return vDATA_STRI; 	  
 end TO_STRING; 

---------------------------------------------------------
-- Function: WRITE_DATA_ENCODER
-- Return: DATA to write to MEM Array
---------------------------------------------------------
 function WRITE_DATA_ENCODER ( WR_DONT_CARE: std_logic; 
                               UPDATA_DATA : std_logic_vector;
			       MASK_DATA   : std_logic_vector;
			       EN_MASK_REG : std_logic
			      )
 return std_logic_vector is
   variable vWRITE_DATA : std_logic_vector(DATA_WIDTH -1 downto 0) := (others => 'U');
 begin 
	if (EN_MASK_REG = '0') then 
	  vWRITE_DATA := UPDATA_DATA;
	elsif (EN_MASK_REG = '1') then
	  for i in MASK_DATA'low to MASK_DATA'high loop
	    if (MASK_DATA(i) = '0') then
	    	vWRITE_DATA(i) := UPDATA_DATA(i);
	    elsif ( MASK_DATA(i) = '1' and WR_DONT_CARE = '1') then
	    	vWRITE_DATA(i) := 'X';
	    end if;
	  end loop;
        end if;

	return vWRITE_DATA;
 end WRITE_DATA_ENCODER;

---------------------------------------------------------
-- Function: COMPARE_DATA_ENCODER
-- Return: DATA to Compare with MEM contain
---------------------------------------------------------
 function COMPARE_DATA_ENCODER ( COMPARE_DATA : std_logic_vector;
 			         MASK_DATA    : std_logic_vector;
			       	 EN_MASK_REG  : std_logic
				 )
 return std_logic_vector is
   variable vCOMPARE_DATA : std_logic_vector(DATA_WIDTH -1 downto 0) := (others => 'U');
 begin 
	if (EN_MASK_REG = '0') then 
	  vCOMPARE_DATA := COMPARE_DATA;
	elsif (EN_MASK_REG = '1') then
	  for i in MASK_DATA'low to MASK_DATA'high loop
	    if (MASK_DATA(i) = '0') then
	    	vCOMPARE_DATA(i) := COMPARE_DATA(i);
	    elsif ( MASK_DATA(i) = '1' ) then
	    	vCOMPARE_DATA(i) := 'X';
	    end if;
	  end loop;
	end if;

	return vCOMPARE_DATA;
	
 end COMPARE_DATA_ENCODER;
						       
---------------------------------------------------------
-- Function: OUTPUT_ENCODER
-- Return: Binary encoded address
---------------------------------------------------------
 function OUTPUT_ENCODER (UNEN_CAM_OUT: std_logic_vector)
 return std_logic_vector is
   variable vPOINTER : integer := 0;
   variable default_value : std_logic_vector(ADDR_WIDTH-1 downto 0);
 begin
        default_value(ADDR_WIDTH-1) := '1';
        default_value(ADDR_WIDTH-2 downto 0) := (others => '0');

        if (UNEN_CAM_OUT = 0) then
            vPOINTER := CONV_INTEGER(default_value);
        end if;

 	for i in UNEN_CAM_OUT'high downto UNEN_CAM_OUT'low loop
	  if (UNEN_CAM_OUT(i) = '1') then
	    vPOINTER := i;
	  end if;
	end loop;
	
	return CONV_STD_LOGIC_VECTOR(vPOINTER, ADDR_WIDTH);
 end OUTPUT_ENCODER;

---------------------------------------------------------
-- Function: MATCH_FLAG
-- Return: MATCH_OUT Flag 
---------------------------------------------------------
 function MATCH_FLAG (UNEN_CAM_OUT: std_logic_vector)
 return std_logic is
   variable vMATCH_FLAG: std_logic := '0';
 begin
        vMATCH_FLAG := '0';
	for i in 0 to 2**ADDR_WIDTH -1 loop
	  if (UNEN_CAM_OUT(i) = '1') then
	    vMATCH_FLAG := '1';
	    return vMATCH_FLAG;
	  end if;
	end loop;
	return vMATCH_FLAG;

 end MATCH_FLAG;

---------------------------------------------------------
-- Function: MUL_MATCH_FLAG
-- Return: MUL_MATCH_OUT Flag 
---------------------------------------------------------
 function MUL_MATCH_FLAG (UNEN_CAM_OUT: std_logic_vector)
 return std_logic is

   variable vMUL_MATCH_FLAG: std_logic := '0';
   variable vMATCH_COUNTE: integer := 0;
 begin
 	for i in 0 to 2**ADDR_WIDTH -1 loop
	  if (UNEN_CAM_OUT(i) = '1') then
	    vMATCH_COUNTE := vMATCH_COUNTE + 1;
	  end if;
	end loop;

	
	if (vMATCH_COUNTE > 1) then
	  vMUL_MATCH_FLAG := '1';
        else
	  vMUL_MATCH_FLAG := '0';
	end if;
	
	return vMUL_MATCH_FLAG;

 end MUL_MATCH_FLAG;
---------------------------------------------------------
-- Function: WORD_COMPARE
-- Return: Compare Result
---------------------------------------------------------
 function WORD_COMPARE (BRAM_DATA : std_logic_vector;
 			COMP_DATA : std_logic_vector
			)
 return std_logic is
   variable vWORD_FLAG: std_logic := '1';
   variable vCOMP_SECT: std_logic_vector(DATA_WIDTH -1 downto 0) := (others => '0');
 begin
 	vCOMP_SECT := BRAM_DATA;
	
 	for i in vCOMP_SECT'low to vCOMP_SECT'high  loop
	  if ( COMP_DATA(i) /= 'X' and vCOMP_SECT(i) /= 'X') then
	    
	    if ( vCOMP_SECT(i) /= COMP_DATA(i) or vCOMP_SECT(i)= 'Z')  then
	      vWORD_FLAG := '0';
	      return vWORD_FLAG;
	    end if;
	  end if;
	end loop;
	
	return vWORD_FLAG;
 end WORD_COMPARE;

--------------------------------------------------------------------------
-- Function: Valid_Address 
-- Description: 
--------------------------------------------------------------------------
function Valid_Address (
    IN_ADDR : in std_logic_vector
 ) return boolean is

    variable v_Valid_Flag : boolean := TRUE;
 
begin

    for i in IN_ADDR'high downto IN_ADDR'low loop
        if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
            v_Valid_Flag := FALSE;
        end if;
    end loop;

    return v_Valid_Flag;
end Valid_Address;

---------------------------------------------------------
-- Signal Declaration 
---------------------------------------------------------

-- Input Nodes
 signal  CE_node        : STD_LOGIC := 'X' ;
 signal  WE_node        : STD_LOGIC := 'X' ;
 signal  CLK_node       : STD_LOGIC := 'X' ;
 signal  EN_MASK_node   : STD_LOGIC := 'X' ;
 signal  WR_MASK_node   : STD_LOGIC := 'X' ;
 signal  WR_DC_node     : STD_LOGIC := 'X' ;
 signal  RST_node       : STD_LOGIC := 'X' ;
 signal  CS_node        : STD_LOGIC_VECTOR ( 1 downto 0) := (others => 'X') ;
 signal  WAD_node       : STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0) := (others => 'X') ;
 signal  WD_node        : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;
 
-- Register Nodes  
 signal  EN_MASK_reg    : STD_LOGIC := 'X' ;
 signal  MASK_DATA_reg  : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;
 signal  COMP_DATA_reg  : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;
 signal  WAD_reg        : STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0) := (others => 'X') ;
 signal  WEN_reg        : STD_LOGIC := 'X' ;
 signal  WR_DC_reg      : STD_LOGIC := 'X' ;
 
-- From WRITE_DATA_ENCODER to CAM Array
 signal  WRITE_DATA_node   : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;

-- From COMPARE_DATA_ENCODER to CAM Array
 signal  COMPARE_DATA_node : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;
 
-- From CAM Array to MATCH_FLAG_LOGIC/ CAM_OUTPUT_ENCODER
 signal  UNEN_CAM_OUT_node : STD_LOGIC_VECTOR ( 2**ADDR_WIDTH -1 downto 0) := (others => 'X') ;

-- Output Nodes 
 signal  CO_node        : STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0) := (others => 'X') ;
 signal  MATCH_node     : STD_LOGIC := 'X' ;
 signal  MUL_MATCH_node : STD_LOGIC := 'X' ;

--------------------------------------------------------- 
-- Architecture 
---------------------------------------------------------
 begin


	CE_node      <= CE ;
	WE_node      <= WE ;
	CLK_node     <= CLK ;
	EN_MASK_node <= EN_MASK ;
	WR_MASK_node <= WR_MASK ;
	WR_DC_node   <= WR_DC ;
	RST_node     <= RST ;
	CS_node      <= CS ;
	WAD_node     <= WAD ;
	WD_node      <= WD ;
	
	CO           <= CO_node ;
	MATCH        <= MATCH_node ;
	MUL_MATCH    <= MUL_MATCH_node ;

Mul_Match_pro: process(UNEN_CAM_OUT_node)
     begin
	MUL_MATCH_node <= MUL_MATCH_FLAG(UNEN_CAM_OUT_node);
	MATCH_node     <= MATCH_FLAG(UNEN_CAM_OUT_node);
        CO_node      <= OUTPUT_ENCODER(UNEN_CAM_OUT_node);
     end process;

Write_Data_node_pro: process(WR_DC_reg, COMP_DATA_reg, MASK_DATA_reg, EN_MASK_reg)
     begin
	WRITE_DATA_node <= WRITE_DATA_ENCODER(WR_DC_reg, COMP_DATA_reg, MASK_DATA_reg, EN_MASK_reg);
     end process;

Compare_Data_pro: process(COMP_DATA_reg, MASK_DATA_reg, EN_MASK_reg)
     begin
	COMPARE_DATA_node <= COMPARE_DATA_ENCODER(COMP_DATA_reg, MASK_DATA_reg, EN_MASK_reg);
     end process;

   
---------------------------------------------------------
-- Process
-- Register EN_MASK/ COMP_DATA/ WAD/ WEN/ WR_DC inputs 
---------------------------------------------------------

  register_inputs: process (RST_node, CLK_node)
  begin
  	if (RST_node = '1') then
		EN_MASK_reg   <= '0';
		COMP_DATA_reg <= (others => '0');
		WAD_reg       <= (others => '0');
		WEN_reg        <= '0';
		WR_DC_reg     <= '0';
	elsif (CLK_node'event and CLK_node = '1') then
		if ( CE_node = '1') then
			EN_MASK_reg   <= EN_MASK_node;
			COMP_DATA_reg <= WD_node;
			WAD_reg       <= WAD_node;
			WEN_reg       <= WE_node and CS_node(0) and CS_node(1);
			WR_DC_reg     <= WR_DC_node;
		end if;
	end if;
  end process register_inputs;

---------------------------------------------------------
-- Process
-- Register WD input to MASK_DATA_reg  
-- Note:
-- TSPEC Rev D Page 64 of 96 Note 3 
-- "The reset on mask data register is not provided"
---------------------------------------------------------

  register_WD_2_MASK_DATA: process (CLK_node)
  begin
   	if (CLK_node'event and CLK_node = '1') then
		if ( CE_node = '1' and WR_MASK_node = '1') then
			MASK_DATA_reg <= WD_node;
		end if;
	end if;
  end process register_WD_2_MASK_DATA;

---------------------------------------------------------
-- Process
-- CAM_KERNEL
---------------------------------------------------------

  CAM_KERNEL : process (WEN_reg, WAD_reg, COMPARE_DATA_node, WRITE_DATA_node)
  	
    variable vADDR : integer := 0;
    variable vUNEN_CAM_OUT : std_logic_vector (2**ADDR_WIDTH -1 downto 0) := (others => '0');
    variable vMEM          : std_logic_vector (2**ADDR_WIDTH*DATA_WIDTH -1 downto 0) := ( others => 'Z');
    variable v_WAD_Valid_Flag : boolean := TRUE;
    variable v_INI_DONE    : boolean := FALSE;

    begin
    
    if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
	READ_CAM_INIT_FILE(MEM_INIT_FILE, vMEM);
	v_INI_DONE := TRUE;
    end if;

    v_WAD_Valid_Flag := Valid_Address(WAD_reg);	

    if (v_WAD_Valid_Flag = TRUE) then
 	vADDR := CONV_INTEGER(WAD_reg);

    --else
    --  assert false
    --    report "Write Address of Port contains invalid bit!"
    --    severity warning;

    end if;	

    if (WEN_reg = '1') then
    	vMEM((vADDR*DATA_WIDTH + DATA_WIDTH -1) downto (vADDR*DATA_WIDTH)) := WRITE_DATA_node;
        for i in 0 to 2**ADDR_WIDTH -1 loop
	  if (WORD_COMPARE(vMEM((i*DATA_WIDTH + DATA_WIDTH -1) downto (i*DATA_WIDTH)), COMPARE_DATA_node) = '1') then
            vUNEN_CAM_OUT(i) := '1';
          else 
	    vUNEN_CAM_OUT(i) := '0';
	  end if;
	UNEN_CAM_OUT_node(i) <= vUNEN_CAM_OUT(i);
	end loop;
--	UNEN_CAM_OUT_node <= vUNEN_CAM_OUT;
    
    elsif (WEN_reg = '0') then
    	for i in 0 to 2**ADDR_WIDTH -1 loop
	  if (WORD_COMPARE(vMEM((i*DATA_WIDTH + DATA_WIDTH -1) downto (i*DATA_WIDTH)), COMPARE_DATA_node) = '1') then
            vUNEN_CAM_OUT(i) := '1';
          else 
	    vUNEN_CAM_OUT(i) := '0';
	  end if;
	end loop;
	UNEN_CAM_OUT_node <= vUNEN_CAM_OUT;	
	    
    end if;


end process CAM_KERNEL;

end LATTICE_BEHAV;



---------------------------------------------------------
--
--  CAM (Content Addressable Memory)
--  Behavioral Model
--  VHDL
--
---------------------------------------------------------
--
-- Init: Apr. 2002
-- Written by: Zhou Xiao-qiu (Sean ZHOU)
-- Email: xqzhou@lscsh.latticesemi.com
-- Tel: 86-21-64852865 ext. 226
--
---------------------------------------------------------
-- 
-- Filename: SC_CAM_CL.vhd
-- Description: CAM behavioral model.
-- Used for width cascading left
--
---------------------------------------------------------
--
--
-- Main Body of CAM Description
-- 
--
--
---------------------------------------------------------
-- History
--1. 12.5 Support "Z" as never match;
--
---------------------------------------------------------
-- Library Declarations
---------------------------------------------------------

library ieee;
use  ieee.std_logic_1164.all;
use  ieee.std_logic_unsigned.all;
use  ieee.std_logic_arith.all;
use  std.textio.all;

---------------------------------------------------------
-- Main Entity SC_CAMCL_16K
-- Description: 
---------------------------------------------------------

entity SC_CAMCL_16K is

	generic (
		DEVICE_FAMILY : string := "SuperCool";
		ADDR_WIDTH    : integer :=  7;
		DATA_WIDTH    : integer := 48;
                MEM_INIT_FLAG : integer :=  0;  
	        MEM_INIT_FILE : string  := ""

		);
	port (
		CE        :  in  STD_LOGIC ;
		WE        :  in  STD_LOGIC ;
		CLK       :  in  STD_LOGIC ;
		EN_MASK   :  in  STD_LOGIC ;
		WR_MASK   :  in  STD_LOGIC ;
		WR_DC     :  in  STD_LOGIC ;
		RST       :  in  STD_LOGIC ;
		CS        :  in  STD_LOGIC_VECTOR ( 1 downto 0) ;
		WAD       :  in  STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0);
		WD        :  in  STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0);
		--CO        :  out STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0);
		--MATCH     :  out STD_LOGIC;
		--MUL_MATCH :  out STD_LOGIC
                CMO       : out  STD_LOGIC_VECTOR ( 2**ADDR_WIDTH -1 downto 0)
		);

end SC_CAMCL_16K ;




---------------------------------------------------------
-- Architecture LATTICE_BEHAV for Entity SC_CAMCL_16K
---------------------------------------------------------

architecture LATTICE_BEHAV of SC_CAMCL_16K is
---------------------------------------------------------
-- Procedure: READ_CAM_INIT_FILE
-- Return: 
---------------------------------------------------------
procedure READ_CAM_INIT_FILE(
                              f_name : IN    STRING;
                              v_MEM  : OUT   STD_LOGIC_VECTOR
                             ) IS

    file     f_INIT_FILE   : TEXT is MEM_INIT_FILE;
    variable v_WORD        : line;
    variable v_GOODFLAG    : boolean;
    variable v_WORD_BIT    : string (DATA_WIDTH downto 1) ;
    variable v_CHAR        : character;
    variable v_OFFSET      : integer := 0;
    variable v_LINE        : integer := 0;

    begin      
      
      while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**ADDR_WIDTH)) loop

      readline(f_INIT_FILE, v_WORD);
      read(v_WORD, v_WORD_BIT, v_GOODFLAG);

      for k in 0 to DATA_WIDTH - 1 loop
        v_CHAR := v_WORD_BIT (k + 1);
        if (v_CHAR = '1') then
          v_MEM(v_OFFSET + k) := '1';

	elsif (v_CHAR = '0') then
          v_MEM(v_OFFSET + k) := '0';

	elsif (v_CHAR = 'X') then
          v_MEM(v_OFFSET + k) := 'X';

--Support Never Match<
	elsif (v_CHAR = 'Z') then
          v_MEM(v_OFFSET + k) := 'Z';
	end if;
--Support Never Match>

      end loop;

      v_LINE := v_LINE + 1;
      v_OFFSET := v_OFFSET + DATA_WIDTH;

    end loop;

  end READ_CAM_INIT_FILE;


---------------------------------------------------------
-- Function: TO_STRING
-- Return: STD_LOGIC_VECTOR TO STRING
---------------------------------------------------------
 function TO_STRING ( INPUT_VECTOR : std_logic_vector; INPUT_LENGTH: integer)
 return string is

   variable vDATA_STRI: string(INPUT_LENGTH downto 1);
   variable vTRANS: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
 
 begin 
    vTRANS := INPUT_VECTOR;

    for i in INPUT_LENGTH downto 1 loop
      if (vTRANS(i-1) = '1') then
        vDATA_STRI(i) := '1';
      elsif ( vTRANS(i-1) ='0') then
        vDATA_STRI(i) := '0';
      end if;  
    end loop;

  return vDATA_STRI; 	  
 end TO_STRING; 

---------------------------------------------------------
-- Function: WRITE_DATA_ENCODER
-- Return: DATA to write to MEM Array
---------------------------------------------------------
 function WRITE_DATA_ENCODER ( WR_DONT_CARE: std_logic; 
                               UPDATA_DATA : std_logic_vector;
			       MASK_DATA   : std_logic_vector;
			       EN_MASK_REG : std_logic
			      )
 return std_logic_vector is
   variable vWRITE_DATA : std_logic_vector(DATA_WIDTH -1 downto 0) := (others => 'U');
 begin 
	if (EN_MASK_REG = '0') then 
	  vWRITE_DATA := UPDATA_DATA;
	elsif (EN_MASK_REG = '1') then
	  for i in MASK_DATA'low to MASK_DATA'high loop
	    if (MASK_DATA(i) = '0') then
	    	vWRITE_DATA(i) := UPDATA_DATA(i);
	    elsif ( MASK_DATA(i) = '1' and WR_DONT_CARE = '1') then
	    	vWRITE_DATA(i) := 'X';
	    end if;
	  end loop;
        end if;

	return vWRITE_DATA;
 end WRITE_DATA_ENCODER;

---------------------------------------------------------
-- Function: COMPARE_DATA_ENCODER
-- Return: DATA to Compare with MEM contain
---------------------------------------------------------
 function COMPARE_DATA_ENCODER ( COMPARE_DATA : std_logic_vector;
 			         MASK_DATA    : std_logic_vector;
			       	 EN_MASK_REG  : std_logic
				 )
 return std_logic_vector is
   variable vCOMPARE_DATA : std_logic_vector(DATA_WIDTH -1 downto 0) := (others => 'U');
 begin 
	if (EN_MASK_REG = '0') then 
	  vCOMPARE_DATA := COMPARE_DATA;
	elsif (EN_MASK_REG = '1') then
	  for i in MASK_DATA'low to MASK_DATA'high loop
	    if (MASK_DATA(i) = '0') then
	    	vCOMPARE_DATA(i) := COMPARE_DATA(i);
	    elsif ( MASK_DATA(i) = '1' ) then
	    	vCOMPARE_DATA(i) := 'X';
	    end if;
	  end loop;
	end if;

	return vCOMPARE_DATA;
	
 end COMPARE_DATA_ENCODER;
						       
---------------------------------------------------------
-- Function: OUTPUT_ENCODER
-- Return: Binary encoded address
---------------------------------------------------------
 function OUTPUT_ENCODER (UNEN_CAM_OUT: std_logic_vector)
 return std_logic_vector is
   variable vPOINTER : integer := 0;
   variable default_value : std_logic_vector(ADDR_WIDTH-1 downto 0);
 begin
        default_value(ADDR_WIDTH-1) := '1';
        default_value(ADDR_WIDTH-2 downto 0) := (others => '0');

        if (UNEN_CAM_OUT = 0) then
            vPOINTER := CONV_INTEGER(default_value);
        end if;

 	for i in UNEN_CAM_OUT'high downto UNEN_CAM_OUT'low loop
	  if (UNEN_CAM_OUT(i) = '1') then
	    vPOINTER := i;
	  end if;
	end loop;
	
	return CONV_STD_LOGIC_VECTOR(vPOINTER, ADDR_WIDTH);
 end OUTPUT_ENCODER;

---------------------------------------------------------
-- Function: WORD_COMPARE
-- Return: Compare Result
---------------------------------------------------------
 function WORD_COMPARE (BRAM_DATA : std_logic_vector;
 			COMP_DATA : std_logic_vector
			)
 return std_logic is
   variable vWORD_FLAG: std_logic := '1';
   variable vCOMP_SECT: std_logic_vector(DATA_WIDTH -1 downto 0) := (others => '0');
 begin
 	vCOMP_SECT := BRAM_DATA;
	
 	for i in vCOMP_SECT'low to vCOMP_SECT'high  loop
	  if ( COMP_DATA(i) /= 'X' and vCOMP_SECT(i) /= 'X') then
	    
	    if ( vCOMP_SECT(i) /= COMP_DATA(i) or vCOMP_SECT(i) = 'Z')  then
	      vWORD_FLAG := '0';
	      return vWORD_FLAG;
	    end if;
	  end if;
	end loop;
	
	return vWORD_FLAG;
 end WORD_COMPARE;

--------------------------------------------------------------------------
-- Function: Valid_Address 
-- Description: 
--------------------------------------------------------------------------
function Valid_Address (
    IN_ADDR : in std_logic_vector
 ) return boolean is

    variable v_Valid_Flag : boolean := TRUE;
 
begin

    for i in IN_ADDR'high downto IN_ADDR'low loop
        if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
            v_Valid_Flag := FALSE;
        end if;
    end loop;

    return v_Valid_Flag;
end Valid_Address;

---------------------------------------------------------
-- Signal Declaration 
---------------------------------------------------------

-- Input Nodes
 signal  CE_node        : STD_LOGIC := 'X' ;
 signal  WE_node        : STD_LOGIC := 'X' ;
 signal  CLK_node       : STD_LOGIC := 'X' ;
 signal  EN_MASK_node   : STD_LOGIC := 'X' ;
 signal  WR_MASK_node   : STD_LOGIC := 'X' ;
 signal  WR_DC_node     : STD_LOGIC := 'X' ;
 signal  RST_node       : STD_LOGIC := 'X' ;
 signal  CS_node        : STD_LOGIC_VECTOR ( 1 downto 0) := (others => 'X') ;
 signal  WAD_node       : STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0) := (others => 'X') ;
 signal  WD_node        : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;
 
-- Register Nodes  
 signal  EN_MASK_reg    : STD_LOGIC := 'X' ;
 signal  MASK_DATA_reg  : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;
 signal  COMP_DATA_reg  : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;
 signal  WAD_reg        : STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0) := (others => 'X') ;
 signal  WEN_reg        : STD_LOGIC := 'X' ;
 signal  WR_DC_reg      : STD_LOGIC := 'X' ;
 
-- From WRITE_DATA_ENCODER to CAM Array
 signal  WRITE_DATA_node   : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;

-- From COMPARE_DATA_ENCODER to CAM Array
 signal  COMPARE_DATA_node : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;
 
-- From CAM Array to MATCH_FLAG_LOGIC/ CAM_OUTPUT_ENCODER
 --signal  UNEN_CAM_OUT_node : STD_LOGIC_VECTOR ( 2**ADDR_WIDTH -1 downto 0) := (others => 'X') ;

-- Output Nodes 
 --signal  CO_node        : STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0) := (others => 'X') ;
 --signal  MATCH_node     : STD_LOGIC := 'X' ;
 --signal  MUL_MATCH_node : STD_LOGIC := 'X' ;
 signal  CMO_node         : STD_LOGIC_VECTOR ( 2**ADDR_WIDTH -1 downto 0);
--------------------------------------------------------- 
-- Architecture 
---------------------------------------------------------
 begin


	CE_node      <= CE ;
	WE_node      <= WE ;
	CLK_node     <= CLK ;
	EN_MASK_node <= EN_MASK ;
	WR_MASK_node <= WR_MASK ;
	WR_DC_node   <= WR_DC ;
	RST_node     <= RST ;
	CS_node      <= CS ;
	WAD_node     <= WAD ;
	WD_node      <= WD ;
	
--	CO           <= CO_node ;
--	MATCH        <= MATCH_node ;
--	MUL_MATCH    <= MUL_MATCH_node ;
--
--	MUL_MATCH_node <= MUL_MATCH_FLAG(UNEN_CAM_OUT_node);
--	MATCH_node     <= MATCH_FLAG(UNEN_CAM_OUT_node);
        CMO          <= CMO_node;

	WRITE_DATA_node <= WRITE_DATA_ENCODER(WR_DC_reg, COMP_DATA_reg, MASK_DATA_reg, EN_MASK_reg);
	COMPARE_DATA_node <= COMPARE_DATA_ENCODER(COMP_DATA_reg, MASK_DATA_reg, EN_MASK_reg);
        
--        CO_node      <= OUTPUT_ENCODER(UNEN_CAM_OUT_node);
   
---------------------------------------------------------
-- Process
-- Register EN_MASK/ COMP_DATA/ WAD/ WEN/ WR_DC inputs 
---------------------------------------------------------

  register_inputs: process (RST_node, CLK_node)
  begin
  	if (RST_node = '1') then
		EN_MASK_reg   <= '0';
		COMP_DATA_reg <= (others => '0');
		WAD_reg       <= (others => '0');
		WEN_reg        <= '0';
		WR_DC_reg     <= '0';
	elsif (CLK_node'event and CLK_node = '1') then
		if ( CE_node = '1') then
			EN_MASK_reg   <= EN_MASK_node;
			COMP_DATA_reg <= WD_node;
			WAD_reg       <= WAD_node;
			WEN_reg       <= WE_node and CS_node(0) and CS_node(1);
			WR_DC_reg     <= WR_DC_node;
		end if;
	end if;
  end process register_inputs;

---------------------------------------------------------
-- Process
-- Register WD input to MASK_DATA_reg  
-- Note:
-- TSPEC Rev D Page 64 of 96 Note 3 
-- "The reset on mask data register is not provided"
---------------------------------------------------------

  register_WD_2_MASK_DATA: process (CLK_node)
  begin
   	if (CLK_node'event and CLK_node = '1') then
		if ( CE_node = '1' and WR_MASK_node = '1') then
			MASK_DATA_reg <= WD_node;
		end if;
	end if;
  end process register_WD_2_MASK_DATA;

---------------------------------------------------------
-- Process
-- CAM_KERNEL
---------------------------------------------------------

  CAM_KERNEL : process (WEN_reg, WAD_reg, COMPARE_DATA_node, WRITE_DATA_node)
  	
    variable vADDR : integer := 0;
    variable vUNEN_CAM_OUT : std_logic_vector (2**ADDR_WIDTH -1 downto 0) := (others => '0');
    variable vMEM          : std_logic_vector (2**ADDR_WIDTH*DATA_WIDTH -1 downto 0) := ( others => 'Z');
    variable v_WAD_Valid_Flag : boolean := TRUE;
    variable v_INI_DONE    : boolean := FALSE;

    begin
    
    if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
	READ_CAM_INIT_FILE(MEM_INIT_FILE, vMEM);
	v_INI_DONE := TRUE;
    end if;

    v_WAD_Valid_Flag := Valid_Address(WAD_reg);	

    if (v_WAD_Valid_Flag = TRUE) then
 	vADDR := CONV_INTEGER(WAD_reg);

    --else
    --  assert false
    --    report "Write Address of Port contains invalid bit!"
    --    severity warning;

    end if;	

    if (WEN_reg = '1') then
    	vMEM((vADDR*DATA_WIDTH + DATA_WIDTH -1) downto (vADDR*DATA_WIDTH)) := WRITE_DATA_node;
      for i in 0 to 2**ADDR_WIDTH -1 loop
	  if (WORD_COMPARE(vMEM((i*DATA_WIDTH + DATA_WIDTH -1) downto (i*DATA_WIDTH)), COMPARE_DATA_node) = '1') then
            vUNEN_CAM_OUT(i) := '1';

          else 
	    vUNEN_CAM_OUT(i) := '0';

    	  end if;
      end loop;

	--UNEN_CAM_OUT_node <= vUNEN_CAM_OUT;	
        CMO_node <= vUNEN_CAM_OUT;	
    
    elsif (WEN_reg = '0') then
    	for i in 0 to 2**ADDR_WIDTH -1 loop
	  if (WORD_COMPARE(vMEM((i*DATA_WIDTH + DATA_WIDTH -1) downto (i*DATA_WIDTH)), COMPARE_DATA_node) = '1') then
            vUNEN_CAM_OUT(i) := '1';

          else 
	    vUNEN_CAM_OUT(i) := '0';

    	  end if;
	end loop;

	--UNEN_CAM_OUT_node <= vUNEN_CAM_OUT;	
        CMO_node <= vUNEN_CAM_OUT;	

    end if;

		
end process CAM_KERNEL;

end LATTICE_BEHAV;



---------------------------------------------------------
--
--  CAM (Content Addressable Memory)
--  Behavioral Model
--  VHDL
--
---------------------------------------------------------
--
-- Init: Apr. 2002
-- Written by: Zhou Xiao-qiu (Sean ZHOU)
-- Email: xqzhou@lscsh.latticesemi.com
-- Tel: 86-21-64852865 ext. 226
--
---------------------------------------------------------
-- 
-- Filename: SC_CAM_CL.vhd
-- Description: CAM behavioral model.
-- Used for width cascading middle
--
---------------------------------------------------------
--
--
-- Main Body of CAM Description
-- 
--
--
---------------------------------------------------------
-- History
--1. 12.5 Support "Z" as never match;
--
---------------------------------------------------------
-- Library Declarations
---------------------------------------------------------

library ieee;
use  ieee.std_logic_1164.all;
use  ieee.std_logic_unsigned.all;
use  ieee.std_logic_arith.all;
use  std.textio.all;

---------------------------------------------------------
-- Main Entity SC_CAMCM_16K
-- Description: 
---------------------------------------------------------

entity SC_CAMCM_16K is

	generic (
		DEVICE_FAMILY : string := "SuperCool";
		ADDR_WIDTH    : integer :=  7;
		DATA_WIDTH    : integer := 48;
                MEM_INIT_FLAG : integer :=  0;  
	        MEM_INIT_FILE : string  := ""

		);
	port (
		CE        :  in  STD_LOGIC ;
		WE        :  in  STD_LOGIC ;
		CLK       :  in  STD_LOGIC ;
		EN_MASK   :  in  STD_LOGIC ;
		WR_MASK   :  in  STD_LOGIC ;
		WR_DC     :  in  STD_LOGIC ;
		RST       :  in  STD_LOGIC ;
		CS        :  in  STD_LOGIC_VECTOR ( 1 downto 0) ;
		WAD       :  in  STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0);
		WD        :  in  STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0);
                CMI       :  in  STD_LOGIC_VECTOR ( 2**ADDR_WIDTH -1 downto 0);
		--CO        :  out STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0);
		--MATCH     :  out STD_LOGIC;
		--MUL_MATCH :  out STD_LOGIC
                CMO       : out  STD_LOGIC_VECTOR ( 2**ADDR_WIDTH -1 downto 0)
		);

end SC_CAMCM_16K ;




---------------------------------------------------------
-- Architecture LATTICE_BEHAV for Entity SC_CAMCM_16K
---------------------------------------------------------

architecture LATTICE_BEHAV of SC_CAMCM_16K is
---------------------------------------------------------
-- Procedure: READ_CAM_INIT_FILE
-- Return: 
---------------------------------------------------------
procedure READ_CAM_INIT_FILE(
                              f_name : IN    STRING;
                              v_MEM  : OUT   STD_LOGIC_VECTOR
                             ) IS

    file     f_INIT_FILE   : TEXT is MEM_INIT_FILE;
    variable v_WORD        : line;
    variable v_GOODFLAG    : boolean;
    variable v_WORD_BIT    : string (DATA_WIDTH downto 1) ;
    variable v_CHAR        : character;
    variable v_OFFSET      : integer := 0;
    variable v_LINE        : integer := 0;

    begin      
      
      while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**ADDR_WIDTH)) loop

      readline(f_INIT_FILE, v_WORD);
      read(v_WORD, v_WORD_BIT, v_GOODFLAG);

      for k in 0 to DATA_WIDTH - 1 loop
        v_CHAR := v_WORD_BIT (k + 1);
        if (v_CHAR = '1') then
          v_MEM(v_OFFSET + k) := '1';

	elsif (v_CHAR = '0') then
          v_MEM(v_OFFSET + k) := '0';

	elsif (v_CHAR = 'X') then
          v_MEM(v_OFFSET + k) := 'X';

--Support Never Match<
	elsif (v_CHAR = 'Z') then
          v_MEM(v_OFFSET + k) := 'Z';
	end if;
--Support Never Match>

      end loop;

      v_LINE := v_LINE + 1;
      v_OFFSET := v_OFFSET + DATA_WIDTH;

    end loop;

  end READ_CAM_INIT_FILE;


---------------------------------------------------------
-- Function: TO_STRING
-- Return: STD_LOGIC_VECTOR TO STRING
---------------------------------------------------------
 function TO_STRING ( INPUT_VECTOR : std_logic_vector; INPUT_LENGTH: integer)
 return string is

   variable vDATA_STRI: string(INPUT_LENGTH downto 1);
   variable vTRANS: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
 
 begin 
    vTRANS := INPUT_VECTOR;

    for i in INPUT_LENGTH downto 1 loop
      if (vTRANS(i-1) = '1') then
        vDATA_STRI(i) := '1';
      elsif ( vTRANS(i-1) ='0') then
        vDATA_STRI(i) := '0';
      end if;  
    end loop;

  return vDATA_STRI; 	  
 end TO_STRING; 

---------------------------------------------------------
-- Function: WRITE_DATA_ENCODER
-- Return: DATA to write to MEM Array
---------------------------------------------------------
 function WRITE_DATA_ENCODER ( WR_DONT_CARE: std_logic; 
                               UPDATA_DATA : std_logic_vector;
			       MASK_DATA   : std_logic_vector;
			       EN_MASK_REG : std_logic
			      )
 return std_logic_vector is
   variable vWRITE_DATA : std_logic_vector(DATA_WIDTH -1 downto 0) := (others => 'U');
 begin 
	if (EN_MASK_REG = '0') then 
	  vWRITE_DATA := UPDATA_DATA;
	elsif (EN_MASK_REG = '1') then
	  for i in MASK_DATA'low to MASK_DATA'high loop
	    if (MASK_DATA(i) = '0') then
	    	vWRITE_DATA(i) := UPDATA_DATA(i);
	    elsif ( MASK_DATA(i) = '1' and WR_DONT_CARE = '1') then
	    	vWRITE_DATA(i) := 'X';
	    end if;
	  end loop;
        end if;

	return vWRITE_DATA;
 end WRITE_DATA_ENCODER;

---------------------------------------------------------
-- Function: COMPARE_DATA_ENCODER
-- Return: DATA to Compare with MEM contain
---------------------------------------------------------
 function COMPARE_DATA_ENCODER ( COMPARE_DATA : std_logic_vector;
 			         MASK_DATA    : std_logic_vector;
			       	 EN_MASK_REG  : std_logic
				 )
 return std_logic_vector is
   variable vCOMPARE_DATA : std_logic_vector(DATA_WIDTH -1 downto 0) := (others => 'U');
 begin 
	if (EN_MASK_REG = '0') then 
	  vCOMPARE_DATA := COMPARE_DATA;
	elsif (EN_MASK_REG = '1') then
	  for i in MASK_DATA'low to MASK_DATA'high loop
	    if (MASK_DATA(i) = '0') then
	    	vCOMPARE_DATA(i) := COMPARE_DATA(i);
	    elsif ( MASK_DATA(i) = '1' ) then
	    	vCOMPARE_DATA(i) := 'X';
	    end if;
	  end loop;
	end if;

	return vCOMPARE_DATA;
	
 end COMPARE_DATA_ENCODER;
						       
---------------------------------------------------------
-- Function: OUTPUT_ENCODER
-- Return: Binary encoded address
---------------------------------------------------------
 function OUTPUT_ENCODER (UNEN_CAM_OUT: std_logic_vector)
 return std_logic_vector is
   variable vPOINTER : integer := 0;
   variable default_value : std_logic_vector(ADDR_WIDTH-1 downto 0);
 begin
        default_value(ADDR_WIDTH-1) := '1';
        default_value(ADDR_WIDTH-2 downto 0) := (others => '0');

        if (UNEN_CAM_OUT = 0) then
            vPOINTER := CONV_INTEGER(default_value);
        end if;

 	for i in UNEN_CAM_OUT'high downto UNEN_CAM_OUT'low loop
	  if (UNEN_CAM_OUT(i) = '1') then
	    vPOINTER := i;
	  end if;
	end loop;
	
	return CONV_STD_LOGIC_VECTOR(vPOINTER, ADDR_WIDTH);
 end OUTPUT_ENCODER;

---------------------------------------------------------
-- Function: WORD_COMPARE
-- Return: Compare Result
---------------------------------------------------------
 function WORD_COMPARE (BRAM_DATA : std_logic_vector;
 			COMP_DATA : std_logic_vector
			)
 return std_logic is
   variable vWORD_FLAG: std_logic := '1';
   variable vCOMP_SECT: std_logic_vector(DATA_WIDTH -1 downto 0) := (others => '0');
 begin
 	vCOMP_SECT := BRAM_DATA;
	
 	for i in vCOMP_SECT'low to vCOMP_SECT'high  loop
	  if ( COMP_DATA(i) /= 'X' and vCOMP_SECT(i) /= 'X') then
	    
	    if ( vCOMP_SECT(i) /= COMP_DATA(i) or vCOMP_SECT(i) = 'Z')  then
	      vWORD_FLAG := '0';
	      return vWORD_FLAG;
	    end if;
	  end if;
	end loop;
	
	return vWORD_FLAG;
 end WORD_COMPARE;

--------------------------------------------------------------------------
-- Function: Valid_Address 
-- Description: 
--------------------------------------------------------------------------
function Valid_Address (
    IN_ADDR : in std_logic_vector
 ) return boolean is

    variable v_Valid_Flag : boolean := TRUE;
 
begin

    for i in IN_ADDR'high downto IN_ADDR'low loop
        if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
            v_Valid_Flag := FALSE;
        end if;
    end loop;

    return v_Valid_Flag;
end Valid_Address;

---------------------------------------------------------
-- Signal Declaration 
---------------------------------------------------------

-- Input Nodes
 signal  CE_node        : STD_LOGIC := 'X' ;
 signal  WE_node        : STD_LOGIC := 'X' ;
 signal  CLK_node       : STD_LOGIC := 'X' ;
 signal  EN_MASK_node   : STD_LOGIC := 'X' ;
 signal  WR_MASK_node   : STD_LOGIC := 'X' ;
 signal  WR_DC_node     : STD_LOGIC := 'X' ;
 signal  RST_node       : STD_LOGIC := 'X' ;
 signal  CS_node        : STD_LOGIC_VECTOR ( 1 downto 0) := (others => 'X') ;
 signal  WAD_node       : STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0) := (others => 'X') ;
 signal  WD_node        : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;
 
-- Register Nodes  
 signal  EN_MASK_reg    : STD_LOGIC := 'X' ;
 signal  MASK_DATA_reg  : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;
 signal  COMP_DATA_reg  : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;
 signal  WAD_reg        : STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0) := (others => 'X') ;
 signal  WEN_reg        : STD_LOGIC := 'X' ;
 signal  WR_DC_reg      : STD_LOGIC := 'X' ;
 
-- From WRITE_DATA_ENCODER to CAM Array
 signal  WRITE_DATA_node   : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;

-- From COMPARE_DATA_ENCODER to CAM Array
 signal  COMPARE_DATA_node : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;
 
-- From CAM Array to MATCH_FLAG_LOGIC/ CAM_OUTPUT_ENCODER
 --signal  UNEN_CAM_OUT_node : STD_LOGIC_VECTOR ( 2**ADDR_WIDTH -1 downto 0) := (others => 'X') ;

-- Output Nodes 
 --signal  CO_node        : STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0) := (others => 'X') ;
 --signal  MATCH_node     : STD_LOGIC := 'X' ;
 --signal  MUL_MATCH_node : STD_LOGIC := 'X' ;
 signal  CMI_node         : STD_LOGIC_VECTOR ( 2**ADDR_WIDTH -1 downto 0);
 signal  CMO_node         : STD_LOGIC_VECTOR ( 2**ADDR_WIDTH -1 downto 0);
--------------------------------------------------------- 
-- Architecture 
---------------------------------------------------------
 begin


	CE_node      <= CE ;
	WE_node      <= WE ;
	CLK_node     <= CLK ;
	EN_MASK_node <= EN_MASK ;
	WR_MASK_node <= WR_MASK ;
	WR_DC_node   <= WR_DC ;
	RST_node     <= RST ;
	CS_node      <= CS ;
	WAD_node     <= WAD ;
	WD_node      <= WD ;
        CMI_node     <= CMI ;	
--	CO           <= CO_node ;
--	MATCH        <= MATCH_node ;
--	MUL_MATCH    <= MUL_MATCH_node ;
--
--	MUL_MATCH_node <= MUL_MATCH_FLAG(UNEN_CAM_OUT_node);
--	MATCH_node     <= MATCH_FLAG(UNEN_CAM_OUT_node);
        CMO          <= CMO_node;

	WRITE_DATA_node <= WRITE_DATA_ENCODER(WR_DC_reg, COMP_DATA_reg, MASK_DATA_reg, EN_MASK_reg);
	COMPARE_DATA_node <= COMPARE_DATA_ENCODER(COMP_DATA_reg, MASK_DATA_reg, EN_MASK_reg);
        
--        CO_node      <= OUTPUT_ENCODER(UNEN_CAM_OUT_node);
   
---------------------------------------------------------
-- Process
-- Register EN_MASK/ COMP_DATA/ WAD/ WEN/ WR_DC inputs 
---------------------------------------------------------

  register_inputs: process (RST_node, CLK_node)
  begin
  	if (RST_node = '1') then
		EN_MASK_reg   <= '0';
		COMP_DATA_reg <= (others => '0');
		WAD_reg       <= (others => '0');
		WEN_reg        <= '0';
		WR_DC_reg     <= '0';
	elsif (CLK_node'event and CLK_node = '1') then
		if ( CE_node = '1') then
			EN_MASK_reg   <= EN_MASK_node;
			COMP_DATA_reg <= WD_node;
			WAD_reg       <= WAD_node;
			WEN_reg       <= WE_node and CS_node(0) and CS_node(1);
			WR_DC_reg     <= WR_DC_node;
		end if;
	end if;
  end process register_inputs;

---------------------------------------------------------
-- Process
-- Register WD input to MASK_DATA_reg  
-- Note:
-- TSPEC Rev D Page 64 of 96 Note 3 
-- "The reset on mask data register is not provided"
---------------------------------------------------------

  register_WD_2_MASK_DATA: process (CLK_node)
  begin
   	if (CLK_node'event and CLK_node = '1') then
		if ( CE_node = '1' and WR_MASK_node = '1') then
			MASK_DATA_reg <= WD_node;
		end if;
	end if;
  end process register_WD_2_MASK_DATA;

---------------------------------------------------------
-- Process
-- CAM_KERNEL
---------------------------------------------------------

  CAM_KERNEL : process (WEN_reg, WAD_reg, COMPARE_DATA_node, WRITE_DATA_node, CMI_node)
  	
    variable vADDR : integer := 0;
    variable vUNEN_CAM_OUT : std_logic_vector (2**ADDR_WIDTH -1 downto 0) := (others => '0');
    variable vMEM          : std_logic_vector (2**ADDR_WIDTH*DATA_WIDTH -1 downto 0) := ( others => 'Z');
    variable v_WAD_Valid_Flag : boolean := TRUE;
    variable v_INI_DONE    : boolean := FALSE;

    begin
    
    if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
	READ_CAM_INIT_FILE(MEM_INIT_FILE, vMEM);
	v_INI_DONE := TRUE;
    end if;

    v_WAD_Valid_Flag := Valid_Address(WAD_reg);	

    if (v_WAD_Valid_Flag = TRUE) then
 	vADDR := CONV_INTEGER(WAD_reg);

    --else
    --  assert false
    --    report "Write Address of Port contains invalid bit!"
    --    severity warning;

    end if;	

    if (WEN_reg = '1') then
    	vMEM((vADDR*DATA_WIDTH + DATA_WIDTH -1) downto (vADDR*DATA_WIDTH)) := WRITE_DATA_node;
	    	for i in 0 to 2**ADDR_WIDTH -1 loop
	  if (WORD_COMPARE(vMEM((i*DATA_WIDTH + DATA_WIDTH -1) downto (i*DATA_WIDTH)), COMPARE_DATA_node) = '1') then
            vUNEN_CAM_OUT(i) := '1';

          else 
	    vUNEN_CAM_OUT(i) := '0';

    	  end if;
	end loop;

	--UNEN_CAM_OUT_node <= vUNEN_CAM_OUT;	
        CMO_node <= vUNEN_CAM_OUT and CMI_node;	
    
    elsif (WEN_reg = '0') then
    	for i in 0 to 2**ADDR_WIDTH -1 loop
	  if (WORD_COMPARE(vMEM((i*DATA_WIDTH + DATA_WIDTH -1) downto (i*DATA_WIDTH)), COMPARE_DATA_node) = '1') then
            vUNEN_CAM_OUT(i) := '1';

          else 
	    vUNEN_CAM_OUT(i) := '0';

    	  end if;
	end loop;

	--UNEN_CAM_OUT_node <= vUNEN_CAM_OUT;	
        CMO_node <= vUNEN_CAM_OUT and CMI_node;	

    end if;

		
end process CAM_KERNEL;

end LATTICE_BEHAV;



---------------------------------------------------------
--
--  CAM (Content Addressable Memory)
--  Behavioral Model
--  VHDL
--
---------------------------------------------------------
--
-- Init: Apr. 2002
-- Written by: Zhou Xiao-qiu (Sean ZHOU)
-- Email: xqzhou@lscsh.latticesemi.com
-- Tel: 86-21-64852865 ext. 226
--
---------------------------------------------------------
-- 
-- Filename: SC_CAM_CL.vhd
-- Description: CAM behavioral model.
-- Used for width cascading right
--
---------------------------------------------------------
--
--
-- Main Body of CAM Description
-- 
--
--
---------------------------------------------------------
-- History
--1. 12.5 Support "Z" as never match;
--
---------------------------------------------------------
-- Library Declarations
---------------------------------------------------------

library ieee;
use  ieee.std_logic_1164.all;
use  ieee.std_logic_unsigned.all;
use  ieee.std_logic_arith.all;
use  std.textio.all;

---------------------------------------------------------
-- Main Entity SC_CAMCR_16K
-- Description: 
---------------------------------------------------------

entity SC_CAMCR_16K is

	generic (
		DEVICE_FAMILY : string := "SuperCool";
		ADDR_WIDTH    : integer :=  7;
		DATA_WIDTH    : integer := 48;
                MEM_INIT_FLAG : integer :=  0;  
	        MEM_INIT_FILE : string  := ""

		);
	port (
		CE        :  in  STD_LOGIC ;
		WE        :  in  STD_LOGIC ;
		CLK       :  in  STD_LOGIC ;
		EN_MASK   :  in  STD_LOGIC ;
		WR_MASK   :  in  STD_LOGIC ;
		WR_DC     :  in  STD_LOGIC ;
		RST       :  in  STD_LOGIC ;
		CS        :  in  STD_LOGIC_VECTOR ( 1 downto 0) ;
		WAD       :  in  STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0);
		WD        :  in  STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0);
                CMI       :  in  STD_LOGIC_VECTOR ( 2**ADDR_WIDTH -1 downto 0);
		CO        :  out STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0);
		MATCH     :  out STD_LOGIC;
		MUL_MATCH :  out STD_LOGIC
                );

end SC_CAMCR_16K ;




---------------------------------------------------------
-- Architecture LATTICE_BEHAV for Entity SC_CAMCR_16K
---------------------------------------------------------

architecture LATTICE_BEHAV of SC_CAMCR_16K is
---------------------------------------------------------
-- Procedure: READ_CAM_INIT_FILE
-- Return: 
---------------------------------------------------------
procedure READ_CAM_INIT_FILE(
                              f_name : IN    STRING;
                              v_MEM  : OUT   STD_LOGIC_VECTOR
                             ) IS

    file     f_INIT_FILE   : TEXT is MEM_INIT_FILE;
    variable v_WORD        : line;
    variable v_GOODFLAG    : boolean;
    variable v_WORD_BIT    : string (DATA_WIDTH downto 1) ;
    variable v_CHAR        : character;
    variable v_OFFSET      : integer := 0;
    variable v_LINE        : integer := 0;

    begin      
      
      while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**ADDR_WIDTH)) loop

      readline(f_INIT_FILE, v_WORD);
      read(v_WORD, v_WORD_BIT, v_GOODFLAG);

      for k in 0 to DATA_WIDTH - 1 loop
        v_CHAR := v_WORD_BIT (k + 1);
        if (v_CHAR = '1') then
          v_MEM(v_OFFSET + k) := '1';

	elsif (v_CHAR = '0') then
          v_MEM(v_OFFSET + k) := '0';

	elsif (v_CHAR = 'X') then
          v_MEM(v_OFFSET + k) := 'X';

--Support Never Match<
	elsif (v_CHAR = 'Z') then
          v_MEM(v_OFFSET + k) := 'Z';
	end if;
--Support Never Match>
      end loop;

      v_LINE := v_LINE + 1;
      v_OFFSET := v_OFFSET + DATA_WIDTH;

    end loop;

  end READ_CAM_INIT_FILE;


---------------------------------------------------------
-- Function: TO_STRING
-- Return: STD_LOGIC_VECTOR TO STRING
---------------------------------------------------------
 function TO_STRING ( INPUT_VECTOR : std_logic_vector; INPUT_LENGTH: integer)
 return string is

   variable vDATA_STRI: string(INPUT_LENGTH downto 1);
   variable vTRANS: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
 
 begin 
    vTRANS := INPUT_VECTOR;

    for i in INPUT_LENGTH downto 1 loop
      if (vTRANS(i-1) = '1') then
        vDATA_STRI(i) := '1';
      elsif ( vTRANS(i-1) ='0') then
        vDATA_STRI(i) := '0';
      end if;  
    end loop;

  return vDATA_STRI; 	  
 end TO_STRING; 

---------------------------------------------------------
-- Function: WRITE_DATA_ENCODER
-- Return: DATA to write to MEM Array
---------------------------------------------------------
 function WRITE_DATA_ENCODER ( WR_DONT_CARE: std_logic; 
                               UPDATA_DATA : std_logic_vector;
			       MASK_DATA   : std_logic_vector;
			       EN_MASK_REG : std_logic
			      )
 return std_logic_vector is
   variable vWRITE_DATA : std_logic_vector(DATA_WIDTH -1 downto 0) := (others => 'U');
 begin 
	if (EN_MASK_REG = '0') then 
	  vWRITE_DATA := UPDATA_DATA;
	elsif (EN_MASK_REG = '1') then
	  for i in MASK_DATA'low to MASK_DATA'high loop
	    if (MASK_DATA(i) = '0') then
	    	vWRITE_DATA(i) := UPDATA_DATA(i);
	    elsif ( MASK_DATA(i) = '1' and WR_DONT_CARE = '1') then
	    	vWRITE_DATA(i) := 'X';
	    end if;
	  end loop;
        end if;

	return vWRITE_DATA;
 end WRITE_DATA_ENCODER;

---------------------------------------------------------
-- Function: COMPARE_DATA_ENCODER
-- Return: DATA to Compare with MEM contain
---------------------------------------------------------
 function COMPARE_DATA_ENCODER ( COMPARE_DATA : std_logic_vector;
 			         MASK_DATA    : std_logic_vector;
			       	 EN_MASK_REG  : std_logic
				 )
 return std_logic_vector is
   variable vCOMPARE_DATA : std_logic_vector(DATA_WIDTH -1 downto 0) := (others => 'U');
 begin 
	if (EN_MASK_REG = '0') then 
	  vCOMPARE_DATA := COMPARE_DATA;
	elsif (EN_MASK_REG = '1') then
	  for i in MASK_DATA'low to MASK_DATA'high loop
	    if (MASK_DATA(i) = '0') then
	    	vCOMPARE_DATA(i) := COMPARE_DATA(i);
	    elsif ( MASK_DATA(i) = '1' ) then
	    	vCOMPARE_DATA(i) := 'X';
	    end if;
	  end loop;
	end if;

	return vCOMPARE_DATA;
	
 end COMPARE_DATA_ENCODER;
						       
---------------------------------------------------------
-- Function: OUTPUT_ENCODER
-- Return: Binary encoded address
---------------------------------------------------------
 function OUTPUT_ENCODER (UNEN_CAM_OUT: std_logic_vector)
 return std_logic_vector is
   variable vPOINTER : integer := 0;
   variable default_value : std_logic_vector(ADDR_WIDTH-1 downto 0);
 begin
        default_value(ADDR_WIDTH-1) := '1';
        default_value(ADDR_WIDTH-2 downto 0) := (others => '0');

        if (UNEN_CAM_OUT = 0) then
            vPOINTER := CONV_INTEGER(default_value);
        end if;

 	for i in UNEN_CAM_OUT'high downto UNEN_CAM_OUT'low loop
	  if (UNEN_CAM_OUT(i) = '1') then
	    vPOINTER := i;
	  end if;
	end loop;
	
	return CONV_STD_LOGIC_VECTOR(vPOINTER, ADDR_WIDTH);
 end OUTPUT_ENCODER;

---------------------------------------------------------
-- Function: MATCH_FLAG
-- Return: MATCH_OUT Flag 
---------------------------------------------------------
 function MATCH_FLAG (UNEN_CAM_OUT: std_logic_vector)
 return std_logic is
   variable vMATCH_FLAG: std_logic := '0';
 begin
         vMATCH_FLAG := '0';
 	for i in 0 to 2**ADDR_WIDTH -1 loop
	  if (UNEN_CAM_OUT(i) = '1') then
	    vMATCH_FLAG := '1';
	    return vMATCH_FLAG;
	  end if;
	end loop;

	return vMATCH_FLAG;

 end MATCH_FLAG;

---------------------------------------------------------
-- Function: MUL_MATCH_FLAG
-- Return: MUL_MATCH_OUT Flag 
---------------------------------------------------------
 function MUL_MATCH_FLAG (UNEN_CAM_OUT: std_logic_vector)
 return std_logic is

   variable vMUL_MATCH_FLAG: std_logic := '0';
   variable vMATCH_COUNTE: integer := 0;
 begin
 	for i in 0 to 2**ADDR_WIDTH -1 loop
	  if (UNEN_CAM_OUT(i) = '1') then
	    vMATCH_COUNTE := vMATCH_COUNTE + 1;
	  end if;
	end loop;

	if (vMATCH_COUNTE > 1) then
	  vMUL_MATCH_FLAG := '1';
        else 
	  vMUL_MATCH_FLAG := '0';
	end if;
	
	return vMUL_MATCH_FLAG;

 end MUL_MATCH_FLAG;
---------------------------------------------------------
-- Function: WORD_COMPARE
-- Return: Compare Result
---------------------------------------------------------
 function WORD_COMPARE (BRAM_DATA : std_logic_vector;
 			COMP_DATA : std_logic_vector
			)
 return std_logic is
   variable vWORD_FLAG: std_logic := '1';
   variable vCOMP_SECT: std_logic_vector(DATA_WIDTH -1 downto 0) := (others => '0');
 begin
 	vCOMP_SECT := BRAM_DATA;
	
 	for i in vCOMP_SECT'low to vCOMP_SECT'high  loop
	  if ( COMP_DATA(i) /= 'X' and vCOMP_SECT(i) /= 'X') then
	    
	    if ( vCOMP_SECT(i) /= COMP_DATA(i) or vCOMP_SECT(i)= 'Z')  then
	      vWORD_FLAG := '0';
	      return vWORD_FLAG;
	    end if;
	  end if;
	end loop;
	
	return vWORD_FLAG;
 end WORD_COMPARE;

--------------------------------------------------------------------------
-- Function: Valid_Address 
-- Description: 
--------------------------------------------------------------------------
function Valid_Address (
    IN_ADDR : in std_logic_vector
 ) return boolean is

    variable v_Valid_Flag : boolean := TRUE;
 
begin

    for i in IN_ADDR'high downto IN_ADDR'low loop
        if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
            v_Valid_Flag := FALSE;
        end if;
    end loop;

    return v_Valid_Flag;
end Valid_Address;

---------------------------------------------------------
-- Signal Declaration 
---------------------------------------------------------

-- Input Nodes
 signal  CE_node        : STD_LOGIC := 'X' ;
 signal  WE_node        : STD_LOGIC := 'X' ;
 signal  CLK_node       : STD_LOGIC := 'X' ;
 signal  EN_MASK_node   : STD_LOGIC := 'X' ;
 signal  WR_MASK_node   : STD_LOGIC := 'X' ;
 signal  WR_DC_node     : STD_LOGIC := 'X' ;
 signal  RST_node       : STD_LOGIC := 'X' ;
 signal  CS_node        : STD_LOGIC_VECTOR ( 1 downto 0) := (others => 'X') ;
 signal  WAD_node       : STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0) := (others => 'X') ;
 signal  WD_node        : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;
 
-- Register Nodes  
 signal  EN_MASK_reg    : STD_LOGIC := 'X' ;
 signal  MASK_DATA_reg  : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;
 signal  COMP_DATA_reg  : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;
 signal  WAD_reg        : STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0) := (others => 'X') ;
 signal  WEN_reg        : STD_LOGIC := 'X' ;
 signal  WR_DC_reg      : STD_LOGIC := 'X' ;
 
-- From WRITE_DATA_ENCODER to CAM Array
 signal  WRITE_DATA_node   : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;

-- From COMPARE_DATA_ENCODER to CAM Array
 signal  COMPARE_DATA_node : STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0) := (others => 'X') ;
 
-- From CAM Array to MATCH_FLAG_LOGIC/ CAM_OUTPUT_ENCODER
 signal  UNEN_CAM_OUT_node : STD_LOGIC_VECTOR ( 2**ADDR_WIDTH -1 downto 0) := (others => 'X') ;

-- Output Nodes 
 signal  CO_node        : STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0) := (others => 'X') ;
 signal  MATCH_node     : STD_LOGIC := 'X' ;
 signal  MUL_MATCH_node : STD_LOGIC := 'X' ;
 signal  CMI_node         : STD_LOGIC_VECTOR ( 2**ADDR_WIDTH -1 downto 0);
 
--------------------------------------------------------- 
-- Architecture 
---------------------------------------------------------
 begin


	CE_node      <= CE ;
	WE_node      <= WE ;
	CLK_node     <= CLK ;
	EN_MASK_node <= EN_MASK ;
	WR_MASK_node <= WR_MASK ;
	WR_DC_node   <= WR_DC ;
	RST_node     <= RST ;
	CS_node      <= CS ;
	WAD_node     <= WAD ;
	WD_node      <= WD ;
        CMI_node     <= CMI ;	
	CO           <= CO_node ;
	MATCH        <= MATCH_node ;
	MUL_MATCH    <= MUL_MATCH_node ;

	MUL_MATCH_node <= MUL_MATCH_FLAG(UNEN_CAM_OUT_node and CMI_node);
	MATCH_node     <= MATCH_FLAG(UNEN_CAM_OUT_node and CMI_node);


	WRITE_DATA_node <= WRITE_DATA_ENCODER(WR_DC_reg, COMP_DATA_reg, MASK_DATA_reg, EN_MASK_reg);
	COMPARE_DATA_node <= COMPARE_DATA_ENCODER(COMP_DATA_reg, MASK_DATA_reg, EN_MASK_reg);
        
        CO_node      <= OUTPUT_ENCODER(UNEN_CAM_OUT_node and CMI_node);
   
---------------------------------------------------------
-- Process
-- Register EN_MASK/ COMP_DATA/ WAD/ WEN/ WR_DC inputs 
---------------------------------------------------------

  register_inputs: process (RST_node, CLK_node)
  begin
  	if (RST_node = '1') then
		EN_MASK_reg   <= '0';
		COMP_DATA_reg <= (others => '0');
		WAD_reg       <= (others => '0');
		WEN_reg        <= '0';
		WR_DC_reg     <= '0';
	elsif (CLK_node'event and CLK_node = '1') then
		if ( CE_node = '1') then
			EN_MASK_reg   <= EN_MASK_node;
			COMP_DATA_reg <= WD_node;
			WAD_reg       <= WAD_node;
			WEN_reg       <= WE_node and CS_node(0) and CS_node(1);
			WR_DC_reg     <= WR_DC_node;
		end if;
	end if;
  end process register_inputs;

---------------------------------------------------------
-- Process
-- Register WD input to MASK_DATA_reg  
-- Note:
-- TSPEC Rev D Page 64 of 96 Note 3 
-- "The reset on mask data register is not provided"
---------------------------------------------------------

  register_WD_2_MASK_DATA: process (CLK_node)
  begin
   	if (CLK_node'event and CLK_node = '1') then
		if ( CE_node = '1' and WR_MASK_node = '1') then
			MASK_DATA_reg <= WD_node;
		end if;
	end if;
  end process register_WD_2_MASK_DATA;

---------------------------------------------------------
-- Process
-- CAM_KERNEL
---------------------------------------------------------

  CAM_KERNEL : process (WEN_reg, WAD_reg, COMPARE_DATA_node, WRITE_DATA_node)
  	
    variable vADDR : integer := 0;
    variable vUNEN_CAM_OUT : std_logic_vector (2**ADDR_WIDTH -1 downto 0) := (others => '0');
    variable vMEM          : std_logic_vector (2**ADDR_WIDTH*DATA_WIDTH -1 downto 0) := ( others => 'Z');
    variable v_WAD_Valid_Flag : boolean := TRUE;
    variable v_INI_DONE    : boolean := FALSE;

    begin
    
    if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
	READ_CAM_INIT_FILE(MEM_INIT_FILE, vMEM);
	v_INI_DONE := TRUE;
    end if;

    v_WAD_Valid_Flag := Valid_Address(WAD_reg);	

    if (v_WAD_Valid_Flag = TRUE) then
 	vADDR := CONV_INTEGER(WAD_reg);

    --else
    --  assert false
    --    report "Write Address of Port contains invalid bit!"
    --    severity warning;

    end if;	

    if (WEN_reg = '1') then
    	vMEM((vADDR*DATA_WIDTH + DATA_WIDTH -1) downto (vADDR*DATA_WIDTH)) := WRITE_DATA_node;
      for i in 0 to 2**ADDR_WIDTH -1 loop
	  if (WORD_COMPARE(vMEM((i*DATA_WIDTH + DATA_WIDTH -1) downto (i*DATA_WIDTH)), COMPARE_DATA_node) = '1') then
            vUNEN_CAM_OUT(i) := '1';

          else 
	    vUNEN_CAM_OUT(i) := '0';

    	  end if;
	end loop;

	UNEN_CAM_OUT_node <= vUNEN_CAM_OUT;
    
    elsif (WEN_reg = '0') then
    	for i in 0 to 2**ADDR_WIDTH -1 loop
	  if (WORD_COMPARE(vMEM((i*DATA_WIDTH + DATA_WIDTH -1) downto (i*DATA_WIDTH)), COMPARE_DATA_node) = '1') then
            vUNEN_CAM_OUT(i) := '1';

          else 
	    vUNEN_CAM_OUT(i) := '0';

    	  end if;
	end loop;

	UNEN_CAM_OUT_node <= vUNEN_CAM_OUT;	

    end if;

		
end process CAM_KERNEL;

end LATTICE_BEHAV;



-- ************************************************************************
--
--  DPRAM: Behavioral Model
--  
-- ************************************************************************
--
--  Init: Sep. 2001
--  Written by: Zhou Xiao-qiu (Sean ZHOU)
--  Email: xqzhou@lscsh.latticesemi.com
--  Tel: 86-21-64852865 ext. 226
--
-- ************************************************************************
--
--  Filename:  SC_DP_RAM.vhd
--  Description: Single Port BRAM behavioral model. 
--  History:
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

-- ************************************************************************
--  Entity definition  
--  Draft "generic" members 
-- ************************************************************************

entity SC_DPRAM_16K is

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        ADDR_WIDTH_A     : integer := 13;
        DATA_WIDTH_A     : integer := 2;
        ADDR_WIDTH_B     : integer := 14;
        DATA_WIDTH_B     : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
	MEM_INIT_FILE  : string  := "mem_init_file"

         );

  port (
        CENA : in  STD_LOGIC ;
        CLKA : in  STD_LOGIC ;
        WRA  : in  STD_LOGIC ;
        CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
        RSTA : in  STD_LOGIC ;
        DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
        ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
        DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

        CENB : in  STD_LOGIC ;
        CLKB : in  STD_LOGIC ;
        WRB  : in  STD_LOGIC ;
        CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
        RSTB : in  STD_LOGIC ;
        DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
        ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
        DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)

        ); 

end SC_DPRAM_16K ;

-- ************************************************************************
-- architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_DPRAM_16K is

 component SC_BRAM_16K

  generic (
 	     DEVICE_FAMILY : string  := "SuperCool";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
    	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 
 end component;

 -- Signal Declaration
 
 signal CENA_node :  STD_LOGIC := 'X';
 signal CLKA_node :  STD_LOGIC := 'X';
 signal WRA_node  :  STD_LOGIC := 'X';
 signal CSA_node  :  STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
 signal RSTA_node :  STD_LOGIC := 'X';
 signal DIA_node  :  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
 signal ADA_node  :  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0) := (others => 'X');
 signal DOA_node  :  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');

 signal DIA_reg   :  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
 signal ADA_reg   :  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0) := (others => 'X');
 signal ENA_reg   :  STD_LOGIC := 'X';
 signal RENA_reg  :  STD_LOGIC := 'X';

 signal CENB_node :  STD_LOGIC := 'X';
 signal CLKB_node :  STD_LOGIC := 'X';
 signal WRB_node  :  STD_LOGIC := 'X';
 signal CSB_node  :  STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
 signal RSTB_node :  STD_LOGIC := 'X';
 signal DIB_node  :  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
 signal ADB_node  :  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0) := (others => 'X');
 signal DOB_node  :  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');

 signal DIB_reg   :  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
 signal ADB_reg   :  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0) := (others => 'X');
 signal ENB_reg   :  STD_LOGIC := 'X';
 signal RENB_reg  :  STD_LOGIC := 'X';
-- architecture

 begin

  CENA_node <= CENA;
  CLKA_node <= CLKA;
  WRA_node  <= WRA;
  CSA_node  <= CSA;
  RSTA_node <= RSTA;
  DIA_node  <= DIA;
  ADA_node  <= ADA;
  DOA       <= DOA_node; 

  CENB_node <= CENB;
  CLKB_node <= CLKB;
  WRB_node  <= WRB;
  CSB_node  <= CSB;
  RSTB_node <= RSTB;
  DIB_node  <= DIB;
  ADB_node  <= ADB;
  DOB       <= DOB_node;
               
  -- Register Port A DI/ AD / Enable inputs
  register_A_inputs: process (CLKA_node, RSTA_node)
  begin
    if (RSTA_node = '1') then
      DIA_reg <= (others =>'0');
      ADA_reg <= (others =>'0');
      ENA_reg <= '0';
      RENA_reg <= '1';
    elsif (CLKA_node'event and CLKA_node = '1') then
      if (CENA_node = '1') then
        DIA_reg <= DIA_node;
        ADA_reg <= ADA_node;
        ENA_reg <= WRA_node  and CSA_node(0) and CSA_node(1);
        RENA_reg <= '1'; 
      end if;
    end if;
  end process register_A_inputs;   

-- Register Port B DI/ AD / Enable inputs
  register_B_inputs: process (CLKB_node, RSTB_node)
  begin
    if (RSTB_node = '1') then
      DIB_reg <= (others =>'0');
      ADB_reg <= (others =>'0');
      ENB_reg <= '0';
      RENB_reg <= '1';
    elsif (CLKB_node'event and CLKB_node = '1') then
      if (CENB_node = '1') then
        DIB_reg <= DIB_node;
        ADB_reg <= ADB_node;
        ENB_reg <= WRB_node  and CSB_node(0) and CSB_node(1);
        RENB_reg <= '1'; 
      end if;
    end if;
  end process register_B_inputs; 
  
  -- BRAM instance for SPRAM 
  DPRAM_INST: SC_BRAM_16K

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => ADDR_WIDTH_A,
         RADDR_WIDTH_A  => ADDR_WIDTH_A,
         WADDR_WIDTH_B  => ADDR_WIDTH_B,
         RADDR_WIDTH_B  => ADDR_WIDTH_B,
         WDATA_WIDTH_A  => DATA_WIDTH_A,
         RDATA_WIDTH_A  => DATA_WIDTH_A,
         WDATA_WIDTH_B  => DATA_WIDTH_B,
         RDATA_WIDTH_B  => DATA_WIDTH_B,
         ARRAY_SIZE     => 8192,
  	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE

       )
    port map (
         WADA => ADA_reg,
         WEA  => ENA_reg,
         WDA  => DIA_reg,
         RADA => ADA_reg,
         REA  => RENA_reg,
         RDA  => DOA_node,
         
         WADB => ADB_reg,
         WEB  => ENB_reg,
         WDB  => DIB_reg,
         RADB => ADB_reg,
         REB  => RENB_reg,
         RDB  => DOB_node
      );

end LATTICE_BEHAV;



-- ************************************************************************
--
--  DPRAM: Behavioral Model
--  
-- ************************************************************************
--
--  Init: Sep. 2001
--  Written by: Zhou Xiao-qiu (Sean ZHOU)
--  Email: xqzhou@lscsh.latticesemi.com
--  Tel: 86-21-64852865 ext. 226
--
-- ************************************************************************
--
--  Filename:  SC_DP_RAM.vhd
--  Description: Single Port BRAM behavioral model. 
--  History:
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

-- ************************************************************************
--  Entity definition  
--  Draft "generic" members 
-- ************************************************************************

entity SC_DPRAM_16K_L is

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        ADDR_WIDTH_A     : integer := 13;
        DATA_WIDTH_A     : integer := 2;
        ADDR_WIDTH_B     : integer := 14;
        DATA_WIDTH_B     : integer := 1;
        MEM_INIT_FLAG  : integer := 1;  
        ARRAY_SIZE       : integer := 16384;
	MEM_INIT_FILE  : string  := "mem_init_file"

         );

  port (
        CENA : in  STD_LOGIC ;
        CLKA : in  STD_LOGIC ;
        WRA  : in  STD_LOGIC ;
        CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
        RSTA : in  STD_LOGIC ;
        DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
        ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
        DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

        CENB : in  STD_LOGIC ;
        CLKB : in  STD_LOGIC ;
        WRB  : in  STD_LOGIC ;
        CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
        RSTB : in  STD_LOGIC ;
        DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
        ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
        DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)

        ); 

end SC_DPRAM_16K_L ;

-- ************************************************************************
-- architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_DPRAM_16K_L is

 component SC_BRAM_16K_L

  generic (
 	     DEVICE_FAMILY : string  := "SuperCool";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
    	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 
 end component;

 -- Signal Declaration
 
 signal CENA_node :  STD_LOGIC := 'X';
 signal CLKA_node :  STD_LOGIC := 'X';
 signal WRA_node  :  STD_LOGIC := 'X';
 signal CSA_node  :  STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
 signal RSTA_node :  STD_LOGIC := 'X';
 signal DIA_node  :  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
 signal ADA_node  :  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0) := (others => 'X');
 signal DOA_node  :  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');

 signal DIA_reg   :  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
 signal ADA_reg   :  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0) := (others => 'X');
 signal ENA_reg   :  STD_LOGIC := 'X';
 signal RENA_reg  :  STD_LOGIC := 'X';

 signal CENB_node :  STD_LOGIC := 'X';
 signal CLKB_node :  STD_LOGIC := 'X';
 signal WRB_node  :  STD_LOGIC := 'X';
 signal CSB_node  :  STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
 signal RSTB_node :  STD_LOGIC := 'X';
 signal DIB_node  :  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
 signal ADB_node  :  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0) := (others => 'X');
 signal DOB_node  :  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');

 signal DIB_reg   :  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
 signal ADB_reg   :  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0) := (others => 'X');
 signal ENB_reg   :  STD_LOGIC := 'X';
 signal RENB_reg  :  STD_LOGIC := 'X';
-- architecture

 begin

  CENA_node <= CENA;
  CLKA_node <= CLKA;
  WRA_node  <= WRA;
  CSA_node  <= CSA;
  RSTA_node <= RSTA;
  DIA_node  <= DIA;
  ADA_node  <= ADA;
  DOA       <= DOA_node; 

  CENB_node <= CENB;
  CLKB_node <= CLKB;
  WRB_node  <= WRB;
  CSB_node  <= CSB;
  RSTB_node <= RSTB;
  DIB_node  <= DIB;
  ADB_node  <= ADB;
  DOB       <= DOB_node;
               
  -- Register Port A DI/ AD / Enable inputs
  register_A_inputs: process (CLKA_node, RSTA_node)
  begin
    if (RSTA_node = '1') then
      DIA_reg <= (others =>'0');
      ADA_reg <= (others =>'0');
      ENA_reg <= '0';
      RENA_reg <= '1';
    elsif (CLKA_node'event and CLKA_node = '1') then
      if (CENA_node = '1') then
        DIA_reg <= DIA_node;
        ADA_reg <= ADA_node;
        ENA_reg <= WRA_node  and CSA_node(0) and CSA_node(1);
        RENA_reg <= '1'; 
      end if;
    end if;
  end process register_A_inputs;   

-- Register Port B DI/ AD / Enable inputs
  register_B_inputs: process (CLKB_node, RSTB_node)
  begin
    if (RSTB_node = '1') then
      DIB_reg <= (others =>'0');
      ADB_reg <= (others =>'0');
      ENB_reg <= '0';
      RENB_reg <= '1';
    elsif (CLKB_node'event and CLKB_node = '1') then
      if (CENB_node = '1') then
        DIB_reg <= DIB_node;
        ADB_reg <= ADB_node;
        ENB_reg <= WRB_node  and CSB_node(0) and CSB_node(1);
        RENB_reg <= '1'; 
      end if;
    end if;
  end process register_B_inputs; 
  
  -- BRAM instance for SPRAM 
  DPRAM_INST: SC_BRAM_16K_L

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => ADDR_WIDTH_A,
         RADDR_WIDTH_A  => ADDR_WIDTH_A,
         WADDR_WIDTH_B  => ADDR_WIDTH_B,
         RADDR_WIDTH_B  => ADDR_WIDTH_B,
         WDATA_WIDTH_A  => DATA_WIDTH_A,
         RDATA_WIDTH_A  => DATA_WIDTH_A,
         WDATA_WIDTH_B  => DATA_WIDTH_B,
         RDATA_WIDTH_B  => DATA_WIDTH_B,
         ARRAY_SIZE     => ARRAY_SIZE,
  	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE

       )
    port map (
         WADA => ADA_reg,
         WEA  => ENA_reg,
         WDA  => DIA_reg,
         RADA => ADA_reg,
         REA  => RENA_reg,
         RDA  => DOA_node,
         
         WADB => ADB_reg,
         WEB  => ENB_reg,
         WDB  => DIB_reg,
         RADB => ADB_reg,
         REB  => RENB_reg,
         RDB  => DOB_node
      );

end LATTICE_BEHAV;




-- ************************************************************************
--
--  FIFO: Behavioral Model
--  VHDL
--  
-- ************************************************************************
--
--  Init: Oct. 2001
--  Written by: Zhou Xiao-qiu (Sean ZHOU)
--  Email: xqzhou@lscsh.latticesemi.com
--  Tel: 86-21-64852865 ext. 226
--
-- ************************************************************************
--
--  Filename:  SC_FIFO.vhd
--  Description: FIFO behavioral model. 
--     
-- ************************************************************************

-- ************************************************************************
-- History: 
-- 1. Reset EMPTY & AMEMPTY to '0', '0' means 'Ture';   
-- 2. May. 30, 2002 Read memory initialization file feature
-- 3. Add control signal RE WE to BlockRAM 
-- 4. Add programable TERMINAL_COUNT
-- 5. Fix the Write 1-5, Read 2-6 issue
-- ************************************************************************

-- ************************************************************************
-- FIFO COMPONENTS READ_POINTER_CTRL
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity READ_POINTER_CTRL is
	generic (
              RPOINTER_WIDTH : integer := 9
		);
	port (
                TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
		GLOBAL_RST   : in STD_LOGIC ;
                RESET_RP     : in STD_LOGIC ;
                READ_EN      : in STD_LOGIC ;
                READ_CLK     : in STD_LOGIC ;
	        EMPTY_FLAG   : in STD_LOGIC ;
		READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
	     );
end READ_POINTER_CTRL;

architecture LATTICE_BEHAV of READ_POINTER_CTRL is

  signal s_READ_POINTER : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');

begin

  READ_POINTER <= s_READ_POINTER; 

process  (GLOBAL_RST, RESET_RP, READ_EN, READ_CLK)

	variable v_READ_POINTER: STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0');

begin

	if GLOBAL_RST = '1'  or RESET_RP = '1' then 

          s_READ_POINTER <= (others => '0');

	elsif (READ_CLK'EVENT and READ_CLK = '1') then
		if (READ_EN = '1' and EMPTY_FLAG = '1') then
                  v_READ_POINTER := s_READ_POINTER + '1';
                else  
                  v_READ_POINTER := s_READ_POINTER;
		end if;

		if (v_READ_POINTER = TERMINAL_COUNT + 1) then
		   s_READ_POINTER <= (others => '0');
		else
		   s_READ_POINTER <= v_READ_POINTER;
		end if;
	end if;

end process;
end LATTICE_BEHAV;

-- ************************************************************************
-- FIFO COMPONENTS WRITE_POINTER_CTRL
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity WRITE_POINTER_CTRL is
        generic (
                WPOINTER_WIDTH : integer := 9;
                WDATA_WIDTH : integer := 32
		);
        port (
		TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
		GLOBAL_RST    : in STD_LOGIC ;
                WRITE_EN      : in STD_LOGIC ;
                WRITE_CLK     : in STD_LOGIC ;
                FULL_FLAG     : in STD_LOGIC ;
                WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
            
	     );
end WRITE_POINTER_CTRL;

architecture LATTICE_BEHAV of WRITE_POINTER_CTRL is

 signal s_WRITE_POINTER : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');

begin 

  WRITE_POINTER <= s_WRITE_POINTER;

  process  (GLOBAL_RST, WRITE_EN, WRITE_CLK)

    variable v_WRITE_POINTER: STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');

begin
	if GLOBAL_RST = '1'  then 
		s_WRITE_POINTER <= (others => '0'); 

	elsif (WRITE_CLK'EVENT and WRITE_CLK = '1') then
		if (WRITE_EN = '1' and FULL_FLAG /= '1') then
		   v_WRITE_POINTER := s_WRITE_POINTER + '1';
                else
		   v_WRITE_POINTER := s_WRITE_POINTER ;
                end if; 

		if (v_WRITE_POINTER = TERMINAL_COUNT + 1) then
		   s_WRITE_POINTER <= (others => '0');
		else
		   s_WRITE_POINTER <= v_WRITE_POINTER;
		end if;
	end if;
end process;
end LATTICE_BEHAV;

-- ************************************************************************
-- FIFO COMPONENTS FLAG LOGIC
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity FLAG_LOGIC is
 	generic (
                WPOINTER_WIDTH : integer := 9;
                RPOINTER_WIDTH : integer := 9;
                WDATA_WIDTH    : integer := 32; 
                RDATA_WIDTH    : integer := 32; 
                AMFULL_X      : integer := 1;
                AMEMPTY_Y     : integer := 1
		);
	port (
		TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0) := (others => '0');--QQ
		R_POINTER  : in STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
                W_POINTER  : in STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0');
                GLOBAL_RST : in STD_LOGIC ;
                READ_EN    : in STD_LOGIC ;
                READ_CLK   : in STD_LOGIC ;
                WRITE_EN   : in STD_LOGIC ;
                WRITE_CLK  : in STD_LOGIC ; 
                FULL_D     : out STD_LOGIC ;
                EMPTY_D    : out STD_LOGIC ;
                AMFULL_D   : out STD_LOGIC ;
                AMEMPTY_D  : out STD_LOGIC 
	);
end FLAG_LOGIC;

architecture LATTICE_BEHAV of FLAG_LOGIC is
--------------------------------------------------------------------------
-- Function: Valid_Address 
-- Description: 
--------------------------------------------------------------------------
function Valid_Pointer (
    IN_ADDR : in STD_LOGIC_VECTOR
 ) return BOOLEAN is

    variable v_Valid_Flag : BOOLEAN := TRUE;
 
begin

    for i in IN_ADDR'high downto IN_ADDR'low loop
        if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
            v_Valid_Flag := FALSE;
        end if;
    end loop;

    return v_Valid_Flag;
end Valid_Pointer;

--------------------------------------------------------------------------
-- Function: Calculate_Offset 
-- Description: 
--------------------------------------------------------------------------
function Calculate_Offset (
    IN_TC : in  STD_LOGIC_VECTOR;
    TC_LENGTH: in INTEGER
 ) return STD_LOGIC_VECTOR is

    variable vTC_FULL: STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '1');
    variable vTC_TEMP: STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '0');
    variable vOFFSET : STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '0');
begin
    vTC_TEMP := IN_TC;
    vOFFSET := vTC_FULL-vTC_TEMP;
    return vOFFSET;
end Calculate_Offset;
   
begin 

--------------------------------------------------------------------------
-- Function: Main Process 
-- Description: 
--------------------------------------------------------------------------
FULL_AMFULL: process  (GLOBAL_RST, WRITE_EN, WRITE_CLK, W_POINTER, R_POINTER)
    variable v_WP_Valid_Flag : boolean := TRUE;
    variable v_RP_Valid_Flag : boolean := TRUE;
    --variable v_WP_Check_FULL_TMP : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
    variable v_WP_Check_AMFL_TMP : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
    variable v_WP_Check_AMFL_TMP1 : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
    variable v_WP_Check_FULL : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
    variable v_WP_Check_AMFL : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ

begin
        v_WP_Valid_Flag := Valid_Pointer(W_POINTER);	
        v_RP_Valid_Flag := Valid_Pointer(R_POINTER);
	if( v_WP_Valid_Flag = TRUE) then
             v_WP_Check_AMFL_TMP := W_POINTER + AMFULL_X + 1;
        end if;

        v_WP_Check_AMFL_TMP1 := v_WP_Check_AMFL_TMP + Calculate_Offset(TERMINAL_COUNT, WPOINTER_WIDTH);

	if ( v_WP_Valid_Flag = TRUE and W_POINTER = TERMINAL_COUNT ) then 
	    v_WP_Check_FULL := (others => '0');
	elsif( v_WP_Valid_Flag = TRUE ) then 
	    v_WP_Check_FULL := W_POINTER + 1; 
	end if;

	if GLOBAL_RST = '1'  then 
	    FULL_D <= '0';
	    AMFULL_D <= '0';

	elsif( v_WP_Valid_Flag = TRUE and v_RP_Valid_Flag = TRUE) then

	    if R_POINTER = v_WP_Check_FULL then
	     FULL_D <= '1';
            else
	     FULL_D <= '0';	
            end if;

            if (W_POINTER > R_POINTER) then
	      if (v_WP_Check_AMFL_TMP1 < W_POINTER) then
                if v_WP_Check_AMFL_TMP1 >= R_POINTER then
	         AMFULL_D <= '1';
	        else
	         AMFULL_D <= '0'; 	
	        end if; 
              else 
	         AMFULL_D <= '0'; 	
              end if;    
            elsif (W_POINTER < R_POINTER) then
	      if (v_WP_Check_AMFL_TMP1 < W_POINTER) then
	         AMFULL_D <= '1';
	      elsif (v_WP_Check_AMFL_TMP >= R_POINTER) then
	         AMFULL_D <= '1';
	      else 
	         AMFULL_D <= '0'; 	
	      end if; 
            end if;    

        end if;

end process FULL_AMFULL;

EMPTY_AMEMPTY: process  (GLOBAL_RST, READ_EN, READ_CLK, W_POINTER, R_POINTER)
    variable v_WP_Valid_Flag : boolean := TRUE;
    variable v_RP_Valid_Flag : boolean := TRUE;
    variable v_RP_Check_EMPT_TMP : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
    variable v_RP_Check_AMET_TMP : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
    variable v_RP_Check_AMET_TMP1 : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
    --variable v_RP_Check_EMPT : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
    variable v_RP_Check_AMET : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ

begin
        v_WP_Valid_Flag := Valid_Pointer(W_POINTER);	
        v_RP_Valid_Flag := Valid_Pointer(R_POINTER);
	if( v_RP_Valid_Flag = TRUE and v_WP_Valid_Flag = TRUE) then
	    v_RP_Check_AMET_TMP := R_POINTER + AMEMPTY_Y ; -- Different from TSPEC QQ 07 17,2002
        end if;
        v_RP_Check_AMET_TMP1 := v_RP_Check_AMET_TMP + Calculate_Offset(TERMINAL_COUNT, RPOINTER_WIDTH);

	if GLOBAL_RST = '1'  then 
	  EMPTY_D <= '0';
	  AMEMPTY_D <= '0';
	elsif( v_WP_Valid_Flag = TRUE and v_RP_Valid_Flag = TRUE) then
            if R_POINTER  = W_POINTER then   -- Different from TSPEC QQ 07 17,2002
                    EMPTY_D <= '0';
            else
                    EMPTY_D <= '1';
            end if;

	    
	    if (W_POINTER < R_POINTER) then
	      if (v_RP_Check_AMET_TMP1 < R_POINTER) then
	          v_RP_Check_AMET := v_RP_Check_AMET_TMP + Calculate_Offset(TERMINAL_COUNT, RPOINTER_WIDTH);
                if v_RP_Check_AMET >= W_POINTER then
	         AMEMPTY_D <= '0';
	        else
	         AMEMPTY_D <= '1'; 	
	        end if; 
              else 
	         AMEMPTY_D <= '1'; 	
              end if;    
            elsif (W_POINTER > R_POINTER) then
	      if (v_RP_Check_AMET_TMP1 < R_POINTER) then
	         AMEMPTY_D <= '0';
	      elsif (v_RP_Check_AMET_TMP >= W_POINTER) then
	         AMEMPTY_D <= '0';
	      else 
	         AMEMPTY_D <= '1'; 	
	      end if; 
            elsif (W_POINTER = R_POINTER) then
              AMEMPTY_D <= '0';
            end if;    
       end if;
end process EMPTY_AMEMPTY;

end LATTICE_BEHAV;

-- **********************************************************************
-- SC_FIFO_16K
-- **********************************************************************
-- **********************************************************************
-- Top Design Entity definition  
-- **********************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;

--LIBRARY SC_LIB;
--USE SC_LIB.SC_FIFO_COMPS.ALL;
-- ctse 0622

 entity SC_FIFO_16K is 
  generic (
	DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer := 511; --QQ: Word number < 2**WADDR_WIDTH
	WADDR_WIDTH    : integer :=   9;
        WDATA_WIDTH    : integer :=  32;
        RADDR_WIDTH    : integer :=   9;
        RDATA_WIDTH    : integer :=  32;
        ALMOST_FULL_X  : integer :=   1;
        ALMOST_EMPTY_Y : integer :=   1;
        MEM_INIT_FLAG  : integer :=   0;  
        MEM_INIT_FILE  : string  := "mem_init_file"

         );

  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);

        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)

        ); 

end SC_FIFO_16K; 

-- ************************************************************************
-- ARCHITECTURE
-- ************************************************************************
architecture LATTICE_BEHAV of SC_FIFO_16K is 

-- ************************************************************************
-- COMPONENT DECLARATIONS
-- ************************************************************************
component SC_BRAM_16K_SYNC 

  generic (
 	     
         DEVICE_FAMILY : string  := "SuperCool";
         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
         MEM_INIT_FLAG : integer := 0;  
         MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
	 WCLK : in  STD_LOGIC;
	 RCLK : in  STD_LOGIC
        ); 
 end component;

-- ************************************************************************
-- SIGNAL DECLARATIONS
-- ************************************************************************
signal we_ram : STD_LOGIC := '0';
signal re_ram : STD_LOGIC := '0';
signal full_bit : STD_LOGIC := '0';
signal empty_bit : STD_LOGIC := '0';
signal wptr_wrap_bit : STD_LOGIC := '0';
signal rptr_wrap_bit : STD_LOGIC := '0';
signal wptr : STD_LOGIC_VECTOR (WADDR_WIDTH - 1 downto 0) := (others => '0');
signal rptr : STD_LOGIC_VECTOR (RADDR_WIDTH - 1 downto 0) := (others => '0');
signal wptr_wrap_appended : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
				:= (others => '0');
signal rptr_wrap_appended : STD_LOGIC_VECTOR (RADDR_WIDTH downto 0) 
				:= (others => '0');
signal next_wptr_wrap_appended : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
				:= (others => '0');

signal next_rptr_wrap_appended : STD_LOGIC_VECTOR (RADDR_WIDTH downto 0) 
				:= (others => '0');

--ct092804
--signal num_unread_loc : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
--				:= (others => '0');
--signal num_empty_loc : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
--				:= (others => '0');

signal num_unread_loc_wdomain : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
				:= (others => '0');
signal num_unread_loc_rdomain : STD_LOGIC_VECTOR (RADDR_WIDTH downto 0) 
				:= (others => '0');
				
signal TERM_CNT_VEC : STD_LOGIC_VECTOR (WADDR_WIDTH  downto 0);
signal DEPTH : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0);   

signal wptr_rdomain : STD_LOGIC_VECTOR (WADDR_WIDTH - 1 downto 0) := (others => '0');
signal rptr_wdomain : STD_LOGIC_VECTOR (RADDR_WIDTH - 1 downto 0) := (others => '0');

signal wptr_wrap_bit_rdomain : STD_LOGIC := '0';
signal rptr_wrap_bit_wdomain : STD_LOGIC := '0';

signal wptr_wrap_appended_rdomain : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
				  := (others => '0');
signal rptr_wrap_appended_wdomain : STD_LOGIC_VECTOR (RADDR_WIDTH downto 0) --ct092704
				  := (others => '0');


signal rden_p1, empty_p1: std_logic; --ct092804
signal do_ram: STD_LOGIC_VECTOR (RDATA_WIDTH - 1 downto 0); --ct092804
-- ************************************************************************
-- FUNCTIONS
-- ************************************************************************
function next_ptr (
   ptr_wrap_bit :  STD_LOGIC;
   ptr :  STD_LOGIC_VECTOR;
   TERMINAL_COUNT :  integer )

  return STD_LOGIC_VECTOR is

  variable result_ptr : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0); 
  variable tmp_ptr : STD_LOGIC_VECTOR (WADDR_WIDTH - 1 downto 0);
  
begin
   if (ptr = TERMINAL_COUNT) then
      tmp_ptr := (others => '1');
   else
      tmp_ptr :=  ptr;
   end if;
   result_ptr := (ptr_wrap_bit & tmp_ptr) + 1;
  
   return result_ptr;

end next_ptr;

function INT_TO_VEC ( INPUT_INT : integer; INPUT_LENGTH: integer)
 return std_logic_vector is

   variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
   variable vTRANS: integer := 0;
   variable vQUOTIENT: integer := 0;
 
 begin 
    vQUOTIENT := INPUT_INT;

    for i in 0 to INPUT_LENGTH -1 loop
	vTRANS := 0;
	while vQUOTIENT >1 loop
	    vQUOTIENT := vQUOTIENT - 2;
            vTRANS := vTRANS + 1;
	end loop;
        case vQUOTIENT is
              when 1 =>
                 vDATA_STD_VEC(i) := '1';
              when 0 =>
                 vDATA_STD_VEC(i) := '0';
              when others =>
                 null;
        end case;
        vQUOTIENT := vTRANS; 
    end loop;
  return vDATA_STD_VEC; 	  
 end INT_TO_VEC; 

-- ************************************************************************
-- BODY
-- ************************************************************************

begin 

-- ************************************************************************
-- INSTANTIATIONS
-- ************************************************************************

FIFO_BRAM_INST: SC_BRAM_16K_SYNC

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => WADDR_WIDTH, 
         RADDR_WIDTH_A  => RADDR_WIDTH, 
         WADDR_WIDTH_B  => WADDR_WIDTH, 
         RADDR_WIDTH_B  => RADDR_WIDTH, 
         WDATA_WIDTH_A  => WDATA_WIDTH, 
         RDATA_WIDTH_A  => RDATA_WIDTH, 
         WDATA_WIDTH_B  => WDATA_WIDTH, 
         RDATA_WIDTH_B  => RDATA_WIDTH, 
         ARRAY_SIZE     => open,
    	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE

       )
    port map (
         WADA => wptr,
         WEA  => we_ram,
         WDA  => DI, 
         RADA => rptr,
         REA  => re_ram,
         --ct092804 RDA  => DO, 
         RDA  => do_ram, --ct092804
         
         WADB => wptr, 
         WEB  => '0', 
         WDB  => DI, 
         RADB => rptr, 
         REB  => '0', 
         RDB  => open,
	 WCLK => WCLK,
	 RCLK => RCLK
      );


-- ************************************************************************
-- CONCURRENT ASSIGNMENTS
-- ************************************************************************
TERM_CNT_VEC (WADDR_WIDTH downto 0) <= INT_TO_VEC(TERMINAL_COUNT, WADDR_WIDTH + 1);

DEPTH (WADDR_WIDTH downto 0)  <= TERM_CNT_VEC  + 1;


we_ram  <= WE and not(full_bit);
re_ram <= RE and not(empty_bit);

wptr <= wptr_wrap_appended(WADDR_WIDTH - 1 downto 0);
rptr <= rptr_wrap_appended(RADDR_WIDTH - 1 downto 0);
wptr_rdomain <= wptr_wrap_appended_rdomain(WADDR_WIDTH - 1 downto 0);
rptr_wdomain <= rptr_wrap_appended_wdomain(RADDR_WIDTH - 1 downto 0);

wptr_wrap_bit <= wptr_wrap_appended(WADDR_WIDTH);
rptr_wrap_bit <= rptr_wrap_appended(RADDR_WIDTH);
wptr_wrap_bit_rdomain  <= wptr_wrap_appended_rdomain (WADDR_WIDTH);
rptr_wrap_bit_wdomain  <= rptr_wrap_appended_wdomain (RADDR_WIDTH);

next_rptr_wrap_appended <= next_ptr(rptr_wrap_bit, rptr, TERMINAL_COUNT);
next_wptr_wrap_appended <= next_ptr(wptr_wrap_bit, wptr, TERMINAL_COUNT);

--ct092704
--num_empty_loc <= -- used for full, computed in wdomain
--   ( DEPTH + rptr_wdomain) - wptr when (rptr_wrap_bit_wdomain = wptr_wrap_bit)
--else
--   "0" & (rptr_wdomain -  wptr);

--num_unread_loc <= --used for empty, computed in rdomain
--   ( DEPTH + wptr_rdomain) - rptr when (wptr_wrap_bit_rdomain /= rptr_wrap_bit)
--else
--   "0" & (wptr_rdomain -  rptr);

process (rptr_wdomain, rptr_wrap_bit_wdomain, wptr, wptr_wrap_bit)
begin
   if (rptr_wrap_bit_wdomain /= wptr_wrap_bit) then
      -- An improper use of RPRST could cause num_unread_loc >= DEPTH,
      -- when the wrap bits are different but wptr > rptr
      num_unread_loc_wdomain <=  ( DEPTH + wptr) - rptr_wdomain;
   else 
      num_unread_loc_wdomain <= "0" & (wptr -  rptr_wdomain);
   end if;
end process;

process (wptr_rdomain, wptr_wrap_bit_rdomain, rptr, rptr_wrap_bit)
begin
   if (wptr_wrap_bit_rdomain /= rptr_wrap_bit) then
      -- An improper use of RPRST could cause num_unread_loc >= DEPTH,
      -- when the wrap bits are different but wptr > rptr
      num_unread_loc_rdomain <=  ( DEPTH + wptr_rdomain) - rptr;
   else 
      num_unread_loc_rdomain <= "0" & (wptr_rdomain - rptr  );
   end if;
end process;
--full_bit <= '1' when (num_empty_loc = 0) else '0';
--empty_bit <= '1' when (num_unread_loc = 0) else '0';

full_bit <= '1' when (num_unread_loc_wdomain >= DEPTH) else '0';
FULL <= full_bit;
AMFULL <= '1' when (num_unread_loc_wdomain >= DEPTH - ALMOST_FULL_X) else '0';

-- AMEMPTY/EMPTY  are ACTIVE LOW !!!!!!!!!!!!!!!!!!!!!!!!!!!!
empty_bit <= '1' when (num_unread_loc_rdomain = 0 ) else '0';
EMPTY <= not(empty_bit); 
AMEMPTY <= '0' when (num_unread_loc_rdomain <= ALMOST_EMPTY_Y) else '1';

-- **********************************************************************
-- DO LATCH
-- **********************************************************************
process (RCLK)
begin
   if (rising_edge (RCLK)) then 
      rden_p1 <= RE;
      empty_p1 <= empty_bit;
   end if;
end process;

process (do_ram, RST, rden_p1, empty_p1)
begin
   if (RST = '1') then
      DO <= (others => '0');
   elsif (rden_p1 = '1' and empty_p1 = '0') then
      DO <= do_ram;
   end if;
end process;
-- **********************************************************************
-- WRITE READ POINTERS
-- **********************************************************************
process (RST, WCLK)
begin

   if (RST = '1')  then
      wptr_wrap_appended <= (others => '0');
   elsif ( WCLK'event and WCLK = '1') then
      if (WE = '1' and full_bit = '0') then
         wptr_wrap_appended <= next_wptr_wrap_appended after 1 ns;
      end if;
   end if;
end process;

--ct092804
process (RST, RPRST, RCLK)
begin

   if (RST = '1'or RPRST = '1')  then
      rptr_wrap_appended <= (others => '0') ;
   elsif ( RCLK'event and RCLK = '1') then
      if ( (RE and not(empty_bit)) = '1') then
         rptr_wrap_appended <= next_rptr_wrap_appended after 1 ns;
      end if;
   end if ;   
end process;



-- ************************************************************************
-- POINTER SYNCHRONIZATIONS (SIMPLY DONE TO MATCH THE GATE-LEVEL MODEL)
-- ************************************************************************

process (RST, WCLK)
begin
   if (RST = '1')  then
      rptr_wrap_appended_wdomain <= (others => '0');
   elsif ( WCLK'event and WCLK = '1') then
      rptr_wrap_appended_wdomain <= rptr_wrap_appended after 1 ns;
   end if;
end process;


process (RST, RCLK)
begin
   if (RST = '1')  then
      wptr_wrap_appended_rdomain <= (others => '0');
   elsif ( RCLK'event and RCLK = '1') then
      wptr_wrap_appended_rdomain <= wptr_wrap_appended after 1 ns;
   end if;
end process;

-- ************************************************************************
-- END ARCHITECTURE: SC_FIFO_16K
-- ************************************************************************
end LATTICE_BEHAV; 


--**********************************************************************
--**  SC_FIFO_16K_L 
--**********************************************************************
--**********************************************************************
-- Top Design Entity definition  
--**********************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;

--LIBRARY SC_LIB;
--USE SC_LIB.SC_FIFO_COMPS.ALL;
-- ctse 0622

 entity SC_FIFO_16K_L is 
  generic (
	DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer := 511; --QQ: Word number < 2**WADDR_WIDTH
	WADDR_WIDTH    : integer :=   9;
        WDATA_WIDTH    : integer :=  32;
        RADDR_WIDTH    : integer :=   9;
        RDATA_WIDTH    : integer :=  32;
        ALMOST_FULL_X  : integer :=   1;
        ALMOST_EMPTY_Y : integer :=   1;
        MEM_INIT_FLAG  : integer :=   0;  
        MEM_INIT_FILE  : string  := "mem_init_file"

         );

  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);

        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)

        ); 

end SC_FIFO_16K_L; 

-- ************************************************************************
-- ARCHITECTURE
-- ************************************************************************
architecture LATTICE_BEHAV of SC_FIFO_16K_L is 

-- ************************************************************************
-- COMPONENT DECLARATIONS
-- ************************************************************************
component SC_BRAM_16K_L_SYNC 

  generic (
 	     
         DEVICE_FAMILY : string  := "SuperCool";
         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
         MEM_INIT_FLAG : integer := 0;  
         MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
	 WCLK : in  STD_LOGIC;
	 RCLK : in  STD_LOGIC
        ); 
 end component;

-- ************************************************************************
-- SIGNAL DECLARATIONS
-- ************************************************************************
signal we_ram : STD_LOGIC := '0';
signal re_ram : STD_LOGIC := '0';
signal full_bit : STD_LOGIC := '0';
signal empty_bit : STD_LOGIC := '0';
signal wptr_wrap_bit : STD_LOGIC := '0';
signal rptr_wrap_bit : STD_LOGIC := '0';
signal wptr : STD_LOGIC_VECTOR (WADDR_WIDTH - 1 downto 0) := (others => '0');
signal rptr : STD_LOGIC_VECTOR (RADDR_WIDTH - 1 downto 0) := (others => '0');
signal wptr_wrap_appended : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
				:= (others => '0');
signal rptr_wrap_appended : STD_LOGIC_VECTOR (RADDR_WIDTH downto 0) 
				:= (others => '0');
signal next_wptr_wrap_appended : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
				:= (others => '0');

signal next_rptr_wrap_appended : STD_LOGIC_VECTOR (RADDR_WIDTH downto 0) 
				:= (others => '0');

--ct092804
--signal num_unread_loc : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
--				:= (others => '0');
--signal num_empty_loc : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
--				:= (others => '0');

signal num_unread_loc_wdomain : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
				:= (others => '0');
signal num_unread_loc_rdomain : STD_LOGIC_VECTOR (RADDR_WIDTH downto 0) 
				:= (others => '0');
				
signal TERM_CNT_VEC : STD_LOGIC_VECTOR (WADDR_WIDTH  downto 0);
signal DEPTH : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0);   

signal wptr_rdomain : STD_LOGIC_VECTOR (WADDR_WIDTH - 1 downto 0) := (others => '0');
signal rptr_wdomain : STD_LOGIC_VECTOR (RADDR_WIDTH - 1 downto 0) := (others => '0');

signal wptr_wrap_bit_rdomain : STD_LOGIC := '0';
signal rptr_wrap_bit_wdomain : STD_LOGIC := '0';

signal wptr_wrap_appended_rdomain : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
				  := (others => '0');
signal rptr_wrap_appended_wdomain : STD_LOGIC_VECTOR (RADDR_WIDTH downto 0) --ct092704
				  := (others => '0');


signal rden_p1, empty_p1: std_logic; --ct092804
signal do_ram: STD_LOGIC_VECTOR (RDATA_WIDTH - 1 downto 0); --ct092804
-- ************************************************************************
-- FUNCTIONS
-- ************************************************************************
function next_ptr (
   ptr_wrap_bit :  STD_LOGIC;
   ptr :  STD_LOGIC_VECTOR;
   TERMINAL_COUNT :  integer )

  return STD_LOGIC_VECTOR is

  variable result_ptr : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0); 
  variable tmp_ptr : STD_LOGIC_VECTOR (WADDR_WIDTH - 1 downto 0);
  
begin
   if (ptr = TERMINAL_COUNT) then
      tmp_ptr := (others => '1');
   else
      tmp_ptr :=  ptr;
   end if;
   result_ptr := (ptr_wrap_bit & tmp_ptr) + 1;
  
   return result_ptr;

end next_ptr;

function INT_TO_VEC ( INPUT_INT : integer; INPUT_LENGTH: integer)
 return std_logic_vector is

   variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
   variable vTRANS: integer := 0;
   variable vQUOTIENT: integer := 0;
 
 begin 
    vQUOTIENT := INPUT_INT;

    for i in 0 to INPUT_LENGTH -1 loop
	vTRANS := 0;
	while vQUOTIENT >1 loop
	    vQUOTIENT := vQUOTIENT - 2;
            vTRANS := vTRANS + 1;
	end loop;
        case vQUOTIENT is
              when 1 =>
                 vDATA_STD_VEC(i) := '1';
              when 0 =>
                 vDATA_STD_VEC(i) := '0';
              when others =>
                 null;
        end case;
        vQUOTIENT := vTRANS; 
    end loop;
  return vDATA_STD_VEC; 	  
 end INT_TO_VEC; 

-- ************************************************************************
-- BODY
-- ************************************************************************

begin 

-- ************************************************************************
-- INSTANTIATIONS
-- ************************************************************************

FIFO_BRAM_INST: SC_BRAM_16K_L_SYNC

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => WADDR_WIDTH, 
         RADDR_WIDTH_A  => RADDR_WIDTH, 
         WADDR_WIDTH_B  => WADDR_WIDTH, 
         RADDR_WIDTH_B  => RADDR_WIDTH, 
         WDATA_WIDTH_A  => WDATA_WIDTH, 
         RDATA_WIDTH_A  => RDATA_WIDTH, 
         WDATA_WIDTH_B  => WDATA_WIDTH, 
         RDATA_WIDTH_B  => RDATA_WIDTH, 
         ARRAY_SIZE     => open,
    	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE

       )
    port map (
         WADA => wptr,
         WEA  => we_ram,
         WDA  => DI, 
         RADA => rptr,
         REA  => re_ram,
         --ct092804 RDA  => DO, 
         RDA  => do_ram, --ct092804
         
         WADB => wptr, 
         WEB  => '0', 
         WDB  => DI, 
         RADB => rptr, 
         REB  => '0', 
         RDB  => open,
	 WCLK => WCLK,
	 RCLK => RCLK
      );


-- ************************************************************************
-- CONCURRENT ASSIGNMENTS
-- ************************************************************************
TERM_CNT_VEC (WADDR_WIDTH downto 0) <= INT_TO_VEC(TERMINAL_COUNT, WADDR_WIDTH + 1);

DEPTH (WADDR_WIDTH downto 0)  <= TERM_CNT_VEC  + 1;


we_ram  <= WE and not(full_bit);
re_ram <= RE and not(empty_bit);

wptr <= wptr_wrap_appended(WADDR_WIDTH - 1 downto 0);
rptr <= rptr_wrap_appended(RADDR_WIDTH - 1 downto 0);
wptr_rdomain <= wptr_wrap_appended_rdomain(WADDR_WIDTH - 1 downto 0);
rptr_wdomain <= rptr_wrap_appended_wdomain(RADDR_WIDTH - 1 downto 0);

wptr_wrap_bit <= wptr_wrap_appended(WADDR_WIDTH);
rptr_wrap_bit <= rptr_wrap_appended(RADDR_WIDTH);
wptr_wrap_bit_rdomain  <= wptr_wrap_appended_rdomain (WADDR_WIDTH);
rptr_wrap_bit_wdomain  <= rptr_wrap_appended_wdomain (RADDR_WIDTH);

next_rptr_wrap_appended <= next_ptr(rptr_wrap_bit, rptr, TERMINAL_COUNT);
next_wptr_wrap_appended <= next_ptr(wptr_wrap_bit, wptr, TERMINAL_COUNT);

--ct092704
--num_empty_loc <= -- used for full, computed in wdomain
--   ( DEPTH + rptr_wdomain) - wptr when (rptr_wrap_bit_wdomain = wptr_wrap_bit)
--else
--   "0" & (rptr_wdomain -  wptr);

--num_unread_loc <= --used for empty, computed in rdomain
--   ( DEPTH + wptr_rdomain) - rptr when (wptr_wrap_bit_rdomain /= rptr_wrap_bit)
--else
--   "0" & (wptr_rdomain -  rptr);

process (rptr_wdomain, rptr_wrap_bit_wdomain, wptr, wptr_wrap_bit)
begin
   if (rptr_wrap_bit_wdomain /= wptr_wrap_bit) then
      -- An improper use of RPRST could cause num_unread_loc >= DEPTH,
      -- when the wrap bits are different but wptr > rptr
      num_unread_loc_wdomain <=  ( DEPTH + wptr) - rptr_wdomain;
   else 
      num_unread_loc_wdomain <= "0" & (wptr -  rptr_wdomain);
   end if;
end process;

process (wptr_rdomain, wptr_wrap_bit_rdomain, rptr, rptr_wrap_bit)
begin
   if (wptr_wrap_bit_rdomain /= rptr_wrap_bit) then
      -- An improper use of RPRST could cause num_unread_loc >= DEPTH,
      -- when the wrap bits are different but wptr > rptr
      num_unread_loc_rdomain <=  ( DEPTH + wptr_rdomain) - rptr;
   else 
      num_unread_loc_rdomain <= "0" & (wptr_rdomain - rptr  );
   end if;
end process;
--full_bit <= '1' when (num_empty_loc = 0) else '0';
--empty_bit <= '1' when (num_unread_loc = 0) else '0';

full_bit <= '1' when (num_unread_loc_wdomain >= DEPTH) else '0';
FULL <= full_bit;
AMFULL <= '1' when (num_unread_loc_wdomain >= DEPTH - ALMOST_FULL_X) else '0';

-- AMEMPTY/EMPTY  are ACTIVE LOW !!!!!!!!!!!!!!!!!!!!!!!!!!!!
empty_bit <= '1' when (num_unread_loc_rdomain = 0 ) else '0';
EMPTY <= not(empty_bit); 
AMEMPTY <= '0' when (num_unread_loc_rdomain <= ALMOST_EMPTY_Y) else '1';

-- ************************************************************************
-- DO LATCH
-- ************************************************************************
process (RCLK)
begin
   if (rising_edge (RCLK)) then 
      rden_p1 <= RE;
      empty_p1 <= empty_bit;
   end if;
end process;

process (do_ram, RST, rden_p1, empty_p1)
begin
   if (RST = '1') then
      DO <= (others => '0');
   elsif (rden_p1 = '1' and empty_p1 = '0') then
      DO <= do_ram;
   end if;
end process;
-- ************************************************************************
-- WRITE READ POINTERS
-- ************************************************************************
process (RST, WCLK)
begin

   if (RST = '1')  then
      wptr_wrap_appended <= (others => '0');
   elsif ( WCLK'event and WCLK = '1') then
      if (WE = '1' and full_bit = '0') then
         wptr_wrap_appended <= next_wptr_wrap_appended after 1 ns;
      end if;
   end if;
end process;

--ct092804
process (RST, RPRST, RCLK)
begin

   if (RST = '1'or RPRST = '1')  then
      rptr_wrap_appended <= (others => '0') ;
   elsif ( RCLK'event and RCLK = '1') then
      if ( (RE and not(empty_bit)) = '1') then
         rptr_wrap_appended <= next_rptr_wrap_appended after 1 ns;
      end if;
   end if ;   
end process;



-- ************************************************************************
-- POINTER SYNCHRONIZATIONS (SIMPLY DONE TO MATCH THE GATE-LEVEL MODEL)
-- ************************************************************************

process (RST, WCLK)
begin
   if (RST = '1')  then
      rptr_wrap_appended_wdomain <= (others => '0');
   elsif ( WCLK'event and WCLK = '1') then
      rptr_wrap_appended_wdomain <= rptr_wrap_appended after 1 ns;
   end if;
end process;


process (RST, RCLK)
begin
   if (RST = '1')  then
      wptr_wrap_appended_rdomain <= (others => '0');
   elsif ( RCLK'event and RCLK = '1') then
      wptr_wrap_appended_rdomain <= wptr_wrap_appended after 1 ns;
   end if;
end process;

-- ************************************************************************
-- END ARCHITECTURE: SC_FIFO_16K_L
-- ************************************************************************
end LATTICE_BEHAV; 





-- **********************************************************************
--
--  PseudoDPRAM: Behavioral Model
--  
-- **********************************************************************
--
--  Init: Sep. 2001
--  Written by: Zhou Xiao-qiu (Sean ZHOU)
--  Email: xqzhou@lscsh.latticesemi.com
--  Tel: 86-21-64852865 ext. 226
--
-- ************************************************************************
--
--  Filename:  SC_PDP_RAM.vhd
--  Description: Pseudo Dual Port BRAM behavioral model. 
--  History:
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

-- ************************************************************************
--  Entity definition  
--  Draft "generic" members 
-- ************************************************************************

entity SC_PDPRAM_16K is

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        WADDR_WIDTH    : integer := 13;
        WDATA_WIDTH    : integer := 2;
        RADDR_WIDTH    : integer := 13;
        RDATA_WIDTH    : integer := 2;
        MEM_INIT_FLAG  : integer := 0;  
	MEM_INIT_FILE  : string  := ""

        );

  port (
        WCEN : in  STD_LOGIC ;
        WCLK : in  STD_LOGIC ;
        WE   : in  STD_LOGIC ;
        WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
        RCLK : in  STD_LOGIC;
        RCEN : in  STD_LOGIC;
        RST  : in  STD_LOGIC ;

        WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
        RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);  
        RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
       ); 

end SC_PDPRAM_16K ;

-- ************************************************************************
-- architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_PDPRAM_16K is

 component SC_BRAM_PDP_16K

  generic (
 	     DEVICE_FAMILY : string  := "SuperCool";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
   	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 
 end component;

 -- Signal Declaration
 
 signal WCEN_node :  STD_LOGIC := 'X';
 signal WCLK_node :  STD_LOGIC := 'X';
 signal WE_node   :  STD_LOGIC := 'X';
 signal WCS_node  :  STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
 signal RCEN_node :  STD_LOGIC := 'X';
 signal RCLK_node :  STD_LOGIC := 'X';
 signal RST_node  :  STD_LOGIC := 'X';
 signal WD_node   :  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
 signal WAD_node  :  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
 signal RD_node   :  STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');
 signal RAD_node  :  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => '0'); 
 

 signal WD_reg    :  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
 signal WAD_reg   :  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
 signal RAD_reg   :  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => '0');
 signal EN_reg    :  STD_LOGIC := 'X';
 signal REN_reg    :  STD_LOGIC := '1';
 signal GND_sig   :  STD_LOGIC;
 signal VCC_sig   :  STD_LOGIC;

 -- architecture

 begin
  GND_sig <= '0';
  VCC_sig <= '1';
  WCEN_node <= WCEN;
  WCLK_node <= WCLK;
  WE_node   <= WE;
  WCS_node  <= WCS;
  RCEN_node <= RCEN;
  RCLK_node <= RCLK;
  RST_node  <= RST;
  WD_node   <= WD;
  WAD_node  <= WAD;
  RAD_node  <= RAD;
  RD        <= RD_node;

  -- Register WD/WAD/ Enable inputs
  register_write_inputs: process (WCLK_node, RST_node)
  begin
    if (RST_node = '1') then
      WD_reg <= (others =>'0');
      WAD_reg <= (others =>'0');
      EN_reg <= '0';
      REN_reg <= '1';
    elsif (WCLK_node'event and WCLK_node = '1') then
      if (WCEN_node = '1') then
        WD_reg  <= WD_node;
        WAD_reg <= WAD_node;
        EN_reg  <= WE_node  and WCS_node(0) and WCS_node(1);
       -- REN_reg  <= '1'; 
      end if;
    end if;
  end process register_write_inputs;   

-- Register RAD inputs
  register_read_inputs: process (RCLK_node, RST_node)
  begin
    if (RST_node = '1') then
      RAD_reg <= (others =>'0');
    elsif (RCLK_node'event and RCLK_node = '1') then
      if (RCEN_node = '1') then
        RAD_reg <= RAD_node;
        REN_reg  <= WCS_node(0) and WCS_node(1);
      end if;
    end if;
  end process register_read_inputs;   

-- BRAM instance for SPRAM 
  PDPRAM_INST: SC_BRAM_PDP_16K

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => WADDR_WIDTH,
         RADDR_WIDTH_A  => RADDR_WIDTH,
         WADDR_WIDTH_B  => WADDR_WIDTH,
         RADDR_WIDTH_B  => RADDR_WIDTH,
         WDATA_WIDTH_A  => WDATA_WIDTH,
         RDATA_WIDTH_A  => RDATA_WIDTH,
         WDATA_WIDTH_B  => WDATA_WIDTH,
         RDATA_WIDTH_B  => RDATA_WIDTH,
         ARRAY_SIZE     => open,
 	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE
       )
    port map (
         WADA => WAD_reg,
         WEA  => EN_reg,
         WDA  => WD_reg,
         RADA => RAD_reg,
         REA  => REN_reg,
         RDA  => RD_node,
         
         WADB => WAD_reg,
         WEB  => GND_sig,
         WDB  => WD_reg,
         RADB => RAD_reg,
         REB  => GND_sig,
         RDB  => open
      );

end LATTICE_BEHAV;
 

-- ************************************************************************
--
--  PseudoDPRAM: Behavioral Model
--  
-- ************************************************************************
--
--  Init: Sep. 2001
--  Written by: Zhou Xiao-qiu (Sean ZHOU)
--  Email: xqzhou@lscsh.latticesemi.com
--  Tel: 86-21-64852865 ext. 226
--
-- ************************************************************************
--
--  Filename:  SC_PDP_RAM.vhd
--  Description: Pseudo Dual Port BRAM behavioral model. 
--  History:
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

-- ************************************************************************
--  Entity definition  
--  Draft "generic" members 
-- ************************************************************************

entity SC_PDPRAM_16K_L is

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        WADDR_WIDTH    : integer := 13;
        WDATA_WIDTH    : integer := 2;
        RADDR_WIDTH    : integer := 13;
        RDATA_WIDTH    : integer := 2;
        MEM_INIT_FLAG  : integer := 1;  
        ARRAY_SIZE     : integer := 16384;
	MEM_INIT_FILE  : string  := "mem_init_file"

        );

  port (
        WCEN : in  STD_LOGIC ;
        WCLK : in  STD_LOGIC ;
        WE   : in  STD_LOGIC ;
        WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
        RCLK : in  STD_LOGIC;
        RCEN : in  STD_LOGIC;
        RST  : in  STD_LOGIC ;

        WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
        RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);  
        RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
       ); 

end SC_PDPRAM_16K_L ;

-- ************************************************************************
-- architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_PDPRAM_16K_L is

 component SC_BRAM_PDP_16K_L

  generic (
 	     DEVICE_FAMILY : string  := "SuperCool";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
   	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 
 end component;

 -- Signal Declaration
 
 signal WCEN_node :  STD_LOGIC := 'X';
 signal WCLK_node :  STD_LOGIC := 'X';
 signal WE_node   :  STD_LOGIC := 'X';
 signal WCS_node  :  STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
 signal RCEN_node :  STD_LOGIC := 'X';
 signal RCLK_node :  STD_LOGIC := 'X';
 signal RST_node  :  STD_LOGIC := 'X';
 signal WD_node   :  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
 signal WAD_node  :  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
 signal RD_node   :  STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');
 signal RAD_node  :  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => '0'); 
 

 signal WD_reg    :  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
 signal WAD_reg   :  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
 signal RAD_reg   :  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => '0');
 signal EN_reg    :  STD_LOGIC := 'X';
 signal REN_reg    :  STD_LOGIC := '1';
 signal GND_sig   :  STD_LOGIC;
 signal VCC_sig   :  STD_LOGIC;

 -- architecture

 begin
  GND_sig <= '0';
  VCC_sig <= '1';
  WCEN_node <= WCEN;
  WCLK_node <= WCLK;
  WE_node   <= WE;
  WCS_node  <= WCS;
  RCEN_node <= RCEN;
  RCLK_node <= RCLK;
  RST_node  <= RST;
  WD_node   <= WD;
  WAD_node  <= WAD;
  RAD_node  <= RAD;
  RD        <= RD_node;

  -- Register WD/WAD/ Enable inputs
  register_write_inputs: process (WCLK_node, RST_node)
  begin
    if (RST_node = '1') then
      WD_reg <= (others =>'0');
      WAD_reg <= (others =>'0');
      EN_reg <= '0';
      REN_reg <= '1';
    elsif (WCLK_node'event and WCLK_node = '1') then
      if (WCEN_node = '1') then
        WD_reg  <= WD_node;
        WAD_reg <= WAD_node;
        EN_reg  <= WE_node  and WCS_node(0) and WCS_node(1);
      --  REN_reg  <= '1'; 
      end if;
    end if;
  end process register_write_inputs;   

-- Register RAD inputs
  register_read_inputs: process (RCLK_node, RST_node)
  begin
    if (RST_node = '1') then
      RAD_reg <= (others =>'0');
    elsif (RCLK_node'event and RCLK_node = '1') then
      if (RCEN_node = '1') then
        RAD_reg <= RAD_node;
        REN_reg  <= WCS_node(0) and WCS_node(1);
      end if;
    end if;
  end process register_read_inputs;   

-- BRAM instance for SPRAM 
  PDPRAM_INST: SC_BRAM_PDP_16K_L

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => WADDR_WIDTH,
         RADDR_WIDTH_A  => RADDR_WIDTH,
         WADDR_WIDTH_B  => WADDR_WIDTH,
         RADDR_WIDTH_B  => RADDR_WIDTH,
         WDATA_WIDTH_A  => WDATA_WIDTH,
         RDATA_WIDTH_A  => RDATA_WIDTH,
         WDATA_WIDTH_B  => WDATA_WIDTH,
         RDATA_WIDTH_B  => RDATA_WIDTH,
         ARRAY_SIZE     => ARRAY_SIZE,
 	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE
       )
    port map (
         WADA => WAD_reg,
         WEA  => EN_reg,
         WDA  => WD_reg,
         RADA => RAD_reg,
         REA  => REN_reg,
         RDA  => RD_node,
         
         WADB => WAD_reg,
         WEB  => GND_sig,
         WDB  => WD_reg,
         RADB => RAD_reg,
         REB  => GND_sig,
         RDB  => open
      );

end LATTICE_BEHAV;
 


-- ************************************************************************
--
--  PseudoDPRAM: Behavioral Model
--  
-- ************************************************************************
--
--  Init: Apr. 2002
--  Written by: Zhou Xiao-qiu (Sean ZHOU)
--  Email: xqzhou@lscsh.latticesemi.com
--  Tel: 86-21-64852865 ext. 226
--
-- ************************************************************************
--
--  Filename:  SC_PDP_RAMA.vhd
--  Description: Asynchronous Read Pseudo Dual Port BRAM behavioral model. 
--
--  Compared with synchronous model 
--  Remove RCLK and RCEN ports   
--  
--  History:
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

-- ************************************************************************
--  Entity definition  
--  Draft "generic" members 
-- ************************************************************************

entity SC_PDPRAMA_16K is

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        WADDR_WIDTH    : integer := 13;
        WDATA_WIDTH    : integer := 2;
        RADDR_WIDTH    : integer := 13;
        RDATA_WIDTH    : integer := 2;
        MEM_INIT_FLAG  : integer := 0;  
	MEM_INIT_FILE  : string  := "mem_init_file"

        );

  port (
        WCEN : in  STD_LOGIC ;
        WCLK : in  STD_LOGIC ;
        WE   : in  STD_LOGIC ;
        WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
        RST  : in  STD_LOGIC ;

        WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
        RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);  
        RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
       ); 

end SC_PDPRAMA_16K ;

-- ************************************************************************
-- architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_PDPRAMA_16K is

 component SC_BRAM_PDP_16K

  generic (
 	     DEVICE_FAMILY : string  := "SuperCool";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
    	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 
 end component;

 -- Signal Declaration
 
 signal WCEN_node :  STD_LOGIC := 'X';
 signal WCLK_node :  STD_LOGIC := 'X';
 signal WE_node   :  STD_LOGIC := 'X';
 signal WCS_node  :  STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
 signal RST_node  :  STD_LOGIC := 'X';
 signal WD_node   :  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
 signal WAD_node  :  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
 signal RD_node   :  STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');
 signal RAD_node  :  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => '0'); 
 

 signal WD_reg    :  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
 signal WAD_reg   :  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
 signal RAD_reg   :  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => '0');
 signal EN_reg    :  STD_LOGIC := 'X';
 signal REN_reg   :  STD_LOGIC := '1';
 signal GND_sig   :  STD_LOGIC;
 signal VCC_sig   :  STD_LOGIC;

 -- architecture

 begin
  GND_sig <= '0';
  VCC_sig <= '1';
  WCEN_node <= WCEN;
  WCLK_node <= WCLK;
  WE_node   <= WE;
  WCS_node  <= WCS;
  RST_node  <= RST;
  WD_node   <= WD;
  WAD_node  <= WAD;
  RAD_node  <= RAD;
  RD        <= RD_node;

  -- Register WD/WAD/ Enable inputs
  register_write_inputs: process (WCLK_node, RST_node)
  begin
    if (RST_node = '1') then
      WD_reg <= (others =>'0');
      WAD_reg <= (others =>'0');
      EN_reg <= '0';
      REN_reg <= '1';
    elsif (WCLK_node'event and WCLK_node = '1') then
        if  (WCEN_node = '1') then
        WD_reg  <= WD_node;
        WAD_reg <= WAD_node;
        EN_reg  <= WE_node  and WCS_node(0) and WCS_node(1);
        end if;
    end if;
  end process register_write_inputs;   

-- BRAM instance for SPRAM 
  PDPRAM_INST: SC_BRAM_PDP_16K

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => WADDR_WIDTH,
         RADDR_WIDTH_A  => RADDR_WIDTH,
         WADDR_WIDTH_B  => WADDR_WIDTH,
         RADDR_WIDTH_B  => RADDR_WIDTH,
         WDATA_WIDTH_A  => WDATA_WIDTH,
         RDATA_WIDTH_A  => RDATA_WIDTH,
         WDATA_WIDTH_B  => WDATA_WIDTH,
         RDATA_WIDTH_B  => RDATA_WIDTH,
         ARRAY_SIZE     => open,
  	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE

       )
    port map (
         WADA => WAD_reg,
         WEA  => EN_reg,
         WDA  => WD_reg,
         RADA => RAD_node,   
         REA  => REN_reg,
         RDA  => RD_node,
         
         WADB => WAD_reg,
         WEB  => GND_sig,
         WDB  => WD_reg,
         RADB => RAD_node,   
         REB  => GND_sig,
         RDB  => open
      );

end LATTICE_BEHAV;
 


-- ************************************************************************
--
--  PseudoDPRAM: Behavioral Model
--  
-- ************************************************************************
--
--  Init: Apr. 2002
--  Written by: Zhou Xiao-qiu (Sean ZHOU)
--  Email: xqzhou@lscsh.latticesemi.com
--  Tel: 86-21-64852865 ext. 226
--
-- ************************************************************************
--
--  Filename:  SC_PDP_RAMA.vhd
--  Description: Asynchronous Read Pseudo Dual Port BRAM behavioral model. 
--
--  Compared with synchronous model 
--  Remove RCLK and RCEN ports   
--  
--  History:
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

-- ************************************************************************
--  Entity definition  
--  Draft "generic" members 
-- ************************************************************************

entity SC_PDPRAMA_16K_L is

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        WADDR_WIDTH    : integer := 13;
        WDATA_WIDTH    : integer := 2;
        RADDR_WIDTH    : integer := 13;
        RDATA_WIDTH    : integer := 2;
        ARRAY_SIZE     : integer := 16384;
        MEM_INIT_FLAG  : integer := 1;  
	MEM_INIT_FILE  : string  := "mem_init_file"

        );

  port (
        WCEN : in  STD_LOGIC ;
        WCLK : in  STD_LOGIC ;
        WE   : in  STD_LOGIC ;
        WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
        RST  : in  STD_LOGIC ;

        WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
        RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);  
        RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
       ); 

end SC_PDPRAMA_16K_L ;

-- ************************************************************************
-- architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_PDPRAMA_16K_L is

 component SC_BRAM_PDP_16K_L

  generic (
 	     DEVICE_FAMILY : string  := "SuperCool";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
    	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 
 end component;

 -- Signal Declaration
 
 signal WCEN_node :  STD_LOGIC := 'X';
 signal WCLK_node :  STD_LOGIC := 'X';
 signal WE_node   :  STD_LOGIC := 'X';
 signal WCS_node  :  STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
 signal RST_node  :  STD_LOGIC := 'X';
 signal WD_node   :  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
 signal WAD_node  :  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
 signal RD_node   :  STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');
 signal RAD_node  :  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => '0'); 
 

 signal WD_reg    :  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
 signal WAD_reg   :  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
 signal RAD_reg   :  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => '0');
 signal EN_reg    :  STD_LOGIC := 'X';
 signal REN_reg   :  STD_LOGIC := '1';
 signal GND_sig   :  STD_LOGIC;
 signal VCC_sig   :  STD_LOGIC;

 -- architecture

 begin
  GND_sig <= '0';
  VCC_sig <= '1';
  WCEN_node <= WCEN;
  WCLK_node <= WCLK;
  WE_node   <= WE;
  WCS_node  <= WCS;
  RST_node  <= RST;
  WD_node   <= WD;
  WAD_node  <= WAD;
  RAD_node  <= RAD;
  RD        <= RD_node;

  -- Register WD/WAD/ Enable inputs
  register_write_inputs: process (WCLK_node, RST_node)
  begin
    if (RST_node = '1') then
      WD_reg <= (others =>'0');
      WAD_reg <= (others =>'0');
      EN_reg <= '0';
      REN_reg <= '1';
    elsif (WCLK_node'event and WCLK_node = '1') then
       if (WCEN_node = '1') then
        WD_reg  <= WD_node;
        WAD_reg <= WAD_node;
        EN_reg  <= WE_node  and WCS_node(0) and WCS_node(1);
       end if;
    end if;
  end process register_write_inputs;   

-- BRAM instance for SPRAM 
  PDPRAM_INST: SC_BRAM_PDP_16K_L

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => WADDR_WIDTH,
         RADDR_WIDTH_A  => RADDR_WIDTH,
         WADDR_WIDTH_B  => WADDR_WIDTH,
         RADDR_WIDTH_B  => RADDR_WIDTH,
         WDATA_WIDTH_A  => WDATA_WIDTH,
         RDATA_WIDTH_A  => RDATA_WIDTH,
         WDATA_WIDTH_B  => WDATA_WIDTH,
         RDATA_WIDTH_B  => RDATA_WIDTH,
         ARRAY_SIZE     => ARRAY_SIZE,
  	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE

       )
    port map (
         WADA => WAD_reg,
         WEA  => EN_reg,
         WDA  => WD_reg,
         RADA => RAD_node,   
         REA  => REN_reg,
         RDA  => RD_node,
         
         WADB => WAD_reg,
         WEB  => GND_sig,
         WDB  => WD_reg,
         RADB => RAD_node,   
         REB  => GND_sig,
         RDB  => open
      );

end LATTICE_BEHAV;
 


-- ************************************************************************
--
--  SPRAM: Behavioral Model
--  
-- ************************************************************************
--
--  Init: Sep. 2001
--  Written by: Zhou Xiao-qiu (Sean ZHOU)
--  Email: xqzhou@lscsh.latticesemi.com
--  Tel: 86-21-64852865 ext. 226
--
-- ************************************************************************
--
--  Filename:  SC_SP_RAM.vhd
--  Description: Single Port BRAM behavioral model. 
--  History:
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

-- ************************************************************************
--  Entity definition  
--  Draft "generic" members 
-- ************************************************************************

entity SC_SPRAM_16K is

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        MEM_INIT_FLAG  : integer := 1;  
	MEM_INIT_FILE  : string  := "qq.dat"

	);

  port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

end SC_SPRAM_16K ;

-- ************************************************************************
-- architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_SPRAM_16K is

 component SC_BRAM_16K

  generic (
 	     DEVICE_FAMILY : string  := "SuperCool";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
 	 MEM_INIT_FLAG : integer := 1;  
	 MEM_INIT_FILE : string  := "mem_init_file"

	  );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 
 end component;

 -- Signal Declaration
 
 signal CEN_node :  STD_LOGIC := 'X';
 signal CLK_node :  STD_LOGIC := 'X';
 signal WR_node  :  STD_LOGIC := 'X';
 signal CS_node  :  STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
 signal RST_node :  STD_LOGIC := 'X';
 signal DI_node  :  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
 signal AD_node  :  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => 'X');
 signal DO_node  :  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');

 signal DI_reg   :  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
 signal AD_reg   :  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => 'X');
 signal EN_reg   :  STD_LOGIC := 'X';
 signal REN_reg   :  STD_LOGIC := 'X';

 signal GND_sig   :  STD_LOGIC;
 signal VCC_sig   :  STD_LOGIC;

 -- architecture

 begin
  GND_sig <= '0';
  VCC_sig <= '1';

  CEN_node <= CEN;
  CLK_node <= CLK;
  WR_node  <= WR;
  CS_node  <= CS;
  RST_node <= RST;
  DI_node  <= DI;
  AD_node  <= AD;
  DO       <= DO_node;

  -- Register DI/ AD / Enable inputs
  register_inputs: process (CLK_node, RST_node)
  begin
    if (RST_node = '1') then
      DI_reg <= (others =>'0');
      AD_reg <= (others =>'0');
      EN_reg <= '0';
      REN_reg <= '1';
    elsif (CLK_node'event and CLK_node = '1') then
      if (CEN_node = '1') then
        DI_reg <= DI_node;
        AD_reg <= AD_node;
        EN_reg <= WR_node  and CS_node(0) and CS_node(1);
      --  REN_reg <= '1'; 
        REN_reg <=CS_node(0) and CS_node(1);
      end if;
    end if;
  end process register_inputs;   

  -- BRAM instance for SPRAM 
  SPRAM_INST: SC_BRAM_16K

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => ADDR_WIDTH,
         RADDR_WIDTH_A  => ADDR_WIDTH,
         WADDR_WIDTH_B  => ADDR_WIDTH,
         RADDR_WIDTH_B  => ADDR_WIDTH,
         WDATA_WIDTH_A  => DATA_WIDTH,
         RDATA_WIDTH_A  => DATA_WIDTH,
         WDATA_WIDTH_B  => DATA_WIDTH,
         RDATA_WIDTH_B  => DATA_WIDTH,
         ARRAY_SIZE     => open,
	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE
       )
    port map (
         WADA => AD_reg,
         WEA  => EN_reg,
         WDA  => DI_reg,
         RADA => AD_reg,
         REA  => REN_reg,
         RDA  => DO_node,

         WADB => AD_reg,
         WEB  => GND_sig,
         WDB  => DI_reg,
         RADB => AD_reg,
         REB  => GND_sig,
         RDB  => open
      );

end LATTICE_BEHAV;
 


-- ************************************************************************
--
--  SPRAM: Behavioral Model
--  
-- ************************************************************************
--
--  Init: Sep. 2001
--  Written by: Zhou Xiao-qiu (Sean ZHOU)
--  Email: xqzhou@lscsh.latticesemi.com
--  Tel: 86-21-64852865 ext. 226
--
-- ************************************************************************
--
--  Filename:  SC_SP_RAM.vhd
--  Description: Single Port BRAM behavioral model. 
--  History:
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

-- ************************************************************************
--  Entity definition  
--  Draft "generic" members 
-- ************************************************************************

entity SC_SPRAM_16K_L is

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        MEM_INIT_FLAG  : integer := 1;  
        ARRAY_SIZE     : integer := 16384;
	MEM_INIT_FILE  : string  := "qq.dat"

	);

  port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

end SC_SPRAM_16K_L ;

-- ************************************************************************
-- architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_SPRAM_16K_L is

 component SC_BRAM_16K_L

  generic (
 	     DEVICE_FAMILY : string  := "SuperCool";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
 	 MEM_INIT_FLAG : integer := 1;  
	 MEM_INIT_FILE : string  := "mem_init_file"

	  );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 
 end component;

 -- Signal Declaration
 
 signal CEN_node :  STD_LOGIC := 'X';
 signal CLK_node :  STD_LOGIC := 'X';
 signal WR_node  :  STD_LOGIC := 'X';
 signal CS_node  :  STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
 signal RST_node :  STD_LOGIC := 'X';
 signal DI_node  :  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
 signal AD_node  :  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => 'X');
 signal DO_node  :  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');

 signal DI_reg   :  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
 signal AD_reg   :  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => 'X');
 signal EN_reg   :  STD_LOGIC := 'X';
 signal REN_reg   :  STD_LOGIC := 'X';

 signal GND_sig   :  STD_LOGIC;
 signal VCC_sig   :  STD_LOGIC;

 -- architecture

 begin
  GND_sig <= '0';
  VCC_sig <= '1';

  CEN_node <= CEN;
  CLK_node <= CLK;
  WR_node  <= WR;
  CS_node  <= CS;
  RST_node <= RST;
  DI_node  <= DI;
  AD_node  <= AD;
  DO       <= DO_node;

  -- Register DI/ AD / Enable inputs
  register_inputs: process (CLK_node, RST_node)
  begin
    if (RST_node = '1') then
      DI_reg <= (others =>'0');
      AD_reg <= (others =>'0');
      EN_reg <= '0';
      REN_reg <= '1';
    elsif (CLK_node'event and CLK_node = '1') then
      if (CEN_node = '1') then
        DI_reg <= DI_node;
        AD_reg <= AD_node;
        EN_reg <= WR_node  and CS_node(0) and CS_node(1);
        --REN_reg <= '1'; 
        REN_reg <= CS_node(0) and CS_node(1); 
      end if;
    end if;
  end process register_inputs;   

  -- BRAM instance for SPRAM 
  SPRAM_INST: SC_BRAM_16K_L

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => ADDR_WIDTH,
         RADDR_WIDTH_A  => ADDR_WIDTH,
         WADDR_WIDTH_B  => ADDR_WIDTH,
         RADDR_WIDTH_B  => ADDR_WIDTH,
         WDATA_WIDTH_A  => DATA_WIDTH,
         RDATA_WIDTH_A  => DATA_WIDTH,
         WDATA_WIDTH_B  => DATA_WIDTH,
         RDATA_WIDTH_B  => DATA_WIDTH,
         ARRAY_SIZE     => open,
	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE
       )
    port map (
         WADA => AD_reg,
         WEA  => EN_reg,
         WDA  => DI_reg,
         RADA => AD_reg,
         REA  => REN_reg,
         RDA  => DO_node,

         WADB => AD_reg,
         WEB  => GND_sig,
         WDB  => DI_reg,
         RADB => AD_reg,
         REB  => GND_sig,
         RDB  => open
      );

end LATTICE_BEHAV;
 


-- ************************************************************************
--
--  SPRAM: Behavioral Model
--  
-- ************************************************************************
--
--  Init: Apr. 2002
--  Written by: Zhou Xiao-qiu (Sean ZHOU)
--  Email: xqzhou@lscsh.latticesemi.com
--  Tel: 86-21-64852865 ext. 226
--
-- ************************************************************************
--
--  Filename:  SC_SP_RAMA.vhd
--  Description: Asynchronous Read Single Port BRAM behavioral model. 
--  Compared with synchronous model, 
--  no ports modification, just logic change 
--  History:
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

-- ************************************************************************
--  Entity definition  
--  Draft "generic" members 
-- ************************************************************************

entity SC_SPRAMA_16K is

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        MEM_INIT_FLAG  : integer := 0;  
	MEM_INIT_FILE  : string  := "mem_init_file"

	);

  port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

end SC_SPRAMA_16K ;

-- ************************************************************************
-- architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_SPRAMA_16K is

 component SC_BRAM_16K

  generic (
 	     DEVICE_FAMILY : string  := "SuperCool";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
  	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 
 end component;

 -- Signal Declaration
 
 signal CEN_node :  STD_LOGIC := 'X';
 signal CLK_node :  STD_LOGIC := 'X';
 signal WR_node  :  STD_LOGIC := 'X';
 signal CS_node  :  STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
 signal RST_node :  STD_LOGIC := 'X';
 signal DI_node  :  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
 signal AD_node  :  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => 'X');
 signal DO_node  :  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');

 signal DI_reg   :  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
 signal AD_reg   :  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => 'X');
 signal EN_reg   :  STD_LOGIC := 'X';
 signal REN_reg   :  STD_LOGIC := '1';
 signal GND_sig   :  STD_LOGIC;
 signal VCC_sig   :  STD_LOGIC;

 -- architecture

 begin
  GND_sig <= '0';
  VCC_sig <= '1';

  CEN_node <= CEN;
  CLK_node <= CLK;
  WR_node  <= WR;
  CS_node  <= CS;
  RST_node <= RST;
  DI_node  <= DI;
  AD_node  <= AD;

  DO       <= DO_node;


  -- Register DI/ AD / Enable inputs
  register_inputs: process (CLK_node, RST_node)
  begin
    if (RST_node = '1') then
      DI_reg <= (others =>'0');
      AD_reg <= (others =>'0');
      EN_reg <= '0';
      REN_reg <= '1';
    elsif (CLK_node'event and CLK_node = '1') then
      if (CEN_node = '1') then
        DI_reg <= DI_node;
        AD_reg <= AD_node;
        EN_reg <= WR_node  and CS_node(0) and CS_node(1);
        --REN_reg <= '1'; 
      end if;
    end if;
  end process register_inputs;   

  -- BRAM instance for SPRAM 
  SPRAM_INST: SC_BRAM_16K

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => ADDR_WIDTH,
         RADDR_WIDTH_A  => ADDR_WIDTH,
         WADDR_WIDTH_B  => ADDR_WIDTH,
         RADDR_WIDTH_B  => ADDR_WIDTH,
         WDATA_WIDTH_A  => DATA_WIDTH,
         RDATA_WIDTH_A  => DATA_WIDTH,
         WDATA_WIDTH_B  => DATA_WIDTH,
         RDATA_WIDTH_B  => DATA_WIDTH,
         ARRAY_SIZE     => open,
 	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE

       )
    port map (
--       WADA => AD_reg,
         WADA => AD_reg,
         WEA  => EN_reg,
         WDA  => DI_reg,
--       RADA => AD_reg,  -- Synchronous
         RADA => AD_node, -- Asynchronous
	 REA  => REN_reg,
         RDA  => DO_node,
         
--       WADB => AD_reg,
         WADB => AD_reg,
         WEB  => GND_sig,
         WDB  => DI_reg,
         RADB => AD_reg,
         REB  => GND_sig,
         RDB  => open
      );

end LATTICE_BEHAV;
 

-- ************************************************************************
--
--  SPRAM: Behavioral Model
--  
-- ************************************************************************
--
--  Init: Apr. 2002
--  Written by: Zhou Xiao-qiu (Sean ZHOU)
--  Email: xqzhou@lscsh.latticesemi.com
--  Tel: 86-21-64852865 ext. 226
--
-- ************************************************************************
--
--  Filename:  SC_SP_RAMA.vhd
--  Description: Asynchronous Read Single Port BRAM behavioral model. 
--  Compared with synchronous model, 
--  no ports modification, just logic change 
--  History:
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

-- ************************************************************************
--  Entity definition  
--  Draft "generic" members 
-- ************************************************************************

entity SC_SPRAMA_16K_L is

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        ARRAY_SIZE     : integer := 16384;
        MEM_INIT_FLAG  : integer := 1;  
	MEM_INIT_FILE  : string  := "mem_init_file"

	);

  port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

end SC_SPRAMA_16K_L ;

-- ************************************************************************
-- architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_SPRAMA_16K_L is

 component SC_BRAM_16K_L

  generic (
 	     DEVICE_FAMILY : string  := "SuperCool";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
  	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 
 end component;

 -- Signal Declaration
 
 signal CEN_node :  STD_LOGIC := 'X';
 signal CLK_node :  STD_LOGIC := 'X';
 signal WR_node  :  STD_LOGIC := 'X';
 signal CS_node  :  STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
 signal RST_node :  STD_LOGIC := 'X';
 signal DI_node  :  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
 signal AD_node  :  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => 'X');
 signal DO_node  :  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');

 signal DI_reg   :  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
 signal AD_reg   :  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => 'X');
 signal EN_reg   :  STD_LOGIC := 'X';
 signal REN_reg   :  STD_LOGIC := '1';
 signal GND_sig   :  STD_LOGIC;
 signal VCC_sig   :  STD_LOGIC;

 -- architecture

 begin
  GND_sig <= '0';
  VCC_sig <= '1';

  CEN_node <= CEN;
  CLK_node <= CLK;
  WR_node  <= WR;
  CS_node  <= CS;
  RST_node <= RST;
  DI_node  <= DI;
  AD_node  <= AD;

  DO       <= DO_node;


  -- Register DI/ AD / Enable inputs
  register_inputs: process (CLK_node, RST_node)
  begin
    if (RST_node = '1') then
      DI_reg <= (others =>'0');
      AD_reg <= (others =>'0');
      EN_reg <= '0';
      REN_reg <= '1';
    elsif (CLK_node'event and CLK_node = '1') then
      if (CEN_node = '1') then
        DI_reg <= DI_node;
        AD_reg <= AD_node;
        EN_reg <= WR_node  and CS_node(0) and CS_node(1);
       -- REN_reg <= '1'; 
      end if;
    end if;
  end process register_inputs;   

  -- BRAM instance for SPRAM 
  SPRAM_INST: SC_BRAM_16K_L

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => ADDR_WIDTH,
         RADDR_WIDTH_A  => ADDR_WIDTH,
         WADDR_WIDTH_B  => ADDR_WIDTH,
         RADDR_WIDTH_B  => ADDR_WIDTH,
         WDATA_WIDTH_A  => DATA_WIDTH,
         RDATA_WIDTH_A  => DATA_WIDTH,
         WDATA_WIDTH_B  => DATA_WIDTH,
         RDATA_WIDTH_B  => DATA_WIDTH,
         ARRAY_SIZE     => ARRAY_SIZE,
 	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE

       )
    port map (
--       WADA => AD_reg,
         WADA => AD_reg,
         WEA  => EN_reg,
         WDA  => DI_reg,
--       RADA => AD_reg,  -- Synchronous
         RADA => AD_node, -- Asynchronous
	 REA  => REN_reg,
         RDA  => DO_node,
         
--       WADB => AD_reg,
         WADB => AD_reg,
         WEB  => GND_sig,
         WDB  => DI_reg,
         RADB => AD_reg,
         REB  => GND_sig,
         RDB  => open
      );

end LATTICE_BEHAV;
 

----- CELL RAMB16K_WX1_RX1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX1_RX1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_RAD11_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD11_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_RAD12_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD12_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_RAD13_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD13_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                             :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      WAD13                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RAD11                           :	in    STD_ULOGIC;
      RAD12                           :	in    STD_ULOGIC;
      RAD13                           :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX1_RX1 : entity is FALSE;
end RAMB16K_WX1_RX1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX1_RX1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 14;
		WDATA_WIDTH    : integer := 1;
		RADDR_WIDTH    : integer := 14;
		RDATA_WIDTH    : integer := 1;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_logic_vector (0 downto 0) ;

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';
      signal WAD13_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';
      signal RAD11_ipd     : std_ulogic := 'X';
      signal RAD12_ipd     : std_ulogic := 'X';
      signal RAD13_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (0 downto 0);
 	signal WAD : std_logic_vector (13 downto 0);
	signal RAD : std_logic_vector (13 downto 0);
	signal RD  : std_logic_vector (0 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);

begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD0_ipd;
	WAD <= WAD13_ipd & WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD13_ipd & RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd(0), WD0, tipd_WD0);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);
        VitalWireDelay (WAD13_ipd, WAD13, tipd_WAD13);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);
        VitalWireDelay (RAD13_ipd, RAD13, tipd_RAD13);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD13_WCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge   : std_ulogic  := '0';
        variable Tviol_RAD11_RCLK_posedge   : std_ulogic  := '0';
        variable Tviol_RAD12_RCLK_posedge   : std_ulogic  := '0';
        variable Tviol_RAD13_RCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD13_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD11_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD12_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD13_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD12_WCLK_posedge,
          TimingData              => Tmkr_WAD12_WCLK_posedge,
          TestSignal              => WAD12_ipd,
          TestSignalName          => "WAD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD13_WCLK_posedge,
          TimingData              => Tmkr_WAD13_WCLK_posedge,
          TestSignal              => WAD13_ipd,
          TestSignalName          => "WAD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD11_RCLK_posedge,
          TimingData              => Tmkr_RAD11_RCLK_posedge,
          TestSignal              => RAD11_ipd,
          TestSignalName          => "RAD11",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD11_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD11_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD11_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD11_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD12_RCLK_posedge,
          TimingData              => Tmkr_RAD12_RCLK_posedge,
          TestSignal              => RAD12_ipd,
          TestSignalName          => "RAD12",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD12_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD12_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD12_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD12_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD13_RCLK_posedge,
          TimingData              => Tmkr_RAD13_RCLK_posedge,
          TestSignal              => RAD13_ipd,
          TestSignalName          => "RAD13",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD13_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD13_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD13_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD13_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or Tviol_RAD9_RCLK_posedge or 
                 Tviol_RAD10_RCLK_posedge or Tviol_RAD11_RCLK_posedge or 
                 Tviol_RAD12_RCLK_posedge or Tviol_RAD13_RCLK_posedge or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD, RD;

      end process VITALBehavior;

	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 14,
		WDATA_WIDTH    => 1,
		RADDR_WIDTH    => 14,
		RDATA_WIDTH    => 1,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);


end VITAL;

configuration CFG_RAMB16K_WX1_RX1_VITAL of RAMB16K_WX1_RX1 is
   for VITAL
   end for;
end CFG_RAMB16K_WX1_RX1_VITAL;



----- CELL RAMB16K_WX1_RX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX1_RX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_RAD11_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD11_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_RAD12_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD12_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      WAD13                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RAD11                           :	in    STD_ULOGIC;
      RAD12                           :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX1_RX2 : entity is FALSE;
end RAMB16K_WX1_RX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX1_RX2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 14;
		WDATA_WIDTH    : integer := 1;
		RADDR_WIDTH    : integer := 13;
		RDATA_WIDTH    : integer := 2;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;


      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_logic_vector(0 downto 0) ;

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';
      signal WAD13_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';
      signal RAD11_ipd     : std_ulogic := 'X';
      signal RAD12_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (0 downto 0);
 	signal WAD : std_logic_vector (13 downto 0);
	signal RAD : std_logic_vector (12 downto 0);
	signal RD  : std_logic_vector (1 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);

begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD0_ipd;
	WAD <= WAD13_ipd & WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd(0), WD0, tipd_WD0);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);
        VitalWireDelay (WAD13_ipd, WAD13, tipd_WAD13);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD13_WCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge   : std_ulogic  := '0';
        variable Tviol_RAD11_RCLK_posedge   : std_ulogic  := '0';
        variable Tviol_RAD12_RCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD13_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD11_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD12_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD12_WCLK_posedge,
          TimingData              => Tmkr_WAD12_WCLK_posedge,
          TestSignal              => WAD12_ipd,
          TestSignalName          => "WAD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD13_WCLK_posedge,
          TimingData              => Tmkr_WAD13_WCLK_posedge,
          TestSignal              => WAD13_ipd,
          TestSignalName          => "WAD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD11_RCLK_posedge,
          TimingData              => Tmkr_RAD11_RCLK_posedge,
          TestSignal              => RAD11_ipd,
          TestSignalName          => "RAD11",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD11_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD11_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD11_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD11_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD12_RCLK_posedge,
          TimingData              => Tmkr_RAD12_RCLK_posedge,
          TestSignal              => RAD12_ipd,
          TestSignalName          => "RAD12",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD12_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD12_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD12_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD12_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or Tviol_RAD9_RCLK_posedge or 
                 Tviol_RAD10_RCLK_posedge or Tviol_RAD11_RCLK_posedge or 
                 Tviol_RAD12_RCLK_posedge or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;
    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 14,
		WDATA_WIDTH    => 1,
		RADDR_WIDTH    => 13,
		RDATA_WIDTH    => 2,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16K_WX1_RX2_VITAL of RAMB16K_WX1_RX2 is
   for VITAL
   end for;
end CFG_RAMB16K_WX1_RX2_VITAL;



----- CELL RAMB16K_WX1_RX4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX1_RX4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_RAD11_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD11_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      WAD13                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RAD11                           :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out    STD_ULOGIC;
      RD2                             :	out    STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX1_RX4 : entity is FALSE;
end RAMB16K_WX1_RX4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX1_RX4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 14;
		WDATA_WIDTH    : integer := 1;
		RADDR_WIDTH    : integer := 12;
		RDATA_WIDTH    : integer := 4;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_logic_vector(0 downto 0);

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';
      signal WAD13_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';
      signal RAD11_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (0 downto 0);
 	signal WAD : std_logic_vector (13 downto 0);
	signal RAD : std_logic_vector (11 downto 0);
	signal RD  : std_logic_vector (3 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);

begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD0_ipd;
	WAD <= WAD13_ipd & WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd(0), WD0, tipd_WD0);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);
        VitalWireDelay (WAD13_ipd, WAD13, tipd_WAD13);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD13_WCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge   : std_ulogic  := '0';
        variable Tviol_RAD11_RCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD13_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD11_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD12_WCLK_posedge,
          TimingData              => Tmkr_WAD12_WCLK_posedge,
          TestSignal              => WAD12_ipd,
          TestSignalName          => "WAD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD13_WCLK_posedge,
          TimingData              => Tmkr_WAD13_WCLK_posedge,
          TestSignal              => WAD13_ipd,
          TestSignalName          => "WAD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD11_RCLK_posedge,
          TimingData              => Tmkr_RAD11_RCLK_posedge,
          TestSignal              => RAD11_ipd,
          TestSignalName          => "RAD11",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD11_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD11_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD11_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD11_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or Tviol_RAD9_RCLK_posedge or 
                 Tviol_RAD10_RCLK_posedge or Tviol_RAD11_RCLK_posedge or  
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------



wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD, RD;


      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;



	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 14,
		WDATA_WIDTH    => 1,
		RADDR_WIDTH    => 12,
		RDATA_WIDTH    => 4,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16K_WX1_RX4_VITAL of RAMB16K_WX1_RX4 is
   for VITAL
   end for;
end CFG_RAMB16K_WX1_RX4_VITAL;



----- CELL RAMB16K_WX1_RX8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX1_RX8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      WAD13                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out    STD_ULOGIC;
      RD2                             :	out    STD_ULOGIC;
      RD3                             :	out    STD_ULOGIC;
      RD4                             :	out    STD_ULOGIC;
      RD5                             :	out    STD_ULOGIC;
      RD6                             :	out    STD_ULOGIC;
      RD7                             :	out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX1_RX8 : entity is FALSE;
end RAMB16K_WX1_RX8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX1_RX8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 14;
		WDATA_WIDTH    : integer := 1;
		RADDR_WIDTH    : integer := 11;
		RDATA_WIDTH    : integer := 8;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_logic_vector(0 downto 0);

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';
      signal WAD13_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (0 downto 0);
 	signal WAD : std_logic_vector (13 downto 0);
	signal RAD : std_logic_vector (10 downto 0);
	signal RD  : std_logic_vector (7 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD0_ipd;
	WAD <= WAD13_ipd & WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd(0), WD0, tipd_WD0);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);
        VitalWireDelay (WAD13_ipd, WAD13, tipd_WAD13);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD13_WCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD13_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD12_WCLK_posedge,
          TimingData              => Tmkr_WAD12_WCLK_posedge,
          TestSignal              => WAD12_ipd,
          TestSignalName          => "WAD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD13_WCLK_posedge,
          TimingData              => Tmkr_WAD13_WCLK_posedge,
          TestSignal              => WAD13_ipd,
          TestSignalName          => "WAD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or Tviol_RAD9_RCLK_posedge or 
                 Tviol_RAD10_RCLK_posedge or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;



	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 14,
		WDATA_WIDTH    => 1,
		RADDR_WIDTH    => 11,
		RDATA_WIDTH    => 8,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);


end VITAL;

configuration CFG_RAMB16K_WX1_RX8_VITAL of RAMB16K_WX1_RX8 is
   for VITAL
   end for;
end CFG_RAMB16K_WX1_RX8_VITAL;



----- CELL RAMB16K_WX1_RX16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX1_RX16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD10                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD11                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD12                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD13                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD14                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD15                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      WAD13                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out    STD_ULOGIC;
      RD2                             :	out    STD_ULOGIC;
      RD3                             :	out    STD_ULOGIC;
      RD4                             :	out    STD_ULOGIC;
      RD5                             :	out    STD_ULOGIC;
      RD6                             :	out    STD_ULOGIC;
      RD7                             :	out    STD_ULOGIC;
      RD8                             :	out    STD_ULOGIC;
      RD9                             :	out    STD_ULOGIC;
      RD10                            :	out    STD_ULOGIC;
      RD11                            :	out    STD_ULOGIC;
      RD12                            :	out    STD_ULOGIC;
      RD13                            :	out    STD_ULOGIC;
      RD14                            :	out    STD_ULOGIC;
      RD15                            :	out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX1_RX16 : entity is FALSE;
end RAMB16K_WX1_RX16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX1_RX16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 14;
		WDATA_WIDTH    : integer := 1;
		RADDR_WIDTH    : integer := 10;
		RDATA_WIDTH    : integer := 16;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_logic_vector(0 downto 0);

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';
      signal WAD13_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (0 downto 0);
 	signal WAD : std_logic_vector (13 downto 0);
	signal RAD : std_logic_vector (9 downto 0);
	signal RD  : std_logic_vector (15 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD0_ipd;
	WAD <= WAD13_ipd & WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;


  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd(0), WD0, tipd_WD0);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);
        VitalWireDelay (WAD13_ipd, WAD13, tipd_WAD13);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD13_WCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD13_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd         : std_ulogic := 'X';
        variable RD11_zd         : std_ulogic := 'X';
        variable RD12_zd         : std_ulogic := 'X';
        variable RD13_zd         : std_ulogic := 'X';
        variable RD14_zd         : std_ulogic := 'X';
        variable RD15_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD12_WCLK_posedge,
          TimingData              => Tmkr_WAD12_WCLK_posedge,
          TestSignal              => WAD12_ipd,
          TestSignalName          => "WAD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD13_WCLK_posedge,
          TimingData              => Tmkr_WAD13_WCLK_posedge,
          TestSignal              => WAD13_ipd,
          TestSignalName          => "WAD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or Tviol_RAD9_RCLK_posedge or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;



	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 14,
		WDATA_WIDTH    => 1,
		RADDR_WIDTH    => 10,
		RDATA_WIDTH    => 16,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16K_WX1_RX16_VITAL of RAMB16K_WX1_RX16 is
   for VITAL
   end for;
end CFG_RAMB16K_WX1_RX16_VITAL;



----- CELL RAMB16K_WX1_RX32 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_WX1_RX32 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD10                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD11                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD12                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD13                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD14                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD15                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD26                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD27                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD28                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD29                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD30                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD31                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD16                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD17                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD18                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD19                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD20                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD21                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD22                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD23                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD24                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD25                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      WAD13                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out    STD_ULOGIC;
      RD2                             :	out    STD_ULOGIC;
      RD3                             :	out    STD_ULOGIC;
      RD4                             :	out    STD_ULOGIC;
      RD5                             :	out    STD_ULOGIC;
      RD6                             :	out    STD_ULOGIC;
      RD7                             :	out    STD_ULOGIC;
      RD8                             :	out    STD_ULOGIC;
      RD9                             :	out    STD_ULOGIC;
      RD10                            :	out    STD_ULOGIC;
      RD11                            :	out    STD_ULOGIC;
      RD12                            :	out    STD_ULOGIC;
      RD13                            :	out    STD_ULOGIC;
      RD14                            :	out    STD_ULOGIC;
      RD15                            :	out    STD_ULOGIC;
      RD16                            :	out    STD_ULOGIC;
      RD17                            :	out    STD_ULOGIC;
      RD18                            :	out    STD_ULOGIC;
      RD19                            :	out    STD_ULOGIC;
      RD20                            :	out    STD_ULOGIC;
      RD21                            :	out    STD_ULOGIC;
      RD22                            :	out    STD_ULOGIC;
      RD23                            :	out    STD_ULOGIC;
      RD24                            :	out    STD_ULOGIC;
      RD25                            :	out    STD_ULOGIC;
      RD26                            :	out    STD_ULOGIC;
      RD27                            :	out    STD_ULOGIC;
      RD28                            :	out    STD_ULOGIC;
      RD29                            :	out    STD_ULOGIC;
      RD30                            :	out    STD_ULOGIC;
      RD31                            :	out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX1_RX32 : entity is FALSE;
end RAMB16K_WX1_RX32;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX1_RX32 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 14;
		WDATA_WIDTH    : integer := 1;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_logic_vector(0 downto 0);

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';
      signal WAD13_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (0 downto 0);
 	signal WAD : std_logic_vector (13 downto 0);
	signal RAD : std_logic_vector (8 downto 0);
	signal RD  : std_logic_vector (31 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD0_ipd;
	WAD <= WAD13_ipd & WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd(0), WD0, tipd_WD0);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);
        VitalWireDelay (WAD13_ipd, WAD13, tipd_WAD13);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD13_WCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD13_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd         : std_ulogic := 'X';
        variable RD11_zd         : std_ulogic := 'X';
        variable RD12_zd         : std_ulogic := 'X';
        variable RD13_zd         : std_ulogic := 'X';
        variable RD14_zd         : std_ulogic := 'X';
        variable RD15_zd         : std_ulogic := 'X';
        variable RD16_zd         : std_ulogic := 'X';
        variable RD17_zd         : std_ulogic := 'X';
        variable RD18_zd         : std_ulogic := 'X';
        variable RD19_zd         : std_ulogic := 'X';
        variable RD20_zd         : std_ulogic := 'X';
        variable RD21_zd         : std_ulogic := 'X';
        variable RD22_zd         : std_ulogic := 'X';
        variable RD23_zd         : std_ulogic := 'X';
        variable RD24_zd         : std_ulogic := 'X';
        variable RD25_zd         : std_ulogic := 'X';
        variable RD26_zd         : std_ulogic := 'X';
        variable RD27_zd         : std_ulogic := 'X';
        variable RD28_zd         : std_ulogic := 'X';
        variable RD29_zd         : std_ulogic := 'X';
        variable RD30_zd         : std_ulogic := 'X';
        variable RD31_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD12_WCLK_posedge,
          TimingData              => Tmkr_WAD12_WCLK_posedge,
          TestSignal              => WAD12_ipd,
          TestSignalName          => "WAD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD13_WCLK_posedge,
          TimingData              => Tmkr_WAD13_WCLK_posedge,
          TestSignal              => WAD13_ipd,
          TestSignalName          => "WAD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;

    VitalBehavior_RD16  : process
      variable RD16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD16_zd := RD(16);

    VitalPathDelay01 (
      OutSignal => RD16,
      GlitchData => O_GlitchData,
      OutSignalName => "RD16",
      OutTemp => RD16_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD16, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(16);
      end process;

    VitalBehavior_RD17  : process
      variable RD17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD17_zd := RD(17);

    VitalPathDelay01 (
      OutSignal => RD17,
      GlitchData => O_GlitchData,
      OutSignalName => "RD17",
      OutTemp => RD17_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD17, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(17);
      end process;

    VitalBehavior_RD18  : process
      variable RD18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD18_zd := RD(18);

    VitalPathDelay01 (
      OutSignal => RD18,
      GlitchData => O_GlitchData,
      OutSignalName => "RD18",
      OutTemp => RD18_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD18, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(18);
      end process;

    VitalBehavior_RD19  : process
      variable RD19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD19_zd := RD(19);

    VitalPathDelay01 (
      OutSignal => RD19,
      GlitchData => O_GlitchData,
      OutSignalName => "RD19",
      OutTemp => RD19_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD19, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(19);
      end process;

    VitalBehavior_RD20  : process
      variable RD20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD20_zd := RD(20);

    VitalPathDelay01 (
      OutSignal => RD20,
      GlitchData => O_GlitchData,
      OutSignalName => "RD20",
      OutTemp => RD20_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD20, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(20);
      end process;

    VitalBehavior_RD21  : process
      variable RD21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD21_zd := RD(21);

    VitalPathDelay01 (
      OutSignal => RD21,
      GlitchData => O_GlitchData,
      OutSignalName => "RD21",
      OutTemp => RD21_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD21, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(21);
      end process;

    VitalBehavior_RD22  : process
      variable RD22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD22_zd := RD(22);

    VitalPathDelay01 (
      OutSignal => RD22,
      GlitchData => O_GlitchData,
      OutSignalName => "RD22",
      OutTemp => RD22_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD22, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(22);
      end process;

    VitalBehavior_RD23  : process
      variable RD23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD23_zd := RD(23);

    VitalPathDelay01 (
      OutSignal => RD23,
      GlitchData => O_GlitchData,
      OutSignalName => "RD23",
      OutTemp => RD23_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD23, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(23);
      end process;

    VitalBehavior_RD24  : process
      variable RD24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD24_zd := RD(24);

    VitalPathDelay01 (
      OutSignal => RD24,
      GlitchData => O_GlitchData,
      OutSignalName => "RD24",
      OutTemp => RD24_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD24, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(24);
      end process;

    VitalBehavior_RD25  : process
      variable RD25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD25_zd := RD(25);

    VitalPathDelay01 (
      OutSignal => RD25,
      GlitchData => O_GlitchData,
      OutSignalName => "RD25",
      OutTemp => RD25_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD25, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(25);
      end process;

    VitalBehavior_RD26  : process
      variable RD26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD26_zd := RD(26);

    VitalPathDelay01 (
      OutSignal => RD26,
      GlitchData => O_GlitchData,
      OutSignalName => "RD26",
      OutTemp => RD26_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD26, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(26);
      end process;

    VitalBehavior_RD27  : process
      variable RD27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD27_zd := RD(27);

    VitalPathDelay01 (
      OutSignal => RD27,
      GlitchData => O_GlitchData,
      OutSignalName => "RD27",
      OutTemp => RD27_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD27, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(27);
      end process;

    VitalBehavior_RD28  : process
      variable RD28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD28_zd := RD(28);

    VitalPathDelay01 (
      OutSignal => RD28,
      GlitchData => O_GlitchData,
      OutSignalName => "RD28",
      OutTemp => RD28_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD28, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(28);
      end process;

    VitalBehavior_RD29  : process
      variable RD29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD29_zd := RD(29);

    VitalPathDelay01 (
      OutSignal => RD29,
      GlitchData => O_GlitchData,
      OutSignalName => "RD29",
      OutTemp => RD29_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD29, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(29);
      end process;

    VitalBehavior_RD30  : process
      variable RD30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD30_zd := RD(30);

    VitalPathDelay01 (
      OutSignal => RD30,
      GlitchData => O_GlitchData,
      OutSignalName => "RD30",
      OutTemp => RD30_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD30, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(30);
      end process;

    VitalBehavior_RD31  : process
      variable RD31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD31_zd := RD(31);

    VitalPathDelay01 (
      OutSignal => RD31,
      GlitchData => O_GlitchData,
      OutSignalName => "RD31",
      OutTemp => RD31_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD31, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(31);
      end process;



	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 14,
		WDATA_WIDTH    => 1,
		RADDR_WIDTH    => 9,
		RDATA_WIDTH    => 32,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16K_WX1_RX32_VITAL of RAMB16K_WX1_RX32 is
   for VITAL
   end for;
end CFG_RAMB16K_WX1_RX32_VITAL;



----- CELL RAMB16K_WX2_RX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_WX2_RX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_RAD11_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD11_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_RAD12_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD12_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RAD11                           :	in    STD_ULOGIC;
      RAD12                           :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX2_RX2 : entity is FALSE;
end RAMB16K_WX2_RX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX2_RX2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 13;
		WDATA_WIDTH    : integer := 2;
		RADDR_WIDTH    : integer := 13;
		RDATA_WIDTH    : integer := 2;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';
      signal RAD11_ipd     : std_ulogic := 'X';
      signal RAD12_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (1 downto 0);
 	signal WAD : std_logic_vector (12 downto 0);
	signal RAD : std_logic_vector (12 downto 0);
	signal RD  : std_logic_vector (1 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD1_ipd & WD0_ipd;
	WAD <= WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge   : std_ulogic  := '0';
        variable Tviol_RAD11_RCLK_posedge   : std_ulogic  := '0';
        variable Tviol_RAD12_RCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD11_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD12_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD12_WCLK_posedge,
          TimingData              => Tmkr_WAD12_WCLK_posedge,
          TestSignal              => WAD12_ipd,
          TestSignalName          => "WAD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD11_RCLK_posedge,
          TimingData              => Tmkr_RAD11_RCLK_posedge,
          TestSignal              => RAD11_ipd,
          TestSignalName          => "RAD11",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD11_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD11_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD11_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD11_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD12_RCLK_posedge,
          TimingData              => Tmkr_RAD12_RCLK_posedge,
          TestSignal              => RAD12_ipd,
          TestSignalName          => "RAD12",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD12_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD12_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD12_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD12_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
		 Tviol_WD1_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or Tviol_RAD9_RCLK_posedge or 
                 Tviol_RAD10_RCLK_posedge or Tviol_RAD11_RCLK_posedge or 
                 Tviol_RAD12_RCLK_posedge or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;



	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 13,
		WDATA_WIDTH    => 2,
		RADDR_WIDTH    => 13,
		RDATA_WIDTH    => 2,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16K_WX2_RX2_VITAL of RAMB16K_WX2_RX2 is
   for VITAL
   end for;
end CFG_RAMB16K_WX2_RX2_VITAL;



----- CELL RAMB16K_WX2_RX4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_WX2_RX4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_RAD11_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD11_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RAD11                           :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out    STD_ULOGIC;
      RD2                             :	out    STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX2_RX4 : entity is FALSE;
end RAMB16K_WX2_RX4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX2_RX4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 13;
		WDATA_WIDTH    : integer := 2;
		RADDR_WIDTH    : integer := 12;
		RDATA_WIDTH    : integer := 4;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';
      signal RAD11_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (1 downto 0);
 	signal WAD : std_logic_vector (12 downto 0);
	signal RAD : std_logic_vector (11 downto 0);
	signal RD  : std_logic_vector (3 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD1_ipd & WD0_ipd;
	WAD <= WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge   : std_ulogic  := '0';
        variable Tviol_RAD11_RCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;


        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD11_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD12_WCLK_posedge,
          TimingData              => Tmkr_WAD12_WCLK_posedge,
          TestSignal              => WAD12_ipd,
          TestSignalName          => "WAD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD11_RCLK_posedge,
          TimingData              => Tmkr_RAD11_RCLK_posedge,
          TestSignal              => RAD11_ipd,
          TestSignalName          => "RAD11",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD11_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD11_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD11_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD11_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
		 Tviol_WD1_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or Tviol_RAD9_RCLK_posedge or 
                 Tviol_RAD10_RCLK_posedge or Tviol_RAD11_RCLK_posedge or  
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;



	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 13,
		WDATA_WIDTH    => 2,
		RADDR_WIDTH    => 12,
		RDATA_WIDTH    => 4,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);


end VITAL;

configuration CFG_RAMB16K_WX2_RX4_VITAL of RAMB16K_WX2_RX4 is
   for VITAL
   end for;
end CFG_RAMB16K_WX2_RX4_VITAL;



----- CELL RAMB16K_WX2_RX8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_WX2_RX8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out    STD_ULOGIC;
      RD2                             :	out    STD_ULOGIC;
      RD3                             :	out    STD_ULOGIC;
      RD4                             :	out    STD_ULOGIC;
      RD5                             :	out    STD_ULOGIC;
      RD6                             :	out    STD_ULOGIC;
      RD7                             :	out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX2_RX8 : entity is FALSE;
end RAMB16K_WX2_RX8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX2_RX8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 13;
		WDATA_WIDTH    : integer := 2;
		RADDR_WIDTH    : integer := 11;
		RDATA_WIDTH    : integer := 8;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (1 downto 0);
 	signal WAD : std_logic_vector (12 downto 0);
	signal RAD : std_logic_vector (10 downto 0);
	signal RD  : std_logic_vector (7 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD1_ipd & WD0_ipd;
	WAD <= WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;


  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD12_WCLK_posedge,
          TimingData              => Tmkr_WAD12_WCLK_posedge,
          TestSignal              => WAD12_ipd,
          TestSignalName          => "WAD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
		 Tviol_WD1_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or Tviol_RAD9_RCLK_posedge or 
                 Tviol_RAD10_RCLK_posedge or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;



	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 13,
		WDATA_WIDTH    => 2,
		RADDR_WIDTH    => 11,
		RDATA_WIDTH    => 8,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16K_WX2_RX8_VITAL of RAMB16K_WX2_RX8 is
   for VITAL
   end for;
end CFG_RAMB16K_WX2_RX8_VITAL;



----- CELL RAMB16K_WX2_RX16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_WX2_RX16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD10                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD11                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD12                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD13                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD14                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD15                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out    STD_ULOGIC;
      RD2                             :	out    STD_ULOGIC;
      RD3                             :	out    STD_ULOGIC;
      RD4                             :	out    STD_ULOGIC;
      RD5                             :	out    STD_ULOGIC;
      RD6                             :	out    STD_ULOGIC;
      RD7                             :	out    STD_ULOGIC;
      RD8                             :	out    STD_ULOGIC;
      RD9                             :	out    STD_ULOGIC;
      RD10                            :	out    STD_ULOGIC;
      RD11                            :	out    STD_ULOGIC;
      RD12                            :	out    STD_ULOGIC;
      RD13                            :	out    STD_ULOGIC;
      RD14                            :	out    STD_ULOGIC;
      RD15                            :	out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX2_RX16 : entity is FALSE;
end RAMB16K_WX2_RX16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX2_RX16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 13;
		WDATA_WIDTH    : integer := 2;
		RADDR_WIDTH    : integer := 10;
		RDATA_WIDTH    : integer := 16;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (1 downto 0);
 	signal WAD : std_logic_vector (12 downto 0);
	signal RAD : std_logic_vector (9 downto 0);
	signal RD  : std_logic_vector (15 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD1_ipd & WD0_ipd;
	WAD <= WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);

      end block;

      --------------------
      -- RAMB16K_WX2_RX16 Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd         : std_ulogic := 'X';
        variable RD11_zd         : std_ulogic := 'X';
        variable RD12_zd         : std_ulogic := 'X';
        variable RD13_zd         : std_ulogic := 'X';
        variable RD14_zd         : std_ulogic := 'X';
        variable RD15_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          RefSignal               => WCEN_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD12_WCLK_posedge,
          TimingData              => Tmkr_WAD12_WCLK_posedge,
          TestSignal              => WAD12_ipd,
          TestSignalName          => "WAD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or Tviol_RAD9_RCLK_posedge or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;



	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 13,
		WDATA_WIDTH    => 2,
		RADDR_WIDTH    => 10,
		RDATA_WIDTH    => 16,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16K_WX2_RX16_VITAL of RAMB16K_WX2_RX16 is
   for VITAL
   end for;
end CFG_RAMB16K_WX2_RX16_VITAL;



----- CELL RAMB16K_WX2_RX32 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_WX2_RX32 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD10                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD11                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD12                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD13                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD14                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD15                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD26                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD27                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD28                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD29                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD30                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD31                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD16                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD17                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD18                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD19                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD20                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD21                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD22                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD23                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD24                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD25                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out    STD_ULOGIC;
      RD2                             :	out    STD_ULOGIC;
      RD3                             :	out    STD_ULOGIC;
      RD4                             :	out    STD_ULOGIC;
      RD5                             :	out    STD_ULOGIC;
      RD6                             :	out    STD_ULOGIC;
      RD7                             :	out    STD_ULOGIC;
      RD8                             :	out    STD_ULOGIC;
      RD9                             :	out    STD_ULOGIC;
      RD10                            :	out    STD_ULOGIC;
      RD11                            :	out    STD_ULOGIC;
      RD12                            :	out    STD_ULOGIC;
      RD13                            :	out    STD_ULOGIC;
      RD14                            :	out    STD_ULOGIC;
      RD15                            :	out    STD_ULOGIC;
      RD16                            :	out    STD_ULOGIC;
      RD17                            :	out    STD_ULOGIC;
      RD18                            :	out    STD_ULOGIC;
      RD19                            :	out    STD_ULOGIC;
      RD20                            :	out    STD_ULOGIC;
      RD21                            :	out    STD_ULOGIC;
      RD22                            :	out    STD_ULOGIC;
      RD23                            :	out    STD_ULOGIC;
      RD24                            :	out    STD_ULOGIC;
      RD25                            :	out    STD_ULOGIC;
      RD26                            :	out    STD_ULOGIC;
      RD27                            :	out    STD_ULOGIC;
      RD28                            :	out    STD_ULOGIC;
      RD29                            :	out    STD_ULOGIC;
      RD30                            :	out    STD_ULOGIC;
      RD31                            :	out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX2_RX32 : entity is FALSE;
end RAMB16K_WX2_RX32;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX2_RX32 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 13;
		WDATA_WIDTH    : integer := 2;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';
      signal WAD13_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (1 downto 0);
 	signal WAD : std_logic_vector (12 downto 0);
	signal RAD : std_logic_vector (8 downto 0);
	signal RD  : std_logic_vector (31 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD1_ipd & WD0_ipd;
	WAD <= WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';


        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd         : std_ulogic := 'X';
        variable RD11_zd         : std_ulogic := 'X';
        variable RD12_zd         : std_ulogic := 'X';
        variable RD13_zd         : std_ulogic := 'X';
        variable RD14_zd         : std_ulogic := 'X';
        variable RD15_zd         : std_ulogic := 'X';
        variable RD16_zd         : std_ulogic := 'X';
        variable RD17_zd         : std_ulogic := 'X';
        variable RD18_zd         : std_ulogic := 'X';
        variable RD19_zd         : std_ulogic := 'X';
        variable RD20_zd         : std_ulogic := 'X';
        variable RD21_zd         : std_ulogic := 'X';
        variable RD22_zd         : std_ulogic := 'X';
        variable RD23_zd         : std_ulogic := 'X';
        variable RD24_zd         : std_ulogic := 'X';
        variable RD25_zd         : std_ulogic := 'X';
        variable RD26_zd         : std_ulogic := 'X';
        variable RD27_zd         : std_ulogic := 'X';
        variable RD28_zd         : std_ulogic := 'X';
        variable RD29_zd         : std_ulogic := 'X';
        variable RD30_zd         : std_ulogic := 'X';
        variable RD31_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD12_WCLK_posedge,
          TimingData              => Tmkr_WAD12_WCLK_posedge,
          TestSignal              => WAD12_ipd,
          TestSignalName          => "WAD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
		 Tviol_WD1_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;

    VitalBehavior_RD16  : process
      variable RD16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD16_zd := RD(16);

    VitalPathDelay01 (
      OutSignal => RD16,
      GlitchData => O_GlitchData,
      OutSignalName => "RD16",
      OutTemp => RD16_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD16, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(16);
      end process;

    VitalBehavior_RD17  : process
      variable RD17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD17_zd := RD(17);

    VitalPathDelay01 (
      OutSignal => RD17,
      GlitchData => O_GlitchData,
      OutSignalName => "RD17",
      OutTemp => RD17_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD17, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(17);
      end process;

    VitalBehavior_RD18  : process
      variable RD18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD18_zd := RD(18);

    VitalPathDelay01 (
      OutSignal => RD18,
      GlitchData => O_GlitchData,
      OutSignalName => "RD18",
      OutTemp => RD18_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD18, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(18);
      end process;

    VitalBehavior_RD19  : process
      variable RD19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD19_zd := RD(19);

    VitalPathDelay01 (
      OutSignal => RD19,
      GlitchData => O_GlitchData,
      OutSignalName => "RD19",
      OutTemp => RD19_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD19, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(19);
      end process;

    VitalBehavior_RD20  : process
      variable RD20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD20_zd := RD(20);

    VitalPathDelay01 (
      OutSignal => RD20,
      GlitchData => O_GlitchData,
      OutSignalName => "RD20",
      OutTemp => RD20_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD20, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(20);
      end process;

    VitalBehavior_RD21  : process
      variable RD21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD21_zd := RD(21);

    VitalPathDelay01 (
      OutSignal => RD21,
      GlitchData => O_GlitchData,
      OutSignalName => "RD21",
      OutTemp => RD21_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD21, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(21);
      end process;

    VitalBehavior_RD22  : process
      variable RD22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD22_zd := RD(22);

    VitalPathDelay01 (
      OutSignal => RD22,
      GlitchData => O_GlitchData,
      OutSignalName => "RD22",
      OutTemp => RD22_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD22, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(22);
      end process;

    VitalBehavior_RD23  : process
      variable RD23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD23_zd := RD(23);

    VitalPathDelay01 (
      OutSignal => RD23,
      GlitchData => O_GlitchData,
      OutSignalName => "RD23",
      OutTemp => RD23_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD23, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(23);
      end process;

    VitalBehavior_RD24  : process
      variable RD24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD24_zd := RD(24);

    VitalPathDelay01 (
      OutSignal => RD24,
      GlitchData => O_GlitchData,
      OutSignalName => "RD24",
      OutTemp => RD24_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD24, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(24);
      end process;

    VitalBehavior_RD25  : process
      variable RD25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD25_zd := RD(25);

    VitalPathDelay01 (
      OutSignal => RD25,
      GlitchData => O_GlitchData,
      OutSignalName => "RD25",
      OutTemp => RD25_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD25, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(25);
      end process;

    VitalBehavior_RD26  : process
      variable RD26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD26_zd := RD(26);

    VitalPathDelay01 (
      OutSignal => RD26,
      GlitchData => O_GlitchData,
      OutSignalName => "RD26",
      OutTemp => RD26_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD26, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(26);
      end process;

    VitalBehavior_RD27  : process
      variable RD27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD27_zd := RD(27);

    VitalPathDelay01 (
      OutSignal => RD27,
      GlitchData => O_GlitchData,
      OutSignalName => "RD27",
      OutTemp => RD27_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD27, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(27);
      end process;

    VitalBehavior_RD28  : process
      variable RD28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD28_zd := RD(28);

    VitalPathDelay01 (
      OutSignal => RD28,
      GlitchData => O_GlitchData,
      OutSignalName => "RD28",
      OutTemp => RD28_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD28, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(28);
      end process;

    VitalBehavior_RD29  : process
      variable RD29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD29_zd := RD(29);

    VitalPathDelay01 (
      OutSignal => RD29,
      GlitchData => O_GlitchData,
      OutSignalName => "RD29",
      OutTemp => RD29_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD29, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(29);
      end process;

    VitalBehavior_RD30  : process
      variable RD30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD30_zd := RD(30);

    VitalPathDelay01 (
      OutSignal => RD30,
      GlitchData => O_GlitchData,
      OutSignalName => "RD30",
      OutTemp => RD30_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD30, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(30);
      end process;

    VitalBehavior_RD31  : process
      variable RD31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD31_zd := RD(31);

    VitalPathDelay01 (
      OutSignal => RD31,
      GlitchData => O_GlitchData,
      OutSignalName => "RD31",
      OutTemp => RD31_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD31, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(31);
      end process;



	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 13,
		WDATA_WIDTH    => 2,
		RADDR_WIDTH    => 9,
		RDATA_WIDTH    => 32,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16K_WX2_RX32_VITAL of RAMB16K_WX2_RX32 is
   for VITAL
   end for;
end CFG_RAMB16K_WX2_RX32_VITAL;



----- CELL RAMB16K_WX4_RX4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_WX4_RX4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_RAD11_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD11_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RAD11                           :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out    STD_ULOGIC;
      RD2                             :	out    STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX4_RX4 : entity is FALSE;
end RAMB16K_WX4_RX4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX4_RX4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 12;
		WDATA_WIDTH    : integer := 4;
		RADDR_WIDTH    : integer := 12;
		RDATA_WIDTH    : integer := 4;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';


      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';
      signal RAD11_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (3 downto 0);
 	signal WAD : std_logic_vector (11 downto 0);
	signal RAD : std_logic_vector (11 downto 0);
	signal RD  : std_logic_vector (3 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge   : std_ulogic  := '0';
        variable Tviol_RAD11_RCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD11_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD11_RCLK_posedge,
          TimingData              => Tmkr_RAD11_RCLK_posedge,
          TestSignal              => RAD11_ipd,
          TestSignalName          => "RAD11",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD11_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD11_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD11_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD11_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WD0_WCLK_posedge or Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or Tviol_WD3_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or Tviol_RAD9_RCLK_posedge or 
                 Tviol_RAD10_RCLK_posedge or Tviol_RAD11_RCLK_posedge or  
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;



	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 12,
		WDATA_WIDTH    => 4,
		RADDR_WIDTH    => 12,
		RDATA_WIDTH    => 4,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16K_WX4_RX4_VITAL of RAMB16K_WX4_RX4 is
   for VITAL
   end for;
end CFG_RAMB16K_WX4_RX4_VITAL;



----- CELL RAMB16K_WX4_RX8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_WX4_RX8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out    STD_ULOGIC;
      RD2                             :	out    STD_ULOGIC;
      RD3                             :	out    STD_ULOGIC;
      RD4                             :	out    STD_ULOGIC;
      RD5                             :	out    STD_ULOGIC;
      RD6                             :	out    STD_ULOGIC;
      RD7                             :	out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX4_RX8 : entity is FALSE;
end RAMB16K_WX4_RX8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX4_RX8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 12;
		WDATA_WIDTH    : integer := 4;
		RADDR_WIDTH    : integer := 11;
		RDATA_WIDTH    : integer := 8;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (3 downto 0);
 	signal WAD : std_logic_vector (11 downto 0);
	signal RAD : std_logic_vector (10 downto 0);
	signal RD  : std_logic_vector (7 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;


  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WD0_WCLK_posedge or Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or Tviol_WD3_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or Tviol_RAD9_RCLK_posedge or 
                 Tviol_RAD10_RCLK_posedge or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;



	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 12,
		WDATA_WIDTH    => 4,
		RADDR_WIDTH    => 11,
		RDATA_WIDTH    => 8,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16K_WX4_RX8_VITAL of RAMB16K_WX4_RX8 is
   for VITAL
   end for;
end CFG_RAMB16K_WX4_RX8_VITAL;



----- CELL RAMB16K_WX4_RX16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_WX4_RX16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD10                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD11                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD12                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD13                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD14                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD15                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out    STD_ULOGIC;
      RD2                             :	out    STD_ULOGIC;
      RD3                             :	out    STD_ULOGIC;
      RD4                             :	out    STD_ULOGIC;
      RD5                             :	out    STD_ULOGIC;
      RD6                             :	out    STD_ULOGIC;
      RD7                             :	out    STD_ULOGIC;
      RD8                             :	out    STD_ULOGIC;
      RD9                             :	out    STD_ULOGIC;
      RD10                            :	out    STD_ULOGIC;
      RD11                            :	out    STD_ULOGIC;
      RD12                            :	out    STD_ULOGIC;
      RD13                            :	out    STD_ULOGIC;
      RD14                            :	out    STD_ULOGIC;
      RD15                            :	out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX4_RX16 : entity is FALSE;
end RAMB16K_WX4_RX16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX4_RX16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 12;
		WDATA_WIDTH    : integer := 4;
		RADDR_WIDTH    : integer := 10;
		RDATA_WIDTH    : integer := 16;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (3 downto 0);
 	signal WAD : std_logic_vector (11 downto 0);
	signal RAD : std_logic_vector (9 downto 0);
	signal RD  : std_logic_vector (15 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);

      end block;

      --------------------
      -- RAMB16K_WX4_RX16 Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd         : std_ulogic := 'X';
        variable RD11_zd         : std_ulogic := 'X';
        variable RD12_zd         : std_ulogic := 'X';
        variable RD13_zd         : std_ulogic := 'X';
        variable RD14_zd         : std_ulogic := 'X';
        variable RD15_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WD0_WCLK_posedge or Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or Tviol_WD3_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or Tviol_RAD9_RCLK_posedge or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;



	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 12,
		WDATA_WIDTH    => 4,
		RADDR_WIDTH    => 10,
		RDATA_WIDTH    => 16,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16K_WX4_RX16_VITAL of RAMB16K_WX4_RX16 is
   for VITAL
   end for;
end CFG_RAMB16K_WX4_RX16_VITAL;



----- CELL RAMB16K_WX4_RX32 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_WX4_RX32 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD10                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD11                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD12                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD13                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD14                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD15                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD26                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD27                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD28                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD29                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD30                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD31                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD16                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD17                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD18                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD19                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD20                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD21                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD22                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD23                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD24                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD25                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out    STD_ULOGIC;
      RD2                             :	out    STD_ULOGIC;
      RD3                             :	out    STD_ULOGIC;
      RD4                             :	out    STD_ULOGIC;
      RD5                             :	out    STD_ULOGIC;
      RD6                             :	out    STD_ULOGIC;
      RD7                             :	out    STD_ULOGIC;
      RD8                             :	out    STD_ULOGIC;
      RD9                             :	out    STD_ULOGIC;
      RD10                            :	out    STD_ULOGIC;
      RD11                            :	out    STD_ULOGIC;
      RD12                            :	out    STD_ULOGIC;
      RD13                            :	out    STD_ULOGIC;
      RD14                            :	out    STD_ULOGIC;
      RD15                            :	out    STD_ULOGIC;
      RD16                            :	out    STD_ULOGIC;
      RD17                            :	out    STD_ULOGIC;
      RD18                            :	out    STD_ULOGIC;
      RD19                            :	out    STD_ULOGIC;
      RD20                            :	out    STD_ULOGIC;
      RD21                            :	out    STD_ULOGIC;
      RD22                            :	out    STD_ULOGIC;
      RD23                            :	out    STD_ULOGIC;
      RD24                            :	out    STD_ULOGIC;
      RD25                            :	out    STD_ULOGIC;
      RD26                            :	out    STD_ULOGIC;
      RD27                            :	out    STD_ULOGIC;
      RD28                            :	out    STD_ULOGIC;
      RD29                            :	out    STD_ULOGIC;
      RD30                            :	out    STD_ULOGIC;
      RD31                            :	out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX4_RX32 : entity is FALSE;
end RAMB16K_WX4_RX32;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX4_RX32 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 12;
		WDATA_WIDTH    : integer := 4;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (3 downto 0);
 	signal WAD : std_logic_vector (11 downto 0);
	signal RAD : std_logic_vector (8 downto 0);
	signal RD  : std_logic_vector (31 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd         : std_ulogic := 'X';
        variable RD11_zd         : std_ulogic := 'X';
        variable RD12_zd         : std_ulogic := 'X';
        variable RD13_zd         : std_ulogic := 'X';
        variable RD14_zd         : std_ulogic := 'X';
        variable RD15_zd         : std_ulogic := 'X';
        variable RD16_zd         : std_ulogic := 'X';
        variable RD17_zd         : std_ulogic := 'X';
        variable RD18_zd         : std_ulogic := 'X';
        variable RD19_zd         : std_ulogic := 'X';
        variable RD20_zd         : std_ulogic := 'X';
        variable RD21_zd         : std_ulogic := 'X';
        variable RD22_zd         : std_ulogic := 'X';
        variable RD23_zd         : std_ulogic := 'X';
        variable RD24_zd         : std_ulogic := 'X';
        variable RD25_zd         : std_ulogic := 'X';
        variable RD26_zd         : std_ulogic := 'X';
        variable RD27_zd         : std_ulogic := 'X';
        variable RD28_zd         : std_ulogic := 'X';
        variable RD29_zd         : std_ulogic := 'X';
        variable RD30_zd         : std_ulogic := 'X';
        variable RD31_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCEN_ipd,
          RefSignalName           => "WCEN",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCEN",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WD0_WCLK_posedge or Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or Tviol_WD3_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;

    VitalBehavior_RD16  : process
      variable RD16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD16_zd := RD(16);

    VitalPathDelay01 (
      OutSignal => RD16,
      GlitchData => O_GlitchData,
      OutSignalName => "RD16",
      OutTemp => RD16_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD16, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(16);
      end process;

    VitalBehavior_RD17  : process
      variable RD17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD17_zd := RD(17);

    VitalPathDelay01 (
      OutSignal => RD17,
      GlitchData => O_GlitchData,
      OutSignalName => "RD17",
      OutTemp => RD17_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD17, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(17);
      end process;

    VitalBehavior_RD18  : process
      variable RD18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD18_zd := RD(18);

    VitalPathDelay01 (
      OutSignal => RD18,
      GlitchData => O_GlitchData,
      OutSignalName => "RD18",
      OutTemp => RD18_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD18, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(18);
      end process;

    VitalBehavior_RD19  : process
      variable RD19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD19_zd := RD(19);

    VitalPathDelay01 (
      OutSignal => RD19,
      GlitchData => O_GlitchData,
      OutSignalName => "RD19",
      OutTemp => RD19_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD19, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(19);
      end process;

    VitalBehavior_RD20  : process
      variable RD20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD20_zd := RD(20);

    VitalPathDelay01 (
      OutSignal => RD20,
      GlitchData => O_GlitchData,
      OutSignalName => "RD20",
      OutTemp => RD20_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD20, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(20);
      end process;

    VitalBehavior_RD21  : process
      variable RD21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD21_zd := RD(21);

    VitalPathDelay01 (
      OutSignal => RD21,
      GlitchData => O_GlitchData,
      OutSignalName => "RD21",
      OutTemp => RD21_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD21, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(21);
      end process;

    VitalBehavior_RD22  : process
      variable RD22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD22_zd := RD(22);

    VitalPathDelay01 (
      OutSignal => RD22,
      GlitchData => O_GlitchData,
      OutSignalName => "RD22",
      OutTemp => RD22_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD22, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(22);
      end process;

    VitalBehavior_RD23  : process
      variable RD23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD23_zd := RD(23);

    VitalPathDelay01 (
      OutSignal => RD23,
      GlitchData => O_GlitchData,
      OutSignalName => "RD23",
      OutTemp => RD23_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD23, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(23);
      end process;

    VitalBehavior_RD24  : process
      variable RD24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD24_zd := RD(24);

    VitalPathDelay01 (
      OutSignal => RD24,
      GlitchData => O_GlitchData,
      OutSignalName => "RD24",
      OutTemp => RD24_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD24, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(24);
      end process;

    VitalBehavior_RD25  : process
      variable RD25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD25_zd := RD(25);

    VitalPathDelay01 (
      OutSignal => RD25,
      GlitchData => O_GlitchData,
      OutSignalName => "RD25",
      OutTemp => RD25_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD25, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(25);
      end process;

    VitalBehavior_RD26  : process
      variable RD26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD26_zd := RD(26);

    VitalPathDelay01 (
      OutSignal => RD26,
      GlitchData => O_GlitchData,
      OutSignalName => "RD26",
      OutTemp => RD26_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD26, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(26);
      end process;

    VitalBehavior_RD27  : process
      variable RD27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD27_zd := RD(27);

    VitalPathDelay01 (
      OutSignal => RD27,
      GlitchData => O_GlitchData,
      OutSignalName => "RD27",
      OutTemp => RD27_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD27, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(27);
      end process;

    VitalBehavior_RD28  : process
      variable RD28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD28_zd := RD(28);

    VitalPathDelay01 (
      OutSignal => RD28,
      GlitchData => O_GlitchData,
      OutSignalName => "RD28",
      OutTemp => RD28_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD28, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(28);
      end process;

    VitalBehavior_RD29  : process
      variable RD29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD29_zd := RD(29);

    VitalPathDelay01 (
      OutSignal => RD29,
      GlitchData => O_GlitchData,
      OutSignalName => "RD29",
      OutTemp => RD29_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD29, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(29);
      end process;

    VitalBehavior_RD30  : process
      variable RD30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD30_zd := RD(30);

    VitalPathDelay01 (
      OutSignal => RD30,
      GlitchData => O_GlitchData,
      OutSignalName => "RD30",
      OutTemp => RD30_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD30, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(30);
      end process;

    VitalBehavior_RD31  : process
      variable RD31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD31_zd := RD(31);

    VitalPathDelay01 (
      OutSignal => RD31,
      GlitchData => O_GlitchData,
      OutSignalName => "RD31",
      OutTemp => RD31_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD31, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(31);
      end process;



	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 12,
		WDATA_WIDTH    => 4,
		RADDR_WIDTH    => 9,
		RDATA_WIDTH    => 32,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16K_WX4_RX32_VITAL of RAMB16K_WX4_RX32 is
   for VITAL
   end for;
end CFG_RAMB16K_WX4_RX32_VITAL;



----- CELL RAMB16K_WX8_RX8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_WX8_RX8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out    STD_ULOGIC;
      RD2                             :	out    STD_ULOGIC;
      RD3                             :	out    STD_ULOGIC;
      RD4                             :	out    STD_ULOGIC;
      RD5                             :	out    STD_ULOGIC;
      RD6                             :	out    STD_ULOGIC;
      RD7                             :	out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX8_RX8 : entity is FALSE;
end RAMB16K_WX8_RX8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX8_RX8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 11;
		WDATA_WIDTH    : integer := 8;
		RADDR_WIDTH    : integer := 11;
		RDATA_WIDTH    : integer := 8;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (7 downto 0);
 	signal WAD : std_logic_vector (10 downto 0);
	signal RAD : std_logic_vector (10 downto 0);
	signal RD  : std_logic_vector (7 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;


  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);


        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;


        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or 
                 Tviol_WD0_WCLK_posedge or Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or Tviol_WD7_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or Tviol_RAD9_RCLK_posedge or 
                 Tviol_RAD10_RCLK_posedge or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;



	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 11,
		WDATA_WIDTH    => 8,
		RADDR_WIDTH    => 11,
		RDATA_WIDTH    => 8,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);


end VITAL;

configuration CFG_RAMB16K_WX8_RX8_VITAL of RAMB16K_WX8_RX8 is
   for VITAL
   end for;
end CFG_RAMB16K_WX8_RX8_VITAL;


----- CELL RAMB16K_WX8_RX16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_WX8_RX16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD10                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD11                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD12                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD13                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD14                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD15                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out    STD_ULOGIC;
      RD2                             :	out    STD_ULOGIC;
      RD3                             :	out    STD_ULOGIC;
      RD4                             :	out    STD_ULOGIC;
      RD5                             :	out    STD_ULOGIC;
      RD6                             :	out    STD_ULOGIC;
      RD7                             :	out    STD_ULOGIC;
      RD8                             :	out    STD_ULOGIC;
      RD9                             :	out    STD_ULOGIC;
      RD10                            :	out    STD_ULOGIC;
      RD11                            :	out    STD_ULOGIC;
      RD12                            :	out    STD_ULOGIC;
      RD13                            :	out    STD_ULOGIC;
      RD14                            :	out    STD_ULOGIC;
      RD15                            :	out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX8_RX16 : entity is FALSE;
end RAMB16K_WX8_RX16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX8_RX16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 11;
		WDATA_WIDTH    : integer := 8;
		RADDR_WIDTH    : integer := 10;
		RDATA_WIDTH    : integer := 16;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;


      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (7 downto 0);
 	signal WAD : std_logic_vector (10 downto 0);
	signal RAD : std_logic_vector (9 downto 0);
	signal RD  : std_logic_vector (15 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);

      end block;

      --------------------
      -- RAMB16K_WX8_RX16 Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd         : std_ulogic := 'X';
        variable RD11_zd         : std_ulogic := 'X';
        variable RD12_zd         : std_ulogic := 'X';
        variable RD13_zd         : std_ulogic := 'X';
        variable RD14_zd         : std_ulogic := 'X';
        variable RD15_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or Tviol_WD7_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or Tviol_RAD9_RCLK_posedge or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;



	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 11,
		WDATA_WIDTH    => 8,
		RADDR_WIDTH    => 10,
		RDATA_WIDTH    => 16,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16K_WX8_RX16_VITAL of RAMB16K_WX8_RX16 is
   for VITAL
   end for;
end CFG_RAMB16K_WX8_RX16_VITAL;



----- CELL RAMB16K_WX8_RX32 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_WX8_RX32 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD10                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD11                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD12                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD13                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD14                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD15                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD26                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD27                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD28                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD29                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD30                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD31                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD16                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD17                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD18                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD19                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD20                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD21                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD22                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD23                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD24                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD25                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out    STD_ULOGIC;
      RD2                             :	out    STD_ULOGIC;
      RD3                             :	out    STD_ULOGIC;
      RD4                             :	out    STD_ULOGIC;
      RD5                             :	out    STD_ULOGIC;
      RD6                             :	out    STD_ULOGIC;
      RD7                             :	out    STD_ULOGIC;
      RD8                             :	out    STD_ULOGIC;
      RD9                             :	out    STD_ULOGIC;
      RD10                            :	out    STD_ULOGIC;
      RD11                            :	out    STD_ULOGIC;
      RD12                            :	out    STD_ULOGIC;
      RD13                            :	out    STD_ULOGIC;
      RD14                            :	out    STD_ULOGIC;
      RD15                            :	out    STD_ULOGIC;
      RD16                            :	out    STD_ULOGIC;
      RD17                            :	out    STD_ULOGIC;
      RD18                            :	out    STD_ULOGIC;
      RD19                            :	out    STD_ULOGIC;
      RD20                            :	out    STD_ULOGIC;
      RD21                            :	out    STD_ULOGIC;
      RD22                            :	out    STD_ULOGIC;
      RD23                            :	out    STD_ULOGIC;
      RD24                            :	out    STD_ULOGIC;
      RD25                            :	out    STD_ULOGIC;
      RD26                            :	out    STD_ULOGIC;
      RD27                            :	out    STD_ULOGIC;
      RD28                            :	out    STD_ULOGIC;
      RD29                            :	out    STD_ULOGIC;
      RD30                            :	out    STD_ULOGIC;
      RD31                            :	out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX8_RX32 : entity is FALSE;
end RAMB16K_WX8_RX32;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX8_RX32 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 11;
		WDATA_WIDTH    : integer := 8;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (7 downto 0);
 	signal WAD : std_logic_vector (10 downto 0);
	signal RAD : std_logic_vector (8 downto 0);
	signal RD  : std_logic_vector (31 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd         : std_ulogic := 'X';
        variable RD11_zd         : std_ulogic := 'X';
        variable RD12_zd         : std_ulogic := 'X';
        variable RD13_zd         : std_ulogic := 'X';
        variable RD14_zd         : std_ulogic := 'X';
        variable RD15_zd         : std_ulogic := 'X';
        variable RD16_zd         : std_ulogic := 'X';
        variable RD17_zd         : std_ulogic := 'X';
        variable RD18_zd         : std_ulogic := 'X';
        variable RD19_zd         : std_ulogic := 'X';
        variable RD20_zd         : std_ulogic := 'X';
        variable RD21_zd         : std_ulogic := 'X';
        variable RD22_zd         : std_ulogic := 'X';
        variable RD23_zd         : std_ulogic := 'X';
        variable RD24_zd         : std_ulogic := 'X';
        variable RD25_zd         : std_ulogic := 'X';
        variable RD26_zd         : std_ulogic := 'X';
        variable RD27_zd         : std_ulogic := 'X';
        variable RD28_zd         : std_ulogic := 'X';
        variable RD29_zd         : std_ulogic := 'X';
        variable RD30_zd         : std_ulogic := 'X';
        variable RD31_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          RefSignal               => RCEN_ipd,
          RefSignalName           => "RCEN",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or Tviol_WD7_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;

    VitalBehavior_RD16  : process
      variable RD16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD16_zd := RD(16);

    VitalPathDelay01 (
      OutSignal => RD16,
      GlitchData => O_GlitchData,
      OutSignalName => "RD16",
      OutTemp => RD16_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD16, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(16);
      end process;

    VitalBehavior_RD17  : process
      variable RD17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD17_zd := RD(17);

    VitalPathDelay01 (
      OutSignal => RD17,
      GlitchData => O_GlitchData,
      OutSignalName => "RD17",
      OutTemp => RD17_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD17, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(17);
      end process;

    VitalBehavior_RD18  : process
      variable RD18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD18_zd := RD(18);

    VitalPathDelay01 (
      OutSignal => RD18,
      GlitchData => O_GlitchData,
      OutSignalName => "RD18",
      OutTemp => RD18_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD18, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(18);
      end process;

    VitalBehavior_RD19  : process
      variable RD19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD19_zd := RD(19);

    VitalPathDelay01 (
      OutSignal => RD19,
      GlitchData => O_GlitchData,
      OutSignalName => "RD19",
      OutTemp => RD19_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD19, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(19);
      end process;

    VitalBehavior_RD20  : process
      variable RD20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD20_zd := RD(20);

    VitalPathDelay01 (
      OutSignal => RD20,
      GlitchData => O_GlitchData,
      OutSignalName => "RD20",
      OutTemp => RD20_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD20, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(20);
      end process;

    VitalBehavior_RD21  : process
      variable RD21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD21_zd := RD(21);

    VitalPathDelay01 (
      OutSignal => RD21,
      GlitchData => O_GlitchData,
      OutSignalName => "RD21",
      OutTemp => RD21_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD21, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(21);
      end process;

    VitalBehavior_RD22  : process
      variable RD22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD22_zd := RD(22);

    VitalPathDelay01 (
      OutSignal => RD22,
      GlitchData => O_GlitchData,
      OutSignalName => "RD22",
      OutTemp => RD22_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD22, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(22);
      end process;

    VitalBehavior_RD23  : process
      variable RD23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD23_zd := RD(23);

    VitalPathDelay01 (
      OutSignal => RD23,
      GlitchData => O_GlitchData,
      OutSignalName => "RD23",
      OutTemp => RD23_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD23, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(23);
      end process;

    VitalBehavior_RD24  : process
      variable RD24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD24_zd := RD(24);

    VitalPathDelay01 (
      OutSignal => RD24,
      GlitchData => O_GlitchData,
      OutSignalName => "RD24",
      OutTemp => RD24_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD24, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(24);
      end process;

    VitalBehavior_RD25  : process
      variable RD25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD25_zd := RD(25);

    VitalPathDelay01 (
      OutSignal => RD25,
      GlitchData => O_GlitchData,
      OutSignalName => "RD25",
      OutTemp => RD25_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD25, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(25);
      end process;

    VitalBehavior_RD26  : process
      variable RD26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD26_zd := RD(26);

    VitalPathDelay01 (
      OutSignal => RD26,
      GlitchData => O_GlitchData,
      OutSignalName => "RD26",
      OutTemp => RD26_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD26, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(26);
      end process;

    VitalBehavior_RD27  : process
      variable RD27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD27_zd := RD(27);

    VitalPathDelay01 (
      OutSignal => RD27,
      GlitchData => O_GlitchData,
      OutSignalName => "RD27",
      OutTemp => RD27_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD27, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(27);
      end process;

    VitalBehavior_RD28  : process
      variable RD28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD28_zd := RD(28);

    VitalPathDelay01 (
      OutSignal => RD28,
      GlitchData => O_GlitchData,
      OutSignalName => "RD28",
      OutTemp => RD28_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD28, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(28);
      end process;

    VitalBehavior_RD29  : process
      variable RD29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD29_zd := RD(29);

    VitalPathDelay01 (
      OutSignal => RD29,
      GlitchData => O_GlitchData,
      OutSignalName => "RD29",
      OutTemp => RD29_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD29, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(29);
      end process;

    VitalBehavior_RD30  : process
      variable RD30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD30_zd := RD(30);

    VitalPathDelay01 (
      OutSignal => RD30,
      GlitchData => O_GlitchData,
      OutSignalName => "RD30",
      OutTemp => RD30_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD30, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(30);
      end process;

    VitalBehavior_RD31  : process
      variable RD31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD31_zd := RD(31);

    VitalPathDelay01 (
      OutSignal => RD31,
      GlitchData => O_GlitchData,
      OutSignalName => "RD31",
      OutTemp => RD31_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD31, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(31);
      end process;



	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 11,
		WDATA_WIDTH    => 8,
		RADDR_WIDTH    => 9,
		RDATA_WIDTH    => 32,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16K_WX8_RX32_VITAL of RAMB16K_WX8_RX32 is
   for VITAL
   end for;
end CFG_RAMB16K_WX8_RX32_VITAL;



----- CELL RAMB16K_WX16_RX16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_WX16_RX16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD10                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD11                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD12                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD13                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD14                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD15                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out    STD_ULOGIC;
      RD2                             :	out    STD_ULOGIC;
      RD3                             :	out    STD_ULOGIC;
      RD4                             :	out    STD_ULOGIC;
      RD5                             :	out    STD_ULOGIC;
      RD6                             :	out    STD_ULOGIC;
      RD7                             :	out    STD_ULOGIC;
      RD8                             :	out    STD_ULOGIC;
      RD9                             :	out    STD_ULOGIC;
      RD10                            :	out    STD_ULOGIC;
      RD11                            :	out    STD_ULOGIC;
      RD12                            :	out    STD_ULOGIC;
      RD13                            :	out    STD_ULOGIC;
      RD14                            :	out    STD_ULOGIC;
      RD15                            :	out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX16_RX16 : entity is FALSE;
end RAMB16K_WX16_RX16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX16_RX16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 10;
		RDATA_WIDTH    : integer := 16;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (15 downto 0);
 	signal WAD : std_logic_vector (9 downto 0);
	signal RAD : std_logic_vector (9 downto 0);
	signal RD  : std_logic_vector (15 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);

      end block;

      --------------------
      -- RAMB16K_WX16_RX16 Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd         : std_ulogic := 'X';
        variable RD11_zd         : std_ulogic := 'X';
        variable RD12_zd         : std_ulogic := 'X';
        variable RD13_zd         : std_ulogic := 'X';
        variable RD14_zd         : std_ulogic := 'X';
        variable RD15_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          RefSignal               => RCEN_ipd,
          RefSignalName           => "RCEN",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WD0_WCLK_posedge or Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or Tviol_WD15_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or Tviol_RAD9_RCLK_posedge or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;



	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 10,
		WDATA_WIDTH    => 16,
		RADDR_WIDTH    => 10,
		RDATA_WIDTH    => 16,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16K_WX16_RX16_VITAL of RAMB16K_WX16_RX16 is
   for VITAL
   end for;
end CFG_RAMB16K_WX16_RX16_VITAL;



----- CELL RAMB16K_WX16_RX32 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_WX16_RX32 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD10                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD11                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD12                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD13                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD14                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD15                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD26                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD27                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD28                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD29                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD30                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD31                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD16                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD17                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD18                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD19                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD20                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD21                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD22                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD23                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD24                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD25                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out    STD_ULOGIC;
      RD2                             :	out    STD_ULOGIC;
      RD3                             :	out    STD_ULOGIC;
      RD4                             :	out    STD_ULOGIC;
      RD5                             :	out    STD_ULOGIC;
      RD6                             :	out    STD_ULOGIC;
      RD7                             :	out    STD_ULOGIC;
      RD8                             :	out    STD_ULOGIC;
      RD9                             :	out    STD_ULOGIC;
      RD10                            :	out    STD_ULOGIC;
      RD11                            :	out    STD_ULOGIC;
      RD12                            :	out    STD_ULOGIC;
      RD13                            :	out    STD_ULOGIC;
      RD14                            :	out    STD_ULOGIC;
      RD15                            :	out    STD_ULOGIC;
      RD16                            :	out    STD_ULOGIC;
      RD17                            :	out    STD_ULOGIC;
      RD18                            :	out    STD_ULOGIC;
      RD19                            :	out    STD_ULOGIC;
      RD20                            :	out    STD_ULOGIC;
      RD21                            :	out    STD_ULOGIC;
      RD22                            :	out    STD_ULOGIC;
      RD23                            :	out    STD_ULOGIC;
      RD24                            :	out    STD_ULOGIC;
      RD25                            :	out    STD_ULOGIC;
      RD26                            :	out    STD_ULOGIC;
      RD27                            :	out    STD_ULOGIC;
      RD28                            :	out    STD_ULOGIC;
      RD29                            :	out    STD_ULOGIC;
      RD30                            :	out    STD_ULOGIC;
      RD31                            :	out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX16_RX32 : entity is FALSE;
end RAMB16K_WX16_RX32;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX16_RX32 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (15 downto 0);
 	signal WAD : std_logic_vector (9 downto 0);
	signal RAD : std_logic_vector (8 downto 0);
	signal RD  : std_logic_vector (31 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd         : std_ulogic := 'X';
        variable RD11_zd         : std_ulogic := 'X';
        variable RD12_zd         : std_ulogic := 'X';
        variable RD13_zd         : std_ulogic := 'X';
        variable RD14_zd         : std_ulogic := 'X';
        variable RD15_zd         : std_ulogic := 'X';
        variable RD16_zd         : std_ulogic := 'X';
        variable RD17_zd         : std_ulogic := 'X';
        variable RD18_zd         : std_ulogic := 'X';
        variable RD19_zd         : std_ulogic := 'X';
        variable RD20_zd         : std_ulogic := 'X';
        variable RD21_zd         : std_ulogic := 'X';
        variable RD22_zd         : std_ulogic := 'X';
        variable RD23_zd         : std_ulogic := 'X';
        variable RD24_zd         : std_ulogic := 'X';
        variable RD25_zd         : std_ulogic := 'X';
        variable RD26_zd         : std_ulogic := 'X';
        variable RD27_zd         : std_ulogic := 'X';
        variable RD28_zd         : std_ulogic := 'X';
        variable RD29_zd         : std_ulogic := 'X';
        variable RD30_zd         : std_ulogic := 'X';
        variable RD31_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WD6_WCLK_posedge or Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or Tviol_WD15_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or Tviol_WD7_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;

    VitalBehavior_RD16  : process
      variable RD16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD16_zd := RD(16);

    VitalPathDelay01 (
      OutSignal => RD16,
      GlitchData => O_GlitchData,
      OutSignalName => "RD16",
      OutTemp => RD16_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD16, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(16);
      end process;

    VitalBehavior_RD17  : process
      variable RD17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD17_zd := RD(17);

    VitalPathDelay01 (
      OutSignal => RD17,
      GlitchData => O_GlitchData,
      OutSignalName => "RD17",
      OutTemp => RD17_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD17, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(17);
      end process;

    VitalBehavior_RD18  : process
      variable RD18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD18_zd := RD(18);

    VitalPathDelay01 (
      OutSignal => RD18,
      GlitchData => O_GlitchData,
      OutSignalName => "RD18",
      OutTemp => RD18_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD18, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(18);
      end process;

    VitalBehavior_RD19  : process
      variable RD19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD19_zd := RD(19);

    VitalPathDelay01 (
      OutSignal => RD19,
      GlitchData => O_GlitchData,
      OutSignalName => "RD19",
      OutTemp => RD19_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD19, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(19);
      end process;

    VitalBehavior_RD20  : process
      variable RD20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD20_zd := RD(20);

    VitalPathDelay01 (
      OutSignal => RD20,
      GlitchData => O_GlitchData,
      OutSignalName => "RD20",
      OutTemp => RD20_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD20, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(20);
      end process;

    VitalBehavior_RD21  : process
      variable RD21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD21_zd := RD(21);

    VitalPathDelay01 (
      OutSignal => RD21,
      GlitchData => O_GlitchData,
      OutSignalName => "RD21",
      OutTemp => RD21_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD21, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(21);
      end process;

    VitalBehavior_RD22  : process
      variable RD22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD22_zd := RD(22);

    VitalPathDelay01 (
      OutSignal => RD22,
      GlitchData => O_GlitchData,
      OutSignalName => "RD22",
      OutTemp => RD22_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD22, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(22);
      end process;

    VitalBehavior_RD23  : process
      variable RD23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD23_zd := RD(23);

    VitalPathDelay01 (
      OutSignal => RD23,
      GlitchData => O_GlitchData,
      OutSignalName => "RD23",
      OutTemp => RD23_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD23, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(23);
      end process;

    VitalBehavior_RD24  : process
      variable RD24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD24_zd := RD(24);

    VitalPathDelay01 (
      OutSignal => RD24,
      GlitchData => O_GlitchData,
      OutSignalName => "RD24",
      OutTemp => RD24_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD24, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(24);
      end process;

    VitalBehavior_RD25  : process
      variable RD25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD25_zd := RD(25);

    VitalPathDelay01 (
      OutSignal => RD25,
      GlitchData => O_GlitchData,
      OutSignalName => "RD25",
      OutTemp => RD25_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD25, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(25);
      end process;

    VitalBehavior_RD26  : process
      variable RD26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD26_zd := RD(26);

    VitalPathDelay01 (
      OutSignal => RD26,
      GlitchData => O_GlitchData,
      OutSignalName => "RD26",
      OutTemp => RD26_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD26, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(26);
      end process;

    VitalBehavior_RD27  : process
      variable RD27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD27_zd := RD(27);

    VitalPathDelay01 (
      OutSignal => RD27,
      GlitchData => O_GlitchData,
      OutSignalName => "RD27",
      OutTemp => RD27_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD27, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(27);
      end process;

    VitalBehavior_RD28  : process
      variable RD28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD28_zd := RD(28);

    VitalPathDelay01 (
      OutSignal => RD28,
      GlitchData => O_GlitchData,
      OutSignalName => "RD28",
      OutTemp => RD28_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD28, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(28);
      end process;

    VitalBehavior_RD29  : process
      variable RD29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD29_zd := RD(29);

    VitalPathDelay01 (
      OutSignal => RD29,
      GlitchData => O_GlitchData,
      OutSignalName => "RD29",
      OutTemp => RD29_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD29, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(29);
      end process;

    VitalBehavior_RD30  : process
      variable RD30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD30_zd := RD(30);

    VitalPathDelay01 (
      OutSignal => RD30,
      GlitchData => O_GlitchData,
      OutSignalName => "RD30",
      OutTemp => RD30_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD30, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(30);
      end process;

    VitalBehavior_RD31  : process
      variable RD31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD31_zd := RD(31);

    VitalPathDelay01 (
      OutSignal => RD31,
      GlitchData => O_GlitchData,
      OutSignalName => "RD31",
      OutTemp => RD31_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD31, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(31);
      end process;



	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 10,
		WDATA_WIDTH    => 16,
		RADDR_WIDTH    => 9,
		RDATA_WIDTH    => 32,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16K_WX16_RX32_VITAL of RAMB16K_WX16_RX32 is
   for VITAL
   end for;
end CFG_RAMB16K_WX16_RX32_VITAL;



----- CELL RAMB16K_WX32_RX32 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_WX32_RX32 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD10                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD11                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD12                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD13                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD14                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD15                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD26                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD27                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD28                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD29                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD30                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD31                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD16                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD17                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD18                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD19                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD20                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD21                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD22                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD23                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD24                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD25                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD16_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD16_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD17_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD17_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD18_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD18_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD19_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD19_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD20_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD20_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD21_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD21_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD22_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD22_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD23_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD23_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD24_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD24_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD25_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD25_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD26_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD26_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD27_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD27_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD28_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD28_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD29_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD29_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD30_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD30_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD31_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD31_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD16                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD17                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD18                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD19                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD20                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD21                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD22                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD23                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD24                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD25                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD26                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD27                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD28                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD29                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD30                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD31                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WD16                            :	in    STD_ULOGIC;
      WD17                            :	in    STD_ULOGIC;
      WD18                            :	in    STD_ULOGIC;
      WD19                            :	in    STD_ULOGIC;
      WD20                            :	in    STD_ULOGIC;
      WD21                            :	in    STD_ULOGIC;
      WD22                            :	in    STD_ULOGIC;
      WD23                            :	in    STD_ULOGIC;
      WD24                            :	in    STD_ULOGIC;
      WD25                            :	in    STD_ULOGIC;
      WD26                            :	in    STD_ULOGIC;
      WD27                            :	in    STD_ULOGIC;
      WD28                            :	in    STD_ULOGIC;
      WD29                            :	in    STD_ULOGIC;
      WD30                            :	in    STD_ULOGIC;
      WD31                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RD0                             :	out    STD_ULOGIC;
      RD1                             :	out    STD_ULOGIC;
      RD2                             :	out    STD_ULOGIC;
      RD3                             :	out    STD_ULOGIC;
      RD4                             :	out    STD_ULOGIC;
      RD5                             :	out    STD_ULOGIC;
      RD6                             :	out    STD_ULOGIC;
      RD7                             :	out    STD_ULOGIC;
      RD8                             :	out    STD_ULOGIC;
      RD9                             :	out    STD_ULOGIC;
      RD10                            :	out    STD_ULOGIC;
      RD11                            :	out    STD_ULOGIC;
      RD12                            :	out    STD_ULOGIC;
      RD13                            :	out    STD_ULOGIC;
      RD14                            :	out    STD_ULOGIC;
      RD15                            :	out    STD_ULOGIC;
      RD16                            :	out    STD_ULOGIC;
      RD17                            :	out    STD_ULOGIC;
      RD18                            :	out    STD_ULOGIC;
      RD19                            :	out    STD_ULOGIC;
      RD20                            :	out    STD_ULOGIC;
      RD21                            :	out    STD_ULOGIC;
      RD22                            :	out    STD_ULOGIC;
      RD23                            :	out    STD_ULOGIC;
      RD24                            :	out    STD_ULOGIC;
      RD25                            :	out    STD_ULOGIC;
      RD26                            :	out    STD_ULOGIC;
      RD27                            :	out    STD_ULOGIC;
      RD28                            :	out    STD_ULOGIC;
      RD29                            :	out    STD_ULOGIC;
      RD30                            :	out    STD_ULOGIC;
      RD31                            :	out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_WX32_RX32 : entity is FALSE;
end RAMB16K_WX32_RX32;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX32_RX32 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 9;
		WDATA_WIDTH    : integer := 32;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';
      signal WD16_ipd      : std_ulogic := 'X';
      signal WD17_ipd      : std_ulogic := 'X';
      signal WD18_ipd      : std_ulogic := 'X';
      signal WD19_ipd      : std_ulogic := 'X';
      signal WD20_ipd      : std_ulogic := 'X';
      signal WD21_ipd      : std_ulogic := 'X';
      signal WD22_ipd      : std_ulogic := 'X';
      signal WD23_ipd      : std_ulogic := 'X';
      signal WD24_ipd      : std_ulogic := 'X';
      signal WD25_ipd      : std_ulogic := 'X';
      signal WD26_ipd      : std_ulogic := 'X';
      signal WD27_ipd      : std_ulogic := 'X';
      signal WD28_ipd      : std_ulogic := 'X';
      signal WD29_ipd      : std_ulogic := 'X';
      signal WD30_ipd      : std_ulogic := 'X';
      signal WD31_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (31 downto 0);
 	signal WAD : std_logic_vector (8 downto 0);
	signal RAD : std_logic_vector (8 downto 0);
	signal RD  : std_logic_vector (31 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD31_ipd & WD30_ipd & WD29_ipd & WD28_ipd & WD27_ipd & WD26_ipd & WD25_ipd & WD24_ipd & WD23_ipd & WD22_ipd & WD21_ipd & WD20_ipd & WD19_ipd & WD18_ipd & WD17_ipd & WD16_ipd & WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;


  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);
        VitalWireDelay (WD16_ipd, WD16, tipd_WD16);
        VitalWireDelay (WD17_ipd, WD17, tipd_WD17);
        VitalWireDelay (WD18_ipd, WD18, tipd_WD18);
        VitalWireDelay (WD19_ipd, WD19, tipd_WD19);
        VitalWireDelay (WD20_ipd, WD20, tipd_WD20);
        VitalWireDelay (WD21_ipd, WD21, tipd_WD21);
        VitalWireDelay (WD22_ipd, WD22, tipd_WD22);
        VitalWireDelay (WD23_ipd, WD23, tipd_WD23);
        VitalWireDelay (WD24_ipd, WD24, tipd_WD24);
        VitalWireDelay (WD25_ipd, WD25, tipd_WD25);
        VitalWireDelay (WD26_ipd, WD26, tipd_WD26);
        VitalWireDelay (WD27_ipd, WD27, tipd_WD27);
        VitalWireDelay (WD28_ipd, WD28, tipd_WD28);
        VitalWireDelay (WD29_ipd, WD29, tipd_WD29);
        VitalWireDelay (WD30_ipd, WD30, tipd_WD30);
        VitalWireDelay (WD31_ipd, WD31, tipd_WD31);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD16_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD17_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD18_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD19_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD20_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD21_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD22_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD23_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD24_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD25_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD26_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD27_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD28_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD29_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD30_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD31_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD16_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD17_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD18_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD19_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD20_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD21_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD22_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD23_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD24_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD25_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD26_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD27_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD28_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD29_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD30_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD31_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd         : std_ulogic := 'X';
        variable RD11_zd         : std_ulogic := 'X';
        variable RD12_zd         : std_ulogic := 'X';
        variable RD13_zd         : std_ulogic := 'X';
        variable RD14_zd         : std_ulogic := 'X';
        variable RD15_zd         : std_ulogic := 'X';
        variable RD16_zd         : std_ulogic := 'X';
        variable RD17_zd         : std_ulogic := 'X';
        variable RD18_zd         : std_ulogic := 'X';
        variable RD19_zd         : std_ulogic := 'X';
        variable RD20_zd         : std_ulogic := 'X';
        variable RD21_zd         : std_ulogic := 'X';
        variable RD22_zd         : std_ulogic := 'X';
        variable RD23_zd         : std_ulogic := 'X';
        variable RD24_zd         : std_ulogic := 'X';
        variable RD25_zd         : std_ulogic := 'X';
        variable RD26_zd         : std_ulogic := 'X';
        variable RD27_zd         : std_ulogic := 'X';
        variable RD28_zd         : std_ulogic := 'X';
        variable RD29_zd         : std_ulogic := 'X';
        variable RD30_zd         : std_ulogic := 'X';
        variable RD31_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCEN_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD16_WCLK_posedge,
          TimingData              => Tmkr_WD16_WCLK_posedge,
          TestSignal              => WD16_ipd,
          TestSignalName          => "WD16",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD16_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD16_WCLK_noedge_posedge,
          HoldLow                 => thold_WD16_WCLK_noedge_posedge,
          HoldHigh                => thold_WD16_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD17_WCLK_posedge,
          TimingData              => Tmkr_WD17_WCLK_posedge,
          TestSignal              => WD17_ipd,
          TestSignalName          => "WD17",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD17_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD17_WCLK_noedge_posedge,
          HoldLow                 => thold_WD17_WCLK_noedge_posedge,
          HoldHigh                => thold_WD17_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD18_WCLK_posedge,
          TimingData              => Tmkr_WD18_WCLK_posedge,
          TestSignal              => WD18_ipd,
          TestSignalName          => "WD18",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD18_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD18_WCLK_noedge_posedge,
          HoldLow                 => thold_WD18_WCLK_noedge_posedge,
          HoldHigh                => thold_WD18_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD19_WCLK_posedge,
          TimingData              => Tmkr_WD19_WCLK_posedge,
          TestSignal              => WD19_ipd,
          TestSignalName          => "WD19",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD19_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD19_WCLK_noedge_posedge,
          HoldLow                 => thold_WD19_WCLK_noedge_posedge,
          HoldHigh                => thold_WD19_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD20_WCLK_posedge,
          TimingData              => Tmkr_WD20_WCLK_posedge,
          TestSignal              => WD20_ipd,
          TestSignalName          => "WD20",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD20_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD20_WCLK_noedge_posedge,
          HoldLow                 => thold_WD20_WCLK_noedge_posedge,
          HoldHigh                => thold_WD20_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD21_WCLK_posedge,
          TimingData              => Tmkr_WD21_WCLK_posedge,
          TestSignal              => WD21_ipd,
          TestSignalName          => "WD21",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD21_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD21_WCLK_noedge_posedge,
          HoldLow                 => thold_WD21_WCLK_noedge_posedge,
          HoldHigh                => thold_WD21_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD22_WCLK_posedge,
          TimingData              => Tmkr_WD22_WCLK_posedge,
          TestSignal              => WD22_ipd,
          TestSignalName          => "WD22",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD22_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD22_WCLK_noedge_posedge,
          HoldLow                 => thold_WD22_WCLK_noedge_posedge,
          HoldHigh                => thold_WD22_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD23_WCLK_posedge,
          TimingData              => Tmkr_WD23_WCLK_posedge,
          TestSignal              => WD23_ipd,
          TestSignalName          => "WD23",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD23_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD23_WCLK_noedge_posedge,
          HoldLow                 => thold_WD23_WCLK_noedge_posedge,
          HoldHigh                => thold_WD23_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD24_WCLK_posedge,
          TimingData              => Tmkr_WD24_WCLK_posedge,
          TestSignal              => WD24_ipd,
          TestSignalName          => "WD24",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD24_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD24_WCLK_noedge_posedge,
          HoldLow                 => thold_WD24_WCLK_noedge_posedge,
          HoldHigh                => thold_WD24_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD25_WCLK_posedge,
          TimingData              => Tmkr_WD25_WCLK_posedge,
          TestSignal              => WD25_ipd,
          TestSignalName          => "WD25",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD25_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD25_WCLK_noedge_posedge,
          HoldLow                 => thold_WD25_WCLK_noedge_posedge,
          HoldHigh                => thold_WD25_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD26_WCLK_posedge,
          TimingData              => Tmkr_WD26_WCLK_posedge,
          TestSignal              => WD26_ipd,
          TestSignalName          => "WD26",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD26_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD26_WCLK_noedge_posedge,
          HoldLow                 => thold_WD26_WCLK_noedge_posedge,
          HoldHigh                => thold_WD26_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD27_WCLK_posedge,
          TimingData              => Tmkr_WD27_WCLK_posedge,
          TestSignal              => WD27_ipd,
          TestSignalName          => "WD27",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD27_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD27_WCLK_noedge_posedge,
          HoldLow                 => thold_WD27_WCLK_noedge_posedge,
          HoldHigh                => thold_WD27_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD28_WCLK_posedge,
          TimingData              => Tmkr_WD28_WCLK_posedge,
          TestSignal              => WD28_ipd,
          TestSignalName          => "WD28",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD28_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD28_WCLK_noedge_posedge,
          HoldLow                 => thold_WD28_WCLK_noedge_posedge,
          HoldHigh                => thold_WD28_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD29_WCLK_posedge,
          TimingData              => Tmkr_WD29_WCLK_posedge,
          TestSignal              => WD29_ipd,
          TestSignalName          => "WD29",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD29_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD29_WCLK_noedge_posedge,
          HoldLow                 => thold_WD29_WCLK_noedge_posedge,
          HoldHigh                => thold_WD29_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD30_WCLK_posedge,
          TimingData              => Tmkr_WD30_WCLK_posedge,
          TestSignal              => WD30_ipd,
          TestSignalName          => "WD30",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD30_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD30_WCLK_noedge_posedge,
          HoldLow                 => thold_WD30_WCLK_noedge_posedge,
          HoldHigh                => thold_WD30_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD31_WCLK_posedge,
          TimingData              => Tmkr_WD31_WCLK_posedge,
          TestSignal              => WD31_ipd,
          TestSignalName          => "WD31",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD31_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD31_WCLK_noedge_posedge,
          HoldLow                 => thold_WD31_WCLK_noedge_posedge,
          HoldHigh                => thold_WD31_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or 
                 Tviol_WD0_WCLK_posedge or Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or Tviol_WD15_WCLK_posedge or
                 Tviol_WD16_WCLK_posedge or Tviol_WD17_WCLK_posedge or
                 Tviol_WD18_WCLK_posedge or Tviol_WD19_WCLK_posedge or
                 Tviol_WD20_WCLK_posedge or Tviol_WD21_WCLK_posedge or
                 Tviol_WD22_WCLK_posedge or Tviol_WD23_WCLK_posedge or
                 Tviol_WD24_WCLK_posedge or Tviol_WD25_WCLK_posedge or
                 Tviol_WD26_WCLK_posedge or Tviol_WD27_WCLK_posedge or
                 Tviol_WD28_WCLK_posedge or Tviol_WD29_WCLK_posedge or
                 Tviol_WD30_WCLK_posedge or Tviol_WD31_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or Tviol_RAD1_RCLK_posedge or 
                 Tviol_RAD2_RCLK_posedge or Tviol_RAD3_RCLK_posedge or 
                 Tviol_RAD4_RCLK_posedge or Tviol_RAD5_RCLK_posedge or 
                 Tviol_RAD6_RCLK_posedge or Tviol_RAD7_RCLK_posedge or 
                 Tviol_RAD8_RCLK_posedge or Tviol_RCEN_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;

    VitalBehavior_RD16  : process
      variable RD16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD16_zd := RD(16);

    VitalPathDelay01 (
      OutSignal => RD16,
      GlitchData => O_GlitchData,
      OutSignalName => "RD16",
      OutTemp => RD16_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD16, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(16);
      end process;

    VitalBehavior_RD17  : process
      variable RD17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD17_zd := RD(17);

    VitalPathDelay01 (
      OutSignal => RD17,
      GlitchData => O_GlitchData,
      OutSignalName => "RD17",
      OutTemp => RD17_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD17, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(17);
      end process;

    VitalBehavior_RD18  : process
      variable RD18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD18_zd := RD(18);

    VitalPathDelay01 (
      OutSignal => RD18,
      GlitchData => O_GlitchData,
      OutSignalName => "RD18",
      OutTemp => RD18_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD18, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(18);
      end process;

    VitalBehavior_RD19  : process
      variable RD19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD19_zd := RD(19);

    VitalPathDelay01 (
      OutSignal => RD19,
      GlitchData => O_GlitchData,
      OutSignalName => "RD19",
      OutTemp => RD19_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD19, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(19);
      end process;

    VitalBehavior_RD20  : process
      variable RD20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD20_zd := RD(20);

    VitalPathDelay01 (
      OutSignal => RD20,
      GlitchData => O_GlitchData,
      OutSignalName => "RD20",
      OutTemp => RD20_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD20, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(20);
      end process;

    VitalBehavior_RD21  : process
      variable RD21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD21_zd := RD(21);

    VitalPathDelay01 (
      OutSignal => RD21,
      GlitchData => O_GlitchData,
      OutSignalName => "RD21",
      OutTemp => RD21_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD21, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(21);
      end process;

    VitalBehavior_RD22  : process
      variable RD22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD22_zd := RD(22);

    VitalPathDelay01 (
      OutSignal => RD22,
      GlitchData => O_GlitchData,
      OutSignalName => "RD22",
      OutTemp => RD22_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD22, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(22);
      end process;

    VitalBehavior_RD23  : process
      variable RD23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD23_zd := RD(23);

    VitalPathDelay01 (
      OutSignal => RD23,
      GlitchData => O_GlitchData,
      OutSignalName => "RD23",
      OutTemp => RD23_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD23, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(23);
      end process;

    VitalBehavior_RD24  : process
      variable RD24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD24_zd := RD(24);

    VitalPathDelay01 (
      OutSignal => RD24,
      GlitchData => O_GlitchData,
      OutSignalName => "RD24",
      OutTemp => RD24_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD24, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(24);
      end process;

    VitalBehavior_RD25  : process
      variable RD25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD25_zd := RD(25);

    VitalPathDelay01 (
      OutSignal => RD25,
      GlitchData => O_GlitchData,
      OutSignalName => "RD25",
      OutTemp => RD25_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD25, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(25);
      end process;

    VitalBehavior_RD26  : process
      variable RD26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD26_zd := RD(26);

    VitalPathDelay01 (
      OutSignal => RD26,
      GlitchData => O_GlitchData,
      OutSignalName => "RD26",
      OutTemp => RD26_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD26, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(26);
      end process;

    VitalBehavior_RD27  : process
      variable RD27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD27_zd := RD(27);

    VitalPathDelay01 (
      OutSignal => RD27,
      GlitchData => O_GlitchData,
      OutSignalName => "RD27",
      OutTemp => RD27_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD27, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(27);
      end process;

    VitalBehavior_RD28  : process
      variable RD28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD28_zd := RD(28);

    VitalPathDelay01 (
      OutSignal => RD28,
      GlitchData => O_GlitchData,
      OutSignalName => "RD28",
      OutTemp => RD28_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD28, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(28);
      end process;

    VitalBehavior_RD29  : process
      variable RD29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD29_zd := RD(29);

    VitalPathDelay01 (
      OutSignal => RD29,
      GlitchData => O_GlitchData,
      OutSignalName => "RD29",
      OutTemp => RD29_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD29, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(29);
      end process;

    VitalBehavior_RD30  : process
      variable RD30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD30_zd := RD(30);

    VitalPathDelay01 (
      OutSignal => RD30,
      GlitchData => O_GlitchData,
      OutSignalName => "RD30",
      OutTemp => RD30_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD30, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(30);
      end process;

    VitalBehavior_RD31  : process
      variable RD31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD31_zd := RD(31);

    VitalPathDelay01 (
      OutSignal => RD31,
      GlitchData => O_GlitchData,
      OutSignalName => "RD31",
      OutTemp => RD31_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD31, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(31);
      end process;



	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 9,
		WDATA_WIDTH    => 32,
		RADDR_WIDTH    => 9,
		RDATA_WIDTH    => 32,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);


end VITAL;

configuration CFG_RAMB16K_WX32_RX32_VITAL of RAMB16K_WX32_RX32 is
   for VITAL
   end for;
end CFG_RAMB16K_WX32_RX32_VITAL;



----- CELL RAMB16_X1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_X1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_CLK_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WR_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_CEN_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CEN_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD4_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD4_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD5_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD5_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD6_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD6_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD7_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD7_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD8_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD8_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD9_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD9_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD10_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD10_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD11_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD11_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD12_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD12_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD13_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD13_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RST_CLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_CLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLK_posedge                  :	VitalDelayType   := 2.0 ns;
      tpw_CLK_negedge                  :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                  :	VitalDelayType   := 2.0 ns;
      tipd_CEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD8                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD9                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD10                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD11                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD12                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD13                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CEN                            :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      WR                             :	in    STD_ULOGIC;
      CS0                            :	in    STD_ULOGIC;
      CS1                            :	in    STD_ULOGIC;
      RST                            :	in    STD_ULOGIC;
      DI0                            :	in    STD_ULOGIC;
      AD0                            :	in    STD_ULOGIC;
      AD1                            :	in    STD_ULOGIC;
      AD2                            :	in    STD_ULOGIC;
      AD3                            :	in    STD_ULOGIC;
      AD4                            :	in    STD_ULOGIC;
      AD5                            :	in    STD_ULOGIC;
      AD6                            :	in    STD_ULOGIC;
      AD7                            :	in    STD_ULOGIC;
      AD8                            :	in    STD_ULOGIC;
      AD9                            :	in    STD_ULOGIC;
      AD10                           :	in    STD_ULOGIC;
      AD11                           :	in    STD_ULOGIC;
      AD12                           :	in    STD_ULOGIC;
      AD13                           :	in    STD_ULOGIC;
      DO0                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_X1 : entity is FALSE;
end RAMB16K_X1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_X1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_SPRAM_16K
	   generic (
		ADDR_WIDTH    : integer := 14;
		DATA_WIDTH    : integer := 1;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CEN : in  STD_LOGIC ;
		CLK : in  STD_LOGIC ;
		WR   : in  STD_LOGIC ;
		CS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		DI   : in  STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0);
		AD  : in  STD_LOGIC_VECTOR (ADDR_WIDTH -1 downto 0);
		DO   : out STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0)
		);
	end component ;

      signal CEN_ipd      : std_ulogic := 'X';
      signal CLK_ipd      : std_ulogic := 'X';
      signal WR_ipd       : std_ulogic := 'X';
      signal CS0_ipd      : std_ulogic := 'X';
      signal CS1_ipd      : std_ulogic := 'X';
      signal RST_ipd      : std_ulogic := 'X';

      signal DI0_ipd      : std_logic_vector(0 downto 0);

      signal AD0_ipd      : std_ulogic := 'X';
      signal AD1_ipd      : std_ulogic := 'X';
      signal AD2_ipd      : std_ulogic := 'X';
      signal AD3_ipd      : std_ulogic := 'X';
      signal AD4_ipd      : std_ulogic := 'X';
      signal AD5_ipd      : std_ulogic := 'X';
      signal AD6_ipd      : std_ulogic := 'X';
      signal AD7_ipd      : std_ulogic := 'X';
      signal AD8_ipd      : std_ulogic := 'X';
      signal AD9_ipd      : std_ulogic := 'X';
      signal AD10_ipd     : std_ulogic := 'X';
      signal AD11_ipd     : std_ulogic := 'X';
      signal AD12_ipd     : std_ulogic := 'X';
      signal AD13_ipd     : std_ulogic := 'X';

	signal CS : std_logic_vector (1 downto 0);
	signal DI  : std_logic_vector (0 downto 0);
 	signal AD : std_logic_vector (13 downto 0);
	signal DO  : std_logic_vector (0 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	CS <= CS1_ipd & CS0_ipd;
	DI <= DI0_ipd;
	AD <= AD13_ipd & AD12_ipd & AD11_ipd & AD10_ipd & AD9_ipd & AD8_ipd & AD7_ipd & AD6_ipd & AD5_ipd & AD4_ipd & AD3_ipd & AD2_ipd & AD1_ipd & AD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CEN_ipd, CEN, tipd_CEN);
        VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        VitalWireDelay (WR_ipd, WR, tipd_WR);
        VitalWireDelay (CS0_ipd, CS0, tipd_CS0);
        VitalWireDelay (CS1_ipd, CS1, tipd_CS1);
        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (DI0_ipd(0), DI0, tipd_DI0);

        VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
        VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
        VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
        VitalWireDelay (AD3_ipd, AD3, tipd_AD3);
        VitalWireDelay (AD4_ipd, AD4, tipd_AD4);
        VitalWireDelay (AD5_ipd, AD5, tipd_AD5);
        VitalWireDelay (AD6_ipd, AD6, tipd_AD6);
        VitalWireDelay (AD7_ipd, AD7, tipd_AD7);
        VitalWireDelay (AD8_ipd, AD8, tipd_AD8);
        VitalWireDelay (AD9_ipd, AD9, tipd_AD9);
        VitalWireDelay (AD10_ipd, AD10, tipd_AD10);
        VitalWireDelay (AD11_ipd, AD11, tipd_AD11);
        VitalWireDelay (AD12_ipd, AD12, tipd_AD12);
        VitalWireDelay (AD13_ipd, AD13, tipd_AD13);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CEN_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_WR_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_CS0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_CS1_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_DI0_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_AD0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD3_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD4_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD5_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD6_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD7_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD8_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD9_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD10_CLK_posedge   : std_ulogic  := '0';
        variable Tviol_AD11_CLK_posedge   : std_ulogic  := '0';
        variable Tviol_AD12_CLK_posedge   : std_ulogic  := '0';
        variable Tviol_AD13_CLK_posedge   : std_ulogic  := '0';

        variable Tviol_RST_CLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CEN_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_AD0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD4_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD5_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD6_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD7_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD8_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD9_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD10_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD11_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD12_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD13_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_CLK_posedge_posedge  : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLK       : std_ulogic := '0';
        variable PInfo_CLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CEN_CLK_posedge,
          TimingData              => Tmkr_CEN_CLK_posedge,
          TestSignal              => CEN_ipd,
          TestSignalName          => "CEN",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CEN_CLK_noedge_posedge,
          SetupLow                => tsetup_CEN_CLK_noedge_posedge,
          HoldLow                 => thold_CEN_CLK_noedge_posedge,
          HoldHigh                => thold_CEN_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_CLK_posedge,
          TimingData              => Tmkr_WR_CLK_posedge,
          TestSignal              => WR_ipd,
          TestSignalName          => "WR",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_CLK_noedge_posedge,
          HoldLow                 => thold_WR_CLK_noedge_posedge,
          HoldHigh                => thold_WR_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS0_CLK_posedge,
          TimingData              => Tmkr_CS0_CLK_posedge,
          TestSignal              => CS0_ipd,
          TestSignalName          => "CS0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS0_CLK_noedge_posedge,
          SetupLow                => tsetup_CS0_CLK_noedge_posedge,
          HoldLow                 => thold_CS0_CLK_noedge_posedge,
          HoldHigh                => thold_CS0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS1_CLK_posedge,
          TimingData              => Tmkr_CS1_CLK_posedge,
          TestSignal              => CS1_ipd,
          TestSignalName          => "CS1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS1_CLK_noedge_posedge,
          SetupLow                => tsetup_CS1_CLK_noedge_posedge,
          HoldLow                 => thold_CS1_CLK_noedge_posedge,
          HoldHigh                => thold_CS1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_CLK_posedge,
          TimingData              => Tmkr_DI0_CLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_CLK_noedge_posedge,
          SetupLow                => tsetup_DI0_CLK_noedge_posedge,
          HoldLow                 => thold_DI0_CLK_noedge_posedge,
          HoldHigh                => thold_DI0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_CLK_posedge,
          TimingData              => Tmkr_AD0_CLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_CLK_noedge_posedge,
          SetupLow                => tsetup_AD0_CLK_noedge_posedge,
          HoldLow                 => thold_AD0_CLK_noedge_posedge,
          HoldHigh                => thold_AD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_CLK_posedge,
          TimingData              => Tmkr_AD1_CLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_CLK_noedge_posedge,
          SetupLow                => tsetup_AD1_CLK_noedge_posedge,
          HoldLow                 => thold_AD1_CLK_noedge_posedge,
          HoldHigh                => thold_AD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_CLK_posedge,
          TimingData              => Tmkr_AD2_CLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_CLK_noedge_posedge,
          SetupLow                => tsetup_AD2_CLK_noedge_posedge,
          HoldLow                 => thold_AD2_CLK_noedge_posedge,
          HoldHigh                => thold_AD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_CLK_posedge,
          TimingData              => Tmkr_AD3_CLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_CLK_noedge_posedge,
          SetupLow                => tsetup_AD3_CLK_noedge_posedge,
          HoldLow                 => thold_AD3_CLK_noedge_posedge,
          HoldHigh                => thold_AD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD4_CLK_posedge,
          TimingData              => Tmkr_AD4_CLK_posedge,
          TestSignal              => AD4_ipd,
          TestSignalName          => "AD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD4_CLK_noedge_posedge,
          SetupLow                => tsetup_AD4_CLK_noedge_posedge,
          HoldLow                 => thold_AD4_CLK_noedge_posedge,
          HoldHigh                => thold_AD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD5_CLK_posedge,
          TimingData              => Tmkr_AD5_CLK_posedge,
          TestSignal              => AD5_ipd,
          TestSignalName          => "AD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD5_CLK_noedge_posedge,
          SetupLow                => tsetup_AD5_CLK_noedge_posedge,
          HoldLow                 => thold_AD5_CLK_noedge_posedge,
          HoldHigh                => thold_AD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD6_CLK_posedge,
          TimingData              => Tmkr_AD6_CLK_posedge,
          TestSignal              => AD6_ipd,
          TestSignalName          => "AD6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD6_CLK_noedge_posedge,
          SetupLow                => tsetup_AD6_CLK_noedge_posedge,
          HoldLow                 => thold_AD6_CLK_noedge_posedge,
          HoldHigh                => thold_AD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD7_CLK_posedge,
          TimingData              => Tmkr_AD7_CLK_posedge,
          TestSignal              => AD7_ipd,
          TestSignalName          => "AD7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD7_CLK_noedge_posedge,
          SetupLow                => tsetup_AD7_CLK_noedge_posedge,
          HoldLow                 => thold_AD7_CLK_noedge_posedge,
          HoldHigh                => thold_AD7_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD8_CLK_posedge,
          TimingData              => Tmkr_AD8_CLK_posedge,
          TestSignal              => AD8_ipd,
          TestSignalName          => "AD8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD8_CLK_noedge_posedge,
          SetupLow                => tsetup_AD8_CLK_noedge_posedge,
          HoldLow                 => thold_AD8_CLK_noedge_posedge,
          HoldHigh                => thold_AD8_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD9_CLK_posedge,
          TimingData              => Tmkr_AD9_CLK_posedge,
          TestSignal              => AD9_ipd,
          TestSignalName          => "AD9",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD9_CLK_noedge_posedge,
          SetupLow                => tsetup_AD9_CLK_noedge_posedge,
          HoldLow                 => thold_AD9_CLK_noedge_posedge,
          HoldHigh                => thold_AD9_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD10_CLK_posedge,
          TimingData              => Tmkr_AD10_CLK_posedge,
          TestSignal              => AD10_ipd,
          TestSignalName          => "AD10",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD10_CLK_noedge_posedge,
          SetupLow                => tsetup_AD10_CLK_noedge_posedge,
          HoldLow                 => thold_AD10_CLK_noedge_posedge,
          HoldHigh                => thold_AD10_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD11_CLK_posedge,
          TimingData              => Tmkr_AD11_CLK_posedge,
          TestSignal              => AD11_ipd,
          TestSignalName          => "AD11",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD11_CLK_noedge_posedge,
          SetupLow                => tsetup_AD11_CLK_noedge_posedge,
          HoldLow                 => thold_AD11_CLK_noedge_posedge,
          HoldHigh                => thold_AD11_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD12_CLK_posedge,
          TimingData              => Tmkr_AD12_CLK_posedge,
          TestSignal              => AD12_ipd,
          TestSignalName          => "AD12",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD12_CLK_noedge_posedge,
          SetupLow                => tsetup_AD12_CLK_noedge_posedge,
          HoldLow                 => thold_AD12_CLK_noedge_posedge,
          HoldHigh                => thold_AD12_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD13_CLK_posedge,
          TimingData              => Tmkr_AD13_CLK_posedge,
          TestSignal              => AD13_ipd,
          TestSignalName          => "AD13",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD13_CLK_noedge_posedge,
          SetupLow                => tsetup_AD13_CLK_noedge_posedge,
          HoldLow                 => thold_AD13_CLK_noedge_posedge,
          HoldHigh                => thold_AD13_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_CLK_posedge_posedge,
          TimingData              => Tmkr_RST_CLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_CLK_posedge_posedge,
          Removal                 => thold_RST_CLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_negedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CEN_CLK_posedge or Tviol_WR_CLK_posedge or 
                 Tviol_CS0_CLK_posedge or Tviol_CS1_CLK_posedge or 
                 Tviol_AD0_CLK_posedge or Tviol_AD1_CLK_posedge or 
                 Tviol_AD2_CLK_posedge or Tviol_AD3_CLK_posedge or 
                 Tviol_AD4_CLK_posedge or Tviol_AD5_CLK_posedge or 
                 Tviol_AD6_CLK_posedge or Tviol_AD7_CLK_posedge or 
                 Tviol_AD8_CLK_posedge or Tviol_AD9_CLK_posedge or 
                 Tviol_AD10_CLK_posedge or Tviol_AD11_CLK_posedge or 
                 Tviol_AD12_CLK_posedge or Tviol_DI0_CLK_posedge or
                 Tviol_AD13_CLK_posedge or Pviol_CLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------
	DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

wait on CEN_ipd, CLK_ipd, WR_ipd, CS,  RST_ipd, DI, AD, DO;

      end process VITALBehavior;

	SPRAM_INST: SC_SPRAM_16K
	   generic map (
		ADDR_WIDTH    => 14,
		DATA_WIDTH    => 1,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CEN => CEN_ipd,
		CLK => CLK_ipd,
		WR  => WR_ipd,
		CS  => CS,
		RST => RST_ipd,
		DI  => DI,
		AD  => AD,
		DO  => DO
		);

end VITAL;

configuration CFG_RAMB16K_X1_VITAL of RAMB16K_X1 is
   for VITAL
   end for;
end CFG_RAMB16K_X1_VITAL;



----- CELL RAMB16K_X2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_X2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_CLK_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WR_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_CEN_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CEN_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_AD0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD4_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD4_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD5_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD5_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD6_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD6_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD7_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD7_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD8_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD8_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD9_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD9_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD10_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD10_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD11_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD11_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD12_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD12_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RST_CLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_CLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLK_posedge                  :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                  :	VitalDelayType   := 2.0 ns;
      tipd_CEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_AD0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD8                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD9                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD10                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD11                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD12                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CEN                            :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      WR                             :	in    STD_ULOGIC;
      CS0                            :	in    STD_ULOGIC;
      CS1                            :	in    STD_ULOGIC;
      RST                            :	in    STD_ULOGIC;
      DI0                            :	in    STD_ULOGIC;
      DI1                            :	in    STD_ULOGIC;
      AD0                            :	in    STD_ULOGIC;
      AD1                            :	in    STD_ULOGIC;
      AD2                            :	in    STD_ULOGIC;
      AD3                            :	in    STD_ULOGIC;
      AD4                            :	in    STD_ULOGIC;
      AD5                            :	in    STD_ULOGIC;
      AD6                            :	in    STD_ULOGIC;
      AD7                            :	in    STD_ULOGIC;
      AD8                            :	in    STD_ULOGIC;
      AD9                            :	in    STD_ULOGIC;
      AD10                           :	in    STD_ULOGIC;
      AD11                           :	in    STD_ULOGIC;
      AD12                           :	in    STD_ULOGIC;
      DO0                            :	out   STD_ULOGIC;
      DO1                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_X2 : entity is FALSE;
end RAMB16K_X2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_X2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_SPRAM_16K
	   generic (
		ADDR_WIDTH    : integer := 13;
		DATA_WIDTH    : integer := 2;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CEN : in  STD_LOGIC ;
		CLK : in  STD_LOGIC ;
		WR   : in  STD_LOGIC ;
		CS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		DI   : in  STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0);
		AD  : in  STD_LOGIC_VECTOR (ADDR_WIDTH -1 downto 0);
		DO   : out STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0)
		);
	end component ;

      signal CEN_ipd      : std_ulogic := 'X';
      signal CLK_ipd      : std_ulogic := 'X';
      signal WR_ipd       : std_ulogic := 'X';
      signal CS0_ipd      : std_ulogic := 'X';
      signal CS1_ipd      : std_ulogic := 'X';
      signal RST_ipd      : std_ulogic := 'X';

      signal DI0_ipd      : std_ulogic := 'X';
      signal DI1_ipd      : std_ulogic := 'X';

      signal AD0_ipd      : std_ulogic := 'X';
      signal AD1_ipd      : std_ulogic := 'X';
      signal AD2_ipd      : std_ulogic := 'X';
      signal AD3_ipd      : std_ulogic := 'X';
      signal AD4_ipd      : std_ulogic := 'X';
      signal AD5_ipd      : std_ulogic := 'X';
      signal AD6_ipd      : std_ulogic := 'X';
      signal AD7_ipd      : std_ulogic := 'X';
      signal AD8_ipd      : std_ulogic := 'X';
      signal AD9_ipd      : std_ulogic := 'X';
      signal AD10_ipd     : std_ulogic := 'X';
      signal AD11_ipd     : std_ulogic := 'X';
      signal AD12_ipd     : std_ulogic := 'X';

	signal CS : std_logic_vector (1 downto 0);
	signal DI  : std_logic_vector (1 downto 0);
 	signal AD : std_logic_vector (12 downto 0);
	signal DO  : std_logic_vector (1 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	CS <= CS1_ipd & CS0_ipd;
	DI <= DI1_ipd & DI0_ipd;
	AD <= AD12_ipd & AD11_ipd & AD10_ipd & AD9_ipd & AD8_ipd & AD7_ipd & AD6_ipd & AD5_ipd & AD4_ipd & AD3_ipd & AD2_ipd & AD1_ipd & AD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CEN_ipd, CEN, tipd_CEN);
        VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        VitalWireDelay (WR_ipd, WR, tipd_WR);
        VitalWireDelay (CS0_ipd, CS0, tipd_CS0);
        VitalWireDelay (CS1_ipd, CS1, tipd_CS1);
        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);

        VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
        VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
        VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
        VitalWireDelay (AD3_ipd, AD3, tipd_AD3);
        VitalWireDelay (AD4_ipd, AD4, tipd_AD4);
        VitalWireDelay (AD5_ipd, AD5, tipd_AD5);
        VitalWireDelay (AD6_ipd, AD6, tipd_AD6);
        VitalWireDelay (AD7_ipd, AD7, tipd_AD7);
        VitalWireDelay (AD8_ipd, AD8, tipd_AD8);
        VitalWireDelay (AD9_ipd, AD9, tipd_AD9);
        VitalWireDelay (AD10_ipd, AD10, tipd_AD10);
        VitalWireDelay (AD11_ipd, AD11, tipd_AD11);
        VitalWireDelay (AD12_ipd, AD12, tipd_AD12);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CEN_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_WR_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_CS0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_CS1_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_DI0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI1_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_AD0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD3_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD4_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD5_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD6_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD7_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD8_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD9_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD10_CLK_posedge   : std_ulogic  := '0';
        variable Tviol_AD11_CLK_posedge   : std_ulogic  := '0';
        variable Tviol_AD12_CLK_posedge   : std_ulogic  := '0';

        variable Tviol_RST_CLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CEN_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_AD0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD4_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD5_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD6_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD7_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD8_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD9_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD10_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD11_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD12_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_CLK_posedge_posedge  : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLK       : std_ulogic := '0';
        variable PInfo_CLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CEN_CLK_posedge,
          TimingData              => Tmkr_CEN_CLK_posedge,
          TestSignal              => CEN_ipd,
          TestSignalName          => "CEN",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CEN_CLK_noedge_posedge,
          SetupLow                => tsetup_CEN_CLK_noedge_posedge,
          HoldLow                 => thold_CEN_CLK_noedge_posedge,
          HoldHigh                => thold_CEN_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_CLK_posedge,
          TimingData              => Tmkr_WR_CLK_posedge,
          TestSignal              => WR_ipd,
          TestSignalName          => "WR",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_CLK_noedge_posedge,
          HoldLow                 => thold_WR_CLK_noedge_posedge,
          HoldHigh                => thold_WR_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS0_CLK_posedge,
          TimingData              => Tmkr_CS0_CLK_posedge,
          TestSignal              => CS0_ipd,
          TestSignalName          => "CS0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS0_CLK_noedge_posedge,
          SetupLow                => tsetup_CS0_CLK_noedge_posedge,
          HoldLow                 => thold_CS0_CLK_noedge_posedge,
          HoldHigh                => thold_CS0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS1_CLK_posedge,
          TimingData              => Tmkr_CS1_CLK_posedge,
          TestSignal              => CS1_ipd,
          TestSignalName          => "CS1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS1_CLK_noedge_posedge,
          SetupLow                => tsetup_CS1_CLK_noedge_posedge,
          HoldLow                 => thold_CS1_CLK_noedge_posedge,
          HoldHigh                => thold_CS1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_CLK_posedge,
          TimingData              => Tmkr_DI0_CLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_CLK_noedge_posedge,
          SetupLow                => tsetup_DI0_CLK_noedge_posedge,
          HoldLow                 => thold_DI0_CLK_noedge_posedge,
          HoldHigh                => thold_DI0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_CLK_posedge,
          TimingData              => Tmkr_DI1_CLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_CLK_noedge_posedge,
          SetupLow                => tsetup_DI1_CLK_noedge_posedge,
          HoldLow                 => thold_DI1_CLK_noedge_posedge,
          HoldHigh                => thold_DI1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_CLK_posedge,
          TimingData              => Tmkr_AD0_CLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_CLK_noedge_posedge,
          SetupLow                => tsetup_AD0_CLK_noedge_posedge,
          HoldLow                 => thold_AD0_CLK_noedge_posedge,
          HoldHigh                => thold_AD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_CLK_posedge,
          TimingData              => Tmkr_AD1_CLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_CLK_noedge_posedge,
          SetupLow                => tsetup_AD1_CLK_noedge_posedge,
          HoldLow                 => thold_AD1_CLK_noedge_posedge,
          HoldHigh                => thold_AD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_CLK_posedge,
          TimingData              => Tmkr_AD2_CLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_CLK_noedge_posedge,
          SetupLow                => tsetup_AD2_CLK_noedge_posedge,
          HoldLow                 => thold_AD2_CLK_noedge_posedge,
          HoldHigh                => thold_AD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_CLK_posedge,
          TimingData              => Tmkr_AD3_CLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_CLK_noedge_posedge,
          SetupLow                => tsetup_AD3_CLK_noedge_posedge,
          HoldLow                 => thold_AD3_CLK_noedge_posedge,
          HoldHigh                => thold_AD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD4_CLK_posedge,
          TimingData              => Tmkr_AD4_CLK_posedge,
          TestSignal              => AD4_ipd,
          TestSignalName          => "AD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD4_CLK_noedge_posedge,
          SetupLow                => tsetup_AD4_CLK_noedge_posedge,
          HoldLow                 => thold_AD4_CLK_noedge_posedge,
          HoldHigh                => thold_AD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD5_CLK_posedge,
          TimingData              => Tmkr_AD5_CLK_posedge,
          TestSignal              => AD5_ipd,
          TestSignalName          => "AD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD5_CLK_noedge_posedge,
          SetupLow                => tsetup_AD5_CLK_noedge_posedge,
          HoldLow                 => thold_AD5_CLK_noedge_posedge,
          HoldHigh                => thold_AD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD6_CLK_posedge,
          TimingData              => Tmkr_AD6_CLK_posedge,
          TestSignal              => AD6_ipd,
          TestSignalName          => "AD6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD6_CLK_noedge_posedge,
          SetupLow                => tsetup_AD6_CLK_noedge_posedge,
          HoldLow                 => thold_AD6_CLK_noedge_posedge,
          HoldHigh                => thold_AD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD7_CLK_posedge,
          TimingData              => Tmkr_AD7_CLK_posedge,
          TestSignal              => AD7_ipd,
          TestSignalName          => "AD7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD7_CLK_noedge_posedge,
          SetupLow                => tsetup_AD7_CLK_noedge_posedge,
          HoldLow                 => thold_AD7_CLK_noedge_posedge,
          HoldHigh                => thold_AD7_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD8_CLK_posedge,
          TimingData              => Tmkr_AD8_CLK_posedge,
          TestSignal              => AD8_ipd,
          TestSignalName          => "AD8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD8_CLK_noedge_posedge,
          SetupLow                => tsetup_AD8_CLK_noedge_posedge,
          HoldLow                 => thold_AD8_CLK_noedge_posedge,
          HoldHigh                => thold_AD8_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD9_CLK_posedge,
          TimingData              => Tmkr_AD9_CLK_posedge,
          TestSignal              => AD9_ipd,
          TestSignalName          => "AD9",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD9_CLK_noedge_posedge,
          SetupLow                => tsetup_AD9_CLK_noedge_posedge,
          HoldLow                 => thold_AD9_CLK_noedge_posedge,
          HoldHigh                => thold_AD9_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD10_CLK_posedge,
          TimingData              => Tmkr_AD10_CLK_posedge,
          TestSignal              => AD10_ipd,
          TestSignalName          => "AD10",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD10_CLK_noedge_posedge,
          SetupLow                => tsetup_AD10_CLK_noedge_posedge,
          HoldLow                 => thold_AD10_CLK_noedge_posedge,
          HoldHigh                => thold_AD10_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD11_CLK_posedge,
          TimingData              => Tmkr_AD11_CLK_posedge,
          TestSignal              => AD11_ipd,
          TestSignalName          => "AD11",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD11_CLK_noedge_posedge,
          SetupLow                => tsetup_AD11_CLK_noedge_posedge,
          HoldLow                 => thold_AD11_CLK_noedge_posedge,
          HoldHigh                => thold_AD11_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD12_CLK_posedge,
          TimingData              => Tmkr_AD12_CLK_posedge,
          TestSignal              => AD12_ipd,
          TestSignalName          => "AD12",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD12_CLK_noedge_posedge,
          SetupLow                => tsetup_AD12_CLK_noedge_posedge,
          HoldLow                 => thold_AD12_CLK_noedge_posedge,
          HoldHigh                => thold_AD12_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_CLK_posedge_posedge,
          TimingData              => Tmkr_RST_CLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_CLK_posedge_posedge,
          Removal                 => thold_RST_CLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CEN_CLK_posedge or Tviol_WR_CLK_posedge or 
                 Tviol_CS0_CLK_posedge or Tviol_CS1_CLK_posedge or 
                 Tviol_AD0_CLK_posedge or Tviol_AD1_CLK_posedge or 
                 Tviol_AD2_CLK_posedge or Tviol_AD3_CLK_posedge or 
                 Tviol_AD4_CLK_posedge or Tviol_AD5_CLK_posedge or 
                 Tviol_AD6_CLK_posedge or Tviol_AD7_CLK_posedge or 
                 Tviol_AD8_CLK_posedge or Tviol_AD9_CLK_posedge or 
                 Tviol_AD10_CLK_posedge or Tviol_AD11_CLK_posedge or 
                 Tviol_AD12_CLK_posedge or Tviol_DI0_CLK_posedge or
		 Tviol_DI1_CLK_posedge or
                 Pviol_CLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on CEN_ipd, CLK_ipd, WR_ipd, CS,  RST_ipd, DI, AD;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;



	SPRAM_INST: SC_SPRAM_16K
	   generic map (
		ADDR_WIDTH    => 13,
		DATA_WIDTH    => 2,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CEN => CEN_ipd,
		CLK => CLK_ipd,
		WR  => WR_ipd,
		CS  => CS,
		RST => RST_ipd,
		DI  => DI,
		AD  => AD,
		DO  => DO
		);

end VITAL;

configuration CFG_RAMB16K_X2_VITAL of RAMB16K_X2 is
   for VITAL
   end for;
end CFG_RAMB16K_X2_VITAL;



----- CELL RAMB16K_X4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_X4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_CLK_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WR_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_CEN_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CEN_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_AD0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD4_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD4_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD5_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD5_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD6_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD6_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD7_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD7_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD8_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD8_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD9_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD9_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD10_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD10_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD11_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD11_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RST_CLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_CLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLK_posedge                  :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                  :	VitalDelayType   := 2.0 ns;
      tipd_CEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_AD0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD8                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD9                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD10                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD11                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CEN                            :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      WR                             :	in    STD_ULOGIC;
      CS0                            :	in    STD_ULOGIC;
      CS1                            :	in    STD_ULOGIC;
      RST                            :	in    STD_ULOGIC;
      DI0                            :	in    STD_ULOGIC;
      DI1                            :	in    STD_ULOGIC;
      DI2                            :	in    STD_ULOGIC;
      DI3                            :	in    STD_ULOGIC;
      AD0                            :	in    STD_ULOGIC;
      AD1                            :	in    STD_ULOGIC;
      AD2                            :	in    STD_ULOGIC;
      AD3                            :	in    STD_ULOGIC;
      AD4                            :	in    STD_ULOGIC;
      AD5                            :	in    STD_ULOGIC;
      AD6                            :	in    STD_ULOGIC;
      AD7                            :	in    STD_ULOGIC;
      AD8                            :	in    STD_ULOGIC;
      AD9                            :	in    STD_ULOGIC;
      AD10                           :	in    STD_ULOGIC;
      AD11                           :	in    STD_ULOGIC;
      DO0                            :	out   STD_ULOGIC;
      DO1                            :	out   STD_ULOGIC;
      DO2                            :	out   STD_ULOGIC;
      DO3                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_X4 : entity is FALSE;
end RAMB16K_X4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_X4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_SPRAM_16K
	   generic (
		ADDR_WIDTH    : integer := 12;
		DATA_WIDTH    : integer := 4;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CEN : in  STD_LOGIC ;
		CLK : in  STD_LOGIC ;
		WR   : in  STD_LOGIC ;
		CS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		DI   : in  STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0);
		AD  : in  STD_LOGIC_VECTOR (ADDR_WIDTH -1 downto 0);
		DO   : out STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0)
		);
	end component ;

      signal CEN_ipd      : std_ulogic := 'X';
      signal CLK_ipd      : std_ulogic := 'X';
      signal WR_ipd       : std_ulogic := 'X';
      signal CS0_ipd      : std_ulogic := 'X';
      signal CS1_ipd      : std_ulogic := 'X';
      signal RST_ipd      : std_ulogic := 'X';

      signal DI0_ipd      : std_ulogic := 'X';
      signal DI1_ipd      : std_ulogic := 'X';
      signal DI2_ipd      : std_ulogic := 'X';
      signal DI3_ipd      : std_ulogic := 'X';

      signal AD0_ipd      : std_ulogic := 'X';
      signal AD1_ipd      : std_ulogic := 'X';
      signal AD2_ipd      : std_ulogic := 'X';
      signal AD3_ipd      : std_ulogic := 'X';
      signal AD4_ipd      : std_ulogic := 'X';
      signal AD5_ipd      : std_ulogic := 'X';
      signal AD6_ipd      : std_ulogic := 'X';
      signal AD7_ipd      : std_ulogic := 'X';
      signal AD8_ipd      : std_ulogic := 'X';
      signal AD9_ipd      : std_ulogic := 'X';
      signal AD10_ipd     : std_ulogic := 'X';
      signal AD11_ipd     : std_ulogic := 'X';

	signal CS : std_logic_vector (1 downto 0);
	signal DI  : std_logic_vector (3 downto 0);
 	signal AD : std_logic_vector (11 downto 0);
	signal DO  : std_logic_vector (3 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	CS <= CS1_ipd & CS0_ipd;
	DI <= DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd;
	AD <= AD11_ipd & AD10_ipd & AD9_ipd & AD8_ipd & AD7_ipd & AD6_ipd & AD5_ipd & AD4_ipd & AD3_ipd & AD2_ipd & AD1_ipd & AD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CEN_ipd, CEN, tipd_CEN);
        VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        VitalWireDelay (WR_ipd, WR, tipd_WR);
        VitalWireDelay (CS0_ipd, CS0, tipd_CS0);
        VitalWireDelay (CS1_ipd, CS1, tipd_CS1);
        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);

        VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
        VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
        VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
        VitalWireDelay (AD3_ipd, AD3, tipd_AD3);
        VitalWireDelay (AD4_ipd, AD4, tipd_AD4);
        VitalWireDelay (AD5_ipd, AD5, tipd_AD5);
        VitalWireDelay (AD6_ipd, AD6, tipd_AD6);
        VitalWireDelay (AD7_ipd, AD7, tipd_AD7);
        VitalWireDelay (AD8_ipd, AD8, tipd_AD8);
        VitalWireDelay (AD9_ipd, AD9, tipd_AD9);
        VitalWireDelay (AD10_ipd, AD10, tipd_AD10);
        VitalWireDelay (AD11_ipd, AD11, tipd_AD11);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CEN_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_WR_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_CS0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_CS1_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_DI0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI3_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_AD0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD3_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD4_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD5_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD6_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD7_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD8_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD9_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD10_CLK_posedge   : std_ulogic  := '0';
        variable Tviol_AD11_CLK_posedge   : std_ulogic  := '0';

        variable Tviol_RST_CLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CEN_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_AD0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD4_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD5_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD6_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD7_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD8_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD9_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD10_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD11_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_CLK_posedge_posedge  : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLK       : std_ulogic := '0';
        variable PInfo_CLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CEN_CLK_posedge,
          TimingData              => Tmkr_CEN_CLK_posedge,
          TestSignal              => CEN_ipd,
          TestSignalName          => "CEN",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CEN_CLK_noedge_posedge,
          SetupLow                => tsetup_CEN_CLK_noedge_posedge,
          HoldLow                 => thold_CEN_CLK_noedge_posedge,
          HoldHigh                => thold_CEN_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_CLK_posedge,
          TimingData              => Tmkr_WR_CLK_posedge,
          TestSignal              => WR_ipd,
          TestSignalName          => "WR",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_CLK_noedge_posedge,
          HoldLow                 => thold_WR_CLK_noedge_posedge,
          HoldHigh                => thold_WR_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS0_CLK_posedge,
          TimingData              => Tmkr_CS0_CLK_posedge,
          TestSignal              => CS0_ipd,
          TestSignalName          => "CS0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS0_CLK_noedge_posedge,
          SetupLow                => tsetup_CS0_CLK_noedge_posedge,
          HoldLow                 => thold_CS0_CLK_noedge_posedge,
          HoldHigh                => thold_CS0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS1_CLK_posedge,
          TimingData              => Tmkr_CS1_CLK_posedge,
          TestSignal              => CS1_ipd,
          TestSignalName          => "CS1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS1_CLK_noedge_posedge,
          SetupLow                => tsetup_CS1_CLK_noedge_posedge,
          HoldLow                 => thold_CS1_CLK_noedge_posedge,
          HoldHigh                => thold_CS1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_CLK_posedge,
          TimingData              => Tmkr_DI0_CLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_CLK_noedge_posedge,
          SetupLow                => tsetup_DI0_CLK_noedge_posedge,
          HoldLow                 => thold_DI0_CLK_noedge_posedge,
          HoldHigh                => thold_DI0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_CLK_posedge,
          TimingData              => Tmkr_DI1_CLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_CLK_noedge_posedge,
          SetupLow                => tsetup_DI1_CLK_noedge_posedge,
          HoldLow                 => thold_DI1_CLK_noedge_posedge,
          HoldHigh                => thold_DI1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_CLK_posedge,
          TimingData              => Tmkr_DI2_CLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_CLK_noedge_posedge,
          SetupLow                => tsetup_DI2_CLK_noedge_posedge,
          HoldLow                 => thold_DI2_CLK_noedge_posedge,
          HoldHigh                => thold_DI2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_CLK_posedge,
          TimingData              => Tmkr_DI3_CLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_CLK_noedge_posedge,
          SetupLow                => tsetup_DI3_CLK_noedge_posedge,
          HoldLow                 => thold_DI3_CLK_noedge_posedge,
          HoldHigh                => thold_DI3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_CLK_posedge,
          TimingData              => Tmkr_AD0_CLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_CLK_noedge_posedge,
          SetupLow                => tsetup_AD0_CLK_noedge_posedge,
          HoldLow                 => thold_AD0_CLK_noedge_posedge,
          HoldHigh                => thold_AD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_CLK_posedge,
          TimingData              => Tmkr_AD1_CLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_CLK_noedge_posedge,
          SetupLow                => tsetup_AD1_CLK_noedge_posedge,
          HoldLow                 => thold_AD1_CLK_noedge_posedge,
          HoldHigh                => thold_AD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_CLK_posedge,
          TimingData              => Tmkr_AD2_CLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_CLK_noedge_posedge,
          SetupLow                => tsetup_AD2_CLK_noedge_posedge,
          HoldLow                 => thold_AD2_CLK_noedge_posedge,
          HoldHigh                => thold_AD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_CLK_posedge,
          TimingData              => Tmkr_AD3_CLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_CLK_noedge_posedge,
          SetupLow                => tsetup_AD3_CLK_noedge_posedge,
          HoldLow                 => thold_AD3_CLK_noedge_posedge,
          HoldHigh                => thold_AD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD4_CLK_posedge,
          TimingData              => Tmkr_AD4_CLK_posedge,
          TestSignal              => AD4_ipd,
          TestSignalName          => "AD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD4_CLK_noedge_posedge,
          SetupLow                => tsetup_AD4_CLK_noedge_posedge,
          HoldLow                 => thold_AD4_CLK_noedge_posedge,
          HoldHigh                => thold_AD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD5_CLK_posedge,
          TimingData              => Tmkr_AD5_CLK_posedge,
          TestSignal              => AD5_ipd,
          TestSignalName          => "AD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD5_CLK_noedge_posedge,
          SetupLow                => tsetup_AD5_CLK_noedge_posedge,
          HoldLow                 => thold_AD5_CLK_noedge_posedge,
          HoldHigh                => thold_AD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD6_CLK_posedge,
          TimingData              => Tmkr_AD6_CLK_posedge,
          TestSignal              => AD6_ipd,
          TestSignalName          => "AD6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD6_CLK_noedge_posedge,
          SetupLow                => tsetup_AD6_CLK_noedge_posedge,
          HoldLow                 => thold_AD6_CLK_noedge_posedge,
          HoldHigh                => thold_AD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD7_CLK_posedge,
          TimingData              => Tmkr_AD7_CLK_posedge,
          TestSignal              => AD7_ipd,
          TestSignalName          => "AD7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD7_CLK_noedge_posedge,
          SetupLow                => tsetup_AD7_CLK_noedge_posedge,
          HoldLow                 => thold_AD7_CLK_noedge_posedge,
          HoldHigh                => thold_AD7_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD8_CLK_posedge,
          TimingData              => Tmkr_AD8_CLK_posedge,
          TestSignal              => AD8_ipd,
          TestSignalName          => "AD8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD8_CLK_noedge_posedge,
          SetupLow                => tsetup_AD8_CLK_noedge_posedge,
          HoldLow                 => thold_AD8_CLK_noedge_posedge,
          HoldHigh                => thold_AD8_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD9_CLK_posedge,
          TimingData              => Tmkr_AD9_CLK_posedge,
          TestSignal              => AD9_ipd,
          TestSignalName          => "AD9",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD9_CLK_noedge_posedge,
          SetupLow                => tsetup_AD9_CLK_noedge_posedge,
          HoldLow                 => thold_AD9_CLK_noedge_posedge,
          HoldHigh                => thold_AD9_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD10_CLK_posedge,
          TimingData              => Tmkr_AD10_CLK_posedge,
          TestSignal              => AD10_ipd,
          TestSignalName          => "AD10",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD10_CLK_noedge_posedge,
          SetupLow                => tsetup_AD10_CLK_noedge_posedge,
          HoldLow                 => thold_AD10_CLK_noedge_posedge,
          HoldHigh                => thold_AD10_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD11_CLK_posedge,
          TimingData              => Tmkr_AD11_CLK_posedge,
          TestSignal              => AD11_ipd,
          TestSignalName          => "AD11",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD11_CLK_noedge_posedge,
          SetupLow                => tsetup_AD11_CLK_noedge_posedge,
          HoldLow                 => thold_AD11_CLK_noedge_posedge,
          HoldHigh                => thold_AD11_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_CLK_posedge_posedge,
          TimingData              => Tmkr_RST_CLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_CLK_posedge_posedge,
          Removal                 => thold_RST_CLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CEN_CLK_posedge or Tviol_WR_CLK_posedge or 
                 Tviol_CS0_CLK_posedge or Tviol_CS1_CLK_posedge or 
                 Tviol_AD0_CLK_posedge or Tviol_AD1_CLK_posedge or 
                 Tviol_AD2_CLK_posedge or Tviol_AD3_CLK_posedge or 
                 Tviol_AD4_CLK_posedge or Tviol_AD5_CLK_posedge or 
                 Tviol_AD6_CLK_posedge or Tviol_AD7_CLK_posedge or 
                 Tviol_AD8_CLK_posedge or Tviol_AD9_CLK_posedge or 
                 Tviol_AD10_CLK_posedge or Tviol_AD11_CLK_posedge or 
                 Tviol_DI0_CLK_posedge  or Tviol_DI1_CLK_posedge or
                 Tviol_DI2_CLK_posedge  or Tviol_DI3_CLK_posedge or
                 Pviol_CLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on CEN_ipd, CLK_ipd, WR_ipd, CS,  RST_ipd, DI, AD;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;



	SPRAM_INST: SC_SPRAM_16K
	   generic map (
		ADDR_WIDTH    => 12,
		DATA_WIDTH    => 4,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CEN => CEN_ipd,
		CLK => CLK_ipd,
		WR  => WR_ipd,
		CS  => CS,
		RST => RST_ipd,
		DI  => DI,
		AD  => AD,
		DO  => DO
		);

end VITAL;

configuration CFG_RAMB16K_X4_VITAL of RAMB16K_X4 is
   for VITAL
   end for;
end CFG_RAMB16K_X4_VITAL;



----- CELL RAMB16K_X8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_X8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_CLK_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WR_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_CEN_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CEN_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI4_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI5_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI6_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI7_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_AD0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD4_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD4_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD5_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD5_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD6_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD6_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD7_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD7_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD8_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD8_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD9_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD9_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD10_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD10_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RST_CLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_CLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLK_posedge                  :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                  :	VitalDelayType   := 2.0 ns;
      tipd_CEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_AD0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD8                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD9                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD10                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CEN                            :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      WR                             :	in    STD_ULOGIC;
      CS0                            :	in    STD_ULOGIC;
      CS1                            :	in    STD_ULOGIC;
      RST                            :	in    STD_ULOGIC;
      DI0                            :	in    STD_ULOGIC;
      DI1                            :	in    STD_ULOGIC;
      DI2                            :	in    STD_ULOGIC;
      DI3                            :	in    STD_ULOGIC;
      DI4                            :	in    STD_ULOGIC;
      DI5                            :	in    STD_ULOGIC;
      DI6                            :	in    STD_ULOGIC;
      DI7                            :	in    STD_ULOGIC;
      AD0                            :	in    STD_ULOGIC;
      AD1                            :	in    STD_ULOGIC;
      AD2                            :	in    STD_ULOGIC;
      AD3                            :	in    STD_ULOGIC;
      AD4                            :	in    STD_ULOGIC;
      AD5                            :	in    STD_ULOGIC;
      AD6                            :	in    STD_ULOGIC;
      AD7                            :	in    STD_ULOGIC;
      AD8                            :	in    STD_ULOGIC;
      AD9                            :	in    STD_ULOGIC;
      AD10                           :	in    STD_ULOGIC;
      DO0                            :	out   STD_ULOGIC;
      DO1                            :	out   STD_ULOGIC;
      DO2                            :	out   STD_ULOGIC;
      DO3                            :	out   STD_ULOGIC;
      DO4                            :	out   STD_ULOGIC;
      DO5                            :	out   STD_ULOGIC;
      DO6                            :	out   STD_ULOGIC;
      DO7                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_X8 : entity is FALSE;
end RAMB16K_X8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_X8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_SPRAM_16K
	   generic (
		ADDR_WIDTH    : integer := 11;
		DATA_WIDTH    : integer := 8;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CEN : in  STD_LOGIC ;
		CLK : in  STD_LOGIC ;
		WR   : in  STD_LOGIC ;
		CS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		DI   : in  STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0);
		AD  : in  STD_LOGIC_VECTOR (ADDR_WIDTH -1 downto 0);
		DO   : out STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0)
		);
	end component ;

      signal CEN_ipd      : std_ulogic := 'X';
      signal CLK_ipd      : std_ulogic := 'X';
      signal WR_ipd       : std_ulogic := 'X';
      signal CS0_ipd      : std_ulogic := 'X';
      signal CS1_ipd      : std_ulogic := 'X';
      signal RST_ipd      : std_ulogic := 'X';

      signal DI0_ipd      : std_ulogic := 'X';
      signal DI1_ipd      : std_ulogic := 'X';
      signal DI2_ipd      : std_ulogic := 'X';
      signal DI3_ipd      : std_ulogic := 'X';
      signal DI4_ipd      : std_ulogic := 'X';
      signal DI5_ipd      : std_ulogic := 'X';
      signal DI6_ipd      : std_ulogic := 'X';
      signal DI7_ipd      : std_ulogic := 'X';

      signal AD0_ipd      : std_ulogic := 'X';
      signal AD1_ipd      : std_ulogic := 'X';
      signal AD2_ipd      : std_ulogic := 'X';
      signal AD3_ipd      : std_ulogic := 'X';
      signal AD4_ipd      : std_ulogic := 'X';
      signal AD5_ipd      : std_ulogic := 'X';
      signal AD6_ipd      : std_ulogic := 'X';
      signal AD7_ipd      : std_ulogic := 'X';
      signal AD8_ipd      : std_ulogic := 'X';
      signal AD9_ipd      : std_ulogic := 'X';
      signal AD10_ipd     : std_ulogic := 'X';

	signal CS : std_logic_vector (1 downto 0);
	signal DI  : std_logic_vector (7 downto 0);
 	signal AD : std_logic_vector (10 downto 0);
	signal DO  : std_logic_vector (7 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	CS <= CS1_ipd & CS0_ipd;
	DI <= DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd;
	AD <= AD10_ipd & AD9_ipd & AD8_ipd & AD7_ipd & AD6_ipd & AD5_ipd & AD4_ipd & AD3_ipd & AD2_ipd & AD1_ipd & AD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CEN_ipd, CEN, tipd_CEN);
        VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        VitalWireDelay (WR_ipd, WR, tipd_WR);
        VitalWireDelay (CS0_ipd, CS0, tipd_CS0);
        VitalWireDelay (CS1_ipd, CS1, tipd_CS1);
        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);

        VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
        VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
        VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
        VitalWireDelay (AD3_ipd, AD3, tipd_AD3);
        VitalWireDelay (AD4_ipd, AD4, tipd_AD4);
        VitalWireDelay (AD5_ipd, AD5, tipd_AD5);
        VitalWireDelay (AD6_ipd, AD6, tipd_AD6);
        VitalWireDelay (AD7_ipd, AD7, tipd_AD7);
        VitalWireDelay (AD8_ipd, AD8, tipd_AD8);
        VitalWireDelay (AD9_ipd, AD9, tipd_AD9);
        VitalWireDelay (AD10_ipd, AD10, tipd_AD10);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CEN_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_WR_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_CS0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_CS1_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_DI0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI3_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI4_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI5_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI6_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI7_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_AD0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD3_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD4_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD5_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD6_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD7_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD8_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD9_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD10_CLK_posedge   : std_ulogic  := '0';

        variable Tviol_RST_CLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CEN_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_AD0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD4_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD5_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD6_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD7_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD8_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD9_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD10_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_CLK_posedge_posedge  : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLK       : std_ulogic := '0';
        variable PInfo_CLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CEN_CLK_posedge,
          TimingData              => Tmkr_CEN_CLK_posedge,
          TestSignal              => CEN_ipd,
          TestSignalName          => "CEN",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CEN_CLK_noedge_posedge,
          SetupLow                => tsetup_CEN_CLK_noedge_posedge,
          HoldLow                 => thold_CEN_CLK_noedge_posedge,
          HoldHigh                => thold_CEN_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_CLK_posedge,
          TimingData              => Tmkr_WR_CLK_posedge,
          TestSignal              => WR_ipd,
          TestSignalName          => "WR",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_CLK_noedge_posedge,
          HoldLow                 => thold_WR_CLK_noedge_posedge,
          HoldHigh                => thold_WR_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS0_CLK_posedge,
          TimingData              => Tmkr_CS0_CLK_posedge,
          TestSignal              => CS0_ipd,
          TestSignalName          => "CS0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS0_CLK_noedge_posedge,
          SetupLow                => tsetup_CS0_CLK_noedge_posedge,
          HoldLow                 => thold_CS0_CLK_noedge_posedge,
          HoldHigh                => thold_CS0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS1_CLK_posedge,
          TimingData              => Tmkr_CS1_CLK_posedge,
          TestSignal              => CS1_ipd,
          TestSignalName          => "CS1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS1_CLK_noedge_posedge,
          SetupLow                => tsetup_CS1_CLK_noedge_posedge,
          HoldLow                 => thold_CS1_CLK_noedge_posedge,
          HoldHigh                => thold_CS1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_CLK_posedge,
          TimingData              => Tmkr_DI0_CLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_CLK_noedge_posedge,
          SetupLow                => tsetup_DI0_CLK_noedge_posedge,
          HoldLow                 => thold_DI0_CLK_noedge_posedge,
          HoldHigh                => thold_DI0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_CLK_posedge,
          TimingData              => Tmkr_DI1_CLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_CLK_noedge_posedge,
          SetupLow                => tsetup_DI1_CLK_noedge_posedge,
          HoldLow                 => thold_DI1_CLK_noedge_posedge,
          HoldHigh                => thold_DI1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_CLK_posedge,
          TimingData              => Tmkr_DI2_CLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_CLK_noedge_posedge,
          SetupLow                => tsetup_DI2_CLK_noedge_posedge,
          HoldLow                 => thold_DI2_CLK_noedge_posedge,
          HoldHigh                => thold_DI2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_CLK_posedge,
          TimingData              => Tmkr_DI3_CLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_CLK_noedge_posedge,
          SetupLow                => tsetup_DI3_CLK_noedge_posedge,
          HoldLow                 => thold_DI3_CLK_noedge_posedge,
          HoldHigh                => thold_DI3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_CLK_posedge,
          TimingData              => Tmkr_DI4_CLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_CLK_noedge_posedge,
          SetupLow                => tsetup_DI4_CLK_noedge_posedge,
          HoldLow                 => thold_DI4_CLK_noedge_posedge,
          HoldHigh                => thold_DI4_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_CLK_posedge,
          TimingData              => Tmkr_DI5_CLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_CLK_noedge_posedge,
          SetupLow                => tsetup_DI5_CLK_noedge_posedge,
          HoldLow                 => thold_DI5_CLK_noedge_posedge,
          HoldHigh                => thold_DI5_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_CLK_posedge,
          TimingData              => Tmkr_DI6_CLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_CLK_noedge_posedge,
          SetupLow                => tsetup_DI6_CLK_noedge_posedge,
          HoldLow                 => thold_DI6_CLK_noedge_posedge,
          HoldHigh                => thold_DI6_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_CLK_posedge,
          TimingData              => Tmkr_DI7_CLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_CLK_noedge_posedge,
          SetupLow                => tsetup_DI7_CLK_noedge_posedge,
          HoldLow                 => thold_DI7_CLK_noedge_posedge,
          HoldHigh                => thold_DI7_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_CLK_posedge,
          TimingData              => Tmkr_AD0_CLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_CLK_noedge_posedge,
          SetupLow                => tsetup_AD0_CLK_noedge_posedge,
          HoldLow                 => thold_AD0_CLK_noedge_posedge,
          HoldHigh                => thold_AD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_CLK_posedge,
          TimingData              => Tmkr_AD1_CLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_CLK_noedge_posedge,
          SetupLow                => tsetup_AD1_CLK_noedge_posedge,
          HoldLow                 => thold_AD1_CLK_noedge_posedge,
          HoldHigh                => thold_AD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_CLK_posedge,
          TimingData              => Tmkr_AD2_CLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_CLK_noedge_posedge,
          SetupLow                => tsetup_AD2_CLK_noedge_posedge,
          HoldLow                 => thold_AD2_CLK_noedge_posedge,
          HoldHigh                => thold_AD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_CLK_posedge,
          TimingData              => Tmkr_AD3_CLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_CLK_noedge_posedge,
          SetupLow                => tsetup_AD3_CLK_noedge_posedge,
          HoldLow                 => thold_AD3_CLK_noedge_posedge,
          HoldHigh                => thold_AD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD4_CLK_posedge,
          TimingData              => Tmkr_AD4_CLK_posedge,
          TestSignal              => AD4_ipd,
          TestSignalName          => "AD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD4_CLK_noedge_posedge,
          SetupLow                => tsetup_AD4_CLK_noedge_posedge,
          HoldLow                 => thold_AD4_CLK_noedge_posedge,
          HoldHigh                => thold_AD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD5_CLK_posedge,
          TimingData              => Tmkr_AD5_CLK_posedge,
          TestSignal              => AD5_ipd,
          TestSignalName          => "AD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD5_CLK_noedge_posedge,
          SetupLow                => tsetup_AD5_CLK_noedge_posedge,
          HoldLow                 => thold_AD5_CLK_noedge_posedge,
          HoldHigh                => thold_AD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD6_CLK_posedge,
          TimingData              => Tmkr_AD6_CLK_posedge,
          TestSignal              => AD6_ipd,
          TestSignalName          => "AD6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD6_CLK_noedge_posedge,
          SetupLow                => tsetup_AD6_CLK_noedge_posedge,
          HoldLow                 => thold_AD6_CLK_noedge_posedge,
          HoldHigh                => thold_AD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD7_CLK_posedge,
          TimingData              => Tmkr_AD7_CLK_posedge,
          TestSignal              => AD7_ipd,
          TestSignalName          => "AD7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD7_CLK_noedge_posedge,
          SetupLow                => tsetup_AD7_CLK_noedge_posedge,
          HoldLow                 => thold_AD7_CLK_noedge_posedge,
          HoldHigh                => thold_AD7_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD8_CLK_posedge,
          TimingData              => Tmkr_AD8_CLK_posedge,
          TestSignal              => AD8_ipd,
          TestSignalName          => "AD8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD8_CLK_noedge_posedge,
          SetupLow                => tsetup_AD8_CLK_noedge_posedge,
          HoldLow                 => thold_AD8_CLK_noedge_posedge,
          HoldHigh                => thold_AD8_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD9_CLK_posedge,
          TimingData              => Tmkr_AD9_CLK_posedge,
          TestSignal              => AD9_ipd,
          TestSignalName          => "AD9",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD9_CLK_noedge_posedge,
          SetupLow                => tsetup_AD9_CLK_noedge_posedge,
          HoldLow                 => thold_AD9_CLK_noedge_posedge,
          HoldHigh                => thold_AD9_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD10_CLK_posedge,
          TimingData              => Tmkr_AD10_CLK_posedge,
          TestSignal              => AD10_ipd,
          TestSignalName          => "AD10",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD10_CLK_noedge_posedge,
          SetupLow                => tsetup_AD10_CLK_noedge_posedge,
          HoldLow                 => thold_AD10_CLK_noedge_posedge,
          HoldHigh                => thold_AD10_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_CLK_posedge_posedge,
          TimingData              => Tmkr_RST_CLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_CLK_posedge_posedge,
          Removal                 => thold_RST_CLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CEN_CLK_posedge or Tviol_WR_CLK_posedge or 
                 Tviol_CS0_CLK_posedge or Tviol_CS1_CLK_posedge or 
                 Tviol_AD0_CLK_posedge or Tviol_AD1_CLK_posedge or 
                 Tviol_AD2_CLK_posedge or Tviol_AD3_CLK_posedge or 
                 Tviol_AD4_CLK_posedge or Tviol_AD5_CLK_posedge or 
                 Tviol_AD6_CLK_posedge or Tviol_AD7_CLK_posedge or 
                 Tviol_AD8_CLK_posedge or Tviol_AD9_CLK_posedge or 
                 Tviol_AD10_CLK_posedge or
                 Tviol_DI0_CLK_posedge  or Tviol_DI1_CLK_posedge or
                 Tviol_DI2_CLK_posedge  or Tviol_DI3_CLK_posedge or
                 Tviol_DI4_CLK_posedge  or Tviol_DI5_CLK_posedge or
                 Tviol_DI6_CLK_posedge  or Tviol_DI7_CLK_posedge or
                 Pviol_CLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on CEN_ipd, CLK_ipd, WR_ipd, CS,  RST_ipd, DI, AD;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;



	SPRAM_INST: SC_SPRAM_16K
	   generic map (
		ADDR_WIDTH    => 11,
		DATA_WIDTH    => 8,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CEN => CEN_ipd,
		CLK => CLK_ipd,
		WR  => WR_ipd,
		CS  => CS,
		RST => RST_ipd,
		DI  => DI,
		AD  => AD,
		DO  => DO
		);

end VITAL;

configuration CFG_RAMB16K_X8_VITAL of RAMB16K_X8 is
   for VITAL
   end for;
end CFG_RAMB16K_X8_VITAL;



----- CELL RAMB16K_X16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_X16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_CLK_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO10                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO11                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO12                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO13                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO14                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO15                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO10                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO11                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO12                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO13                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO14                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO15                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WR_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_CEN_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CEN_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI4_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI5_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI6_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI7_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI8_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI8_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI9_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI9_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI10_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI10_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI11_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI11_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI12_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI12_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI13_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI13_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI14_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI14_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI15_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI15_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_AD0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD4_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD4_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD5_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD5_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD6_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD6_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD7_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD7_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD8_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD8_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD9_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD9_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_CLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_CLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLK_posedge                  :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                  :	VitalDelayType   := 2.0 ns;
      tipd_CEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI8                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI9                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI10                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI11                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI12                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI13                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI14                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI15                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_AD0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD8                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD9                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CEN                            :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      WR                             :	in    STD_ULOGIC;
      CS0                            :	in    STD_ULOGIC;
      CS1                            :	in    STD_ULOGIC;
      RST                            :	in    STD_ULOGIC;
      DI0                            :	in    STD_ULOGIC;
      DI1                            :	in    STD_ULOGIC;
      DI2                            :	in    STD_ULOGIC;
      DI3                            :	in    STD_ULOGIC;
      DI4                            :	in    STD_ULOGIC;
      DI5                            :	in    STD_ULOGIC;
      DI6                            :	in    STD_ULOGIC;
      DI7                            :	in    STD_ULOGIC;
      DI8                            :	in    STD_ULOGIC;
      DI9                            :	in    STD_ULOGIC;
      DI10                           :	in    STD_ULOGIC;
      DI11                           :	in    STD_ULOGIC;
      DI12                           :	in    STD_ULOGIC;
      DI13                           :	in    STD_ULOGIC;
      DI14                           :	in    STD_ULOGIC;
      DI15                           :	in    STD_ULOGIC;
      AD0                            :	in    STD_ULOGIC;
      AD1                            :	in    STD_ULOGIC;
      AD2                            :	in    STD_ULOGIC;
      AD3                            :	in    STD_ULOGIC;
      AD4                            :	in    STD_ULOGIC;
      AD5                            :	in    STD_ULOGIC;
      AD6                            :	in    STD_ULOGIC;
      AD7                            :	in    STD_ULOGIC;
      AD8                            :	in    STD_ULOGIC;
      AD9                            :	in    STD_ULOGIC;
      DO0                            :	out   STD_ULOGIC;
      DO1                            :	out   STD_ULOGIC;
      DO2                            :	out   STD_ULOGIC;
      DO3                            :	out   STD_ULOGIC;
      DO4                            :	out   STD_ULOGIC;
      DO5                            :	out   STD_ULOGIC;
      DO6                            :	out   STD_ULOGIC;
      DO7                            :	out   STD_ULOGIC;
      DO8                            :	out   STD_ULOGIC;
      DO9                            :	out   STD_ULOGIC;
      DO10                            :	out   STD_ULOGIC;
      DO11                            :	out   STD_ULOGIC;
      DO12                            :	out   STD_ULOGIC;
      DO13                            :	out   STD_ULOGIC;
      DO14                            :	out   STD_ULOGIC;
      DO15                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_X16 : entity is FALSE;
end RAMB16K_X16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_X16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_SPRAM_16K
	   generic (
		ADDR_WIDTH    : integer := 10;
		DATA_WIDTH    : integer := 16;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CEN : in  STD_LOGIC ;
		CLK : in  STD_LOGIC ;
		WR   : in  STD_LOGIC ;
		CS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		DI   : in  STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0);
		AD  : in  STD_LOGIC_VECTOR (ADDR_WIDTH -1 downto 0);
		DO   : out STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0)
		);
	end component ;

      signal CEN_ipd      : std_ulogic := 'X';
      signal CLK_ipd      : std_ulogic := 'X';
      signal WR_ipd       : std_ulogic := 'X';
      signal CS0_ipd      : std_ulogic := 'X';
      signal CS1_ipd      : std_ulogic := 'X';
      signal RST_ipd      : std_ulogic := 'X';

      signal DI0_ipd      : std_ulogic := 'X';
      signal DI1_ipd      : std_ulogic := 'X';
      signal DI2_ipd      : std_ulogic := 'X';
      signal DI3_ipd      : std_ulogic := 'X';
      signal DI4_ipd      : std_ulogic := 'X';
      signal DI5_ipd      : std_ulogic := 'X';
      signal DI6_ipd      : std_ulogic := 'X';
      signal DI7_ipd      : std_ulogic := 'X';
      signal DI8_ipd      : std_ulogic := 'X';
      signal DI9_ipd      : std_ulogic := 'X';
      signal DI10_ipd      : std_ulogic := 'X';
      signal DI11_ipd      : std_ulogic := 'X';
      signal DI12_ipd      : std_ulogic := 'X';
      signal DI13_ipd      : std_ulogic := 'X';
      signal DI14_ipd      : std_ulogic := 'X';
      signal DI15_ipd      : std_ulogic := 'X';

      signal AD0_ipd      : std_ulogic := 'X';
      signal AD1_ipd      : std_ulogic := 'X';
      signal AD2_ipd      : std_ulogic := 'X';
      signal AD3_ipd      : std_ulogic := 'X';
      signal AD4_ipd      : std_ulogic := 'X';
      signal AD5_ipd      : std_ulogic := 'X';
      signal AD6_ipd      : std_ulogic := 'X';
      signal AD7_ipd      : std_ulogic := 'X';
      signal AD8_ipd      : std_ulogic := 'X';
      signal AD9_ipd      : std_ulogic := 'X';

	signal CS : std_logic_vector (1 downto 0);
	signal DI  : std_logic_vector (15 downto 0);
 	signal AD : std_logic_vector (9 downto 0);
	signal DO  : std_logic_vector (15 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	CS <= CS1_ipd & CS0_ipd;
	DI <= DI15_ipd & DI14_ipd & DI13_ipd & DI12_ipd & DI11_ipd & DI10_ipd & DI9_ipd & DI8_ipd & DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd;
	AD <= AD9_ipd & AD8_ipd & AD7_ipd & AD6_ipd & AD5_ipd & AD4_ipd & AD3_ipd & AD2_ipd & AD1_ipd & AD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CEN_ipd, CEN, tipd_CEN);
        VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        VitalWireDelay (WR_ipd, WR, tipd_WR);
        VitalWireDelay (CS0_ipd, CS0, tipd_CS0);
        VitalWireDelay (CS1_ipd, CS1, tipd_CS1);
        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);
        VitalWireDelay (DI8_ipd, DI8, tipd_DI8);
        VitalWireDelay (DI9_ipd, DI9, tipd_DI9);
        VitalWireDelay (DI10_ipd, DI10, tipd_DI10);
        VitalWireDelay (DI11_ipd, DI11, tipd_DI11);
        VitalWireDelay (DI12_ipd, DI12, tipd_DI12);
        VitalWireDelay (DI13_ipd, DI13, tipd_DI13);
        VitalWireDelay (DI14_ipd, DI14, tipd_DI14);
        VitalWireDelay (DI15_ipd, DI15, tipd_DI15);

        VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
        VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
        VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
        VitalWireDelay (AD3_ipd, AD3, tipd_AD3);
        VitalWireDelay (AD4_ipd, AD4, tipd_AD4);
        VitalWireDelay (AD5_ipd, AD5, tipd_AD5);
        VitalWireDelay (AD6_ipd, AD6, tipd_AD6);
        VitalWireDelay (AD7_ipd, AD7, tipd_AD7);
        VitalWireDelay (AD8_ipd, AD8, tipd_AD8);
        VitalWireDelay (AD9_ipd, AD9, tipd_AD9);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CEN_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_WR_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_CS0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_CS1_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_DI0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI3_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI4_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI5_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI6_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI7_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI8_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI9_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI10_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI11_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI12_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI13_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI14_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI15_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_AD0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD3_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD4_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD5_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD6_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD7_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD8_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD9_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_CLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CEN_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI8_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI9_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI10_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI11_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI12_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI13_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI14_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI15_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_AD0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD4_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD5_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD6_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD7_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD8_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD9_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_CLK_posedge_posedge  : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLK       : std_ulogic := '0';
        variable PInfo_CLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable DO8_zd          : std_ulogic := 'X';
        variable DO9_zd          : std_ulogic := 'X';
        variable DO10_zd          : std_ulogic := 'X';
        variable DO11_zd          : std_ulogic := 'X';
        variable DO12_zd          : std_ulogic := 'X';
        variable DO13_zd          : std_ulogic := 'X';
        variable DO14_zd          : std_ulogic := 'X';
        variable DO15_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CEN_CLK_posedge,
          TimingData              => Tmkr_CEN_CLK_posedge,
          TestSignal              => CEN_ipd,
          TestSignalName          => "CEN",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CEN_CLK_noedge_posedge,
          SetupLow                => tsetup_CEN_CLK_noedge_posedge,
          HoldLow                 => thold_CEN_CLK_noedge_posedge,
          HoldHigh                => thold_CEN_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_CLK_posedge,
          TimingData              => Tmkr_WR_CLK_posedge,
          TestSignal              => WR_ipd,
          TestSignalName          => "WR",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_CLK_noedge_posedge,
          HoldLow                 => thold_WR_CLK_noedge_posedge,
          HoldHigh                => thold_WR_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS0_CLK_posedge,
          TimingData              => Tmkr_CS0_CLK_posedge,
          TestSignal              => CS0_ipd,
          TestSignalName          => "CS0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS0_CLK_noedge_posedge,
          SetupLow                => tsetup_CS0_CLK_noedge_posedge,
          HoldLow                 => thold_CS0_CLK_noedge_posedge,
          HoldHigh                => thold_CS0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS1_CLK_posedge,
          TimingData              => Tmkr_CS1_CLK_posedge,
          TestSignal              => CS1_ipd,
          TestSignalName          => "CS1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS1_CLK_noedge_posedge,
          SetupLow                => tsetup_CS1_CLK_noedge_posedge,
          HoldLow                 => thold_CS1_CLK_noedge_posedge,
          HoldHigh                => thold_CS1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_CLK_posedge,
          TimingData              => Tmkr_DI0_CLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_CLK_noedge_posedge,
          SetupLow                => tsetup_DI0_CLK_noedge_posedge,
          HoldLow                 => thold_DI0_CLK_noedge_posedge,
          HoldHigh                => thold_DI0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_CLK_posedge,
          TimingData              => Tmkr_DI1_CLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_CLK_noedge_posedge,
          SetupLow                => tsetup_DI1_CLK_noedge_posedge,
          HoldLow                 => thold_DI1_CLK_noedge_posedge,
          HoldHigh                => thold_DI1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_CLK_posedge,
          TimingData              => Tmkr_DI2_CLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_CLK_noedge_posedge,
          SetupLow                => tsetup_DI2_CLK_noedge_posedge,
          HoldLow                 => thold_DI2_CLK_noedge_posedge,
          HoldHigh                => thold_DI2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_CLK_posedge,
          TimingData              => Tmkr_DI3_CLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_CLK_noedge_posedge,
          SetupLow                => tsetup_DI3_CLK_noedge_posedge,
          HoldLow                 => thold_DI3_CLK_noedge_posedge,
          HoldHigh                => thold_DI3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_CLK_posedge,
          TimingData              => Tmkr_DI4_CLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_CLK_noedge_posedge,
          SetupLow                => tsetup_DI4_CLK_noedge_posedge,
          HoldLow                 => thold_DI4_CLK_noedge_posedge,
          HoldHigh                => thold_DI4_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_CLK_posedge,
          TimingData              => Tmkr_DI5_CLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_CLK_noedge_posedge,
          SetupLow                => tsetup_DI5_CLK_noedge_posedge,
          HoldLow                 => thold_DI5_CLK_noedge_posedge,
          HoldHigh                => thold_DI5_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_CLK_posedge,
          TimingData              => Tmkr_DI6_CLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_CLK_noedge_posedge,
          SetupLow                => tsetup_DI6_CLK_noedge_posedge,
          HoldLow                 => thold_DI6_CLK_noedge_posedge,
          HoldHigh                => thold_DI6_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_CLK_posedge,
          TimingData              => Tmkr_DI7_CLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_CLK_noedge_posedge,
          SetupLow                => tsetup_DI7_CLK_noedge_posedge,
          HoldLow                 => thold_DI7_CLK_noedge_posedge,
          HoldHigh                => thold_DI7_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI8_CLK_posedge,
          TimingData              => Tmkr_DI8_CLK_posedge,
          TestSignal              => DI8_ipd,
          TestSignalName          => "DI8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI8_CLK_noedge_posedge,
          SetupLow                => tsetup_DI8_CLK_noedge_posedge,
          HoldLow                 => thold_DI8_CLK_noedge_posedge,
          HoldHigh                => thold_DI8_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI9_CLK_posedge,
          TimingData              => Tmkr_DI9_CLK_posedge,
          TestSignal              => DI9_ipd,
          TestSignalName          => "DI9",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI9_CLK_noedge_posedge,
          SetupLow                => tsetup_DI9_CLK_noedge_posedge,
          HoldLow                 => thold_DI9_CLK_noedge_posedge,
          HoldHigh                => thold_DI9_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI10_CLK_posedge,
          TimingData              => Tmkr_DI10_CLK_posedge,
          TestSignal              => DI10_ipd,
          TestSignalName          => "DI10",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI10_CLK_noedge_posedge,
          SetupLow                => tsetup_DI10_CLK_noedge_posedge,
          HoldLow                 => thold_DI10_CLK_noedge_posedge,
          HoldHigh                => thold_DI10_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI11_CLK_posedge,
          TimingData              => Tmkr_DI11_CLK_posedge,
          TestSignal              => DI11_ipd,
          TestSignalName          => "DI11",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI11_CLK_noedge_posedge,
          SetupLow                => tsetup_DI11_CLK_noedge_posedge,
          HoldLow                 => thold_DI11_CLK_noedge_posedge,
          HoldHigh                => thold_DI11_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI12_CLK_posedge,
          TimingData              => Tmkr_DI12_CLK_posedge,
          TestSignal              => DI12_ipd,
          TestSignalName          => "DI12",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI12_CLK_noedge_posedge,
          SetupLow                => tsetup_DI12_CLK_noedge_posedge,
          HoldLow                 => thold_DI12_CLK_noedge_posedge,
          HoldHigh                => thold_DI12_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI13_CLK_posedge,
          TimingData              => Tmkr_DI13_CLK_posedge,
          TestSignal              => DI13_ipd,
          TestSignalName          => "DI13",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI13_CLK_noedge_posedge,
          SetupLow                => tsetup_DI13_CLK_noedge_posedge,
          HoldLow                 => thold_DI13_CLK_noedge_posedge,
          HoldHigh                => thold_DI13_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI14_CLK_posedge,
          TimingData              => Tmkr_DI14_CLK_posedge,
          TestSignal              => DI14_ipd,
          TestSignalName          => "DI14",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI14_CLK_noedge_posedge,
          SetupLow                => tsetup_DI14_CLK_noedge_posedge,
          HoldLow                 => thold_DI14_CLK_noedge_posedge,
          HoldHigh                => thold_DI14_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI15_CLK_posedge,
          TimingData              => Tmkr_DI15_CLK_posedge,
          TestSignal              => DI15_ipd,
          TestSignalName          => "DI15",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI15_CLK_noedge_posedge,
          SetupLow                => tsetup_DI15_CLK_noedge_posedge,
          HoldLow                 => thold_DI15_CLK_noedge_posedge,
          HoldHigh                => thold_DI15_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_CLK_posedge,
          TimingData              => Tmkr_AD0_CLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_CLK_noedge_posedge,
          SetupLow                => tsetup_AD0_CLK_noedge_posedge,
          HoldLow                 => thold_AD0_CLK_noedge_posedge,
          HoldHigh                => thold_AD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_CLK_posedge,
          TimingData              => Tmkr_AD1_CLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_CLK_noedge_posedge,
          SetupLow                => tsetup_AD1_CLK_noedge_posedge,
          HoldLow                 => thold_AD1_CLK_noedge_posedge,
          HoldHigh                => thold_AD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_CLK_posedge,
          TimingData              => Tmkr_AD2_CLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_CLK_noedge_posedge,
          SetupLow                => tsetup_AD2_CLK_noedge_posedge,
          HoldLow                 => thold_AD2_CLK_noedge_posedge,
          HoldHigh                => thold_AD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_CLK_posedge,
          TimingData              => Tmkr_AD3_CLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_CLK_noedge_posedge,
          SetupLow                => tsetup_AD3_CLK_noedge_posedge,
          HoldLow                 => thold_AD3_CLK_noedge_posedge,
          HoldHigh                => thold_AD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD4_CLK_posedge,
          TimingData              => Tmkr_AD4_CLK_posedge,
          TestSignal              => AD4_ipd,
          TestSignalName          => "AD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD4_CLK_noedge_posedge,
          SetupLow                => tsetup_AD4_CLK_noedge_posedge,
          HoldLow                 => thold_AD4_CLK_noedge_posedge,
          HoldHigh                => thold_AD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD5_CLK_posedge,
          TimingData              => Tmkr_AD5_CLK_posedge,
          TestSignal              => AD5_ipd,
          TestSignalName          => "AD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD5_CLK_noedge_posedge,
          SetupLow                => tsetup_AD5_CLK_noedge_posedge,
          HoldLow                 => thold_AD5_CLK_noedge_posedge,
          HoldHigh                => thold_AD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD6_CLK_posedge,
          TimingData              => Tmkr_AD6_CLK_posedge,
          TestSignal              => AD6_ipd,
          TestSignalName          => "AD6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD6_CLK_noedge_posedge,
          SetupLow                => tsetup_AD6_CLK_noedge_posedge,
          HoldLow                 => thold_AD6_CLK_noedge_posedge,
          HoldHigh                => thold_AD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD7_CLK_posedge,
          TimingData              => Tmkr_AD7_CLK_posedge,
          TestSignal              => AD7_ipd,
          TestSignalName          => "AD7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD7_CLK_noedge_posedge,
          SetupLow                => tsetup_AD7_CLK_noedge_posedge,
          HoldLow                 => thold_AD7_CLK_noedge_posedge,
          HoldHigh                => thold_AD7_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD8_CLK_posedge,
          TimingData              => Tmkr_AD8_CLK_posedge,
          TestSignal              => AD8_ipd,
          TestSignalName          => "AD8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD8_CLK_noedge_posedge,
          SetupLow                => tsetup_AD8_CLK_noedge_posedge,
          HoldLow                 => thold_AD8_CLK_noedge_posedge,
          HoldHigh                => thold_AD8_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD9_CLK_posedge,
          TimingData              => Tmkr_AD9_CLK_posedge,
          TestSignal              => AD9_ipd,
          TestSignalName          => "AD9",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD9_CLK_noedge_posedge,
          SetupLow                => tsetup_AD9_CLK_noedge_posedge,
          HoldLow                 => thold_AD9_CLK_noedge_posedge,
          HoldHigh                => thold_AD9_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_CLK_posedge_posedge,
          TimingData              => Tmkr_RST_CLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_CLK_posedge_posedge,
          Removal                 => thold_RST_CLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CEN_CLK_posedge or Tviol_WR_CLK_posedge or 
                 Tviol_CS0_CLK_posedge or Tviol_CS1_CLK_posedge or 
                 Tviol_AD0_CLK_posedge or Tviol_AD1_CLK_posedge or 
                 Tviol_AD2_CLK_posedge or Tviol_AD3_CLK_posedge or 
                 Tviol_AD4_CLK_posedge or Tviol_AD5_CLK_posedge or 
                 Tviol_AD6_CLK_posedge or Tviol_AD7_CLK_posedge or 
                 Tviol_AD8_CLK_posedge or Tviol_AD9_CLK_posedge or 
                 Tviol_DI0_CLK_posedge  or Tviol_DI1_CLK_posedge or
                 Tviol_DI2_CLK_posedge  or Tviol_DI3_CLK_posedge or
                 Tviol_DI4_CLK_posedge  or Tviol_DI5_CLK_posedge or
                 Tviol_DI6_CLK_posedge  or Tviol_DI7_CLK_posedge or
                 Tviol_DI8_CLK_posedge  or Tviol_DI9_CLK_posedge or
                 Tviol_DI10_CLK_posedge  or Tviol_DI11_CLK_posedge or
                 Tviol_DI12_CLK_posedge  or Tviol_DI13_CLK_posedge or
                 Tviol_DI14_CLK_posedge  or Tviol_DI15_CLK_posedge or
                 Pviol_CLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on CEN_ipd, CLK_ipd, WR_ipd, CS,  RST_ipd, DI, AD;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_DO8  : process
      variable DO8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO8_zd := DO(8);

    VitalPathDelay01 (
      OutSignal => DO8,
      GlitchData => O_GlitchData,
      OutSignalName => "DO8",
      OutTemp => DO8_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(8);
      end process;

    VitalBehavior_DO9  : process
      variable DO9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO9_zd := DO(9);

    VitalPathDelay01 (
      OutSignal => DO9,
      GlitchData => O_GlitchData,
      OutSignalName => "DO9",
      OutTemp => DO9_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(9);
      end process;

    VitalBehavior_DO10  : process
      variable DO10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO10_zd := DO(10);

    VitalPathDelay01 (
      OutSignal => DO10,
      GlitchData => O_GlitchData,
      OutSignalName => "DO10",
      OutTemp => DO10_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(10);
      end process;

    VitalBehavior_DO11  : process
      variable DO11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO11_zd := DO(11);

    VitalPathDelay01 (
      OutSignal => DO11,
      GlitchData => O_GlitchData,
      OutSignalName => "DO11",
      OutTemp => DO11_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(11);
      end process;

    VitalBehavior_DO12  : process
      variable DO12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO12_zd := DO(12);

    VitalPathDelay01 (
      OutSignal => DO12,
      GlitchData => O_GlitchData,
      OutSignalName => "DO12",
      OutTemp => DO12_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(12);
      end process;

    VitalBehavior_DO13  : process
      variable DO13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO13_zd := DO(13);

    VitalPathDelay01 (
      OutSignal => DO13,
      GlitchData => O_GlitchData,
      OutSignalName => "DO13",
      OutTemp => DO13_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(13);
      end process;

    VitalBehavior_DO14  : process
      variable DO14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO14_zd := DO(14);

    VitalPathDelay01 (
      OutSignal => DO14,
      GlitchData => O_GlitchData,
      OutSignalName => "DO14",
      OutTemp => DO14_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(14);
      end process;

    VitalBehavior_DO15  : process
      variable DO15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO15_zd := DO(15);

    VitalPathDelay01 (
      OutSignal => DO15,
      GlitchData => O_GlitchData,
      OutSignalName => "DO15",
      OutTemp => DO15_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(15);
      end process;



	SPRAM_INST: SC_SPRAM_16K
	   generic map (
		ADDR_WIDTH    => 10,
		DATA_WIDTH    => 16,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CEN => CEN_ipd,
		CLK => CLK_ipd,
		WR  => WR_ipd,
		CS  => CS,
		RST => RST_ipd,
		DI  => DI,
		AD  => AD,
		DO  => DO
		);


end VITAL;

configuration CFG_RAMB16K_X16_VITAL of RAMB16K_X16 is
   for VITAL
   end for;
end CFG_RAMB16K_X16_VITAL;



----- CELL RAMB16K_X32 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16K_X32 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_CLK_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO10                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO11                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO12                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO13                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO14                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO15                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO16                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO17                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO18                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO19                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO20                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO21                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO22                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO23                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO24                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO25                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO26                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO27                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO28                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO29                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO30                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO31                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO10                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO11                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO12                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO13                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO14                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO15                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO26                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO27                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO28                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO29                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO30                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO31                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WR_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_CEN_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CEN_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI4_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI5_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI6_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI7_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI8_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI8_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI9_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI9_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI10_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI10_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI11_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI11_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI12_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI12_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI13_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI13_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI14_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI14_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI15_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI15_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI16_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI16_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI17_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI17_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI18_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI18_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI19_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI19_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI20_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI20_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI21_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI21_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI22_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI22_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI23_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI23_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI24_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI24_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI25_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI25_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI26_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI26_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI27_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI27_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI28_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI28_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI29_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI29_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI30_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI30_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI31_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI31_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;


      tsetup_AD0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD4_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD4_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD5_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD5_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD6_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD6_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD7_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD7_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD8_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD8_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_CLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_CLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLK_posedge                  :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                  :	VitalDelayType   := 2.0 ns;
      tipd_CEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI8                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI9                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI10                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI11                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI12                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI13                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI14                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI15                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI16                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI17                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI18                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI19                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI20                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI21                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI22                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI23                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI24                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI25                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI26                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI27                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI28                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI29                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI30                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI31                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_AD0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD8                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD9                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CEN                            :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      WR                             :	in    STD_ULOGIC;
      CS0                            :	in    STD_ULOGIC;
      CS1                            :	in    STD_ULOGIC;
      RST                            :	in    STD_ULOGIC;
      DI0                            :	in    STD_ULOGIC;
      DI1                            :	in    STD_ULOGIC;
      DI2                            :	in    STD_ULOGIC;
      DI3                            :	in    STD_ULOGIC;
      DI4                            :	in    STD_ULOGIC;
      DI5                            :	in    STD_ULOGIC;
      DI6                            :	in    STD_ULOGIC;
      DI7                            :	in    STD_ULOGIC;
      DI8                            :	in    STD_ULOGIC;
      DI9                            :	in    STD_ULOGIC;
      DI10                           :	in    STD_ULOGIC;
      DI11                           :	in    STD_ULOGIC;
      DI12                           :	in    STD_ULOGIC;
      DI13                           :	in    STD_ULOGIC;
      DI14                           :	in    STD_ULOGIC;
      DI15                           :	in    STD_ULOGIC;
      DI16                            :	in    STD_ULOGIC;
      DI17                            :	in    STD_ULOGIC;
      DI18                            :	in    STD_ULOGIC;
      DI19                            :	in    STD_ULOGIC;
      DI20                            :	in    STD_ULOGIC;
      DI21                            :	in    STD_ULOGIC;
      DI22                            :	in    STD_ULOGIC;
      DI23                            :	in    STD_ULOGIC;
      DI24                            :	in    STD_ULOGIC;
      DI25                            :	in    STD_ULOGIC;
      DI26                           :	in    STD_ULOGIC;
      DI27                           :	in    STD_ULOGIC;
      DI28                           :	in    STD_ULOGIC;
      DI29                           :	in    STD_ULOGIC;
      DI30                           :	in    STD_ULOGIC;
      DI31                           :	in    STD_ULOGIC;
      AD0                            :	in    STD_ULOGIC;
      AD1                            :	in    STD_ULOGIC;
      AD2                            :	in    STD_ULOGIC;
      AD3                            :	in    STD_ULOGIC;
      AD4                            :	in    STD_ULOGIC;
      AD5                            :	in    STD_ULOGIC;
      AD6                            :	in    STD_ULOGIC;
      AD7                            :	in    STD_ULOGIC;
      AD8                            :	in    STD_ULOGIC;
      DO0                            :	out   STD_ULOGIC;
      DO1                            :	out   STD_ULOGIC;
      DO2                            :	out   STD_ULOGIC;
      DO3                            :	out   STD_ULOGIC;
      DO4                            :	out   STD_ULOGIC;
      DO5                            :	out   STD_ULOGIC;
      DO6                            :	out   STD_ULOGIC;
      DO7                            :	out   STD_ULOGIC;
      DO8                            :	out   STD_ULOGIC;
      DO9                            :	out   STD_ULOGIC;
      DO10                            :	out   STD_ULOGIC;
      DO11                            :	out   STD_ULOGIC;
      DO12                            :	out   STD_ULOGIC;
      DO13                            :	out   STD_ULOGIC;
      DO14                            :	out   STD_ULOGIC;
      DO15                            :	out   STD_ULOGIC;
      DO16                            :	out   STD_ULOGIC;
      DO17                            :	out   STD_ULOGIC;
      DO18                            :	out   STD_ULOGIC;
      DO19                            :	out   STD_ULOGIC;
      DO20                            :	out   STD_ULOGIC;
      DO21                            :	out   STD_ULOGIC;
      DO22                            :	out   STD_ULOGIC;
      DO23                            :	out   STD_ULOGIC;
      DO24                            :	out   STD_ULOGIC;
      DO25                            :	out   STD_ULOGIC;
      DO26                            :	out   STD_ULOGIC;
      DO27                            :	out   STD_ULOGIC;
      DO28                            :	out   STD_ULOGIC;
      DO29                            :	out   STD_ULOGIC;
      DO30                            :	out   STD_ULOGIC;
      DO31                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16K_X32 : entity is FALSE;
end RAMB16K_X32;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_X32 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_SPRAM_16K
	   generic (
		ADDR_WIDTH    : integer := 9;
		DATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CEN : in  STD_LOGIC ;
		CLK : in  STD_LOGIC ;
		WR   : in  STD_LOGIC ;
		CS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		DI   : in  STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0);
		AD  : in  STD_LOGIC_VECTOR (ADDR_WIDTH -1 downto 0);
		DO   : out STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0)
		);
	end component ;

      signal CEN_ipd      : std_ulogic := 'X';
      signal CLK_ipd      : std_ulogic := 'X';
      signal WR_ipd       : std_ulogic := 'X';
      signal CS0_ipd      : std_ulogic := 'X';
      signal CS1_ipd      : std_ulogic := 'X';
      signal RST_ipd      : std_ulogic := 'X';

      signal DI0_ipd      : std_ulogic := 'X';
      signal DI1_ipd      : std_ulogic := 'X';
      signal DI2_ipd      : std_ulogic := 'X';
      signal DI3_ipd      : std_ulogic := 'X';
      signal DI4_ipd      : std_ulogic := 'X';
      signal DI5_ipd      : std_ulogic := 'X';
      signal DI6_ipd      : std_ulogic := 'X';
      signal DI7_ipd      : std_ulogic := 'X';
      signal DI8_ipd      : std_ulogic := 'X';
      signal DI9_ipd      : std_ulogic := 'X';
      signal DI10_ipd      : std_ulogic := 'X';
      signal DI11_ipd      : std_ulogic := 'X';
      signal DI12_ipd      : std_ulogic := 'X';
      signal DI13_ipd      : std_ulogic := 'X';
      signal DI14_ipd      : std_ulogic := 'X';
      signal DI15_ipd      : std_ulogic := 'X';
      signal DI16_ipd      : std_ulogic := 'X';
      signal DI17_ipd      : std_ulogic := 'X';
      signal DI18_ipd      : std_ulogic := 'X';
      signal DI19_ipd      : std_ulogic := 'X';
      signal DI20_ipd      : std_ulogic := 'X';
      signal DI21_ipd      : std_ulogic := 'X';
      signal DI22_ipd      : std_ulogic := 'X';
      signal DI23_ipd      : std_ulogic := 'X';
      signal DI24_ipd      : std_ulogic := 'X';
      signal DI25_ipd      : std_ulogic := 'X';
      signal DI26_ipd      : std_ulogic := 'X';
      signal DI27_ipd      : std_ulogic := 'X';
      signal DI28_ipd      : std_ulogic := 'X';
      signal DI29_ipd      : std_ulogic := 'X';
      signal DI30_ipd      : std_ulogic := 'X';
      signal DI31_ipd      : std_ulogic := 'X';

      signal AD0_ipd      : std_ulogic := 'X';
      signal AD1_ipd      : std_ulogic := 'X';
      signal AD2_ipd      : std_ulogic := 'X';
      signal AD3_ipd      : std_ulogic := 'X';
      signal AD4_ipd      : std_ulogic := 'X';
      signal AD5_ipd      : std_ulogic := 'X';
      signal AD6_ipd      : std_ulogic := 'X';
      signal AD7_ipd      : std_ulogic := 'X';
      signal AD8_ipd      : std_ulogic := 'X';

	signal CS : std_logic_vector (1 downto 0);
	signal DI  : std_logic_vector (31 downto 0);
 	signal AD : std_logic_vector (8 downto 0);
	signal DO  : std_logic_vector (31 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	CS <= CS1_ipd & CS0_ipd;
	DI <= DI31_ipd & DI30_ipd & DI29_ipd & DI28_ipd & DI27_ipd & DI26_ipd & DI25_ipd & DI24_ipd & DI23_ipd & DI22_ipd & DI21_ipd & DI20_ipd & DI19_ipd & DI18_ipd & DI17_ipd & DI16_ipd & DI15_ipd & DI14_ipd & DI13_ipd & DI12_ipd & DI11_ipd & DI10_ipd & DI9_ipd & DI8_ipd & DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd;
	AD <= AD8_ipd & AD7_ipd & AD6_ipd & AD5_ipd & AD4_ipd & AD3_ipd & AD2_ipd & AD1_ipd & AD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CEN_ipd, CEN, tipd_CEN);
        VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        VitalWireDelay (WR_ipd, WR, tipd_WR);
        VitalWireDelay (CS0_ipd, CS0, tipd_CS0);
        VitalWireDelay (CS1_ipd, CS1, tipd_CS1);
        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);
        VitalWireDelay (DI8_ipd, DI8, tipd_DI8);
        VitalWireDelay (DI9_ipd, DI9, tipd_DI9);
        VitalWireDelay (DI10_ipd, DI10, tipd_DI10);
        VitalWireDelay (DI11_ipd, DI11, tipd_DI11);
        VitalWireDelay (DI12_ipd, DI12, tipd_DI12);
        VitalWireDelay (DI13_ipd, DI13, tipd_DI13);
        VitalWireDelay (DI14_ipd, DI14, tipd_DI14);
        VitalWireDelay (DI15_ipd, DI15, tipd_DI15);
        VitalWireDelay (DI16_ipd, DI16, tipd_DI16);
        VitalWireDelay (DI17_ipd, DI17, tipd_DI17);
        VitalWireDelay (DI18_ipd, DI18, tipd_DI18);
        VitalWireDelay (DI19_ipd, DI19, tipd_DI19);
        VitalWireDelay (DI20_ipd, DI20, tipd_DI20);
        VitalWireDelay (DI21_ipd, DI21, tipd_DI21);
        VitalWireDelay (DI22_ipd, DI22, tipd_DI22);
        VitalWireDelay (DI23_ipd, DI23, tipd_DI23);
        VitalWireDelay (DI24_ipd, DI24, tipd_DI24);
        VitalWireDelay (DI25_ipd, DI25, tipd_DI25);
        VitalWireDelay (DI26_ipd, DI26, tipd_DI26);
        VitalWireDelay (DI27_ipd, DI27, tipd_DI27);
        VitalWireDelay (DI28_ipd, DI28, tipd_DI28);
        VitalWireDelay (DI29_ipd, DI29, tipd_DI29);
        VitalWireDelay (DI30_ipd, DI30, tipd_DI30);
        VitalWireDelay (DI31_ipd, DI31, tipd_DI31);

        VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
        VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
        VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
        VitalWireDelay (AD3_ipd, AD3, tipd_AD3);
        VitalWireDelay (AD4_ipd, AD4, tipd_AD4);
        VitalWireDelay (AD5_ipd, AD5, tipd_AD5);
        VitalWireDelay (AD6_ipd, AD6, tipd_AD6);
        VitalWireDelay (AD7_ipd, AD7, tipd_AD7);
        VitalWireDelay (AD8_ipd, AD8, tipd_AD8);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CEN_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_WR_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_CS0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_CS1_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_DI0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI3_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI4_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI5_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI6_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI7_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI8_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI9_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI10_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI11_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI12_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI13_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI14_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI15_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI16_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI17_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI18_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI19_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI20_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI21_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI22_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI23_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI24_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI25_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI26_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI27_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI28_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI29_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI30_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI31_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_AD0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD3_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD4_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD5_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD6_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD7_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD8_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_CLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CEN_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI8_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI9_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI10_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI11_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI12_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI13_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI14_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI15_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI16_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI17_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI18_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI19_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI20_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI21_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI22_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI23_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI24_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI25_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI26_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI27_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI28_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI29_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI30_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI31_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_AD0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD4_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD5_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD6_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD7_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD8_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_CLK_posedge_posedge  : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLK       : std_ulogic := '0';
        variable PInfo_CLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable DO8_zd          : std_ulogic := 'X';
        variable DO9_zd          : std_ulogic := 'X';
        variable DO10_zd          : std_ulogic := 'X';
        variable DO11_zd          : std_ulogic := 'X';
        variable DO12_zd          : std_ulogic := 'X';
        variable DO13_zd          : std_ulogic := 'X';
        variable DO14_zd          : std_ulogic := 'X';
        variable DO15_zd          : std_ulogic := 'X';
        variable DO16_zd          : std_ulogic := 'X';
        variable DO17_zd          : std_ulogic := 'X';
        variable DO18_zd          : std_ulogic := 'X';
        variable DO19_zd          : std_ulogic := 'X';
        variable DO20_zd          : std_ulogic := 'X';
        variable DO21_zd          : std_ulogic := 'X';
        variable DO22_zd          : std_ulogic := 'X';
        variable DO23_zd          : std_ulogic := 'X';
        variable DO24_zd          : std_ulogic := 'X';
        variable DO25_zd          : std_ulogic := 'X';
        variable DO26_zd          : std_ulogic := 'X';
        variable DO27_zd          : std_ulogic := 'X';
        variable DO28_zd          : std_ulogic := 'X';
        variable DO29_zd          : std_ulogic := 'X';
        variable DO30_zd          : std_ulogic := 'X';
        variable DO31_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CEN_CLK_posedge,
          TimingData              => Tmkr_CEN_CLK_posedge,
          TestSignal              => CEN_ipd,
          TestSignalName          => "CEN",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CEN_CLK_noedge_posedge,
          SetupLow                => tsetup_CEN_CLK_noedge_posedge,
          HoldLow                 => thold_CEN_CLK_noedge_posedge,
          HoldHigh                => thold_CEN_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_CLK_posedge,
          TimingData              => Tmkr_WR_CLK_posedge,
          TestSignal              => WR_ipd,
          TestSignalName          => "WR",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_CLK_noedge_posedge,
          HoldLow                 => thold_WR_CLK_noedge_posedge,
          HoldHigh                => thold_WR_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS0_CLK_posedge,
          TimingData              => Tmkr_CS0_CLK_posedge,
          TestSignal              => CS0_ipd,
          TestSignalName          => "CS0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS0_CLK_noedge_posedge,
          SetupLow                => tsetup_CS0_CLK_noedge_posedge,
          HoldLow                 => thold_CS0_CLK_noedge_posedge,
          HoldHigh                => thold_CS0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS1_CLK_posedge,
          TimingData              => Tmkr_CS1_CLK_posedge,
          TestSignal              => CS1_ipd,
          TestSignalName          => "CS1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS1_CLK_noedge_posedge,
          SetupLow                => tsetup_CS1_CLK_noedge_posedge,
          HoldLow                 => thold_CS1_CLK_noedge_posedge,
          HoldHigh                => thold_CS1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_CLK_posedge,
          TimingData              => Tmkr_DI0_CLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_CLK_noedge_posedge,
          SetupLow                => tsetup_DI0_CLK_noedge_posedge,
          HoldLow                 => thold_DI0_CLK_noedge_posedge,
          HoldHigh                => thold_DI0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_CLK_posedge,
          TimingData              => Tmkr_DI1_CLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_CLK_noedge_posedge,
          SetupLow                => tsetup_DI1_CLK_noedge_posedge,
          HoldLow                 => thold_DI1_CLK_noedge_posedge,
          HoldHigh                => thold_DI1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_CLK_posedge,
          TimingData              => Tmkr_DI2_CLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_CLK_noedge_posedge,
          SetupLow                => tsetup_DI2_CLK_noedge_posedge,
          HoldLow                 => thold_DI2_CLK_noedge_posedge,
          HoldHigh                => thold_DI2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_CLK_posedge,
          TimingData              => Tmkr_DI3_CLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_CLK_noedge_posedge,
          SetupLow                => tsetup_DI3_CLK_noedge_posedge,
          HoldLow                 => thold_DI3_CLK_noedge_posedge,
          HoldHigh                => thold_DI3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_CLK_posedge,
          TimingData              => Tmkr_DI4_CLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_CLK_noedge_posedge,
          SetupLow                => tsetup_DI4_CLK_noedge_posedge,
          HoldLow                 => thold_DI4_CLK_noedge_posedge,
          HoldHigh                => thold_DI4_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_CLK_posedge,
          TimingData              => Tmkr_DI5_CLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_CLK_noedge_posedge,
          SetupLow                => tsetup_DI5_CLK_noedge_posedge,
          HoldLow                 => thold_DI5_CLK_noedge_posedge,
          HoldHigh                => thold_DI5_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_CLK_posedge,
          TimingData              => Tmkr_DI6_CLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_CLK_noedge_posedge,
          SetupLow                => tsetup_DI6_CLK_noedge_posedge,
          HoldLow                 => thold_DI6_CLK_noedge_posedge,
          HoldHigh                => thold_DI6_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_CLK_posedge,
          TimingData              => Tmkr_DI7_CLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_CLK_noedge_posedge,
          SetupLow                => tsetup_DI7_CLK_noedge_posedge,
          HoldLow                 => thold_DI7_CLK_noedge_posedge,
          HoldHigh                => thold_DI7_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI8_CLK_posedge,
          TimingData              => Tmkr_DI8_CLK_posedge,
          TestSignal              => DI8_ipd,
          TestSignalName          => "DI8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI8_CLK_noedge_posedge,
          SetupLow                => tsetup_DI8_CLK_noedge_posedge,
          HoldLow                 => thold_DI8_CLK_noedge_posedge,
          HoldHigh                => thold_DI8_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI9_CLK_posedge,
          TimingData              => Tmkr_DI9_CLK_posedge,
          TestSignal              => DI9_ipd,
          TestSignalName          => "DI9",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI9_CLK_noedge_posedge,
          SetupLow                => tsetup_DI9_CLK_noedge_posedge,
          HoldLow                 => thold_DI9_CLK_noedge_posedge,
          HoldHigh                => thold_DI9_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI10_CLK_posedge,
          TimingData              => Tmkr_DI10_CLK_posedge,
          TestSignal              => DI10_ipd,
          TestSignalName          => "DI10",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI10_CLK_noedge_posedge,
          SetupLow                => tsetup_DI10_CLK_noedge_posedge,
          HoldLow                 => thold_DI10_CLK_noedge_posedge,
          HoldHigh                => thold_DI10_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI11_CLK_posedge,
          TimingData              => Tmkr_DI11_CLK_posedge,
          TestSignal              => DI11_ipd,
          TestSignalName          => "DI11",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI11_CLK_noedge_posedge,
          SetupLow                => tsetup_DI11_CLK_noedge_posedge,
          HoldLow                 => thold_DI11_CLK_noedge_posedge,
          HoldHigh                => thold_DI11_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI12_CLK_posedge,
          TimingData              => Tmkr_DI12_CLK_posedge,
          TestSignal              => DI12_ipd,
          TestSignalName          => "DI12",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI12_CLK_noedge_posedge,
          SetupLow                => tsetup_DI12_CLK_noedge_posedge,
          HoldLow                 => thold_DI12_CLK_noedge_posedge,
          HoldHigh                => thold_DI12_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI13_CLK_posedge,
          TimingData              => Tmkr_DI13_CLK_posedge,
          TestSignal              => DI13_ipd,
          TestSignalName          => "DI13",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI13_CLK_noedge_posedge,
          SetupLow                => tsetup_DI13_CLK_noedge_posedge,
          HoldLow                 => thold_DI13_CLK_noedge_posedge,
          HoldHigh                => thold_DI13_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI14_CLK_posedge,
          TimingData              => Tmkr_DI14_CLK_posedge,
          TestSignal              => DI14_ipd,
          TestSignalName          => "DI14",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI14_CLK_noedge_posedge,
          SetupLow                => tsetup_DI14_CLK_noedge_posedge,
          HoldLow                 => thold_DI14_CLK_noedge_posedge,
          HoldHigh                => thold_DI14_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI15_CLK_posedge,
          TimingData              => Tmkr_DI15_CLK_posedge,
          TestSignal              => DI15_ipd,
          TestSignalName          => "DI15",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI15_CLK_noedge_posedge,
          SetupLow                => tsetup_DI15_CLK_noedge_posedge,
          HoldLow                 => thold_DI15_CLK_noedge_posedge,
          HoldHigh                => thold_DI15_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI16_CLK_posedge,
          TimingData              => Tmkr_DI16_CLK_posedge,
          TestSignal              => DI16_ipd,
          TestSignalName          => "DI16",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI16_CLK_noedge_posedge,
          SetupLow                => tsetup_DI16_CLK_noedge_posedge,
          HoldLow                 => thold_DI16_CLK_noedge_posedge,
          HoldHigh                => thold_DI16_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI17_CLK_posedge,
          TimingData              => Tmkr_DI17_CLK_posedge,
          TestSignal              => DI17_ipd,
          TestSignalName          => "DI17",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI17_CLK_noedge_posedge,
          SetupLow                => tsetup_DI17_CLK_noedge_posedge,
          HoldLow                 => thold_DI17_CLK_noedge_posedge,
          HoldHigh                => thold_DI17_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI18_CLK_posedge,
          TimingData              => Tmkr_DI18_CLK_posedge,
          TestSignal              => DI18_ipd,
          TestSignalName          => "DI18",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI18_CLK_noedge_posedge,
          SetupLow                => tsetup_DI18_CLK_noedge_posedge,
          HoldLow                 => thold_DI18_CLK_noedge_posedge,
          HoldHigh                => thold_DI18_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI19_CLK_posedge,
          TimingData              => Tmkr_DI19_CLK_posedge,
          TestSignal              => DI19_ipd,
          TestSignalName          => "DI19",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI19_CLK_noedge_posedge,
          SetupLow                => tsetup_DI19_CLK_noedge_posedge,
          HoldLow                 => thold_DI19_CLK_noedge_posedge,
          HoldHigh                => thold_DI19_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI20_CLK_posedge,
          TimingData              => Tmkr_DI20_CLK_posedge,
          TestSignal              => DI20_ipd,
          TestSignalName          => "DI20",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI20_CLK_noedge_posedge,
          SetupLow                => tsetup_DI20_CLK_noedge_posedge,
          HoldLow                 => thold_DI20_CLK_noedge_posedge,
          HoldHigh                => thold_DI20_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI21_CLK_posedge,
          TimingData              => Tmkr_DI21_CLK_posedge,
          TestSignal              => DI21_ipd,
          TestSignalName          => "DI21",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI21_CLK_noedge_posedge,
          SetupLow                => tsetup_DI21_CLK_noedge_posedge,
          HoldLow                 => thold_DI21_CLK_noedge_posedge,
          HoldHigh                => thold_DI21_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI22_CLK_posedge,
          TimingData              => Tmkr_DI22_CLK_posedge,
          TestSignal              => DI22_ipd,
          TestSignalName          => "DI22",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI22_CLK_noedge_posedge,
          SetupLow                => tsetup_DI22_CLK_noedge_posedge,
          HoldLow                 => thold_DI22_CLK_noedge_posedge,
          HoldHigh                => thold_DI22_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI23_CLK_posedge,
          TimingData              => Tmkr_DI23_CLK_posedge,
          TestSignal              => DI23_ipd,
          TestSignalName          => "DI23",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI23_CLK_noedge_posedge,
          SetupLow                => tsetup_DI23_CLK_noedge_posedge,
          HoldLow                 => thold_DI23_CLK_noedge_posedge,
          HoldHigh                => thold_DI23_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI24_CLK_posedge,
          TimingData              => Tmkr_DI24_CLK_posedge,
          TestSignal              => DI24_ipd,
          TestSignalName          => "DI24",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI24_CLK_noedge_posedge,
          SetupLow                => tsetup_DI24_CLK_noedge_posedge,
          HoldLow                 => thold_DI24_CLK_noedge_posedge,
          HoldHigh                => thold_DI24_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI25_CLK_posedge,
          TimingData              => Tmkr_DI25_CLK_posedge,
          TestSignal              => DI25_ipd,
          TestSignalName          => "DI25",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI25_CLK_noedge_posedge,
          SetupLow                => tsetup_DI25_CLK_noedge_posedge,
          HoldLow                 => thold_DI25_CLK_noedge_posedge,
          HoldHigh                => thold_DI25_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI26_CLK_posedge,
          TimingData              => Tmkr_DI26_CLK_posedge,
          TestSignal              => DI26_ipd,
          TestSignalName          => "DI26",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI26_CLK_noedge_posedge,
          SetupLow                => tsetup_DI26_CLK_noedge_posedge,
          HoldLow                 => thold_DI26_CLK_noedge_posedge,
          HoldHigh                => thold_DI26_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI27_CLK_posedge,
          TimingData              => Tmkr_DI27_CLK_posedge,
          TestSignal              => DI27_ipd,
          TestSignalName          => "DI27",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI27_CLK_noedge_posedge,
          SetupLow                => tsetup_DI27_CLK_noedge_posedge,
          HoldLow                 => thold_DI27_CLK_noedge_posedge,
          HoldHigh                => thold_DI27_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI28_CLK_posedge,
          TimingData              => Tmkr_DI28_CLK_posedge,
          TestSignal              => DI28_ipd,
          TestSignalName          => "DI28",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI28_CLK_noedge_posedge,
          SetupLow                => tsetup_DI28_CLK_noedge_posedge,
          HoldLow                 => thold_DI28_CLK_noedge_posedge,
          HoldHigh                => thold_DI28_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI29_CLK_posedge,
          TimingData              => Tmkr_DI29_CLK_posedge,
          TestSignal              => DI29_ipd,
          TestSignalName          => "DI13",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI29_CLK_noedge_posedge,
          SetupLow                => tsetup_DI29_CLK_noedge_posedge,
          HoldLow                 => thold_DI29_CLK_noedge_posedge,
          HoldHigh                => thold_DI29_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI30_CLK_posedge,
          TimingData              => Tmkr_DI30_CLK_posedge,
          TestSignal              => DI30_ipd,
          TestSignalName          => "DI30",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI30_CLK_noedge_posedge,
          SetupLow                => tsetup_DI30_CLK_noedge_posedge,
          HoldLow                 => thold_DI30_CLK_noedge_posedge,
          HoldHigh                => thold_DI30_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI31_CLK_posedge,
          TimingData              => Tmkr_DI31_CLK_posedge,
          TestSignal              => DI31_ipd,
          TestSignalName          => "DI31",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI31_CLK_noedge_posedge,
          SetupLow                => tsetup_DI31_CLK_noedge_posedge,
          HoldLow                 => thold_DI31_CLK_noedge_posedge,
          HoldHigh                => thold_DI31_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_CLK_posedge,
          TimingData              => Tmkr_AD0_CLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_CLK_noedge_posedge,
          SetupLow                => tsetup_AD0_CLK_noedge_posedge,
          HoldLow                 => thold_AD0_CLK_noedge_posedge,
          HoldHigh                => thold_AD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_CLK_posedge,
          TimingData              => Tmkr_AD1_CLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_CLK_noedge_posedge,
          SetupLow                => tsetup_AD1_CLK_noedge_posedge,
          HoldLow                 => thold_AD1_CLK_noedge_posedge,
          HoldHigh                => thold_AD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_CLK_posedge,
          TimingData              => Tmkr_AD2_CLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_CLK_noedge_posedge,
          SetupLow                => tsetup_AD2_CLK_noedge_posedge,
          HoldLow                 => thold_AD2_CLK_noedge_posedge,
          HoldHigh                => thold_AD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_CLK_posedge,
          TimingData              => Tmkr_AD3_CLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_CLK_noedge_posedge,
          SetupLow                => tsetup_AD3_CLK_noedge_posedge,
          HoldLow                 => thold_AD3_CLK_noedge_posedge,
          HoldHigh                => thold_AD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD4_CLK_posedge,
          TimingData              => Tmkr_AD4_CLK_posedge,
          TestSignal              => AD4_ipd,
          TestSignalName          => "AD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD4_CLK_noedge_posedge,
          SetupLow                => tsetup_AD4_CLK_noedge_posedge,
          HoldLow                 => thold_AD4_CLK_noedge_posedge,
          HoldHigh                => thold_AD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD5_CLK_posedge,
          TimingData              => Tmkr_AD5_CLK_posedge,
          TestSignal              => AD5_ipd,
          TestSignalName          => "AD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD5_CLK_noedge_posedge,
          SetupLow                => tsetup_AD5_CLK_noedge_posedge,
          HoldLow                 => thold_AD5_CLK_noedge_posedge,
          HoldHigh                => thold_AD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD6_CLK_posedge,
          TimingData              => Tmkr_AD6_CLK_posedge,
          TestSignal              => AD6_ipd,
          TestSignalName          => "AD6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD6_CLK_noedge_posedge,
          SetupLow                => tsetup_AD6_CLK_noedge_posedge,
          HoldLow                 => thold_AD6_CLK_noedge_posedge,
          HoldHigh                => thold_AD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD7_CLK_posedge,
          TimingData              => Tmkr_AD7_CLK_posedge,
          TestSignal              => AD7_ipd,
          TestSignalName          => "AD7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD7_CLK_noedge_posedge,
          SetupLow                => tsetup_AD7_CLK_noedge_posedge,
          HoldLow                 => thold_AD7_CLK_noedge_posedge,
          HoldHigh                => thold_AD7_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD8_CLK_posedge,
          TimingData              => Tmkr_AD8_CLK_posedge,
          TestSignal              => AD8_ipd,
          TestSignalName          => "AD8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD8_CLK_noedge_posedge,
          SetupLow                => tsetup_AD8_CLK_noedge_posedge,
          HoldLow                 => thold_AD8_CLK_noedge_posedge,
          HoldHigh                => thold_AD8_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_CLK_posedge_posedge,
          TimingData              => Tmkr_RST_CLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_CLK_posedge_posedge,
          Removal                 => thold_RST_CLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16K_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CEN_CLK_posedge or Tviol_WR_CLK_posedge or 
                 Tviol_CS0_CLK_posedge or Tviol_CS1_CLK_posedge or 
                 Tviol_AD0_CLK_posedge or Tviol_AD1_CLK_posedge or 
                 Tviol_AD2_CLK_posedge or Tviol_AD3_CLK_posedge or 
                 Tviol_AD4_CLK_posedge or Tviol_AD5_CLK_posedge or 
                 Tviol_AD6_CLK_posedge or Tviol_AD7_CLK_posedge or 
                 Tviol_AD8_CLK_posedge or 
                 Tviol_DI0_CLK_posedge  or Tviol_DI1_CLK_posedge or
                 Tviol_DI2_CLK_posedge  or Tviol_DI3_CLK_posedge or
                 Tviol_DI4_CLK_posedge  or Tviol_DI5_CLK_posedge or
                 Tviol_DI6_CLK_posedge  or Tviol_DI7_CLK_posedge or
                 Tviol_DI8_CLK_posedge  or Tviol_DI9_CLK_posedge or
                 Tviol_DI10_CLK_posedge  or Tviol_DI11_CLK_posedge or
                 Tviol_DI12_CLK_posedge  or Tviol_DI13_CLK_posedge or
                 Tviol_DI14_CLK_posedge  or Tviol_DI15_CLK_posedge or
                 Tviol_DI16_CLK_posedge  or Tviol_DI17_CLK_posedge or
                 Tviol_DI18_CLK_posedge  or Tviol_DI19_CLK_posedge or
                 Tviol_DI20_CLK_posedge  or Tviol_DI21_CLK_posedge or
                 Tviol_DI22_CLK_posedge  or Tviol_DI23_CLK_posedge or
                 Tviol_DI24_CLK_posedge  or Tviol_DI25_CLK_posedge or
                 Tviol_DI26_CLK_posedge  or Tviol_DI27_CLK_posedge or
                 Tviol_DI28_CLK_posedge  or Tviol_DI29_CLK_posedge or
                 Tviol_DI30_CLK_posedge  or Tviol_DI31_CLK_posedge or
                 Pviol_CLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on CEN_ipd, CLK_ipd, WR_ipd, CS,  RST_ipd, DI, AD;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_DO8  : process
      variable DO8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO8_zd := DO(8);

    VitalPathDelay01 (
      OutSignal => DO8,
      GlitchData => O_GlitchData,
      OutSignalName => "DO8",
      OutTemp => DO8_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(8);
      end process;

    VitalBehavior_DO9  : process
      variable DO9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO9_zd := DO(9);

    VitalPathDelay01 (
      OutSignal => DO9,
      GlitchData => O_GlitchData,
      OutSignalName => "DO9",
      OutTemp => DO9_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(9);
      end process;

    VitalBehavior_DO10  : process
      variable DO10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO10_zd := DO(10);

    VitalPathDelay01 (
      OutSignal => DO10,
      GlitchData => O_GlitchData,
      OutSignalName => "DO10",
      OutTemp => DO10_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(10);
      end process;

    VitalBehavior_DO11  : process
      variable DO11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO11_zd := DO(11);

    VitalPathDelay01 (
      OutSignal => DO11,
      GlitchData => O_GlitchData,
      OutSignalName => "DO11",
      OutTemp => DO11_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(11);
      end process;

    VitalBehavior_DO12  : process
      variable DO12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO12_zd := DO(12);

    VitalPathDelay01 (
      OutSignal => DO12,
      GlitchData => O_GlitchData,
      OutSignalName => "DO12",
      OutTemp => DO12_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(12);
      end process;

    VitalBehavior_DO13  : process
      variable DO13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO13_zd := DO(13);

    VitalPathDelay01 (
      OutSignal => DO13,
      GlitchData => O_GlitchData,
      OutSignalName => "DO13",
      OutTemp => DO13_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(13);
      end process;

    VitalBehavior_DO14  : process
      variable DO14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO14_zd := DO(14);

    VitalPathDelay01 (
      OutSignal => DO14,
      GlitchData => O_GlitchData,
      OutSignalName => "DO14",
      OutTemp => DO14_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(14);
      end process;

    VitalBehavior_DO15  : process
      variable DO15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO15_zd := DO(15);

    VitalPathDelay01 (
      OutSignal => DO15,
      GlitchData => O_GlitchData,
      OutSignalName => "DO15",
      OutTemp => DO15_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(15);
      end process;

    VitalBehavior_DO16  : process
      variable DO16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO16_zd := DO(16);

    VitalPathDelay01 (
      OutSignal => DO16,
      GlitchData => O_GlitchData,
      OutSignalName => "DO16",
      OutTemp => DO16_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(16);
      end process;

    VitalBehavior_DO17  : process
      variable DO17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO17_zd := DO(17);

    VitalPathDelay01 (
      OutSignal => DO17,
      GlitchData => O_GlitchData,
      OutSignalName => "DO17",
      OutTemp => DO17_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(17);
      end process;

    VitalBehavior_DO18  : process
      variable DO18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO18_zd := DO(18);

    VitalPathDelay01 (
      OutSignal => DO18,
      GlitchData => O_GlitchData,
      OutSignalName => "DO18",
      OutTemp => DO18_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(18);
      end process;

    VitalBehavior_DO19  : process
      variable DO19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO19_zd := DO(19);

    VitalPathDelay01 (
      OutSignal => DO19,
      GlitchData => O_GlitchData,
      OutSignalName => "DO19",
      OutTemp => DO19_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(19);
      end process;

    VitalBehavior_DO20  : process
      variable DO20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO20_zd := DO(20);

    VitalPathDelay01 (
      OutSignal => DO20,
      GlitchData => O_GlitchData,
      OutSignalName => "DO20",
      OutTemp => DO20_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(20);
      end process;

    VitalBehavior_DO21  : process
      variable DO21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO21_zd := DO(21);

    VitalPathDelay01 (
      OutSignal => DO21,
      GlitchData => O_GlitchData,
      OutSignalName => "DO21",
      OutTemp => DO21_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(21);
      end process;

    VitalBehavior_DO22  : process
      variable DO22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO22_zd := DO(22);

    VitalPathDelay01 (
      OutSignal => DO22,
      GlitchData => O_GlitchData,
      OutSignalName => "DO22",
      OutTemp => DO22_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(22);
      end process;

    VitalBehavior_DO23  : process
      variable DO23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO23_zd := DO(23);

    VitalPathDelay01 (
      OutSignal => DO23,
      GlitchData => O_GlitchData,
      OutSignalName => "DO23",
      OutTemp => DO23_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(23);
      end process;

    VitalBehavior_DO24  : process
      variable DO24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO24_zd := DO(24);

    VitalPathDelay01 (
      OutSignal => DO24,
      GlitchData => O_GlitchData,
      OutSignalName => "DO24",
      OutTemp => DO24_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(24);
      end process;

    VitalBehavior_DO25  : process
      variable DO25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO25_zd := DO(25);

    VitalPathDelay01 (
      OutSignal => DO25,
      GlitchData => O_GlitchData,
      OutSignalName => "DO25",
      OutTemp => DO25_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(25);
      end process;

    VitalBehavior_DO26  : process
      variable DO26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO26_zd := DO(26);

    VitalPathDelay01 (
      OutSignal => DO26,
      GlitchData => O_GlitchData,
      OutSignalName => "DO26",
      OutTemp => DO26_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(26);
      end process;

    VitalBehavior_DO27  : process
      variable DO27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO27_zd := DO(27);

    VitalPathDelay01 (
      OutSignal => DO27,
      GlitchData => O_GlitchData,
      OutSignalName => "DO27",
      OutTemp => DO27_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(27);
      end process;

    VitalBehavior_DO28  : process
      variable DO28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO28_zd := DO(28);

    VitalPathDelay01 (
      OutSignal => DO28,
      GlitchData => O_GlitchData,
      OutSignalName => "DO28",
      OutTemp => DO28_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(28);
      end process;

    VitalBehavior_DO29  : process
      variable DO29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO29_zd := DO(29);

    VitalPathDelay01 (
      OutSignal => DO29,
      GlitchData => O_GlitchData,
      OutSignalName => "DO29",
      OutTemp => DO29_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(29);
      end process;

    VitalBehavior_DO30  : process
      variable DO30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO30_zd := DO(30);

    VitalPathDelay01 (
      OutSignal => DO30,
      GlitchData => O_GlitchData,
      OutSignalName => "DO30",
      OutTemp => DO30_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(30);
      end process;

    VitalBehavior_DO31  : process
      variable DO31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO31_zd := DO(31);

    VitalPathDelay01 (
      OutSignal => DO31,
      GlitchData => O_GlitchData,
      OutSignalName => "DO31",
      OutTemp => DO31_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_DO31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(31);
      end process;



	SPRAM_INST: SC_SPRAM_16K
	   generic map (
		ADDR_WIDTH    => 9,
		DATA_WIDTH    => 32,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CEN => CEN_ipd,
		CLK => CLK_ipd,
		WR  => WR_ipd,
		CS  => CS,
		RST => RST_ipd,
		DI  => DI,
		AD  => AD,
		DO  => DO
		);

end VITAL;

configuration CFG_RAMB16K_X32_VITAL of RAMB16K_X32 is
   for VITAL
   end for;
end CFG_RAMB16K_X32_VITAL;



----- CELL RAMB8K_X1_X1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB8K_X1_X1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "dummy";
      tpd_CLKA_DOA0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_CENA_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENA_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRA_CLKA_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRA_CLKA_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CENB_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENB_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRB_CLKB_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRB_CLKB_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_DIA0_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB0_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA2_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA3_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA4_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA4_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA5_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA5_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA6_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA6_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA7_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA7_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA8_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA8_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA9_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA9_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA10_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA10_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_ADA11_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA11_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_ADA12_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA12_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB2_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB3_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB4_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB5_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB6_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB7_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB8_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB9_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB9_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB10_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADB10_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_ADB11_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADB11_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_ADB12_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADB12_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RSTA_CLKA_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTA_CLKA_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTB_CLKB_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTB_CLKB_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLKA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_CLKB_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTB_posedge                   :	VitalDelayType   := 2.0 ns;
      tipd_CENA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRA                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CENB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRB                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CENA                            :	in    STD_ULOGIC;
      CLKA                            :	in    STD_ULOGIC;
      WRA                             :	in    STD_ULOGIC;
      CSA0                            :	in    STD_ULOGIC;
      CSA1                            :	in    STD_ULOGIC;
      RSTA                            :	in    STD_ULOGIC;
      CENB                            :	in    STD_ULOGIC;
      CLKB                            :	in    STD_ULOGIC;
      WRB                             :	in    STD_ULOGIC;
      CSB0                            :	in    STD_ULOGIC;
      CSB1                            :	in    STD_ULOGIC;
      RSTB                            :	in    STD_ULOGIC;
      DIA0                            :	in    STD_ULOGIC;
      ADA0                            :	in    STD_ULOGIC;
      ADA1                            :	in    STD_ULOGIC;
      ADA2                            :	in    STD_ULOGIC;
      ADA3                            :	in    STD_ULOGIC;
      ADA4                            :	in    STD_ULOGIC;
      ADA5                            :	in    STD_ULOGIC;
      ADA6                            :	in    STD_ULOGIC;
      ADA7                            :	in    STD_ULOGIC;
      ADA8                            :	in    STD_ULOGIC;
      ADA9                            :	in    STD_ULOGIC;
      ADA10                           :	in    STD_ULOGIC;
      ADA11                           :	in    STD_ULOGIC;
      ADA12                           :	in    STD_ULOGIC;
      DIB0                            :	in    STD_ULOGIC;
      ADB0                            :	in    STD_ULOGIC;
      ADB1                            :	in    STD_ULOGIC;
      ADB2                            :	in    STD_ULOGIC;
      ADB3                            :	in    STD_ULOGIC;
      ADB4                            :	in    STD_ULOGIC;
      ADB5                            :	in    STD_ULOGIC;
      ADB6                            :	in    STD_ULOGIC;
      ADB7                            :	in    STD_ULOGIC;
      ADB8                            :	in    STD_ULOGIC;
      ADB9                            :	in    STD_ULOGIC;
      ADB10                           :	in    STD_ULOGIC;
      ADB11                           :	in    STD_ULOGIC;
      ADB12                           :	in    STD_ULOGIC;
      DOA0                            :	out   STD_ULOGIC;
      DOB0                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB8K_X1_X1 : entity is FALSE;
end RAMB8K_X1_X1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB8K_X1_X1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_DPRAM_16K
	   generic (
		ADDR_WIDTH_A    : integer := 13;
		DATA_WIDTH_A    : integer := 1;
		ADDR_WIDTH_B    : integer := 13;
		DATA_WIDTH_B    : integer := 1;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CENA : in  STD_LOGIC ;
		CLKA : in  STD_LOGIC ;
		WRA  : in  STD_LOGIC ;
		CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTA : in  STD_LOGIC ;
		DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
		ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
		DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

		CENB : in  STD_LOGIC ;
		CLKB : in  STD_LOGIC ;
		WRB  : in  STD_LOGIC ;
		CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTB : in  STD_LOGIC ;
		DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
		ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
		DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
		);
	end component ;

      signal CENA_ipd      : std_ulogic := 'X';
      signal CLKA_ipd      : std_ulogic := 'X';
      signal WRA_ipd       : std_ulogic := 'X';
      signal CSA0_ipd      : std_ulogic := 'X';
      signal CSA1_ipd      : std_ulogic := 'X';
      signal RSTA_ipd      : std_ulogic := 'X';

      signal CENB_ipd      : std_ulogic := 'X';
      signal CLKB_ipd      : std_ulogic := 'X';
      signal WRB_ipd       : std_ulogic := 'X';
      signal CSB0_ipd      : std_ulogic := 'X';
      signal CSB1_ipd      : std_ulogic := 'X';
      signal RSTB_ipd      : std_ulogic := 'X';

      signal DIA0_ipd      : std_logic_vector(0 downto 0);

      signal ADA0_ipd      : std_ulogic := 'X';
      signal ADA1_ipd      : std_ulogic := 'X';
      signal ADA2_ipd      : std_ulogic := 'X';
      signal ADA3_ipd      : std_ulogic := 'X';
      signal ADA4_ipd      : std_ulogic := 'X';
      signal ADA5_ipd      : std_ulogic := 'X';
      signal ADA6_ipd      : std_ulogic := 'X';
      signal ADA7_ipd      : std_ulogic := 'X';
      signal ADA8_ipd      : std_ulogic := 'X';
      signal ADA9_ipd      : std_ulogic := 'X';
      signal ADA10_ipd     : std_ulogic := 'X';
      signal ADA11_ipd     : std_ulogic := 'X';
      signal ADA12_ipd     : std_ulogic := 'X';

      signal DIB0_ipd      : std_logic_vector(0 downto 0);

      signal ADB0_ipd      : std_ulogic := 'X';
      signal ADB1_ipd      : std_ulogic := 'X';
      signal ADB2_ipd      : std_ulogic := 'X';
      signal ADB3_ipd      : std_ulogic := 'X';
      signal ADB4_ipd      : std_ulogic := 'X';
      signal ADB5_ipd      : std_ulogic := 'X';
      signal ADB6_ipd      : std_ulogic := 'X';
      signal ADB7_ipd      : std_ulogic := 'X';
      signal ADB8_ipd      : std_ulogic := 'X';
      signal ADB9_ipd      : std_ulogic := 'X';
      signal ADB10_ipd     : std_ulogic := 'X';
      signal ADB11_ipd     : std_ulogic := 'X';
      signal ADB12_ipd     : std_ulogic := 'X';

	signal CSA : std_logic_vector (1 downto 0);
	signal CSB : std_logic_vector (1 downto 0);
	signal DIA : std_logic_vector (0 downto 0);
	signal DOA : std_logic_vector (0 downto 0);
	signal DIB : std_logic_vector (0 downto 0);
	signal DOB : std_logic_vector (0 downto 0);
	signal ADA : std_logic_vector (12 downto 0);
	signal ADB : std_logic_vector (12 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 
	CSA <= CSA1_ipd & CSA0_ipd;
	CSB <= CSB1_ipd & CSB0_ipd;
	DIA <= DIA0_ipd;
	DIB <= DIB0_ipd;
	ADA <= ADA12_ipd & ADA11_ipd & ADA10_ipd & ADA9_ipd & ADA8_ipd & ADA7_ipd & ADA6_ipd & ADA5_ipd & ADA4_ipd & ADA3_ipd & ADA2_ipd & ADA1_ipd & ADA0_ipd;
	ADB <= ADB12_ipd & ADB11_ipd & ADB10_ipd & ADB9_ipd & ADB8_ipd & ADB7_ipd & ADB6_ipd & ADB5_ipd & ADB4_ipd & ADB3_ipd & ADB2_ipd & ADB1_ipd & ADB0_ipd;


  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CENA_ipd, CENA, tipd_CENA);
        VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
        VitalWireDelay (CSA0_ipd, CSA0, tipd_CSA0);
        VitalWireDelay (CSA1_ipd, CSA1, tipd_CSA1);
        VitalWireDelay (WRA_ipd, WRA, tipd_WRA);
        VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);

        VitalWireDelay (CENB_ipd, CENB, tipd_CENB);
        VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
        VitalWireDelay (CSB0_ipd, CSB0, tipd_CSB0);
        VitalWireDelay (CSB1_ipd, CSB1, tipd_CSB1);
        VitalWireDelay (WRB_ipd, WRB, tipd_WRB);
        VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);

        VitalWireDelay (DIA0_ipd(0), DIA0, tipd_DIA0);

        VitalWireDelay (ADA0_ipd, ADA0, tipd_ADA0);
        VitalWireDelay (ADA1_ipd, ADA1, tipd_ADA1);
        VitalWireDelay (ADA2_ipd, ADA2, tipd_ADA2);
        VitalWireDelay (ADA3_ipd, ADA3, tipd_ADA3);
        VitalWireDelay (ADA4_ipd, ADA4, tipd_ADA4);
        VitalWireDelay (ADA5_ipd, ADA5, tipd_ADA5);
        VitalWireDelay (ADA6_ipd, ADA6, tipd_ADA6);
        VitalWireDelay (ADA7_ipd, ADA7, tipd_ADA7);
        VitalWireDelay (ADA8_ipd, ADA8, tipd_ADA8);
        VitalWireDelay (ADA9_ipd, ADA9, tipd_ADA9);
        VitalWireDelay (ADA10_ipd, ADA10, tipd_ADA10);
        VitalWireDelay (ADA11_ipd, ADA11, tipd_ADA11);
        VitalWireDelay (ADA12_ipd, ADA12, tipd_ADA12);

        VitalWireDelay (DIB0_ipd(0), DIB0, tipd_DIB0);

        VitalWireDelay (ADB0_ipd, ADB0, tipd_ADB0);
        VitalWireDelay (ADB1_ipd, ADB1, tipd_ADB1);
        VitalWireDelay (ADB2_ipd, ADB2, tipd_ADB2);
        VitalWireDelay (ADB3_ipd, ADB3, tipd_ADB3);
        VitalWireDelay (ADB4_ipd, ADB4, tipd_ADB4);
        VitalWireDelay (ADB5_ipd, ADB5, tipd_ADB5);
        VitalWireDelay (ADB6_ipd, ADB6, tipd_ADB6);
        VitalWireDelay (ADB7_ipd, ADB7, tipd_ADB7);
        VitalWireDelay (ADB8_ipd, ADB8, tipd_ADB8);
        VitalWireDelay (ADB9_ipd, ADB9, tipd_ADB9);
        VitalWireDelay (ADB10_ipd, ADB10, tipd_ADB10);
        VitalWireDelay (ADB11_ipd, ADB11, tipd_ADB11);
        VitalWireDelay (ADB12_ipd, ADB12, tipd_ADB12);

      end block;

      --------------------
      -- RAM16X1S Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CENA_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_WRA_CLKA_posedge     : std_ulogic  := '0';

        variable Tviol_CENB_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_WRB_CLKB_posedge      : std_ulogic  := '0';


        variable Tviol_DIA0_CLKA_posedge    : std_ulogic  := '0';

        variable Tviol_ADA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA3_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA4_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA5_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA6_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA7_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA8_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA9_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA10_CLKA_posedge   : std_ulogic  := '0';
        variable Tviol_ADA11_CLKA_posedge   : std_ulogic  := '0';
        variable Tviol_ADA12_CLKA_posedge   : std_ulogic  := '0';
        variable Tviol_ADA13_CLKA_posedge   : std_ulogic  := '0';

        variable Tviol_DIB0_CLKB_posedge    : std_ulogic  := '0';

        variable Tviol_ADB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB8_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB9_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB10_CLKB_posedge   : std_ulogic  := '0';
        variable Tviol_ADB11_CLKB_posedge   : std_ulogic  := '0';
        variable Tviol_ADB12_CLKB_posedge   : std_ulogic  := '0';

        variable Tviol_RSTA_CLKA_posedge_posedge : std_ulogic  := '0';
        variable Tviol_RSTB_CLKB_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CENA_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRA_CLKA_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CENB_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRB_CLKB_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA4_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA5_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA6_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA7_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA8_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA9_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA10_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA11_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA12_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB9_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB10_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB11_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB12_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RSTA_CLKA_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RSTB_CLKB_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLKA       : std_ulogic := '0';
        variable PInfo_CLKA       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_CLKB       : std_ulogic := '0';
        variable PInfo_CLkB       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTA        : std_ulogic := '0';
        variable PInfo_RSTA        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTB        : std_ulogic := '0';
        variable PInfo_RSTB        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DOA0_zd         : std_ulogic := 'X';
        variable DOB0_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CENA_CLKA_posedge,
          TimingData              => Tmkr_CENA_CLKA_posedge,
          TestSignal              => CENA_ipd,
          TestSignalName          => "CENA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENA_CLKA_noedge_posedge,
          SetupLow                => tsetup_CENA_CLKA_noedge_posedge,
          HoldLow                 => thold_CENA_CLKA_noedge_posedge,
          HoldHigh                => thold_CENA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRA_CLKA_posedge,
          TimingData              => Tmkr_WRA_CLKA_posedge,
          TestSignal              => WRA_ipd,
          TestSignalName          => "WRA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRA_CLKA_noedge_posedge,
          SetupLow                => tsetup_WRA_CLKA_noedge_posedge,
          HoldLow                 => thold_WRA_CLKA_noedge_posedge,
          HoldHigh                => thold_WRA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA0_CLKA_posedge,
          TimingData              => Tmkr_CSA0_CLKA_posedge,
          TestSignal              => CSA0_ipd,
          TestSignalName          => "CSA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA0_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA0_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA1_CLKA_posedge,
          TimingData              => Tmkr_CSA1_CLKA_posedge,
          TestSignal              => CSA1_ipd,
          TestSignalName          => "CSA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA1_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA1_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CENB_CLKB_posedge,
          TimingData              => Tmkr_CENB_CLKB_posedge,
          TestSignal              => CENB_ipd,
          TestSignalName          => "CENB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENB_CLKB_noedge_posedge,
          SetupLow                => tsetup_CENB_CLKB_noedge_posedge,
          HoldLow                 => thold_CENB_CLKB_noedge_posedge,
          HoldHigh                => thold_CENB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRB_CLKB_posedge,
          TimingData              => Tmkr_WRB_CLKB_posedge,
          TestSignal              => WRB_ipd,
          TestSignalName          => "WRB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRB_CLKB_noedge_posedge,
          SetupLow                => tsetup_WRB_CLKB_noedge_posedge,
          HoldLow                 => thold_WRB_CLKB_noedge_posedge,
          HoldHigh                => thold_WRB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB0_CLKB_posedge,
          TimingData              => Tmkr_CSB0_CLKB_posedge,
          TestSignal              => CSB0_ipd,
          TestSignalName          => "CSB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB0_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB0_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB1_CLKB_posedge,
          TimingData              => Tmkr_CSB1_CLKB_posedge,
          TestSignal              => CSB1_ipd,
          TestSignalName          => "CSB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB1_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB1_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA0_CLKA_posedge,
          TimingData              => Tmkr_ADA0_CLKA_posedge,
          TestSignal              => ADA0_ipd,
          TestSignalName          => "ADA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA0_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA0_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA1_CLKA_posedge,
          TimingData              => Tmkr_ADA1_CLKA_posedge,
          TestSignal              => ADA1_ipd,
          TestSignalName          => "ADA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA1_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA1_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA2_CLKA_posedge,
          TimingData              => Tmkr_ADA2_CLKA_posedge,
          TestSignal              => ADA2_ipd,
          TestSignalName          => "ADA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA2_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA2_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA3_CLKA_posedge,
          TimingData              => Tmkr_ADA3_CLKA_posedge,
          TestSignal              => ADA3_ipd,
          TestSignalName          => "ADA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA3_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA3_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA4_CLKA_posedge,
          TimingData              => Tmkr_ADA4_CLKA_posedge,
          TestSignal              => ADA4_ipd,
          TestSignalName          => "ADA4",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA4_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA4_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA4_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA4_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA5_CLKA_posedge,
          TimingData              => Tmkr_ADA5_CLKA_posedge,
          TestSignal              => ADA5_ipd,
          TestSignalName          => "ADA5",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA5_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA5_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA5_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA5_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA6_CLKA_posedge,
          TimingData              => Tmkr_ADA6_CLKA_posedge,
          TestSignal              => ADA6_ipd,
          TestSignalName          => "ADA6",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA6_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA6_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA6_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA6_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA7_CLKA_posedge,
          TimingData              => Tmkr_ADA7_CLKA_posedge,
          TestSignal              => ADA7_ipd,
          TestSignalName          => "ADA7",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA7_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA7_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA7_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA7_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA8_CLKA_posedge,
          TimingData              => Tmkr_ADA8_CLKA_posedge,
          TestSignal              => ADA8_ipd,
          TestSignalName          => "ADA8",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA8_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA8_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA8_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA8_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA9_CLKA_posedge,
          TimingData              => Tmkr_ADA9_CLKA_posedge,
          TestSignal              => ADA9_ipd,
          TestSignalName          => "ADA9",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA9_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA9_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA9_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA9_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA10_CLKA_posedge,
          TimingData              => Tmkr_ADA10_CLKA_posedge,
          TestSignal              => ADA10_ipd,
          TestSignalName          => "ADA10",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA10_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA10_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA10_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA10_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA11_CLKA_posedge,
          TimingData              => Tmkr_ADA11_CLKA_posedge,
          TestSignal              => ADA11_ipd,
          TestSignalName          => "ADA11",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA11_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA11_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA11_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA11_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA12_CLKA_posedge,
          TimingData              => Tmkr_ADA12_CLKA_posedge,
          TestSignal              => ADA12_ipd,
          TestSignalName          => "ADA12",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA12_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA12_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA12_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA12_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB0_CLKB_posedge,
          TimingData              => Tmkr_ADB0_CLKB_posedge,
          TestSignal              => ADB0_ipd,
          TestSignalName          => "ADB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB0_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB0_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB1_CLKB_posedge,
          TimingData              => Tmkr_ADB1_CLKB_posedge,
          TestSignal              => ADB1_ipd,
          TestSignalName          => "ADB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB1_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB1_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB2_CLKB_posedge,
          TimingData              => Tmkr_ADB2_CLKB_posedge,
          TestSignal              => ADB2_ipd,
          TestSignalName          => "ADB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB2_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB2_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB3_CLKB_posedge,
          TimingData              => Tmkr_ADB3_CLKB_posedge,
          TestSignal              => ADB3_ipd,
          TestSignalName          => "ADB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB3_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB3_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB4_CLKB_posedge,
          TimingData              => Tmkr_ADB4_CLKB_posedge,
          TestSignal              => ADB4_ipd,
          TestSignalName          => "ADB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB4_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB4_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB5_CLKB_posedge,
          TimingData              => Tmkr_ADB5_CLKB_posedge,
          TestSignal              => ADB5_ipd,
          TestSignalName          => "ADB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB5_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB5_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB6_CLKB_posedge,
          TimingData              => Tmkr_ADB6_CLKB_posedge,
          TestSignal              => ADB6_ipd,
          TestSignalName          => "ADB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB6_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB6_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB7_CLKB_posedge,
          TimingData              => Tmkr_ADB7_CLKB_posedge,
          TestSignal              => ADB7_ipd,
          TestSignalName          => "ADB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB7_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB7_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB8_CLKB_posedge,
          TimingData              => Tmkr_ADB8_CLKB_posedge,
          TestSignal              => ADB8_ipd,
          TestSignalName          => "ADB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB8_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB8_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB9_CLKB_posedge,
          TimingData              => Tmkr_ADB9_CLKB_posedge,
          TestSignal              => ADB9_ipd,
          TestSignalName          => "ADB9",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB9_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB9_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB9_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB9_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB10_CLKB_posedge,
          TimingData              => Tmkr_ADB10_CLKB_posedge,
          TestSignal              => ADB10_ipd,
          TestSignalName          => "ADB10",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB10_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB10_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB10_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB10_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB11_CLKB_posedge,
          TimingData              => Tmkr_ADB11_CLKB_posedge,
          TestSignal              => ADB11_ipd,
          TestSignalName          => "ADB11",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB11_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB11_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB11_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB11_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB12_CLKB_posedge,
          TimingData              => Tmkr_ADB12_CLKB_posedge,
          TestSignal              => ADB12_ipd,
          TestSignalName          => "ADB12",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB12_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB12_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB12_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB12_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKA,
          PeriodData              => PInfo_CLKA,
          TestSignal              => CLKA_ipd,
          TestSignalName          => "CLKA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKA_posedge,
          PulseWidthLow           => tpw_CLKA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAM16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKB,
          PeriodData              => PInfo_CLKB,
          TestSignal              => CLKB_ipd,
          TestSignalName          => "CLKB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKB_posedge,
          PulseWidthLow           => tpw_CLKB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAM16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTA,
          PeriodData              => PInfo_RSTA,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTA_posedge,
          PulseWidthLow           => tpw_RSTA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAM16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTB,
          PeriodData              => PInfo_RSTB,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTB_posedge,
          PulseWidthLow           => tpw_RSTB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAM16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTA_CLKA_posedge_posedge,
          TimingData              => Tmkr_RSTA_CLKA_posedge_posedge,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName          => "CLKA",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTA_CLKA_posedge_posedge,
          Removal                 => thold_RSTA_CLKA_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTB_CLKB_posedge_posedge,
          TimingData              => Tmkr_RSTB_CLKB_posedge_posedge,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName          => "CLKB",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTB_CLKB_posedge_posedge,
          Removal                 => thold_RSTB_CLKB_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CENA_CLKA_posedge or Tviol_WRA_CLKA_posedge or 
                 Tviol_CSA0_CLKA_posedge or Tviol_CSA1_CLKA_posedge or 
                 Tviol_ADA0_CLKA_posedge or Tviol_ADA1_CLKA_posedge or 
                 Tviol_ADA2_CLKA_posedge or Tviol_ADA3_CLKA_posedge or 
                 Tviol_ADA4_CLKA_posedge or Tviol_ADA5_CLKA_posedge or 
                 Tviol_ADA6_CLKA_posedge or Tviol_ADA7_CLKA_posedge or 
                 Tviol_ADA8_CLKA_posedge or Tviol_ADA9_CLKA_posedge or 
                 Tviol_ADA10_CLKA_posedge or Tviol_ADA11_CLKA_posedge or 
                 Tviol_ADA12_CLKA_posedge or Tviol_DIA0_CLKA_posedge or
                 Tviol_ADB0_CLKB_posedge or Tviol_ADB1_CLKB_posedge or 
                 Tviol_ADB2_CLKB_posedge or Tviol_ADB3_CLKB_posedge or 
                 Tviol_ADB4_CLKB_posedge or Tviol_ADB5_CLKB_posedge or 
                 Tviol_ADB6_CLKB_posedge or Tviol_ADB7_CLKB_posedge or 
                 Tviol_ADB8_CLKB_posedge or Tviol_ADB9_CLKB_posedge or 
                 Tviol_ADB10_CLKB_posedge or Tviol_ADB11_CLKB_posedge or 
                 Tviol_ADB12_CLKB_posedge or 
                 Pviol_CLKA or Pviol_CLKB or Pviol_RSTA or Pviol_RSTB;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on CENA_ipd, CLKA_ipd, WRA_ipd, CSA, RSTA_ipd, DIA, ADA, CENB_ipd, CLKB_ipd, WRB_ipd, CSB, 
	RSTB_ipd, DIB, ADB;

      end process VITALBehavior;

    VitalBehavior_DOA0  : process
      variable DOA0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA0_zd := DOA(0);

    VitalPathDelay01 (
      OutSignal => DOA0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA0",
      OutTemp => DOA0_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA0, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(0);
      end process;

    VitalBehavior_DOB0  : process
      variable DOB0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB0_zd := DOB(0);

    VitalPathDelay01 (
      OutSignal => DOB0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB0",
      OutTemp => DOB0_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB0, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(0);
      end process;



	DPRAM_INST: SC_DPRAM_16K
	   generic map(
		ADDR_WIDTH_A => 13,
		DATA_WIDTH_A => 1,
		ADDR_WIDTH_B => 13,
		DATA_WIDTH_B => 1,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CENA => CENA_ipd,
	        CLKA => CLKA_ipd,
	        WRA  => WRA_ipd,
	        CSA  => CSA,
	        RSTA => RSTA_ipd,
	        DIA  => DIA,
	        ADA  => ADA,
	        DOA  => DOA,

	        CENB => CENB_ipd,
	        CLKB => CLKB_ipd,
	        WRB  => WRB_ipd,
	        CSB  => CSB,
	        RSTB => RSTB_ipd,
	        DIB  => DIB,
	        ADB  => ADB,
	        DOB  => DOB);

end VITAL;

configuration CFG_RAMB8K_X1_X1_VITAL of RAMB8K_X1_X1 is
   for VITAL
   end for;
end CFG_RAMB8K_X1_X1_VITAL;



----- CELL RAMB8K_X1_X2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB8K_X1_X2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "dummy";
      tpd_CLKA_DOA0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTA_DOA0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_CENA_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENA_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRA_CLKA_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRA_CLKA_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CENB_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENB_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRB_CLKB_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRB_CLKB_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_DIA0_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_DIB0_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB1_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA2_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA3_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA4_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA4_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA5_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA5_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA6_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA6_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA7_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA7_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA8_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA8_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA9_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA9_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA10_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA10_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_ADA11_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA11_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_ADA12_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA12_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB2_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB3_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB4_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB5_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB6_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB7_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB8_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB9_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB9_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB10_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADB10_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_ADB11_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADB11_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RSTA_CLKA_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTA_CLKA_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTB_CLKB_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTB_CLKB_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLKA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_CLKB_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTB_posedge                   :	VitalDelayType   := 2.0 ns;
      tipd_CENA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRA                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CENB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRB                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CENA                            :	in    STD_ULOGIC;
      CLKA                            :	in    STD_ULOGIC;
      WRA                             :	in    STD_ULOGIC;
      CSA0                            :	in    STD_ULOGIC;
      CSA1                            :	in    STD_ULOGIC;
      RSTA                            :	in    STD_ULOGIC;
      CENB                            :	in    STD_ULOGIC;
      CLKB                            :	in    STD_ULOGIC;
      WRB                             :	in    STD_ULOGIC;
      CSB0                            :	in    STD_ULOGIC;
      CSB1                            :	in    STD_ULOGIC;
      RSTB                            :	in    STD_ULOGIC;
      DIA0                            :	in    STD_ULOGIC;
      ADA0                            :	in    STD_ULOGIC;
      ADA1                            :	in    STD_ULOGIC;
      ADA2                            :	in    STD_ULOGIC;
      ADA3                            :	in    STD_ULOGIC;
      ADA4                            :	in    STD_ULOGIC;
      ADA5                            :	in    STD_ULOGIC;
      ADA6                            :	in    STD_ULOGIC;
      ADA7                            :	in    STD_ULOGIC;
      ADA8                            :	in    STD_ULOGIC;
      ADA9                            :	in    STD_ULOGIC;
      ADA10                           :	in    STD_ULOGIC;
      ADA11                           :	in    STD_ULOGIC;
      ADA12                           :	in    STD_ULOGIC;
      DIB0                            :	in    STD_ULOGIC;
      DIB1                            :	in    STD_ULOGIC;
      ADB0                            :	in    STD_ULOGIC;
      ADB1                            :	in    STD_ULOGIC;
      ADB2                            :	in    STD_ULOGIC;
      ADB3                            :	in    STD_ULOGIC;
      ADB4                            :	in    STD_ULOGIC;
      ADB5                            :	in    STD_ULOGIC;
      ADB6                            :	in    STD_ULOGIC;
      ADB7                            :	in    STD_ULOGIC;
      ADB8                            :	in    STD_ULOGIC;
      ADB9                            :	in    STD_ULOGIC;
      ADB10                           :	in    STD_ULOGIC;
      ADB11                           :	in    STD_ULOGIC;
      DOA0                            :	out   STD_ULOGIC;
      DOB0                            :	out   STD_ULOGIC;
      DOB1                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB8K_X1_X2 : entity is FALSE;
end RAMB8K_X1_X2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB8K_X1_X2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_DPRAM_16K
	   generic (
		ADDR_WIDTH_A    : integer := 13;
		DATA_WIDTH_A    : integer := 1;
		ADDR_WIDTH_B    : integer := 12;
		DATA_WIDTH_B    : integer := 2;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CENA : in  STD_LOGIC ;
		CLKA : in  STD_LOGIC ;
		WRA  : in  STD_LOGIC ;
		CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTA : in  STD_LOGIC ;
		DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
		ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
		DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

		CENB : in  STD_LOGIC ;
		CLKB : in  STD_LOGIC ;
		WRB  : in  STD_LOGIC ;
		CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTB : in  STD_LOGIC ;
		DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
		ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
		DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
		);
	end component ;

      signal CENA_ipd      : std_ulogic := 'X';
      signal CLKA_ipd      : std_ulogic := 'X';
      signal WRA_ipd       : std_ulogic := 'X';
      signal CSA0_ipd      : std_ulogic := 'X';
      signal CSA1_ipd      : std_ulogic := 'X';
      signal RSTA_ipd      : std_ulogic := 'X';

      signal CENB_ipd      : std_ulogic := 'X';
      signal CLKB_ipd      : std_ulogic := 'X';
      signal WRB_ipd       : std_ulogic := 'X';
      signal CSB0_ipd      : std_ulogic := 'X';
      signal CSB1_ipd      : std_ulogic := 'X';
      signal RSTB_ipd      : std_ulogic := 'X';

      signal DIA0_ipd      : std_logic_vector(0 downto 0);

      signal ADA0_ipd      : std_ulogic := 'X';
      signal ADA1_ipd      : std_ulogic := 'X';
      signal ADA2_ipd      : std_ulogic := 'X';
      signal ADA3_ipd      : std_ulogic := 'X';
      signal ADA4_ipd      : std_ulogic := 'X';
      signal ADA5_ipd      : std_ulogic := 'X';
      signal ADA6_ipd      : std_ulogic := 'X';
      signal ADA7_ipd      : std_ulogic := 'X';
      signal ADA8_ipd      : std_ulogic := 'X';
      signal ADA9_ipd      : std_ulogic := 'X';
      signal ADA10_ipd     : std_ulogic := 'X';
      signal ADA11_ipd     : std_ulogic := 'X';
      signal ADA12_ipd     : std_ulogic := 'X';

      signal DIB0_ipd       : std_ulogic := 'X';
      signal DIB1_ipd       : std_ulogic := 'X';

      signal ADB0_ipd      : std_ulogic := 'X';
      signal ADB1_ipd      : std_ulogic := 'X';
      signal ADB2_ipd      : std_ulogic := 'X';
      signal ADB3_ipd      : std_ulogic := 'X';
      signal ADB4_ipd      : std_ulogic := 'X';
      signal ADB5_ipd      : std_ulogic := 'X';
      signal ADB6_ipd      : std_ulogic := 'X';
      signal ADB7_ipd      : std_ulogic := 'X';
      signal ADB8_ipd      : std_ulogic := 'X';
      signal ADB9_ipd      : std_ulogic := 'X';
      signal ADB10_ipd     : std_ulogic := 'X';
      signal ADB11_ipd     : std_ulogic := 'X';

	signal CSA : std_logic_vector (1 downto 0);
	signal CSB : std_logic_vector (1 downto 0);
	signal DIA : std_logic_vector (0 downto 0);
	signal DOA : std_logic_vector (0 downto 0);
	signal DIB : std_logic_vector (1 downto 0);
	signal DOB : std_logic_vector (1 downto 0);
	signal ADA : std_logic_vector (12 downto 0);
	signal ADB : std_logic_vector (11 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	CSA <= CSA1_ipd & CSA0_ipd;
	CSB <= CSB1_ipd & CSB0_ipd;
	DIA <= DIA0_ipd;
	DIB <= DIB1_ipd & DIB0_ipd;
	ADA <= ADA12_ipd & ADA11_ipd & ADA10_ipd & ADA9_ipd & ADA8_ipd & ADA7_ipd & ADA6_ipd & ADA5_ipd & ADA4_ipd & ADA3_ipd & ADA2_ipd & ADA1_ipd & ADA0_ipd;
	ADB <= ADB11_ipd & ADB10_ipd & ADB9_ipd & ADB8_ipd & ADB7_ipd & ADB6_ipd & ADB5_ipd & ADB4_ipd & ADB3_ipd & ADB2_ipd & ADB1_ipd & ADB0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CENA_ipd, CENA, tipd_CENA);
        VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
        VitalWireDelay (CSA0_ipd, CSA0, tipd_CSA0);
        VitalWireDelay (CSA1_ipd, CSA1, tipd_CSA1);
        VitalWireDelay (WRA_ipd, WRA, tipd_WRA);
        VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);

        VitalWireDelay (CENB_ipd, CENB, tipd_CENB);
        VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
        VitalWireDelay (CSB0_ipd, CSB0, tipd_CSB0);
        VitalWireDelay (CSB1_ipd, CSB1, tipd_CSB1);
        VitalWireDelay (WRB_ipd, WRB, tipd_WRB);
        VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);

        VitalWireDelay (DIA0_ipd(0), DIA0, tipd_DIA0);

        VitalWireDelay (ADA0_ipd, ADA0, tipd_ADA0);
        VitalWireDelay (ADA1_ipd, ADA1, tipd_ADA1);
        VitalWireDelay (ADA2_ipd, ADA2, tipd_ADA2);
        VitalWireDelay (ADA3_ipd, ADA3, tipd_ADA3);
        VitalWireDelay (ADA4_ipd, ADA4, tipd_ADA4);
        VitalWireDelay (ADA5_ipd, ADA5, tipd_ADA5);
        VitalWireDelay (ADA6_ipd, ADA6, tipd_ADA6);
        VitalWireDelay (ADA7_ipd, ADA7, tipd_ADA7);
        VitalWireDelay (ADA8_ipd, ADA8, tipd_ADA8);
        VitalWireDelay (ADA9_ipd, ADA9, tipd_ADA9);
        VitalWireDelay (ADA10_ipd, ADA10, tipd_ADA10);
        VitalWireDelay (ADA11_ipd, ADA11, tipd_ADA11);
        VitalWireDelay (ADA12_ipd, ADA12, tipd_ADA12);

        VitalWireDelay (DIB0_ipd, DIB0, tipd_DIB0);
        VitalWireDelay (DIB1_ipd, DIB1, tipd_DIB1);

        VitalWireDelay (ADB0_ipd, ADB0, tipd_ADB0);
        VitalWireDelay (ADB1_ipd, ADB1, tipd_ADB1);
        VitalWireDelay (ADB2_ipd, ADB2, tipd_ADB2);
        VitalWireDelay (ADB3_ipd, ADB3, tipd_ADB3);
        VitalWireDelay (ADB4_ipd, ADB4, tipd_ADB4);
        VitalWireDelay (ADB5_ipd, ADB5, tipd_ADB5);
        VitalWireDelay (ADB6_ipd, ADB6, tipd_ADB6);
        VitalWireDelay (ADB7_ipd, ADB7, tipd_ADB7);
        VitalWireDelay (ADB8_ipd, ADB8, tipd_ADB8);
        VitalWireDelay (ADB9_ipd, ADB9, tipd_ADB9);
        VitalWireDelay (ADB10_ipd, ADB10, tipd_ADB10);
        VitalWireDelay (ADB11_ipd, ADB11, tipd_ADB11);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CENA_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_WRA_CLKA_posedge     : std_ulogic  := '0';

        variable Tviol_CENB_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_WRB_CLKB_posedge      : std_ulogic  := '0';


        variable Tviol_DIA0_CLKA_posedge    : std_ulogic  := '0';

        variable Tviol_ADA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA3_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA4_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA5_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA6_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA7_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA8_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA9_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA10_CLKA_posedge   : std_ulogic  := '0';
        variable Tviol_ADA11_CLKA_posedge   : std_ulogic  := '0';
        variable Tviol_ADA12_CLKA_posedge   : std_ulogic  := '0';

        variable Tviol_DIB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB1_CLKB_posedge    : std_ulogic  := '0';

        variable Tviol_ADB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB8_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB9_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB10_CLKB_posedge   : std_ulogic  := '0';
        variable Tviol_ADB11_CLKB_posedge   : std_ulogic  := '0';

        variable Tviol_RSTA_CLKA_posedge_posedge : std_ulogic  := '0';
        variable Tviol_RSTB_CLKB_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CENA_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRA_CLKA_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CENB_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRB_CLKB_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA4_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA5_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA6_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA7_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA8_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA9_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA10_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA11_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA12_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB9_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB10_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB11_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RSTA_CLKA_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RSTB_CLKB_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLKA       : std_ulogic := '0';
        variable PInfo_CLKA       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_CLKB       : std_ulogic := '0';
        variable PInfo_CLkB       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTA        : std_ulogic := '0';
        variable PInfo_RSTA        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTB        : std_ulogic := '0';
        variable PInfo_RSTB        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DOA0_zd         : std_ulogic := 'X';
        variable DOB0_zd         : std_ulogic := 'X';
        variable DOB1_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CENA_CLKA_posedge,
          TimingData              => Tmkr_CENA_CLKA_posedge,
          TestSignal              => CENA_ipd,
          TestSignalName          => "CENA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENA_CLKA_noedge_posedge,
          SetupLow                => tsetup_CENA_CLKA_noedge_posedge,
          HoldLow                 => thold_CENA_CLKA_noedge_posedge,
          HoldHigh                => thold_CENA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRA_CLKA_posedge,
          TimingData              => Tmkr_WRA_CLKA_posedge,
          TestSignal              => WRA_ipd,
          TestSignalName          => "WRA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRA_CLKA_noedge_posedge,
          SetupLow                => tsetup_WRA_CLKA_noedge_posedge,
          HoldLow                 => thold_WRA_CLKA_noedge_posedge,
          HoldHigh                => thold_WRA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA0_CLKA_posedge,
          TimingData              => Tmkr_CSA0_CLKA_posedge,
          TestSignal              => CSA0_ipd,
          TestSignalName          => "CSA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA0_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA0_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA1_CLKA_posedge,
          TimingData              => Tmkr_CSA1_CLKA_posedge,
          TestSignal              => CSA1_ipd,
          TestSignalName          => "CSA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA1_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA1_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CENB_CLKB_posedge,
          TimingData              => Tmkr_CENB_CLKB_posedge,
          TestSignal              => CENB_ipd,
          TestSignalName          => "CENB",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENB_CLKB_noedge_posedge,
          SetupLow                => tsetup_CENB_CLKB_noedge_posedge,
          HoldLow                 => thold_CENB_CLKB_noedge_posedge,
          HoldHigh                => thold_CENB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRB_CLKB_posedge,
          TimingData              => Tmkr_WRB_CLKB_posedge,
          TestSignal              => WRB_ipd,
          TestSignalName          => "WRB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRB_CLKB_noedge_posedge,
          SetupLow                => tsetup_WRB_CLKB_noedge_posedge,
          HoldLow                 => thold_WRB_CLKB_noedge_posedge,
          HoldHigh                => thold_WRB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB0_CLKB_posedge,
          TimingData              => Tmkr_CSB0_CLKB_posedge,
          TestSignal              => CSB0_ipd,
          TestSignalName          => "CSB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB0_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB0_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB1_CLKB_posedge,
          TimingData              => Tmkr_CSB1_CLKB_posedge,
          TestSignal              => CSB1_ipd,
          TestSignalName          => "CSB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB1_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB1_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA0_CLKA_posedge,
          TimingData              => Tmkr_DIA0_CLKA_posedge,
          TestSignal              => DIA0_ipd,
          TestSignalName          => "DIA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA0_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA0_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA0_CLKA_posedge,
          TimingData              => Tmkr_ADA0_CLKA_posedge,
          TestSignal              => ADA0_ipd,
          TestSignalName          => "ADA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA0_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA0_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA1_CLKA_posedge,
          TimingData              => Tmkr_ADA1_CLKA_posedge,
          TestSignal              => ADA1_ipd,
          TestSignalName          => "ADA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA1_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA1_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA2_CLKA_posedge,
          TimingData              => Tmkr_ADA2_CLKA_posedge,
          TestSignal              => ADA2_ipd,
          TestSignalName          => "ADA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA2_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA2_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA3_CLKA_posedge,
          TimingData              => Tmkr_ADA3_CLKA_posedge,
          TestSignal              => ADA3_ipd,
          TestSignalName          => "ADA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA3_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA3_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA4_CLKA_posedge,
          TimingData              => Tmkr_ADA4_CLKA_posedge,
          TestSignal              => ADA4_ipd,
          TestSignalName          => "ADA4",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA4_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA4_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA4_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA4_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA5_CLKA_posedge,
          TimingData              => Tmkr_ADA5_CLKA_posedge,
          TestSignal              => ADA5_ipd,
          TestSignalName          => "ADA5",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA5_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA5_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA5_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA5_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA6_CLKA_posedge,
          TimingData              => Tmkr_ADA6_CLKA_posedge,
          TestSignal              => ADA6_ipd,
          TestSignalName          => "ADA6",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA6_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA6_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA6_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA6_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA7_CLKA_posedge,
          TimingData              => Tmkr_ADA7_CLKA_posedge,
          TestSignal              => ADA7_ipd,
          TestSignalName          => "ADA7",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA7_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA7_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA7_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA7_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA8_CLKA_posedge,
          TimingData              => Tmkr_ADA8_CLKA_posedge,
          TestSignal              => ADA8_ipd,
          TestSignalName          => "ADA8",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA8_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA8_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA8_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA8_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA9_CLKA_posedge,
          TimingData              => Tmkr_ADA9_CLKA_posedge,
          TestSignal              => ADA9_ipd,
          TestSignalName          => "ADA9",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA9_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA9_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA9_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA9_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA10_CLKA_posedge,
          TimingData              => Tmkr_ADA10_CLKA_posedge,
          TestSignal              => ADA10_ipd,
          TestSignalName          => "ADA10",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA10_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA10_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA10_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA10_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA11_CLKA_posedge,
          TimingData              => Tmkr_ADA11_CLKA_posedge,
          TestSignal              => ADA11_ipd,
          TestSignalName          => "ADA11",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA11_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA11_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA11_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA11_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA12_CLKA_posedge,
          TimingData              => Tmkr_ADA12_CLKA_posedge,
          TestSignal              => ADA12_ipd,
          TestSignalName          => "ADA12",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA12_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA12_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA12_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA12_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB0_CLKB_posedge,
          TimingData              => Tmkr_DIB0_CLKB_posedge,
          TestSignal              => DIB0_ipd,
          TestSignalName          => "DIB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB0_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB0_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB1_CLKB_posedge,
          TimingData              => Tmkr_DIB1_CLKB_posedge,
          TestSignal              => DIB1_ipd,
          TestSignalName          => "DIB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB1_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB1_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB0_CLKB_posedge,
          TimingData              => Tmkr_ADB0_CLKB_posedge,
          TestSignal              => ADB0_ipd,
          TestSignalName          => "ADB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB0_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB0_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB1_CLKB_posedge,
          TimingData              => Tmkr_ADB1_CLKB_posedge,
          TestSignal              => ADB1_ipd,
          TestSignalName          => "ADB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB1_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB1_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB2_CLKB_posedge,
          TimingData              => Tmkr_ADB2_CLKB_posedge,
          TestSignal              => ADB2_ipd,
          TestSignalName          => "ADB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB2_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB2_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB3_CLKB_posedge,
          TimingData              => Tmkr_ADB3_CLKB_posedge,
          TestSignal              => ADB3_ipd,
          TestSignalName          => "ADB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB3_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB3_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB4_CLKB_posedge,
          TimingData              => Tmkr_ADB4_CLKB_posedge,
          TestSignal              => ADB4_ipd,
          TestSignalName          => "ADB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB4_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB4_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB5_CLKB_posedge,
          TimingData              => Tmkr_ADB5_CLKB_posedge,
          TestSignal              => ADB5_ipd,
          TestSignalName          => "ADB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB5_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB5_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB6_CLKB_posedge,
          TimingData              => Tmkr_ADB6_CLKB_posedge,
          TestSignal              => ADB6_ipd,
          TestSignalName          => "ADB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB6_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB6_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB7_CLKB_posedge,
          TimingData              => Tmkr_ADB7_CLKB_posedge,
          TestSignal              => ADB7_ipd,
          TestSignalName          => "ADB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB7_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB7_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB8_CLKB_posedge,
          TimingData              => Tmkr_ADB8_CLKB_posedge,
          TestSignal              => ADB8_ipd,
          TestSignalName          => "ADB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB8_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB8_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB9_CLKB_posedge,
          TimingData              => Tmkr_ADB9_CLKB_posedge,
          TestSignal              => ADB9_ipd,
          TestSignalName          => "ADB9",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB9_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB9_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB9_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB9_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB10_CLKB_posedge,
          TimingData              => Tmkr_ADB10_CLKB_posedge,
          TestSignal              => ADB10_ipd,
          TestSignalName          => "ADB10",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB10_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB10_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB10_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB10_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB11_CLKB_posedge,
          TimingData              => Tmkr_ADB11_CLKB_posedge,
          TestSignal              => ADB11_ipd,
          TestSignalName          => "ADB11",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB11_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB11_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB11_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB11_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKA,
          PeriodData              => PInfo_CLKA,
          TestSignal              => CLKA_ipd,
          TestSignalName          => "CLKA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKA_posedge,
          PulseWidthLow           => tpw_CLKA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKB,
          PeriodData              => PInfo_CLKB,
          TestSignal              => CLKB_ipd,
          TestSignalName          => "CLKB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKB_posedge,
          PulseWidthLow           => tpw_CLKB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTA,
          PeriodData              => PInfo_RSTA,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTA_posedge,
          PulseWidthLow           => tpw_RSTA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTB,
          PeriodData              => PInfo_RSTB,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTB_posedge,
          PulseWidthLow           => tpw_RSTB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X1_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTA_CLKA_posedge_posedge,
          TimingData              => Tmkr_RSTA_CLKA_posedge_posedge,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName          => "CLKA",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTA_CLKA_posedge_posedge,
          Removal                 => thold_RSTA_CLKA_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTB_CLKB_posedge_posedge,
          TimingData              => Tmkr_RSTB_CLKB_posedge_posedge,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName          => "CLKB",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTB_CLKB_posedge_posedge,
          Removal                 => thold_RSTB_CLKB_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CENA_CLKA_posedge or Tviol_WRA_CLKA_posedge or 
                 Tviol_CSA0_CLKA_posedge or Tviol_CSA1_CLKA_posedge or 
                 Tviol_ADA0_CLKA_posedge or Tviol_ADA1_CLKA_posedge or 
                 Tviol_ADA2_CLKA_posedge or Tviol_ADA3_CLKA_posedge or 
                 Tviol_ADA4_CLKA_posedge or Tviol_ADA5_CLKA_posedge or 
                 Tviol_ADA6_CLKA_posedge or Tviol_ADA7_CLKA_posedge or 
                 Tviol_ADA8_CLKA_posedge or Tviol_ADA9_CLKA_posedge or 
                 Tviol_ADA10_CLKA_posedge or Tviol_ADA11_CLKA_posedge or 
                 Tviol_ADA12_CLKA_posedge or Tviol_DIA0_CLKA_posedge or
                 Tviol_ADB0_CLKB_posedge or Tviol_ADB1_CLKB_posedge or 
                 Tviol_ADB2_CLKB_posedge or Tviol_ADB3_CLKB_posedge or 
                 Tviol_ADB4_CLKB_posedge or Tviol_ADB5_CLKB_posedge or 
                 Tviol_ADB6_CLKB_posedge or Tviol_ADB7_CLKB_posedge or 
                 Tviol_ADB8_CLKB_posedge or Tviol_ADB9_CLKB_posedge or 
                 Tviol_ADB10_CLKB_posedge or Tviol_ADB11_CLKB_posedge or
 		 Tviol_DIB0_CLKB_posedge or  Tviol_DIB1_CLKB_posedge or 
                 Pviol_CLKA or Pviol_CLKB or Pviol_RSTA or Pviol_RSTB;

    -------------------------
    --  Functionality Section
    -------------------------

wait on CENA_ipd, CLKA_ipd, WRA_ipd, CSA, RSTA_ipd, DIA, ADA, CENB_ipd, CLKB_ipd, WRB_ipd, CSB, RSTB_ipd, DIB, ADB;

      end process VITALBehavior;

    VitalBehavior_DOA0  : process
      variable DOA0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA0_zd := DOA(0);

    VitalPathDelay01 (
      OutSignal => DOA0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA0",
      OutTemp => DOA0_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA0, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(0);
      end process;

    VitalBehavior_DOB0  : process
      variable DOB0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB0_zd := DOB(0);

    VitalPathDelay01 (
      OutSignal => DOB0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB0",
      OutTemp => DOB0_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB0, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(0);
      end process;

    VitalBehavior_DOB1  : process
      variable DOB1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB1_zd := DOB(1);

    VitalPathDelay01 (
      OutSignal => DOB1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB1",
      OutTemp => DOB1_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB1, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(1);
      end process;





	DPRAM_INST: SC_DPRAM_16K
	   generic map(
		ADDR_WIDTH_A => 13,
		DATA_WIDTH_A => 1,
		ADDR_WIDTH_B => 12,
		DATA_WIDTH_B => 2,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CENA => CENA_ipd,
	        CLKA => CLKA_ipd,
	        WRA  => WRA_ipd,
	        CSA  => CSA,
	        RSTA => RSTA_ipd,
	        DIA  => DIA,
	        ADA  => ADA,
	        DOA  => DOA,

	        CENB => CENB_ipd,
	        CLKB => CLKB_ipd,
	        WRB  => WRB_ipd,
	        CSB  => CSB,
	        RSTB => RSTB_ipd,
	        DIB  => DIB,
	        ADB  => ADB,
	        DOB  => DOB);

end VITAL;

configuration CFG_RAMB8K_X1_X2_VITAL of RAMB8K_X1_X2 is
   for VITAL
   end for;
end CFG_RAMB8K_X1_X2_VITAL;



----- CELL RAMB8K_X1_X4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB8K_X1_X4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "dummy";
      tpd_CLKA_DOA0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTA_DOA0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_CENA_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENA_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRA_CLKA_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRA_CLKA_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CENB_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENB_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRB_CLKB_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRB_CLKB_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_DIA0_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_DIB0_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB1_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB2_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB3_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA2_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA3_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA4_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA4_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA5_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA5_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA6_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA6_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA7_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA7_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA8_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA8_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA9_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA9_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA10_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA10_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_ADA11_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA11_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_ADA12_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA12_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB2_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB3_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB4_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB5_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB6_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB7_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB8_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB9_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB9_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB10_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADB10_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RSTA_CLKA_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTA_CLKA_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTB_CLKB_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTB_CLKB_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLKA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_CLKB_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTB_posedge                   :	VitalDelayType   := 2.0 ns;
      tipd_CENA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRA                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CENB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRB                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CENA                            :	in    STD_ULOGIC;
      CLKA                            :	in    STD_ULOGIC;
      WRA                             :	in    STD_ULOGIC;
      CSA0                            :	in    STD_ULOGIC;
      CSA1                            :	in    STD_ULOGIC;
      RSTA                            :	in    STD_ULOGIC;
      CENB                            :	in    STD_ULOGIC;
      CLKB                            :	in    STD_ULOGIC;
      WRB                             :	in    STD_ULOGIC;
      CSB0                            :	in    STD_ULOGIC;
      CSB1                            :	in    STD_ULOGIC;
      RSTB                            :	in    STD_ULOGIC;
      DIA0                            :	in    STD_ULOGIC;
      ADA0                            :	in    STD_ULOGIC;
      ADA1                            :	in    STD_ULOGIC;
      ADA2                            :	in    STD_ULOGIC;
      ADA3                            :	in    STD_ULOGIC;
      ADA4                            :	in    STD_ULOGIC;
      ADA5                            :	in    STD_ULOGIC;
      ADA6                            :	in    STD_ULOGIC;
      ADA7                            :	in    STD_ULOGIC;
      ADA8                            :	in    STD_ULOGIC;
      ADA9                            :	in    STD_ULOGIC;
      ADA10                           :	in    STD_ULOGIC;
      ADA11                           :	in    STD_ULOGIC;
      ADA12                           :	in    STD_ULOGIC;
      DIB0                            :	in    STD_ULOGIC;
      DIB1                            :	in    STD_ULOGIC;
      DIB2                            :	in    STD_ULOGIC;
      DIB3                            :	in    STD_ULOGIC;
      ADB0                            :	in    STD_ULOGIC;
      ADB1                            :	in    STD_ULOGIC;
      ADB2                            :	in    STD_ULOGIC;
      ADB3                            :	in    STD_ULOGIC;
      ADB4                            :	in    STD_ULOGIC;
      ADB5                            :	in    STD_ULOGIC;
      ADB6                            :	in    STD_ULOGIC;
      ADB7                            :	in    STD_ULOGIC;
      ADB8                            :	in    STD_ULOGIC;
      ADB9                            :	in    STD_ULOGIC;
      ADB10                           :	in    STD_ULOGIC;
      DOA0                            :	out   STD_ULOGIC;
      DOB0                            :	out   STD_ULOGIC;
      DOB1                            :	out   STD_ULOGIC;
      DOB2                            :	out   STD_ULOGIC;
      DOB3                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB8K_X1_X4 : entity is FALSE;
end RAMB8K_X1_X4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB8K_X1_X4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_DPRAM_16K
	   generic (
		ADDR_WIDTH_A    : integer := 13;
		DATA_WIDTH_A    : integer := 1;
		ADDR_WIDTH_B    : integer := 11;
		DATA_WIDTH_B    : integer := 4;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CENA : in  STD_LOGIC ;
		CLKA : in  STD_LOGIC ;
		WRA  : in  STD_LOGIC ;
		CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTA : in  STD_LOGIC ;
		DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
		ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
		DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

		CENB : in  STD_LOGIC ;
		CLKB : in  STD_LOGIC ;
		WRB  : in  STD_LOGIC ;
		CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTB : in  STD_LOGIC ;
		DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
		ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
		DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
		);
	end component ;

      signal CENA_ipd      : std_ulogic := 'X';
      signal CLKA_ipd      : std_ulogic := 'X';
      signal WRA_ipd       : std_ulogic := 'X';
      signal CSA0_ipd      : std_ulogic := 'X';
      signal CSA1_ipd      : std_ulogic := 'X';
      signal RSTA_ipd      : std_ulogic := 'X';

      signal CENB_ipd      : std_ulogic := 'X';
      signal CLKB_ipd      : std_ulogic := 'X';
      signal WRB_ipd       : std_ulogic := 'X';
      signal CSB0_ipd      : std_ulogic := 'X';
      signal CSB1_ipd      : std_ulogic := 'X';
      signal RSTB_ipd      : std_ulogic := 'X';

      signal DIA0_ipd      : std_logic_vector(0 downto 0);

      signal ADA0_ipd      : std_ulogic := 'X';
      signal ADA1_ipd      : std_ulogic := 'X';
      signal ADA2_ipd      : std_ulogic := 'X';
      signal ADA3_ipd      : std_ulogic := 'X';
      signal ADA4_ipd      : std_ulogic := 'X';
      signal ADA5_ipd      : std_ulogic := 'X';
      signal ADA6_ipd      : std_ulogic := 'X';
      signal ADA7_ipd      : std_ulogic := 'X';
      signal ADA8_ipd      : std_ulogic := 'X';
      signal ADA9_ipd      : std_ulogic := 'X';
      signal ADA10_ipd     : std_ulogic := 'X';
      signal ADA11_ipd     : std_ulogic := 'X';
      signal ADA12_ipd     : std_ulogic := 'X';

      signal DIB0_ipd       : std_ulogic := 'X';
      signal DIB1_ipd       : std_ulogic := 'X';
      signal DIB2_ipd       : std_ulogic := 'X';
      signal DIB3_ipd       : std_ulogic := 'X';

      signal ADB0_ipd      : std_ulogic := 'X';
      signal ADB1_ipd      : std_ulogic := 'X';
      signal ADB2_ipd      : std_ulogic := 'X';
      signal ADB3_ipd      : std_ulogic := 'X';
      signal ADB4_ipd      : std_ulogic := 'X';
      signal ADB5_ipd      : std_ulogic := 'X';
      signal ADB6_ipd      : std_ulogic := 'X';
      signal ADB7_ipd      : std_ulogic := 'X';
      signal ADB8_ipd      : std_ulogic := 'X';
      signal ADB9_ipd      : std_ulogic := 'X';
      signal ADB10_ipd     : std_ulogic := 'X';

	signal CSA : std_logic_vector (1 downto 0);
	signal CSB : std_logic_vector (1 downto 0);
	signal DIA : std_logic_vector (0 downto 0);
	signal DOA : std_logic_vector (0 downto 0);
	signal DIB : std_logic_vector (3 downto 0);
	signal DOB : std_logic_vector (3 downto 0);
	signal ADA : std_logic_vector (12 downto 0);
	signal ADB : std_logic_vector (10 downto 0);
      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	CSA <= CSA1_ipd & CSA0_ipd;
	CSB <= CSB1_ipd & CSB0_ipd;
	DIA <= DIA0_ipd;
	DIB <= DIB3_ipd & DIB2_ipd & DIB1_ipd & DIB0_ipd;
	ADA <= ADA12_ipd & ADA11_ipd & ADA10_ipd & ADA9_ipd & ADA8_ipd & ADA7_ipd & ADA6_ipd & ADA5_ipd & ADA4_ipd & ADA3_ipd & ADA2_ipd & ADA1_ipd & ADA0_ipd;
	ADB <= ADB10_ipd & ADB9_ipd & ADB8_ipd & ADB7_ipd & ADB6_ipd & ADB5_ipd & ADB4_ipd & ADB3_ipd & ADB2_ipd & ADB1_ipd & ADB0_ipd;


  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CENA_ipd, CENA, tipd_CENA);
        VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
        VitalWireDelay (CSA0_ipd, CSA0, tipd_CSA0);
        VitalWireDelay (CSA1_ipd, CSA1, tipd_CSA1);
        VitalWireDelay (WRA_ipd, WRA, tipd_WRA);
        VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);

        VitalWireDelay (CENB_ipd, CENB, tipd_CENB);
        VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
        VitalWireDelay (CSB0_ipd, CSB0, tipd_CSB0);
        VitalWireDelay (CSB1_ipd, CSB1, tipd_CSB1);
        VitalWireDelay (WRB_ipd, WRB, tipd_WRB);
        VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);

        VitalWireDelay (DIA0_ipd(0), DIA0, tipd_DIA0);

        VitalWireDelay (ADA0_ipd, ADA0, tipd_ADA0);
        VitalWireDelay (ADA1_ipd, ADA1, tipd_ADA1);
        VitalWireDelay (ADA2_ipd, ADA2, tipd_ADA2);
        VitalWireDelay (ADA3_ipd, ADA3, tipd_ADA3);
        VitalWireDelay (ADA4_ipd, ADA4, tipd_ADA4);
        VitalWireDelay (ADA5_ipd, ADA5, tipd_ADA5);
        VitalWireDelay (ADA6_ipd, ADA6, tipd_ADA6);
        VitalWireDelay (ADA7_ipd, ADA7, tipd_ADA7);
        VitalWireDelay (ADA8_ipd, ADA8, tipd_ADA8);
        VitalWireDelay (ADA9_ipd, ADA9, tipd_ADA9);
        VitalWireDelay (ADA10_ipd, ADA10, tipd_ADA10);
        VitalWireDelay (ADA11_ipd, ADA11, tipd_ADA11);
        VitalWireDelay (ADA12_ipd, ADA12, tipd_ADA12);

        VitalWireDelay (DIB0_ipd, DIB0, tipd_DIB0);
        VitalWireDelay (DIB1_ipd, DIB1, tipd_DIB1);
        VitalWireDelay (DIB2_ipd, DIB2, tipd_DIB2);
        VitalWireDelay (DIB3_ipd, DIB3, tipd_DIB3);

        VitalWireDelay (ADB0_ipd, ADB0, tipd_ADB0);
        VitalWireDelay (ADB1_ipd, ADB1, tipd_ADB1);
        VitalWireDelay (ADB2_ipd, ADB2, tipd_ADB2);
        VitalWireDelay (ADB3_ipd, ADB3, tipd_ADB3);
        VitalWireDelay (ADB4_ipd, ADB4, tipd_ADB4);
        VitalWireDelay (ADB5_ipd, ADB5, tipd_ADB5);
        VitalWireDelay (ADB6_ipd, ADB6, tipd_ADB6);
        VitalWireDelay (ADB7_ipd, ADB7, tipd_ADB7);
        VitalWireDelay (ADB8_ipd, ADB8, tipd_ADB8);
        VitalWireDelay (ADB9_ipd, ADB9, tipd_ADB9);
        VitalWireDelay (ADB10_ipd, ADB10, tipd_ADB10);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CENA_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_WRA_CLKA_posedge     : std_ulogic  := '0';

        variable Tviol_CENB_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_WRB_CLKB_posedge      : std_ulogic  := '0';


        variable Tviol_DIA0_CLKA_posedge    : std_ulogic  := '0';

        variable Tviol_ADA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA3_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA4_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA5_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA6_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA7_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA8_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA9_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA10_CLKA_posedge   : std_ulogic  := '0';
        variable Tviol_ADA11_CLKA_posedge   : std_ulogic  := '0';
        variable Tviol_ADA12_CLKA_posedge   : std_ulogic  := '0';

        variable Tviol_DIB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB3_CLKB_posedge    : std_ulogic  := '0';

        variable Tviol_ADB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB8_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB9_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB10_CLKB_posedge   : std_ulogic  := '0';

        variable Tviol_RSTA_CLKA_posedge_posedge : std_ulogic  := '0';
        variable Tviol_RSTB_CLKB_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CENA_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRA_CLKA_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CENB_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRB_CLKB_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA4_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA5_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA6_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA7_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA8_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA9_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA10_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA11_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA12_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB9_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB10_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RSTA_CLKA_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RSTB_CLKB_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLKA       : std_ulogic := '0';
        variable PInfo_CLKA       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_CLKB       : std_ulogic := '0';
        variable PInfo_CLkB       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTA        : std_ulogic := '0';
        variable PInfo_RSTA        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTB        : std_ulogic := '0';
        variable PInfo_RSTB        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DOA0_zd         : std_ulogic := 'X';
        variable DOB0_zd         : std_ulogic := 'X';
        variable DOB1_zd         : std_ulogic := 'X';
        variable DOB2_zd         : std_ulogic := 'X';
        variable DOB3_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CENA_CLKA_posedge,
          TimingData              => Tmkr_CENA_CLKA_posedge,
          TestSignal              => CENA_ipd,
          TestSignalName          => "CENA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENA_CLKA_noedge_posedge,
          SetupLow                => tsetup_CENA_CLKA_noedge_posedge,
          HoldLow                 => thold_CENA_CLKA_noedge_posedge,
          HoldHigh                => thold_CENA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRA_CLKA_posedge,
          TimingData              => Tmkr_WRA_CLKA_posedge,
          TestSignal              => WRA_ipd,
          TestSignalName          => "WRA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRA_CLKA_noedge_posedge,
          SetupLow                => tsetup_WRA_CLKA_noedge_posedge,
          HoldLow                 => thold_WRA_CLKA_noedge_posedge,
          HoldHigh                => thold_WRA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA0_CLKA_posedge,
          TimingData              => Tmkr_CSA0_CLKA_posedge,
          TestSignal              => CSA0_ipd,
          TestSignalName          => "CSA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA0_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA0_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA1_CLKA_posedge,
          TimingData              => Tmkr_CSA1_CLKA_posedge,
          TestSignal              => CSA1_ipd,
          TestSignalName          => "CSA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA1_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA1_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CENB_CLKB_posedge,
          TimingData              => Tmkr_CENB_CLKB_posedge,
          TestSignal              => CENB_ipd,
          TestSignalName          => "CENB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CENB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENB_CLKB_noedge_posedge,
          SetupLow                => tsetup_CENB_CLKB_noedge_posedge,
          HoldLow                 => thold_CENB_CLKB_noedge_posedge,
          HoldHigh                => thold_CENB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRB_CLKB_posedge,
          TimingData              => Tmkr_WRB_CLKB_posedge,
          TestSignal              => WRB_ipd,
          TestSignalName          => "WRB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRB_CLKB_noedge_posedge,
          SetupLow                => tsetup_WRB_CLKB_noedge_posedge,
          HoldLow                 => thold_WRB_CLKB_noedge_posedge,
          HoldHigh                => thold_WRB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB0_CLKB_posedge,
          TimingData              => Tmkr_CSB0_CLKB_posedge,
          TestSignal              => CSB0_ipd,
          TestSignalName          => "CSB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB0_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB0_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB1_CLKB_posedge,
          TimingData              => Tmkr_CSB1_CLKB_posedge,
          TestSignal              => CSB1_ipd,
          TestSignalName          => "CSB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB1_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB1_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA0_CLKA_posedge,
          TimingData              => Tmkr_DIA0_CLKA_posedge,
          TestSignal              => DIA0_ipd,
          TestSignalName          => "DIA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA0_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA0_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA0_CLKA_posedge,
          TimingData              => Tmkr_ADA0_CLKA_posedge,
          TestSignal              => ADA0_ipd,
          TestSignalName          => "ADA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA0_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA0_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA1_CLKA_posedge,
          TimingData              => Tmkr_ADA1_CLKA_posedge,
          TestSignal              => ADA1_ipd,
          TestSignalName          => "ADA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA1_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA1_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA2_CLKA_posedge,
          TimingData              => Tmkr_ADA2_CLKA_posedge,
          TestSignal              => ADA2_ipd,
          TestSignalName          => "ADA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA2_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA2_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA3_CLKA_posedge,
          TimingData              => Tmkr_ADA3_CLKA_posedge,
          TestSignal              => ADA3_ipd,
          TestSignalName          => "ADA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA3_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA3_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA4_CLKA_posedge,
          TimingData              => Tmkr_ADA4_CLKA_posedge,
          TestSignal              => ADA4_ipd,
          TestSignalName          => "ADA4",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA4_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA4_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA4_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA4_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA5_CLKA_posedge,
          TimingData              => Tmkr_ADA5_CLKA_posedge,
          TestSignal              => ADA5_ipd,
          TestSignalName          => "ADA5",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA5_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA5_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA5_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA5_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA6_CLKA_posedge,
          TimingData              => Tmkr_ADA6_CLKA_posedge,
          TestSignal              => ADA6_ipd,
          TestSignalName          => "ADA6",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA6_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA6_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA6_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA6_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA7_CLKA_posedge,
          TimingData              => Tmkr_ADA7_CLKA_posedge,
          TestSignal              => ADA7_ipd,
          TestSignalName          => "ADA7",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA7_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA7_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA7_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA7_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA8_CLKA_posedge,
          TimingData              => Tmkr_ADA8_CLKA_posedge,
          TestSignal              => ADA8_ipd,
          TestSignalName          => "ADA8",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA8_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA8_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA8_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA8_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA9_CLKA_posedge,
          TimingData              => Tmkr_ADA9_CLKA_posedge,
          TestSignal              => ADA9_ipd,
          TestSignalName          => "ADA9",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA9_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA9_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA9_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA9_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA10_CLKA_posedge,
          TimingData              => Tmkr_ADA10_CLKA_posedge,
          TestSignal              => ADA10_ipd,
          TestSignalName          => "ADA10",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA10_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA10_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA10_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA10_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA11_CLKA_posedge,
          TimingData              => Tmkr_ADA11_CLKA_posedge,
          TestSignal              => ADA11_ipd,
          TestSignalName          => "ADA11",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA11_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA11_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA11_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA11_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA12_CLKA_posedge,
          TimingData              => Tmkr_ADA12_CLKA_posedge,
          TestSignal              => ADA12_ipd,
          TestSignalName          => "ADA12",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA12_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA12_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA12_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA12_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB0_CLKB_posedge,
          TimingData              => Tmkr_DIB0_CLKB_posedge,
          TestSignal              => DIB0_ipd,
          TestSignalName          => "DIB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB0_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB0_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB1_CLKB_posedge,
          TimingData              => Tmkr_DIB1_CLKB_posedge,
          TestSignal              => DIB1_ipd,
          TestSignalName          => "DIB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB1_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB1_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB2_CLKB_posedge,
          TimingData              => Tmkr_DIB2_CLKB_posedge,
          TestSignal              => DIB2_ipd,
          TestSignalName          => "DIB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB2_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB2_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB3_CLKB_posedge,
          TimingData              => Tmkr_DIB3_CLKB_posedge,
          TestSignal              => DIB3_ipd,
          TestSignalName          => "DIB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB3_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB3_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB0_CLKB_posedge,
          TimingData              => Tmkr_ADB0_CLKB_posedge,
          TestSignal              => ADB0_ipd,
          TestSignalName          => "ADB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB0_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB0_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB1_CLKB_posedge,
          TimingData              => Tmkr_ADB1_CLKB_posedge,
          TestSignal              => ADB1_ipd,
          TestSignalName          => "ADB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB1_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB1_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB2_CLKB_posedge,
          TimingData              => Tmkr_ADB2_CLKB_posedge,
          TestSignal              => ADB2_ipd,
          TestSignalName          => "ADB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB2_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB2_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB3_CLKB_posedge,
          TimingData              => Tmkr_ADB3_CLKB_posedge,
          TestSignal              => ADB3_ipd,
          TestSignalName          => "ADB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB3_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB3_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB4_CLKB_posedge,
          TimingData              => Tmkr_ADB4_CLKB_posedge,
          TestSignal              => ADB4_ipd,
          TestSignalName          => "ADB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB4_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB4_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB5_CLKB_posedge,
          TimingData              => Tmkr_ADB5_CLKB_posedge,
          TestSignal              => ADB5_ipd,
          TestSignalName          => "ADB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB5_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB5_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB6_CLKB_posedge,
          TimingData              => Tmkr_ADB6_CLKB_posedge,
          TestSignal              => ADB6_ipd,
          TestSignalName          => "ADB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB6_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB6_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB7_CLKB_posedge,
          TimingData              => Tmkr_ADB7_CLKB_posedge,
          TestSignal              => ADB7_ipd,
          TestSignalName          => "ADB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB7_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB7_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB8_CLKB_posedge,
          TimingData              => Tmkr_ADB8_CLKB_posedge,
          TestSignal              => ADB8_ipd,
          TestSignalName          => "ADB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB8_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB8_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB9_CLKB_posedge,
          TimingData              => Tmkr_ADB9_CLKB_posedge,
          TestSignal              => ADB9_ipd,
          TestSignalName          => "ADB9",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB9_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB9_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB9_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB9_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB10_CLKB_posedge,
          TimingData              => Tmkr_ADB10_CLKB_posedge,
          TestSignal              => ADB10_ipd,
          TestSignalName          => "ADB10",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB10_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB10_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB10_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB10_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKA,
          PeriodData              => PInfo_CLKA,
          TestSignal              => CLKA_ipd,
          TestSignalName          => "CLKA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKA_posedge,
          PulseWidthLow           => tpw_CLKA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKB,
          PeriodData              => PInfo_CLKB,
          TestSignal              => CLKB_ipd,
          TestSignalName          => "CLKB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKB_posedge,
          PulseWidthLow           => tpw_CLKB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTA,
          PeriodData              => PInfo_RSTA,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTA_posedge,
          PulseWidthLow           => tpw_RSTA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTB,
          PeriodData              => PInfo_RSTB,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTB_posedge,
          PulseWidthLow           => tpw_RSTB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X1_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTA_CLKA_posedge_posedge,
          TimingData              => Tmkr_RSTA_CLKA_posedge_posedge,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName          => "CLKA",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTA_CLKA_posedge_posedge,
          Removal                 => thold_RSTA_CLKA_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTB_CLKB_posedge_posedge,
          TimingData              => Tmkr_RSTB_CLKB_posedge_posedge,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName          => "CLKB",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTB_CLKB_posedge_posedge,
          Removal                 => thold_RSTB_CLKB_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CENA_CLKA_posedge or Tviol_WRA_CLKA_posedge or 
                 Tviol_CSA0_CLKA_posedge or Tviol_CSA1_CLKA_posedge or 
                 Tviol_ADA0_CLKA_posedge or Tviol_ADA1_CLKA_posedge or 
                 Tviol_ADA2_CLKA_posedge or Tviol_ADA3_CLKA_posedge or 
                 Tviol_ADA4_CLKA_posedge or Tviol_ADA5_CLKA_posedge or 
                 Tviol_ADA6_CLKA_posedge or Tviol_ADA7_CLKA_posedge or 
                 Tviol_ADA8_CLKA_posedge or Tviol_ADA9_CLKA_posedge or 
                 Tviol_ADA10_CLKA_posedge or Tviol_ADA11_CLKA_posedge or 
                 Tviol_ADA12_CLKA_posedge or Tviol_DIA0_CLKA_posedge or
                 Tviol_ADB0_CLKB_posedge or Tviol_ADB1_CLKB_posedge or 
                 Tviol_ADB2_CLKB_posedge or Tviol_ADB3_CLKB_posedge or 
                 Tviol_ADB4_CLKB_posedge or Tviol_ADB5_CLKB_posedge or 
                 Tviol_ADB6_CLKB_posedge or Tviol_ADB7_CLKB_posedge or 
                 Tviol_ADB8_CLKB_posedge or Tviol_ADB9_CLKB_posedge or 
                 Tviol_ADB10_CLKB_posedge or 
 		 Tviol_DIB0_CLKB_posedge or  Tviol_DIB1_CLKB_posedge or 
 		 Tviol_DIB2_CLKB_posedge or  Tviol_DIB3_CLKB_posedge or 
                 Pviol_CLKA or Pviol_CLKB or Pviol_RSTA or Pviol_RSTB;

    -------------------------
    --  Functionality Section
    -------------------------

wait on CENA_ipd, CLKA_ipd, WRA_ipd, CSA, RSTA_ipd, DIA, ADA, CENB_ipd, CLKB_ipd, WRB_ipd, CSB, RSTB_ipd, DIB, ADB;

      end process VITALBehavior;

    VitalBehavior_DOA0  : process
      variable DOA0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA0_zd := DOA(0);

    VitalPathDelay01 (
      OutSignal => DOA0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA0",
      OutTemp => DOA0_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA0, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(0);
      end process;

    VitalBehavior_DOB0  : process
      variable DOB0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB0_zd := DOB(0);

    VitalPathDelay01 (
      OutSignal => DOB0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB0",
      OutTemp => DOB0_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB0, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(0);
      end process;

    VitalBehavior_DOB1  : process
      variable DOB1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB1_zd := DOB(1);

    VitalPathDelay01 (
      OutSignal => DOB1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB1",
      OutTemp => DOB1_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB1, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(1);
      end process;

    VitalBehavior_DOB2  : process
      variable DOB2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB2_zd := DOB(2);

    VitalPathDelay01 (
      OutSignal => DOB2,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB2",
      OutTemp => DOB2_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB2, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(2);
      end process;

    VitalBehavior_DOB3  : process
      variable DOB3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB3_zd := DOB(3);

    VitalPathDelay01 (
      OutSignal => DOB3,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB3",
      OutTemp => DOB3_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB3, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(3);
      end process;



	DPRAM_INST: SC_DPRAM_16K
	   generic map(
		ADDR_WIDTH_A => 13,
		DATA_WIDTH_A => 1,
		ADDR_WIDTH_B => 11,
		DATA_WIDTH_B => 4,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CENA => CENA_ipd,
	        CLKA => CLKA_ipd,
	        WRA  => WRA_ipd,
	        CSA  => CSA,
	        RSTA => RSTA_ipd,
	        DIA  => DIA,
	        ADA  => ADA,
	        DOA  => DOA,

	        CENB => CENB_ipd,
	        CLKB => CLKB_ipd,
	        WRB  => WRB_ipd,
	        CSB  => CSB,
	        RSTB => RSTB_ipd,
	        DIB  => DIB,
	        ADB  => ADB,
	        DOB  => DOB);
end VITAL;

configuration CFG_RAMB8K_X1_X4_VITAL of RAMB8K_X1_X4 is
   for VITAL
   end for;
end CFG_RAMB8K_X1_X4_VITAL;



----- CELL RAMB8K_X1_X8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB8K_X1_X8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "dummy";
      tpd_CLKA_DOA0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTA_DOA0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_CENA_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENA_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRA_CLKA_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRA_CLKA_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CENB_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENB_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRB_CLKB_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRB_CLKB_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_DIA0_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_DIB0_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB1_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB2_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB3_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB4_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB5_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB6_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB7_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA2_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA3_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA4_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA4_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA5_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA5_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA6_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA6_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA7_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA7_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA8_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA8_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA9_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA9_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA10_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA10_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_ADA11_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA11_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_ADA12_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA12_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB2_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB3_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB4_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB5_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB6_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB7_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB8_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB9_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB9_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTA_CLKA_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTA_CLKA_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTB_CLKB_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTB_CLKB_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLKA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_CLKB_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTB_posedge                   :	VitalDelayType   := 2.0 ns;
      tipd_CENA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRA                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CENB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRB                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CENA                            :	in    STD_ULOGIC;
      CLKA                            :	in    STD_ULOGIC;
      WRA                             :	in    STD_ULOGIC;
      CSA0                            :	in    STD_ULOGIC;
      CSA1                            :	in    STD_ULOGIC;
      RSTA                            :	in    STD_ULOGIC;
      CENB                            :	in    STD_ULOGIC;
      CLKB                            :	in    STD_ULOGIC;
      WRB                             :	in    STD_ULOGIC;
      CSB0                            :	in    STD_ULOGIC;
      CSB1                            :	in    STD_ULOGIC;
      RSTB                            :	in    STD_ULOGIC;
      DIA0                            :	in    STD_ULOGIC;
      ADA0                            :	in    STD_ULOGIC;
      ADA1                            :	in    STD_ULOGIC;
      ADA2                            :	in    STD_ULOGIC;
      ADA3                            :	in    STD_ULOGIC;
      ADA4                            :	in    STD_ULOGIC;
      ADA5                            :	in    STD_ULOGIC;
      ADA6                            :	in    STD_ULOGIC;
      ADA7                            :	in    STD_ULOGIC;
      ADA8                            :	in    STD_ULOGIC;
      ADA9                            :	in    STD_ULOGIC;
      ADA10                           :	in    STD_ULOGIC;
      ADA11                           :	in    STD_ULOGIC;
      ADA12                           :	in    STD_ULOGIC;
      DIB0                            :	in    STD_ULOGIC;
      DIB1                            :	in    STD_ULOGIC;
      DIB2                            :	in    STD_ULOGIC;
      DIB3                            :	in    STD_ULOGIC;
      DIB4                            :	in    STD_ULOGIC;
      DIB5                            :	in    STD_ULOGIC;
      DIB6                            :	in    STD_ULOGIC;
      DIB7                            :	in    STD_ULOGIC;
      ADB0                            :	in    STD_ULOGIC;
      ADB1                            :	in    STD_ULOGIC;
      ADB2                            :	in    STD_ULOGIC;
      ADB3                            :	in    STD_ULOGIC;
      ADB4                            :	in    STD_ULOGIC;
      ADB5                            :	in    STD_ULOGIC;
      ADB6                            :	in    STD_ULOGIC;
      ADB7                            :	in    STD_ULOGIC;
      ADB8                            :	in    STD_ULOGIC;
      ADB9                            :	in    STD_ULOGIC;
      DOA0                            :	out   STD_ULOGIC;
      DOB0                            :	out   STD_ULOGIC;
      DOB1                            :	out   STD_ULOGIC;
      DOB2                            :	out   STD_ULOGIC;
      DOB3                            :	out   STD_ULOGIC;
      DOB4                            :	out   STD_ULOGIC;
      DOB5                            :	out   STD_ULOGIC;
      DOB6                            :	out   STD_ULOGIC;
      DOB7                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB8K_X1_X8 : entity is FALSE;
end RAMB8K_X1_X8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB8K_X1_X8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_DPRAM_16K
	   generic (
		ADDR_WIDTH_A    : integer := 13;
		DATA_WIDTH_A    : integer := 1;
		ADDR_WIDTH_B    : integer := 10;
		DATA_WIDTH_B    : integer := 8;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CENA : in  STD_LOGIC ;
		CLKA : in  STD_LOGIC ;
		WRA  : in  STD_LOGIC ;
		CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTA : in  STD_LOGIC ;
		DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
		ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
		DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

		CENB : in  STD_LOGIC ;
		CLKB : in  STD_LOGIC ;
		WRB  : in  STD_LOGIC ;
		CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTB : in  STD_LOGIC ;
		DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
		ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
		DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
		);
	end component ;

      signal CENA_ipd      : std_ulogic := 'X';
      signal CLKA_ipd      : std_ulogic := 'X';
      signal WRA_ipd       : std_ulogic := 'X';
      signal CSA0_ipd      : std_ulogic := 'X';
      signal CSA1_ipd      : std_ulogic := 'X';
      signal RSTA_ipd      : std_ulogic := 'X';

      signal CENB_ipd      : std_ulogic := 'X';
      signal CLKB_ipd      : std_ulogic := 'X';
      signal WRB_ipd       : std_ulogic := 'X';
      signal CSB0_ipd      : std_ulogic := 'X';
      signal CSB1_ipd      : std_ulogic := 'X';
      signal RSTB_ipd      : std_ulogic := 'X';

      signal DIA0_ipd      : std_logic_vector(0 downto 0);

      signal ADA0_ipd      : std_ulogic := 'X';
      signal ADA1_ipd      : std_ulogic := 'X';
      signal ADA2_ipd      : std_ulogic := 'X';
      signal ADA3_ipd      : std_ulogic := 'X';
      signal ADA4_ipd      : std_ulogic := 'X';
      signal ADA5_ipd      : std_ulogic := 'X';
      signal ADA6_ipd      : std_ulogic := 'X';
      signal ADA7_ipd      : std_ulogic := 'X';
      signal ADA8_ipd      : std_ulogic := 'X';
      signal ADA9_ipd      : std_ulogic := 'X';
      signal ADA10_ipd     : std_ulogic := 'X';
      signal ADA11_ipd     : std_ulogic := 'X';
      signal ADA12_ipd     : std_ulogic := 'X';

      signal DIB0_ipd       : std_ulogic := 'X';
      signal DIB1_ipd       : std_ulogic := 'X';
      signal DIB2_ipd       : std_ulogic := 'X';
      signal DIB3_ipd       : std_ulogic := 'X';
      signal DIB4_ipd       : std_ulogic := 'X';
      signal DIB5_ipd       : std_ulogic := 'X';
      signal DIB6_ipd       : std_ulogic := 'X';
      signal DIB7_ipd       : std_ulogic := 'X';

      signal ADB0_ipd      : std_ulogic := 'X';
      signal ADB1_ipd      : std_ulogic := 'X';
      signal ADB2_ipd      : std_ulogic := 'X';
      signal ADB3_ipd      : std_ulogic := 'X';
      signal ADB4_ipd      : std_ulogic := 'X';
      signal ADB5_ipd      : std_ulogic := 'X';
      signal ADB6_ipd      : std_ulogic := 'X';
      signal ADB7_ipd      : std_ulogic := 'X';
      signal ADB8_ipd      : std_ulogic := 'X';
      signal ADB9_ipd      : std_ulogic := 'X';

	signal CSA : std_logic_vector (1 downto 0);
	signal CSB : std_logic_vector (1 downto 0);
	signal DIA : std_logic_vector (0 downto 0);
	signal DOA : std_logic_vector (0 downto 0);
	signal DIB : std_logic_vector (7 downto 0);
	signal DOB : std_logic_vector (7 downto 0);
	signal ADA : std_logic_vector (12 downto 0);
	signal ADB : std_logic_vector (9 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	CSA <= CSA1_ipd & CSA0_ipd;
	CSB <= CSB1_ipd & CSB0_ipd;
	DIA <= DIA0_ipd;
	DIB <= DIB7_ipd & DIB6_ipd & DIB5_ipd & DIB4_ipd & DIB3_ipd & DIB2_ipd & DIB1_ipd & DIB0_ipd;
	ADA <= ADA12_ipd & ADA11_ipd & ADA10_ipd & ADA9_ipd & ADA8_ipd & ADA7_ipd & ADA6_ipd & ADA5_ipd & ADA4_ipd & ADA3_ipd & ADA2_ipd & ADA1_ipd & ADA0_ipd;
	ADB <= ADB9_ipd & ADB8_ipd & ADB7_ipd & ADB6_ipd & ADB5_ipd & ADB4_ipd & ADB3_ipd & ADB2_ipd & ADB1_ipd & ADB0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CENA_ipd, CENA, tipd_CENA);
        VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
        VitalWireDelay (CSA0_ipd, CSA0, tipd_CSA0);
        VitalWireDelay (CSA1_ipd, CSA1, tipd_CSA1);
        VitalWireDelay (WRA_ipd, WRA, tipd_WRA);
        VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);

        VitalWireDelay (CENB_ipd, CENB, tipd_CENB);
        VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
        VitalWireDelay (CSB0_ipd, CSB0, tipd_CSB0);
        VitalWireDelay (CSB1_ipd, CSB1, tipd_CSB1);
        VitalWireDelay (WRB_ipd, WRB, tipd_WRB);
        VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);

        VitalWireDelay (DIA0_ipd(0), DIA0, tipd_DIA0);

        VitalWireDelay (ADA0_ipd, ADA0, tipd_ADA0);
        VitalWireDelay (ADA1_ipd, ADA1, tipd_ADA1);
        VitalWireDelay (ADA2_ipd, ADA2, tipd_ADA2);
        VitalWireDelay (ADA3_ipd, ADA3, tipd_ADA3);
        VitalWireDelay (ADA4_ipd, ADA4, tipd_ADA4);
        VitalWireDelay (ADA5_ipd, ADA5, tipd_ADA5);
        VitalWireDelay (ADA6_ipd, ADA6, tipd_ADA6);
        VitalWireDelay (ADA7_ipd, ADA7, tipd_ADA7);
        VitalWireDelay (ADA8_ipd, ADA8, tipd_ADA8);
        VitalWireDelay (ADA9_ipd, ADA9, tipd_ADA9);
        VitalWireDelay (ADA10_ipd, ADA10, tipd_ADA10);
        VitalWireDelay (ADA11_ipd, ADA11, tipd_ADA11);
        VitalWireDelay (ADA12_ipd, ADA12, tipd_ADA12);

        VitalWireDelay (DIB0_ipd, DIB0, tipd_DIB0);
        VitalWireDelay (DIB1_ipd, DIB1, tipd_DIB1);
        VitalWireDelay (DIB2_ipd, DIB2, tipd_DIB2);
        VitalWireDelay (DIB3_ipd, DIB3, tipd_DIB3);
        VitalWireDelay (DIB4_ipd, DIB4, tipd_DIB4);
        VitalWireDelay (DIB5_ipd, DIB5, tipd_DIB5);
        VitalWireDelay (DIB6_ipd, DIB6, tipd_DIB6);
        VitalWireDelay (DIB7_ipd, DIB7, tipd_DIB7);


        VitalWireDelay (ADB0_ipd, ADB0, tipd_ADB0);
        VitalWireDelay (ADB1_ipd, ADB1, tipd_ADB1);
        VitalWireDelay (ADB2_ipd, ADB2, tipd_ADB2);
        VitalWireDelay (ADB3_ipd, ADB3, tipd_ADB3);
        VitalWireDelay (ADB4_ipd, ADB4, tipd_ADB4);
        VitalWireDelay (ADB5_ipd, ADB5, tipd_ADB5);
        VitalWireDelay (ADB6_ipd, ADB6, tipd_ADB6);
        VitalWireDelay (ADB7_ipd, ADB7, tipd_ADB7);
        VitalWireDelay (ADB8_ipd, ADB8, tipd_ADB8);
        VitalWireDelay (ADB9_ipd, ADB9, tipd_ADB9);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CENA_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_WRA_CLKA_posedge     : std_ulogic  := '0';

        variable Tviol_CENB_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_WRB_CLKB_posedge      : std_ulogic  := '0';


        variable Tviol_DIA0_CLKA_posedge    : std_ulogic  := '0';

        variable Tviol_ADA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA3_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA4_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA5_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA6_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA7_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA8_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA9_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA10_CLKA_posedge   : std_ulogic  := '0';
        variable Tviol_ADA11_CLKA_posedge   : std_ulogic  := '0';
        variable Tviol_ADA12_CLKA_posedge   : std_ulogic  := '0';

        variable Tviol_DIB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB7_CLKB_posedge    : std_ulogic  := '0';

        variable Tviol_ADB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB8_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB9_CLKB_posedge    : std_ulogic  := '0';

        variable Tviol_RSTA_CLKA_posedge_posedge : std_ulogic  := '0';
        variable Tviol_RSTB_CLKB_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CENA_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRA_CLKA_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CENB_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRB_CLKB_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA4_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA5_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA6_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA7_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA8_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA9_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA10_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA11_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA12_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB9_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RSTA_CLKA_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RSTB_CLKB_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLKA       : std_ulogic := '0';
        variable PInfo_CLKA       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_CLKB       : std_ulogic := '0';
        variable PInfo_CLkB       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTA        : std_ulogic := '0';
        variable PInfo_RSTA        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTB        : std_ulogic := '0';
        variable PInfo_RSTB        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DOA0_zd         : std_ulogic := 'X';
        variable DOB0_zd         : std_ulogic := 'X';
        variable DOB1_zd         : std_ulogic := 'X';
        variable DOB2_zd         : std_ulogic := 'X';
        variable DOB3_zd         : std_ulogic := 'X';
        variable DOB4_zd         : std_ulogic := 'X';
        variable DOB5_zd         : std_ulogic := 'X';
        variable DOB6_zd         : std_ulogic := 'X';
        variable DOB7_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CENA_CLKA_posedge,
          TimingData              => Tmkr_CENA_CLKA_posedge,
          TestSignal              => CENA_ipd,
          TestSignalName          => "CENA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENA_CLKA_noedge_posedge,
          SetupLow                => tsetup_CENA_CLKA_noedge_posedge,
          HoldLow                 => thold_CENA_CLKA_noedge_posedge,
          HoldHigh                => thold_CENA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRA_CLKA_posedge,
          TimingData              => Tmkr_WRA_CLKA_posedge,
          TestSignal              => WRA_ipd,
          TestSignalName          => "WRA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRA_CLKA_noedge_posedge,
          SetupLow                => tsetup_WRA_CLKA_noedge_posedge,
          HoldLow                 => thold_WRA_CLKA_noedge_posedge,
          HoldHigh                => thold_WRA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA0_CLKA_posedge,
          TimingData              => Tmkr_CSA0_CLKA_posedge,
          TestSignal              => CSA0_ipd,
          TestSignalName          => "CSA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA0_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA0_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA1_CLKA_posedge,
          TimingData              => Tmkr_CSA1_CLKA_posedge,
          TestSignal              => CSA1_ipd,
          TestSignalName          => "CSA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA1_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA1_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CENB_CLKB_posedge,
          TimingData              => Tmkr_CENB_CLKB_posedge,
          TestSignal              => CENB_ipd,
          TestSignalName          => "CENB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENB_CLKB_noedge_posedge,
          SetupLow                => tsetup_CENB_CLKB_noedge_posedge,
          HoldLow                 => thold_CENB_CLKB_noedge_posedge,
          HoldHigh                => thold_CENB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRB_CLKB_posedge,
          TimingData              => Tmkr_WRB_CLKB_posedge,
          TestSignal              => WRB_ipd,
          TestSignalName          => "WRB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRB_CLKB_noedge_posedge,
          SetupLow                => tsetup_WRB_CLKB_noedge_posedge,
          HoldLow                 => thold_WRB_CLKB_noedge_posedge,
          HoldHigh                => thold_WRB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB0_CLKB_posedge,
          TimingData              => Tmkr_CSB0_CLKB_posedge,
          TestSignal              => CSB0_ipd,
          TestSignalName          => "CSB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB0_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB0_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB1_CLKB_posedge,
          TimingData              => Tmkr_CSB1_CLKB_posedge,
          TestSignal              => CSB1_ipd,
          TestSignalName          => "CSB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB1_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB1_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA0_CLKA_posedge,
          TimingData              => Tmkr_DIA0_CLKA_posedge,
          TestSignal              => DIA0_ipd,
          TestSignalName          => "DIA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA0_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA0_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA0_CLKA_posedge,
          TimingData              => Tmkr_ADA0_CLKA_posedge,
          TestSignal              => ADA0_ipd,
          TestSignalName          => "ADA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA0_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA0_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA1_CLKA_posedge,
          TimingData              => Tmkr_ADA1_CLKA_posedge,
          TestSignal              => ADA1_ipd,
          TestSignalName          => "ADA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA1_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA1_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA2_CLKA_posedge,
          TimingData              => Tmkr_ADA2_CLKA_posedge,
          TestSignal              => ADA2_ipd,
          TestSignalName          => "ADA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA2_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA2_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA3_CLKA_posedge,
          TimingData              => Tmkr_ADA3_CLKA_posedge,
          TestSignal              => ADA3_ipd,
          TestSignalName          => "ADA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA3_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA3_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA4_CLKA_posedge,
          TimingData              => Tmkr_ADA4_CLKA_posedge,
          TestSignal              => ADA4_ipd,
          TestSignalName          => "ADA4",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA4_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA4_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA4_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA4_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA5_CLKA_posedge,
          TimingData              => Tmkr_ADA5_CLKA_posedge,
          TestSignal              => ADA5_ipd,
          TestSignalName          => "ADA5",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA5_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA5_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA5_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA5_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA6_CLKA_posedge,
          TimingData              => Tmkr_ADA6_CLKA_posedge,
          TestSignal              => ADA6_ipd,
          TestSignalName          => "ADA6",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA6_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA6_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA6_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA6_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA7_CLKA_posedge,
          TimingData              => Tmkr_ADA7_CLKA_posedge,
          TestSignal              => ADA7_ipd,
          TestSignalName          => "ADA7",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA7_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA7_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA7_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA7_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA8_CLKA_posedge,
          TimingData              => Tmkr_ADA8_CLKA_posedge,
          TestSignal              => ADA8_ipd,
          TestSignalName          => "ADA8",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA8_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA8_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA8_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA8_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA9_CLKA_posedge,
          TimingData              => Tmkr_ADA9_CLKA_posedge,
          TestSignal              => ADA9_ipd,
          TestSignalName          => "ADA9",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA9_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA9_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA9_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA9_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA10_CLKA_posedge,
          TimingData              => Tmkr_ADA10_CLKA_posedge,
          TestSignal              => ADA10_ipd,
          TestSignalName          => "ADA10",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA10_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA10_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA10_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA10_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA11_CLKA_posedge,
          TimingData              => Tmkr_ADA11_CLKA_posedge,
          TestSignal              => ADA11_ipd,
          TestSignalName          => "ADA11",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA11_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA11_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA11_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA11_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA12_CLKA_posedge,
          TimingData              => Tmkr_ADA12_CLKA_posedge,
          TestSignal              => ADA12_ipd,
          TestSignalName          => "ADA12",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA12_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA12_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA12_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA12_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB0_CLKB_posedge,
          TimingData              => Tmkr_DIB0_CLKB_posedge,
          TestSignal              => DIB0_ipd,
          TestSignalName          => "DIB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB0_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB0_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB1_CLKB_posedge,
          TimingData              => Tmkr_DIB1_CLKB_posedge,
          TestSignal              => DIB1_ipd,
          TestSignalName          => "DIB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB1_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB1_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB2_CLKB_posedge,
          TimingData              => Tmkr_DIB2_CLKB_posedge,
          TestSignal              => DIB2_ipd,
          TestSignalName          => "DIB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB2_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB2_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB3_CLKB_posedge,
          TimingData              => Tmkr_DIB3_CLKB_posedge,
          TestSignal              => DIB3_ipd,
          TestSignalName          => "DIB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB3_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB3_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB4_CLKB_posedge,
          TimingData              => Tmkr_DIB4_CLKB_posedge,
          TestSignal              => DIB4_ipd,
          TestSignalName          => "DIB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB4_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB4_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB5_CLKB_posedge,
          TimingData              => Tmkr_DIB5_CLKB_posedge,
          TestSignal              => DIB5_ipd,
          TestSignalName          => "DIB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB5_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB5_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB6_CLKB_posedge,
          TimingData              => Tmkr_DIB6_CLKB_posedge,
          TestSignal              => DIB6_ipd,
          TestSignalName          => "DIB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB6_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB6_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB7_CLKB_posedge,
          TimingData              => Tmkr_DIB7_CLKB_posedge,
          TestSignal              => DIB7_ipd,
          TestSignalName          => "DIB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB7_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB7_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB0_CLKB_posedge,
          TimingData              => Tmkr_ADB0_CLKB_posedge,
          TestSignal              => ADB0_ipd,
          TestSignalName          => "ADB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB0_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB0_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB1_CLKB_posedge,
          TimingData              => Tmkr_ADB1_CLKB_posedge,
          TestSignal              => ADB1_ipd,
          TestSignalName          => "ADB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB1_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB1_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB2_CLKB_posedge,
          TimingData              => Tmkr_ADB2_CLKB_posedge,
          TestSignal              => ADB2_ipd,
          TestSignalName          => "ADB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB2_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB2_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB3_CLKB_posedge,
          TimingData              => Tmkr_ADB3_CLKB_posedge,
          TestSignal              => ADB3_ipd,
          TestSignalName          => "ADB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB3_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB3_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB4_CLKB_posedge,
          TimingData              => Tmkr_ADB4_CLKB_posedge,
          TestSignal              => ADB4_ipd,
          TestSignalName          => "ADB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB4_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB4_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB5_CLKB_posedge,
          TimingData              => Tmkr_ADB5_CLKB_posedge,
          TestSignal              => ADB5_ipd,
          TestSignalName          => "ADB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB5_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB5_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB6_CLKB_posedge,
          TimingData              => Tmkr_ADB6_CLKB_posedge,
          TestSignal              => ADB6_ipd,
          TestSignalName          => "ADB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB6_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB6_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB7_CLKB_posedge,
          TimingData              => Tmkr_ADB7_CLKB_posedge,
          TestSignal              => ADB7_ipd,
          TestSignalName          => "ADB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB7_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB7_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB8_CLKB_posedge,
          TimingData              => Tmkr_ADB8_CLKB_posedge,
          TestSignal              => ADB8_ipd,
          TestSignalName          => "ADB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB8_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB8_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB9_CLKB_posedge,
          TimingData              => Tmkr_ADB9_CLKB_posedge,
          TestSignal              => ADB9_ipd,
          TestSignalName          => "ADB9",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB9_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB9_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB9_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB9_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKA,
          PeriodData              => PInfo_CLKA,
          TestSignal              => CLKA_ipd,
          TestSignalName          => "CLKA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKA_posedge,
          PulseWidthLow           => tpw_CLKA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKB,
          PeriodData              => PInfo_CLKB,
          TestSignal              => CLKB_ipd,
          TestSignalName          => "CLKB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKB_posedge,
          PulseWidthLow           => tpw_CLKB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTA,
          PeriodData              => PInfo_RSTA,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTA_posedge,
          PulseWidthLow           => tpw_RSTA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTB,
          PeriodData              => PInfo_RSTB,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTB_posedge,
          PulseWidthLow           => tpw_RSTB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X1_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTA_CLKA_posedge_posedge,
          TimingData              => Tmkr_RSTA_CLKA_posedge_posedge,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName          => "CLKA",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTA_CLKA_posedge_posedge,
          Removal                 => thold_RSTA_CLKA_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTB_CLKB_posedge_posedge,
          TimingData              => Tmkr_RSTB_CLKB_posedge_posedge,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName          => "CLKB",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTB_CLKB_posedge_posedge,
          Removal                 => thold_RSTB_CLKB_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CENA_CLKA_posedge or Tviol_WRA_CLKA_posedge or 
                 Tviol_CSA0_CLKA_posedge or Tviol_CSA1_CLKA_posedge or 
                 Tviol_ADA0_CLKA_posedge or Tviol_ADA1_CLKA_posedge or 
                 Tviol_ADA2_CLKA_posedge or Tviol_ADA3_CLKA_posedge or 
                 Tviol_ADA4_CLKA_posedge or Tviol_ADA5_CLKA_posedge or 
                 Tviol_ADA6_CLKA_posedge or Tviol_ADA7_CLKA_posedge or 
                 Tviol_ADA8_CLKA_posedge or Tviol_ADA9_CLKA_posedge or 
                 Tviol_ADA10_CLKA_posedge or Tviol_ADA11_CLKA_posedge or 
                 Tviol_ADA12_CLKA_posedge or Tviol_DIA0_CLKA_posedge or
                 Tviol_ADB0_CLKB_posedge or Tviol_ADB1_CLKB_posedge or 
                 Tviol_ADB2_CLKB_posedge or Tviol_ADB3_CLKB_posedge or 
                 Tviol_ADB4_CLKB_posedge or Tviol_ADB5_CLKB_posedge or 
                 Tviol_ADB6_CLKB_posedge or Tviol_ADB7_CLKB_posedge or 
                 Tviol_ADB8_CLKB_posedge or Tviol_ADB9_CLKB_posedge or 
 		 Tviol_DIB0_CLKB_posedge or  Tviol_DIB1_CLKB_posedge or 
 		 Tviol_DIB2_CLKB_posedge or  Tviol_DIB3_CLKB_posedge or 
 		 Tviol_DIB4_CLKB_posedge or  Tviol_DIB5_CLKB_posedge or 
 		 Tviol_DIB6_CLKB_posedge or  Tviol_DIB7_CLKB_posedge or 
                 Pviol_CLKA or Pviol_CLKB or Pviol_RSTA or Pviol_RSTB;

    -------------------------
    --  Functionality Section
    -------------------------

wait on CENA_ipd, CLKA_ipd, WRA_ipd, CSA, RSTA_ipd, DIA, ADA, CENB_ipd, CLKB_ipd, WRB_ipd, CSB, RSTB_ipd, DIB, ADB;

      end process VITALBehavior;

    VitalBehavior_DOA0  : process
      variable DOA0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA0_zd := DOA(0);

    VitalPathDelay01 (
      OutSignal => DOA0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA0",
      OutTemp => DOA0_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA0, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(0);
      end process;

    VitalBehavior_DOB0  : process
      variable DOB0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB0_zd := DOB(0);

    VitalPathDelay01 (
      OutSignal => DOB0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB0",
      OutTemp => DOB0_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB0, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(0);
      end process;

    VitalBehavior_DOB1  : process
      variable DOB1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB1_zd := DOB(1);

    VitalPathDelay01 (
      OutSignal => DOB1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB1",
      OutTemp => DOB1_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB1, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(1);
      end process;

    VitalBehavior_DOB2  : process
      variable DOB2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB2_zd := DOB(2);

    VitalPathDelay01 (
      OutSignal => DOB2,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB2",
      OutTemp => DOB2_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB2, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(2);
      end process;

    VitalBehavior_DOB3  : process
      variable DOB3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB3_zd := DOB(3);

    VitalPathDelay01 (
      OutSignal => DOB3,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB3",
      OutTemp => DOB3_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB3, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(3);
      end process;

    VitalBehavior_DOB4  : process
      variable DOB4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB4_zd := DOB(4);

    VitalPathDelay01 (
      OutSignal => DOB4,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB4",
      OutTemp => DOB4_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB4, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(4);
      end process;

    VitalBehavior_DOB5  : process
      variable DOB5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB5_zd := DOB(5);

    VitalPathDelay01 (
      OutSignal => DOB5,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB5",
      OutTemp => DOB5_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB5, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(5);
      end process;

    VitalBehavior_DOB6  : process
      variable DOB6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB6_zd := DOB(6);

    VitalPathDelay01 (
      OutSignal => DOB6,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB6",
      OutTemp => DOB6_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB6, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(6);
      end process;

    VitalBehavior_DOB7  : process
      variable DOB7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB7_zd := DOB(7);

    VitalPathDelay01 (
      OutSignal => DOB7,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB7",
      OutTemp => DOB7_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB7, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(7);
      end process;



	DPRAM_INST: SC_DPRAM_16K
	   generic map(
		ADDR_WIDTH_A => 13,
		DATA_WIDTH_A => 1,
		ADDR_WIDTH_B => 10,
		DATA_WIDTH_B => 8,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CENA => CENA_ipd,
	        CLKA => CLKA_ipd,
	        WRA  => WRA_ipd,
	        CSA  => CSA,
	        RSTA => RSTA_ipd,
	        DIA  => DIA,
	        ADA  => ADA,
	        DOA  => DOA,

	        CENB => CENB_ipd,
	        CLKB => CLKB_ipd,
	        WRB  => WRB_ipd,
	        CSB  => CSB,
	        RSTB => RSTB_ipd,
	        DIB  => DIB,
	        ADB  => ADB,
	        DOB  => DOB);

end VITAL;

configuration CFG_RAMB8K_X1_X8_VITAL of RAMB8K_X1_X8 is
   for VITAL
   end for;
end CFG_RAMB8K_X1_X8_VITAL;



----- CELL RAMB8K_X1_X16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB8K_X1_X16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "dummy";
      tpd_CLKA_DOA0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_CLKB_DOB0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTA_DOA0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTB_DOB0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_CENA_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENA_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRA_CLKA_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRA_CLKA_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CENB_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENB_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRB_CLKB_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRB_CLKB_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_DIA0_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_DIB0_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB1_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB2_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB3_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB4_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB5_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB6_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB7_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB8_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB9_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB9_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB10_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB10_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB11_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB11_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB12_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB12_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB13_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB13_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB14_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB14_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB15_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB15_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA2_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA3_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA4_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA4_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA5_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA5_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA6_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA6_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA7_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA7_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA8_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA8_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA9_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA9_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA10_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA10_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_ADA11_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA11_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_ADA12_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA12_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB2_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB3_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB4_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB5_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB6_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB7_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB8_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTA_CLKA_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTA_CLKA_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTB_CLKB_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTB_CLKB_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLKA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_CLKB_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTB_posedge                   :	VitalDelayType   := 2.0 ns;
      tipd_CENA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRA                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CENB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRB                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CENA                            :	in    STD_ULOGIC;
      CLKA                            :	in    STD_ULOGIC;
      WRA                             :	in    STD_ULOGIC;
      CSA0                            :	in    STD_ULOGIC;
      CSA1                            :	in    STD_ULOGIC;
      RSTA                            :	in    STD_ULOGIC;
      CENB                            :	in    STD_ULOGIC;
      CLKB                            :	in    STD_ULOGIC;
      WRB                             :	in    STD_ULOGIC;
      CSB0                            :	in    STD_ULOGIC;
      CSB1                            :	in    STD_ULOGIC;
      RSTB                            :	in    STD_ULOGIC;
      DIA0                            :	in    STD_ULOGIC;
      ADA0                            :	in    STD_ULOGIC;
      ADA1                            :	in    STD_ULOGIC;
      ADA2                            :	in    STD_ULOGIC;
      ADA3                            :	in    STD_ULOGIC;
      ADA4                            :	in    STD_ULOGIC;
      ADA5                            :	in    STD_ULOGIC;
      ADA6                            :	in    STD_ULOGIC;
      ADA7                            :	in    STD_ULOGIC;
      ADA8                            :	in    STD_ULOGIC;
      ADA9                            :	in    STD_ULOGIC;
      ADA10                           :	in    STD_ULOGIC;
      ADA11                           :	in    STD_ULOGIC;
      ADA12                           :	in    STD_ULOGIC;
      DIB0                            :	in    STD_ULOGIC;
      DIB1                            :	in    STD_ULOGIC;
      DIB2                            :	in    STD_ULOGIC;
      DIB3                            :	in    STD_ULOGIC;
      DIB4                            :	in    STD_ULOGIC;
      DIB5                            :	in    STD_ULOGIC;
      DIB6                            :	in    STD_ULOGIC;
      DIB7                            :	in    STD_ULOGIC;
      DIB8                            :	in    STD_ULOGIC;
      DIB9                            :	in    STD_ULOGIC;
      DIB10                           :	in    STD_ULOGIC;
      DIB11                           :	in    STD_ULOGIC;
      DIB12                           :	in    STD_ULOGIC;
      DIB13                           :	in    STD_ULOGIC;
      DIB14                           :	in    STD_ULOGIC;
      DIB15                           :	in    STD_ULOGIC;
      ADB0                            :	in    STD_ULOGIC;
      ADB1                            :	in    STD_ULOGIC;
      ADB2                            :	in    STD_ULOGIC;
      ADB3                            :	in    STD_ULOGIC;
      ADB4                            :	in    STD_ULOGIC;
      ADB5                            :	in    STD_ULOGIC;
      ADB6                            :	in    STD_ULOGIC;
      ADB7                            :	in    STD_ULOGIC;
      ADB8                            :	in    STD_ULOGIC;
      DOA0                            :	out   STD_ULOGIC;
      DOB0                            :	out   STD_ULOGIC;
      DOB1                            :	out   STD_ULOGIC;
      DOB2                            :	out   STD_ULOGIC;
      DOB3                            :	out   STD_ULOGIC;
      DOB4                            :	out   STD_ULOGIC;
      DOB5                            :	out   STD_ULOGIC;
      DOB6                            :	out   STD_ULOGIC;
      DOB7                            :	out   STD_ULOGIC;
      DOB8                            :	out   STD_ULOGIC;
      DOB9                            :	out   STD_ULOGIC;
      DOB10                           :	out   STD_ULOGIC;
      DOB11                           :	out   STD_ULOGIC;
      DOB12                           :	out   STD_ULOGIC;
      DOB13                           :	out   STD_ULOGIC;
      DOB14                           :	out   STD_ULOGIC;
      DOB15                           :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB8K_X1_X16 : entity is FALSE;
end RAMB8K_X1_X16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB8K_X1_X16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;
	component SC_DPRAM_16K
	   generic (
		ADDR_WIDTH_A    : integer := 13;
		DATA_WIDTH_A    : integer := 1;
		ADDR_WIDTH_B    : integer := 9;
		DATA_WIDTH_B    : integer := 16;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CENA : in  STD_LOGIC ;
		CLKA : in  STD_LOGIC ;
		WRA  : in  STD_LOGIC ;
		CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTA : in  STD_LOGIC ;
		DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
		ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
		DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

		CENB : in  STD_LOGIC ;
		CLKB : in  STD_LOGIC ;
		WRB  : in  STD_LOGIC ;
		CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTB : in  STD_LOGIC ;
		DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
		ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
		DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
		);
	end component ;


      signal CENA_ipd      : std_ulogic := 'X';
      signal CLKA_ipd      : std_ulogic := 'X';
      signal WRA_ipd       : std_ulogic := 'X';
      signal CSA0_ipd      : std_ulogic := 'X';
      signal CSA1_ipd      : std_ulogic := 'X';
      signal RSTA_ipd      : std_ulogic := 'X';

      signal CENB_ipd      : std_ulogic := 'X';
      signal CLKB_ipd      : std_ulogic := 'X';
      signal WRB_ipd       : std_ulogic := 'X';
      signal CSB0_ipd      : std_ulogic := 'X';
      signal CSB1_ipd      : std_ulogic := 'X';
      signal RSTB_ipd      : std_ulogic := 'X';

      signal DIA0_ipd      : std_logic_vector(0 downto 0);

      signal ADA0_ipd      : std_ulogic := 'X';
      signal ADA1_ipd      : std_ulogic := 'X';
      signal ADA2_ipd      : std_ulogic := 'X';
      signal ADA3_ipd      : std_ulogic := 'X';
      signal ADA4_ipd      : std_ulogic := 'X';
      signal ADA5_ipd      : std_ulogic := 'X';
      signal ADA6_ipd      : std_ulogic := 'X';
      signal ADA7_ipd      : std_ulogic := 'X';
      signal ADA8_ipd      : std_ulogic := 'X';
      signal ADA9_ipd      : std_ulogic := 'X';
      signal ADA10_ipd     : std_ulogic := 'X';
      signal ADA11_ipd     : std_ulogic := 'X';
      signal ADA12_ipd     : std_ulogic := 'X';

      signal DIB0_ipd       : std_ulogic := 'X';
      signal DIB1_ipd       : std_ulogic := 'X';
      signal DIB2_ipd       : std_ulogic := 'X';
      signal DIB3_ipd       : std_ulogic := 'X';
      signal DIB4_ipd       : std_ulogic := 'X';
      signal DIB5_ipd       : std_ulogic := 'X';
      signal DIB6_ipd       : std_ulogic := 'X';
      signal DIB7_ipd       : std_ulogic := 'X';
      signal DIB8_ipd       : std_ulogic := 'X';
      signal DIB9_ipd       : std_ulogic := 'X';
      signal DIB10_ipd      : std_ulogic := 'X';
      signal DIB11_ipd      : std_ulogic := 'X';
      signal DIB12_ipd      : std_ulogic := 'X';
      signal DIB13_ipd      : std_ulogic := 'X';
      signal DIB14_ipd      : std_ulogic := 'X';
      signal DIB15_ipd      : std_ulogic := 'X';

      signal ADB0_ipd      : std_ulogic := 'X';
      signal ADB1_ipd      : std_ulogic := 'X';
      signal ADB2_ipd      : std_ulogic := 'X';
      signal ADB3_ipd      : std_ulogic := 'X';
      signal ADB4_ipd      : std_ulogic := 'X';
      signal ADB5_ipd      : std_ulogic := 'X';
      signal ADB6_ipd      : std_ulogic := 'X';
      signal ADB7_ipd      : std_ulogic := 'X';
      signal ADB8_ipd      : std_ulogic := 'X';

	signal CSA : std_logic_vector (1 downto 0);
	signal CSB : std_logic_vector (1 downto 0);
	signal DIA : std_logic_vector (0 downto 0);
	signal DOA : std_logic_vector (0 downto 0);
	signal DIB : std_logic_vector (15 downto 0);
	signal DOB : std_logic_vector (15 downto 0);
	signal ADA : std_logic_vector (12 downto 0);
	signal ADB : std_logic_vector (8 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);

begin 

	CSA <= CSA1_ipd & CSA0_ipd;
	CSB <= CSB1_ipd & CSB0_ipd;
	DIA <= DIA0_ipd;
	DIB <= DIB15_ipd & DIB14_ipd & DIB13_ipd & DIB12_ipd & DIB11_ipd & DIB10_ipd & DIB9_ipd & DIB8_ipd & DIB7_ipd & DIB6_ipd & DIB5_ipd & DIB4_ipd & DIB3_ipd & DIB2_ipd & DIB1_ipd & DIB0_ipd;
	ADA <= ADA12_ipd & ADA11_ipd & ADA10_ipd & ADA9_ipd & ADA8_ipd & ADA7_ipd & ADA6_ipd & ADA5_ipd & ADA4_ipd & ADA3_ipd & ADA2_ipd & ADA1_ipd & ADA0_ipd;
	ADB <= ADB8_ipd & ADB7_ipd & ADB6_ipd & ADB5_ipd & ADB4_ipd & ADB3_ipd & ADB2_ipd & ADB1_ipd & ADB0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CENA_ipd, CENA, tipd_CENA);
        VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
        VitalWireDelay (CSA0_ipd, CSA0, tipd_CSA0);
        VitalWireDelay (CSA1_ipd, CSA1, tipd_CSA1);
        VitalWireDelay (WRA_ipd, WRA, tipd_WRA);
        VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);

        VitalWireDelay (CENB_ipd, CENB, tipd_CENB);
        VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
        VitalWireDelay (CSB0_ipd, CSB0, tipd_CSB0);
        VitalWireDelay (CSB1_ipd, CSB1, tipd_CSB1);
        VitalWireDelay (WRB_ipd, WRB, tipd_WRB);
        VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);

        VitalWireDelay (DIA0_ipd(0), DIA0, tipd_DIA0);

        VitalWireDelay (ADA0_ipd, ADA0, tipd_ADA0);
        VitalWireDelay (ADA1_ipd, ADA1, tipd_ADA1);
        VitalWireDelay (ADA2_ipd, ADA2, tipd_ADA2);
        VitalWireDelay (ADA3_ipd, ADA3, tipd_ADA3);
        VitalWireDelay (ADA4_ipd, ADA4, tipd_ADA4);
        VitalWireDelay (ADA5_ipd, ADA5, tipd_ADA5);
        VitalWireDelay (ADA6_ipd, ADA6, tipd_ADA6);
        VitalWireDelay (ADA7_ipd, ADA7, tipd_ADA7);
        VitalWireDelay (ADA8_ipd, ADA8, tipd_ADA8);
        VitalWireDelay (ADA9_ipd, ADA9, tipd_ADA9);
        VitalWireDelay (ADA10_ipd, ADA10, tipd_ADA10);
        VitalWireDelay (ADA11_ipd, ADA11, tipd_ADA11);
        VitalWireDelay (ADA12_ipd, ADA12, tipd_ADA12);

        VitalWireDelay (DIB0_ipd, DIB0, tipd_DIB0);
        VitalWireDelay (DIB1_ipd, DIB1, tipd_DIB1);
        VitalWireDelay (DIB2_ipd, DIB2, tipd_DIB2);
        VitalWireDelay (DIB3_ipd, DIB3, tipd_DIB3);
        VitalWireDelay (DIB4_ipd, DIB4, tipd_DIB4);
        VitalWireDelay (DIB5_ipd, DIB5, tipd_DIB5);
        VitalWireDelay (DIB6_ipd, DIB6, tipd_DIB6);
        VitalWireDelay (DIB7_ipd, DIB7, tipd_DIB7);
        VitalWireDelay (DIB8_ipd, DIB8, tipd_DIB8);
        VitalWireDelay (DIB9_ipd, DIB9, tipd_DIB9);
        VitalWireDelay (DIB10_ipd, DIB10, tipd_DIB10);
        VitalWireDelay (DIB11_ipd, DIB11, tipd_DIB11);
        VitalWireDelay (DIB12_ipd, DIB12, tipd_DIB12);
        VitalWireDelay (DIB13_ipd, DIB13, tipd_DIB13);
        VitalWireDelay (DIB14_ipd, DIB14, tipd_DIB14);
        VitalWireDelay (DIB15_ipd, DIB15, tipd_DIB15);


        VitalWireDelay (ADB0_ipd, ADB0, tipd_ADB0);
        VitalWireDelay (ADB1_ipd, ADB1, tipd_ADB1);
        VitalWireDelay (ADB2_ipd, ADB2, tipd_ADB2);
        VitalWireDelay (ADB3_ipd, ADB3, tipd_ADB3);
        VitalWireDelay (ADB4_ipd, ADB4, tipd_ADB4);
        VitalWireDelay (ADB5_ipd, ADB5, tipd_ADB5);
        VitalWireDelay (ADB6_ipd, ADB6, tipd_ADB6);
        VitalWireDelay (ADB7_ipd, ADB7, tipd_ADB7);
        VitalWireDelay (ADB8_ipd, ADB8, tipd_ADB8);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CENA_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_WRA_CLKA_posedge     : std_ulogic  := '0';

        variable Tviol_CENB_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_WRB_CLKB_posedge      : std_ulogic  := '0';


        variable Tviol_DIA0_CLKA_posedge    : std_ulogic  := '0';

        variable Tviol_ADA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA3_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA4_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA5_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA6_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA7_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA8_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA9_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA10_CLKA_posedge   : std_ulogic  := '0';
        variable Tviol_ADA11_CLKA_posedge   : std_ulogic  := '0';
        variable Tviol_ADA12_CLKA_posedge   : std_ulogic  := '0';

        variable Tviol_DIB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB8_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB9_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB10_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB11_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB12_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB13_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB14_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB15_CLKB_posedge    : std_ulogic  := '0';


        variable Tviol_ADB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB8_CLKB_posedge    : std_ulogic  := '0';

        variable Tviol_RSTA_CLKA_posedge_posedge : std_ulogic  := '0';
        variable Tviol_RSTB_CLKB_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CENA_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRA_CLKA_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CENB_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRB_CLKB_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB9_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB10_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB11_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB12_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB13_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB14_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB15_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA4_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA5_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA6_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA7_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA8_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA9_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA10_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA11_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA12_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RSTA_CLKA_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RSTB_CLKB_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLKA       : std_ulogic := '0';
        variable PInfo_CLKA       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_CLKB       : std_ulogic := '0';
        variable PInfo_CLkB       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTA        : std_ulogic := '0';
        variable PInfo_RSTA        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTB        : std_ulogic := '0';
        variable PInfo_RSTB        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DOA0_zd         : std_ulogic := 'X';
        variable DOB0_zd         : std_ulogic := 'X';
        variable DOB1_zd         : std_ulogic := 'X';
        variable DOB2_zd         : std_ulogic := 'X';
        variable DOB3_zd         : std_ulogic := 'X';
        variable DOB4_zd         : std_ulogic := 'X';
        variable DOB5_zd         : std_ulogic := 'X';
        variable DOB6_zd         : std_ulogic := 'X';
        variable DOB7_zd         : std_ulogic := 'X';
        variable DOB8_zd         : std_ulogic := 'X';
        variable DOB9_zd         : std_ulogic := 'X';
        variable DOB10_zd         : std_ulogic := 'X';
        variable DOB11_zd         : std_ulogic := 'X';
        variable DOB12_zd         : std_ulogic := 'X';
        variable DOB13_zd         : std_ulogic := 'X';
        variable DOB14_zd         : std_ulogic := 'X';
        variable DOB15_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CENA_CLKA_posedge,
          TimingData              => Tmkr_CENA_CLKA_posedge,
          TestSignal              => CENA_ipd,
          TestSignalName          => "CENA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENA_CLKA_noedge_posedge,
          SetupLow                => tsetup_CENA_CLKA_noedge_posedge,
          HoldLow                 => thold_CENA_CLKA_noedge_posedge,
          HoldHigh                => thold_CENA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRA_CLKA_posedge,
          TimingData              => Tmkr_WRA_CLKA_posedge,
          TestSignal              => WRA_ipd,
          TestSignalName          => "WRA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRA_CLKA_noedge_posedge,
          SetupLow                => tsetup_WRA_CLKA_noedge_posedge,
          HoldLow                 => thold_WRA_CLKA_noedge_posedge,
          HoldHigh                => thold_WRA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA0_CLKA_posedge,
          TimingData              => Tmkr_CSA0_CLKA_posedge,
          TestSignal              => CSA0_ipd,
          TestSignalName          => "CSA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA0_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA0_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA1_CLKA_posedge,
          TimingData              => Tmkr_CSA1_CLKA_posedge,
          TestSignal              => CSA1_ipd,
          TestSignalName          => "CSA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA1_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA1_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CENB_CLKB_posedge,
          TimingData              => Tmkr_CENB_CLKB_posedge,
          TestSignal              => CENB_ipd,
          TestSignalName          => "CENB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENB_CLKB_noedge_posedge,
          SetupLow                => tsetup_CENB_CLKB_noedge_posedge,
          HoldLow                 => thold_CENB_CLKB_noedge_posedge,
          HoldHigh                => thold_CENB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRB_CLKB_posedge,
          TimingData              => Tmkr_WRB_CLKB_posedge,
          TestSignal              => WRB_ipd,
          TestSignalName          => "WRB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRB_CLKB_noedge_posedge,
          SetupLow                => tsetup_WRB_CLKB_noedge_posedge,
          HoldLow                 => thold_WRB_CLKB_noedge_posedge,
          HoldHigh                => thold_WRB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB0_CLKB_posedge,
          TimingData              => Tmkr_CSB0_CLKB_posedge,
          TestSignal              => CSB0_ipd,
          TestSignalName          => "CSB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB0_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB0_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB1_CLKB_posedge,
          TimingData              => Tmkr_CSB1_CLKB_posedge,
          TestSignal              => CSB1_ipd,
          TestSignalName          => "CSB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB1_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB1_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA0_CLKA_posedge,
          TimingData              => Tmkr_DIA0_CLKA_posedge,
          TestSignal              => DIA0_ipd,
          TestSignalName          => "DIA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA0_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA0_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA0_CLKA_posedge,
          TimingData              => Tmkr_ADA0_CLKA_posedge,
          TestSignal              => ADA0_ipd,
          TestSignalName          => "ADA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA0_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA0_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA1_CLKA_posedge,
          TimingData              => Tmkr_ADA1_CLKA_posedge,
          TestSignal              => ADA1_ipd,
          TestSignalName          => "ADA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA1_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA1_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA2_CLKA_posedge,
          TimingData              => Tmkr_ADA2_CLKA_posedge,
          TestSignal              => ADA2_ipd,
          TestSignalName          => "ADA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA2_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA2_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA3_CLKA_posedge,
          TimingData              => Tmkr_ADA3_CLKA_posedge,
          TestSignal              => ADA3_ipd,
          TestSignalName          => "ADA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA3_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA3_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA4_CLKA_posedge,
          TimingData              => Tmkr_ADA4_CLKA_posedge,
          TestSignal              => ADA4_ipd,
          TestSignalName          => "ADA4",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA4_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA4_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA4_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA4_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA5_CLKA_posedge,
          TimingData              => Tmkr_ADA5_CLKA_posedge,
          TestSignal              => ADA5_ipd,
          TestSignalName          => "ADA5",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA5_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA5_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA5_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA5_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA6_CLKA_posedge,
          TimingData              => Tmkr_ADA6_CLKA_posedge,
          TestSignal              => ADA6_ipd,
          TestSignalName          => "ADA6",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA6_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA6_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA6_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA6_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA7_CLKA_posedge,
          TimingData              => Tmkr_ADA7_CLKA_posedge,
          TestSignal              => ADA7_ipd,
          TestSignalName          => "ADA7",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA7_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA7_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA7_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA7_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA8_CLKA_posedge,
          TimingData              => Tmkr_ADA8_CLKA_posedge,
          TestSignal              => ADA8_ipd,
          TestSignalName          => "ADA8",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA8_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA8_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA8_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA8_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA9_CLKA_posedge,
          TimingData              => Tmkr_ADA9_CLKA_posedge,
          TestSignal              => ADA9_ipd,
          TestSignalName          => "ADA9",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA9_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA9_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA9_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA9_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA10_CLKA_posedge,
          TimingData              => Tmkr_ADA10_CLKA_posedge,
          TestSignal              => ADA10_ipd,
          TestSignalName          => "ADA10",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA10_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA10_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA10_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA10_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA11_CLKA_posedge,
          TimingData              => Tmkr_ADA11_CLKA_posedge,
          TestSignal              => ADA11_ipd,
          TestSignalName          => "ADA11",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA11_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA11_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA11_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA11_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA12_CLKA_posedge,
          TimingData              => Tmkr_ADA12_CLKA_posedge,
          TestSignal              => ADA12_ipd,
          TestSignalName          => "ADA12",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA12_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA12_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA12_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA12_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB0_CLKB_posedge,
          TimingData              => Tmkr_DIB0_CLKB_posedge,
          TestSignal              => DIB0_ipd,
          TestSignalName          => "DIB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB0_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB0_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB1_CLKB_posedge,
          TimingData              => Tmkr_DIB1_CLKB_posedge,
          TestSignal              => DIB1_ipd,
          TestSignalName          => "DIB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB1_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB1_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB2_CLKB_posedge,
          TimingData              => Tmkr_DIB2_CLKB_posedge,
          TestSignal              => DIB2_ipd,
          TestSignalName          => "DIB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB2_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB2_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB3_CLKB_posedge,
          TimingData              => Tmkr_DIB3_CLKB_posedge,
          TestSignal              => DIB3_ipd,
          TestSignalName          => "DIB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB3_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB3_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB4_CLKB_posedge,
          TimingData              => Tmkr_DIB4_CLKB_posedge,
          TestSignal              => DIB4_ipd,
          TestSignalName          => "DIB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB4_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB4_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB5_CLKB_posedge,
          TimingData              => Tmkr_DIB5_CLKB_posedge,
          TestSignal              => DIB5_ipd,
          TestSignalName          => "DIB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB5_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB5_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB6_CLKB_posedge,
          TimingData              => Tmkr_DIB6_CLKB_posedge,
          TestSignal              => DIB6_ipd,
          TestSignalName          => "DIB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB6_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB6_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB7_CLKB_posedge,
          TimingData              => Tmkr_DIB7_CLKB_posedge,
          TestSignal              => DIB7_ipd,
          TestSignalName          => "DIB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB7_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB7_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB8_CLKB_posedge,
          TimingData              => Tmkr_DIB8_CLKB_posedge,
          TestSignal              => DIB8_ipd,
          TestSignalName          => "DIB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB8_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB8_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB9_CLKB_posedge,
          TimingData              => Tmkr_DIB9_CLKB_posedge,
          TestSignal              => DIB9_ipd,
          TestSignalName          => "DIB9",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB9_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB9_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB9_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB9_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB10_CLKB_posedge,
          TimingData              => Tmkr_DIB10_CLKB_posedge,
          TestSignal              => DIB10_ipd,
          TestSignalName          => "DIB10",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB10_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB10_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB10_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB10_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB11_CLKB_posedge,
          TimingData              => Tmkr_DIB11_CLKB_posedge,
          TestSignal              => DIB11_ipd,
          TestSignalName          => "DIB11",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB11_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB11_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB11_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB11_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB12_CLKB_posedge,
          TimingData              => Tmkr_DIB12_CLKB_posedge,
          TestSignal              => DIB12_ipd,
          TestSignalName          => "DIB12",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB12_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB12_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB12_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB12_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB13_CLKB_posedge,
          TimingData              => Tmkr_DIB13_CLKB_posedge,
          TestSignal              => DIB13_ipd,
          TestSignalName          => "DIB13",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB13_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB13_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB13_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB13_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB14_CLKB_posedge,
          TimingData              => Tmkr_DIB14_CLKB_posedge,
          TestSignal              => DIB14_ipd,
          TestSignalName          => "DIB14",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB14_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB14_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB14_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB14_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB15_CLKB_posedge,
          TimingData              => Tmkr_DIB15_CLKB_posedge,
          TestSignal              => DIB15_ipd,
          TestSignalName          => "DIB15",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB15_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB15_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB15_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB15_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB0_CLKB_posedge,
          TimingData              => Tmkr_ADB0_CLKB_posedge,
          TestSignal              => ADB0_ipd,
          TestSignalName          => "ADB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB0_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB0_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB1_CLKB_posedge,
          TimingData              => Tmkr_ADB1_CLKB_posedge,
          TestSignal              => ADB1_ipd,
          TestSignalName          => "ADB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB1_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB1_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB2_CLKB_posedge,
          TimingData              => Tmkr_ADB2_CLKB_posedge,
          TestSignal              => ADB2_ipd,
          TestSignalName          => "ADB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB2_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB2_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB3_CLKB_posedge,
          TimingData              => Tmkr_ADB3_CLKB_posedge,
          TestSignal              => ADB3_ipd,
          TestSignalName          => "ADB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB3_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB3_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB4_CLKB_posedge,
          TimingData              => Tmkr_ADB4_CLKB_posedge,
          TestSignal              => ADB4_ipd,
          TestSignalName          => "ADB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB4_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB4_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB5_CLKB_posedge,
          TimingData              => Tmkr_ADB5_CLKB_posedge,
          TestSignal              => ADB5_ipd,
          TestSignalName          => "ADB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB5_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB5_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB6_CLKB_posedge,
          TimingData              => Tmkr_ADB6_CLKB_posedge,
          TestSignal              => ADB6_ipd,
          TestSignalName          => "ADB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB6_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB6_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB7_CLKB_posedge,
          TimingData              => Tmkr_ADB7_CLKB_posedge,
          TestSignal              => ADB7_ipd,
          TestSignalName          => "ADB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB7_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB7_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB8_CLKB_posedge,
          TimingData              => Tmkr_ADB8_CLKB_posedge,
          TestSignal              => ADB8_ipd,
          TestSignalName          => "ADB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB8_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB8_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKA,
          PeriodData              => PInfo_CLKA,
          TestSignal              => CLKA_ipd,
          TestSignalName          => "CLKA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKA_posedge,
          PulseWidthLow           => tpw_CLKA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKB,
          PeriodData              => PInfo_CLKB,
          TestSignal              => CLKB_ipd,
          TestSignalName          => "CLKB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKB_posedge,
          PulseWidthLow           => tpw_CLKB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTA,
          PeriodData              => PInfo_RSTA,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTA_posedge,
          PulseWidthLow           => tpw_RSTA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTB,
          PeriodData              => PInfo_RSTB,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTB_posedge,
          PulseWidthLow           => tpw_RSTB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X1_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTA_CLKA_posedge_posedge,
          TimingData              => Tmkr_RSTA_CLKA_posedge_posedge,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName          => "CLKA",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTA_CLKA_posedge_posedge,
          Removal                 => thold_RSTA_CLKA_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTB_CLKB_posedge_posedge,
          TimingData              => Tmkr_RSTB_CLKB_posedge_posedge,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName          => "CLKB",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTB_CLKB_posedge_posedge,
          Removal                 => thold_RSTB_CLKB_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CENA_CLKA_posedge or Tviol_WRA_CLKA_posedge or 
                 Tviol_CSA0_CLKA_posedge or Tviol_CSA1_CLKA_posedge or 
                 Tviol_ADA0_CLKA_posedge or Tviol_ADA1_CLKA_posedge or 
                 Tviol_ADA2_CLKA_posedge or Tviol_ADA3_CLKA_posedge or 
                 Tviol_ADA4_CLKA_posedge or Tviol_ADA5_CLKA_posedge or 
                 Tviol_ADA6_CLKA_posedge or Tviol_ADA7_CLKA_posedge or 
                 Tviol_ADA8_CLKA_posedge or Tviol_ADA9_CLKA_posedge or 
                 Tviol_ADA10_CLKA_posedge or Tviol_ADA11_CLKA_posedge or 
                 Tviol_ADA12_CLKA_posedge or Tviol_DIA0_CLKA_posedge or
                 Tviol_ADB0_CLKB_posedge or Tviol_ADB1_CLKB_posedge or 
                 Tviol_ADB2_CLKB_posedge or Tviol_ADB3_CLKB_posedge or 
                 Tviol_ADB4_CLKB_posedge or Tviol_ADB5_CLKB_posedge or 
                 Tviol_ADB6_CLKB_posedge or Tviol_ADB7_CLKB_posedge or 
                 Tviol_ADB8_CLKB_posedge or
 		 Tviol_DIB0_CLKB_posedge or  Tviol_DIB1_CLKB_posedge or 
 		 Tviol_DIB2_CLKB_posedge or  Tviol_DIB3_CLKB_posedge or 
 		 Tviol_DIB4_CLKB_posedge or  Tviol_DIB5_CLKB_posedge or 
 		 Tviol_DIB6_CLKB_posedge or  Tviol_DIB7_CLKB_posedge or 
 		 Tviol_DIB8_CLKB_posedge or  Tviol_DIB9_CLKB_posedge or 
 		 Tviol_DIB10_CLKB_posedge or  Tviol_DIB11_CLKB_posedge or
 		 Tviol_DIB12_CLKB_posedge or  Tviol_DIB13_CLKB_posedge or 
 		 Tviol_DIB14_CLKB_posedge or  Tviol_DIB15_CLKB_posedge or
                 Pviol_CLKA or Pviol_CLKB or Pviol_RSTA or Pviol_RSTB;

    -------------------------
    --  Functionality Section
    -------------------------

wait on CENA_ipd, CLKA_ipd, WRA_ipd, CSA, RSTA_ipd, DIA, ADA, CENB_ipd, CLKB_ipd, WRB_ipd, CSB, RSTB_ipd, DIB, ADB;

      end process VITALBehavior;

    VitalBehavior_DOA0  : process
      variable DOA0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA0_zd := DOA(0);

    VitalPathDelay01 (
      OutSignal => DOA0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA0",
      OutTemp => DOA0_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA0, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(0);
      end process;

    VitalBehavior_DOB0  : process
      variable DOB0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB0_zd := DOB(0);

    VitalPathDelay01 (
      OutSignal => DOB0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB0",
      OutTemp => DOB0_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB0, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(0);
      end process;

    VitalBehavior_DOB1  : process
      variable DOB1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB1_zd := DOB(1);

    VitalPathDelay01 (
      OutSignal => DOB1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB1",
      OutTemp => DOB1_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB1, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(1);
      end process;

    VitalBehavior_DOB2  : process
      variable DOB2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB2_zd := DOB(2);

    VitalPathDelay01 (
      OutSignal => DOB2,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB2",
      OutTemp => DOB2_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB2, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(2);
      end process;

    VitalBehavior_DOB3  : process
      variable DOB3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB3_zd := DOB(3);

    VitalPathDelay01 (
      OutSignal => DOB3,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB3",
      OutTemp => DOB3_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB3, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(3);
      end process;

    VitalBehavior_DOB4  : process
      variable DOB4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB4_zd := DOB(4);

    VitalPathDelay01 (
      OutSignal => DOB4,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB4",
      OutTemp => DOB4_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB4, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(4);
      end process;

    VitalBehavior_DOB5  : process
      variable DOB5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB5_zd := DOB(5);

    VitalPathDelay01 (
      OutSignal => DOB5,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB5",
      OutTemp => DOB5_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB5, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(5);
      end process;

    VitalBehavior_DOB6  : process
      variable DOB6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB6_zd := DOB(6);

    VitalPathDelay01 (
      OutSignal => DOB6,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB6",
      OutTemp => DOB6_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB6, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(6);
      end process;

    VitalBehavior_DOB7  : process
      variable DOB7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB7_zd := DOB(7);

    VitalPathDelay01 (
      OutSignal => DOB7,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB7",
      OutTemp => DOB7_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB7, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(7);
      end process;

    VitalBehavior_DOB8  : process
      variable DOB8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB8_zd := DOB(8);

    VitalPathDelay01 (
      OutSignal => DOB8,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB8",
      OutTemp => DOB8_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB8, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(8);
      end process;

    VitalBehavior_DOB9  : process
      variable DOB9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB9_zd := DOB(9);

    VitalPathDelay01 (
      OutSignal => DOB9,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB9",
      OutTemp => DOB9_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB9, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(9);
      end process;

    VitalBehavior_DOB10  : process
      variable DOB10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB10_zd := DOB(10);

    VitalPathDelay01 (
      OutSignal => DOB10,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB10",
      OutTemp => DOB10_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB10, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(10);
      end process;

    VitalBehavior_DOB11  : process
      variable DOB11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB11_zd := DOB(11);

    VitalPathDelay01 (
      OutSignal => DOB11,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB11",
      OutTemp => DOB11_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB11, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(11);
      end process;

    VitalBehavior_DOB12  : process
      variable DOB12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB12_zd := DOB(12);

    VitalPathDelay01 (
      OutSignal => DOB12,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB12",
      OutTemp => DOB12_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB12, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(12);
      end process;

    VitalBehavior_DOB13  : process
      variable DOB13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB13_zd := DOB(13);

    VitalPathDelay01 (
      OutSignal => DOB13,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB13",
      OutTemp => DOB13_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB13, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(13);
      end process;

    VitalBehavior_DOB14  : process
      variable DOB14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB14_zd := DOB(14);

    VitalPathDelay01 (
      OutSignal => DOB14,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB14",
      OutTemp => DOB14_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB14, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(14);
      end process;

    VitalBehavior_DOB15  : process
      variable DOB15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB15_zd := DOB(15);

    VitalPathDelay01 (
      OutSignal => DOB15,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB15",
      OutTemp => DOB15_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB15, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(15);
      end process;



	DPRAM_INST: SC_DPRAM_16K
	   generic map(
		ADDR_WIDTH_A => 13,
		DATA_WIDTH_A => 1,
		ADDR_WIDTH_B => 9,
		DATA_WIDTH_B => 16,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CENA => CENA_ipd,
	        CLKA => CLKA_ipd,
	        WRA  => WRA_ipd,
	        CSA  => CSA,
	        RSTA => RSTA_ipd,
	        DIA  => DIA,
	        ADA  => ADA,
	        DOA  => DOA,

	        CENB => CENB_ipd,
	        CLKB => CLKB_ipd,
	        WRB  => WRB_ipd,
	        CSB  => CSB,
	        RSTB => RSTB_ipd,
	        DIB  => DIB,
	        ADB  => ADB,
	        DOB  => DOB);

end VITAL;

configuration CFG_RAMB8K_X1_X16_VITAL of RAMB8K_X1_X16 is
   for VITAL
   end for;
end CFG_RAMB8K_X1_X16_VITAL;



----- CELL RAMB8K_X2_X2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB8K_X2_X2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "dummy";
      tpd_CLKA_DOA0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_CLKB_DOB0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTA_DOA0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTB_DOB0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_CENA_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENA_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRA_CLKA_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRA_CLKA_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CENB_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENB_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRB_CLKB_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRB_CLKB_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_DIA0_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA1_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_DIB0_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB1_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA2_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA3_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA4_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA4_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA5_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA5_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA6_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA6_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA7_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA7_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA8_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA8_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA9_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA9_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA10_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA10_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_ADA11_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA11_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB2_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB3_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB4_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB5_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB6_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB7_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB8_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB9_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB9_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB10_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADB10_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_ADB11_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADB11_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RSTA_CLKA_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTA_CLKA_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTB_CLKB_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTB_CLKB_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLKA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_CLKB_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTB_posedge                   :	VitalDelayType   := 2.0 ns;
      tipd_CENA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRA                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CENB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRB                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CENA                            :	in    STD_ULOGIC;
      CLKA                            :	in    STD_ULOGIC;
      WRA                             :	in    STD_ULOGIC;
      CSA0                            :	in    STD_ULOGIC;
      CSA1                            :	in    STD_ULOGIC;
      RSTA                            :	in    STD_ULOGIC;
      CENB                            :	in    STD_ULOGIC;
      CLKB                            :	in    STD_ULOGIC;
      WRB                             :	in    STD_ULOGIC;
      CSB0                            :	in    STD_ULOGIC;
      CSB1                            :	in    STD_ULOGIC;
      RSTB                            :	in    STD_ULOGIC;
      DIA0                            :	in    STD_ULOGIC;
      DIA1                            :	in    STD_ULOGIC;
      ADA0                            :	in    STD_ULOGIC;
      ADA1                            :	in    STD_ULOGIC;
      ADA2                            :	in    STD_ULOGIC;
      ADA3                            :	in    STD_ULOGIC;
      ADA4                            :	in    STD_ULOGIC;
      ADA5                            :	in    STD_ULOGIC;
      ADA6                            :	in    STD_ULOGIC;
      ADA7                            :	in    STD_ULOGIC;
      ADA8                            :	in    STD_ULOGIC;
      ADA9                            :	in    STD_ULOGIC;
      ADA10                           :	in    STD_ULOGIC;
      ADA11                           :	in    STD_ULOGIC;
      DIB0                            :	in    STD_ULOGIC;
      DIB1                            :	in    STD_ULOGIC;
      ADB0                            :	in    STD_ULOGIC;
      ADB1                            :	in    STD_ULOGIC;
      ADB2                            :	in    STD_ULOGIC;
      ADB3                            :	in    STD_ULOGIC;
      ADB4                            :	in    STD_ULOGIC;
      ADB5                            :	in    STD_ULOGIC;
      ADB6                            :	in    STD_ULOGIC;
      ADB7                            :	in    STD_ULOGIC;
      ADB8                            :	in    STD_ULOGIC;
      ADB9                            :	in    STD_ULOGIC;
      ADB10                           :	in    STD_ULOGIC;
      ADB11                           :	in    STD_ULOGIC;
      DOA0                            :	out   STD_ULOGIC;
      DOA1                            :	out   STD_ULOGIC;
      DOB0                            :	out   STD_ULOGIC;
      DOB1                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB8K_X2_X2 : entity is FALSE;
end RAMB8K_X2_X2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB8K_X2_X2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_DPRAM_16K
	   generic (
		ADDR_WIDTH_A    : integer := 12;
		DATA_WIDTH_A    : integer := 2;
		ADDR_WIDTH_B    : integer := 12;
		DATA_WIDTH_B    : integer := 2;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CENA : in  STD_LOGIC ;
		CLKA : in  STD_LOGIC ;
		WRA  : in  STD_LOGIC ;
		CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTA : in  STD_LOGIC ;
		DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
		ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
		DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

		CENB : in  STD_LOGIC ;
		CLKB : in  STD_LOGIC ;
		WRB  : in  STD_LOGIC ;
		CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTB : in  STD_LOGIC ;
		DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
		ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
		DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
		);
	end component ;

      signal CENA_ipd      : std_ulogic := 'X';
      signal CLKA_ipd      : std_ulogic := 'X';
      signal WRA_ipd       : std_ulogic := 'X';
      signal CSA0_ipd      : std_ulogic := 'X';
      signal CSA1_ipd      : std_ulogic := 'X';
      signal RSTA_ipd      : std_ulogic := 'X';

      signal CENB_ipd      : std_ulogic := 'X';
      signal CLKB_ipd      : std_ulogic := 'X';
      signal WRB_ipd       : std_ulogic := 'X';
      signal CSB0_ipd      : std_ulogic := 'X';
      signal CSB1_ipd      : std_ulogic := 'X';
      signal RSTB_ipd      : std_ulogic := 'X';

      signal DIA0_ipd      : std_ulogic := 'X';
      signal DIA1_ipd      : std_ulogic := 'X';

      signal ADA0_ipd      : std_ulogic := 'X';
      signal ADA1_ipd      : std_ulogic := 'X';
      signal ADA2_ipd      : std_ulogic := 'X';
      signal ADA3_ipd      : std_ulogic := 'X';
      signal ADA4_ipd      : std_ulogic := 'X';
      signal ADA5_ipd      : std_ulogic := 'X';
      signal ADA6_ipd      : std_ulogic := 'X';
      signal ADA7_ipd      : std_ulogic := 'X';
      signal ADA8_ipd      : std_ulogic := 'X';
      signal ADA9_ipd      : std_ulogic := 'X';
      signal ADA10_ipd     : std_ulogic := 'X';
      signal ADA11_ipd     : std_ulogic := 'X';

      signal DIB0_ipd       : std_ulogic := 'X';
      signal DIB1_ipd       : std_ulogic := 'X';

      signal ADB0_ipd      : std_ulogic := 'X';
      signal ADB1_ipd      : std_ulogic := 'X';
      signal ADB2_ipd      : std_ulogic := 'X';
      signal ADB3_ipd      : std_ulogic := 'X';
      signal ADB4_ipd      : std_ulogic := 'X';
      signal ADB5_ipd      : std_ulogic := 'X';
      signal ADB6_ipd      : std_ulogic := 'X';
      signal ADB7_ipd      : std_ulogic := 'X';
      signal ADB8_ipd      : std_ulogic := 'X';
      signal ADB9_ipd      : std_ulogic := 'X';
      signal ADB10_ipd     : std_ulogic := 'X';
      signal ADB11_ipd     : std_ulogic := 'X';

	signal CSA : std_logic_vector (1 downto 0);
	signal CSB : std_logic_vector (1 downto 0);
	signal DIA : std_logic_vector (1 downto 0);
	signal DOA : std_logic_vector (1 downto 0);
	signal DIB : std_logic_vector (1 downto 0);
	signal DOB : std_logic_vector (1 downto 0);
	signal ADA : std_logic_vector (11 downto 0);
	signal ADB : std_logic_vector (11 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);

begin 

	CSA <= CSA1_ipd & CSA0_ipd;
	CSB <= CSB1_ipd & CSB0_ipd;
	DIA <= DIA1_ipd & DIA0_ipd;
	DIB <= DIB1_ipd & DIB0_ipd;
	ADA <= ADA11_ipd & ADA10_ipd & ADA9_ipd & ADA8_ipd & ADA7_ipd & ADA6_ipd & ADA5_ipd & ADA4_ipd & ADA3_ipd & ADA2_ipd & ADA1_ipd & ADA0_ipd;
	ADB <= ADB11_ipd & ADB10_ipd & ADB9_ipd & ADB8_ipd & ADB7_ipd & ADB6_ipd & ADB5_ipd & ADB4_ipd & ADB3_ipd & ADB2_ipd & ADB1_ipd & ADB0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CENA_ipd, CENA, tipd_CENA);
        VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
        VitalWireDelay (CSA0_ipd, CSA0, tipd_CSA0);
        VitalWireDelay (CSA1_ipd, CSA1, tipd_CSA1);
        VitalWireDelay (WRA_ipd, WRA, tipd_WRA);
        VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);

        VitalWireDelay (CENB_ipd, CENB, tipd_CENB);
        VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
        VitalWireDelay (CSB0_ipd, CSB0, tipd_CSB0);
        VitalWireDelay (CSB1_ipd, CSB1, tipd_CSB1);
        VitalWireDelay (WRB_ipd, WRB, tipd_WRB);
        VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);

        VitalWireDelay (DIA0_ipd, DIA0, tipd_DIA0);
        VitalWireDelay (DIA1_ipd, DIA1, tipd_DIA1);

        VitalWireDelay (ADA0_ipd, ADA0, tipd_ADA0);
        VitalWireDelay (ADA1_ipd, ADA1, tipd_ADA1);
        VitalWireDelay (ADA2_ipd, ADA2, tipd_ADA2);
        VitalWireDelay (ADA3_ipd, ADA3, tipd_ADA3);
        VitalWireDelay (ADA4_ipd, ADA4, tipd_ADA4);
        VitalWireDelay (ADA5_ipd, ADA5, tipd_ADA5);
        VitalWireDelay (ADA6_ipd, ADA6, tipd_ADA6);
        VitalWireDelay (ADA7_ipd, ADA7, tipd_ADA7);
        VitalWireDelay (ADA8_ipd, ADA8, tipd_ADA8);
        VitalWireDelay (ADA9_ipd, ADA9, tipd_ADA9);
        VitalWireDelay (ADA10_ipd, ADA10, tipd_ADA10);
        VitalWireDelay (ADA11_ipd, ADA11, tipd_ADA11);

        VitalWireDelay (DIB0_ipd, DIB0, tipd_DIB0);
        VitalWireDelay (DIB1_ipd, DIB1, tipd_DIB1);

        VitalWireDelay (ADB0_ipd, ADB0, tipd_ADB0);
        VitalWireDelay (ADB1_ipd, ADB1, tipd_ADB1);
        VitalWireDelay (ADB2_ipd, ADB2, tipd_ADB2);
        VitalWireDelay (ADB3_ipd, ADB3, tipd_ADB3);
        VitalWireDelay (ADB4_ipd, ADB4, tipd_ADB4);
        VitalWireDelay (ADB5_ipd, ADB5, tipd_ADB5);
        VitalWireDelay (ADB6_ipd, ADB6, tipd_ADB6);
        VitalWireDelay (ADB7_ipd, ADB7, tipd_ADB7);
        VitalWireDelay (ADB8_ipd, ADB8, tipd_ADB8);
        VitalWireDelay (ADB9_ipd, ADB9, tipd_ADB9);
        VitalWireDelay (ADB10_ipd, ADB10, tipd_ADB10);
        VitalWireDelay (ADB11_ipd, ADB11, tipd_ADB11);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CENA_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_WRA_CLKA_posedge     : std_ulogic  := '0';

        variable Tviol_CENB_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_WRB_CLKB_posedge      : std_ulogic  := '0';


        variable Tviol_DIA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA1_CLKA_posedge    : std_ulogic  := '0';


        variable Tviol_ADA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA3_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA4_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA5_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA6_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA7_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA8_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA9_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA10_CLKA_posedge   : std_ulogic  := '0';
        variable Tviol_ADA11_CLKA_posedge   : std_ulogic  := '0';

        variable Tviol_DIB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB1_CLKB_posedge    : std_ulogic  := '0';

        variable Tviol_ADB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB8_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB9_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB10_CLKB_posedge   : std_ulogic  := '0';
        variable Tviol_ADB11_CLKB_posedge   : std_ulogic  := '0';

        variable Tviol_RSTA_CLKA_posedge_posedge : std_ulogic  := '0';
        variable Tviol_RSTB_CLKB_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CENA_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRA_CLKA_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CENB_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRB_CLKB_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA4_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA5_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA6_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA7_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA8_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA9_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA10_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA11_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB9_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB10_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB11_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RSTA_CLKA_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RSTB_CLKB_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLKA       : std_ulogic := '0';
        variable PInfo_CLKA       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_CLKB       : std_ulogic := '0';
        variable PInfo_CLkB       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTA        : std_ulogic := '0';
        variable PInfo_RSTA        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTB        : std_ulogic := '0';
        variable PInfo_RSTB        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DOA0_zd         : std_ulogic := 'X';
        variable DOA1_zd         : std_ulogic := 'X';
        variable DOB0_zd         : std_ulogic := 'X';
        variable DOB1_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CENA_CLKA_posedge,
          TimingData              => Tmkr_CENA_CLKA_posedge,
          TestSignal              => CENA_ipd,
          TestSignalName          => "CENA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENA_CLKA_noedge_posedge,
          SetupLow                => tsetup_CENA_CLKA_noedge_posedge,
          HoldLow                 => thold_CENA_CLKA_noedge_posedge,
          HoldHigh                => thold_CENA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRA_CLKA_posedge,
          TimingData              => Tmkr_WRA_CLKA_posedge,
          TestSignal              => WRA_ipd,
          TestSignalName          => "WRA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRA_CLKA_noedge_posedge,
          SetupLow                => tsetup_WRA_CLKA_noedge_posedge,
          HoldLow                 => thold_WRA_CLKA_noedge_posedge,
          HoldHigh                => thold_WRA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA0_CLKA_posedge,
          TimingData              => Tmkr_CSA0_CLKA_posedge,
          TestSignal              => CSA0_ipd,
          TestSignalName          => "CSA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA0_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA0_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA1_CLKA_posedge,
          TimingData              => Tmkr_CSA1_CLKA_posedge,
          TestSignal              => CSA1_ipd,
          TestSignalName          => "CSA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA1_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA1_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CENB_CLKB_posedge,
          TimingData              => Tmkr_CENB_CLKB_posedge,
          TestSignal              => CENB_ipd,
          TestSignalName          => "CENB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENB_CLKB_noedge_posedge,
          SetupLow                => tsetup_CENB_CLKB_noedge_posedge,
          HoldLow                 => thold_CENB_CLKB_noedge_posedge,
          HoldHigh                => thold_CENB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRB_CLKB_posedge,
          TimingData              => Tmkr_WRB_CLKB_posedge,
          TestSignal              => WRB_ipd,
          TestSignalName          => "WRB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRB_CLKB_noedge_posedge,
          SetupLow                => tsetup_WRB_CLKB_noedge_posedge,
          HoldLow                 => thold_WRB_CLKB_noedge_posedge,
          HoldHigh                => thold_WRB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB0_CLKB_posedge,
          TimingData              => Tmkr_CSB0_CLKB_posedge,
          TestSignal              => CSB0_ipd,
          TestSignalName          => "CSB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB0_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB0_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB1_CLKB_posedge,
          TimingData              => Tmkr_CSB1_CLKB_posedge,
          TestSignal              => CSB1_ipd,
          TestSignalName          => "CSB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB1_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB1_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA0_CLKA_posedge,
          TimingData              => Tmkr_DIA0_CLKA_posedge,
          TestSignal              => DIA0_ipd,
          TestSignalName          => "DIA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA0_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA0_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA1_CLKA_posedge,
          TimingData              => Tmkr_DIA1_CLKA_posedge,
          TestSignal              => DIA1_ipd,
          TestSignalName          => "DIA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA1_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA1_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA0_CLKA_posedge,
          TimingData              => Tmkr_ADA0_CLKA_posedge,
          TestSignal              => ADA0_ipd,
          TestSignalName          => "ADA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA0_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA0_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA1_CLKA_posedge,
          TimingData              => Tmkr_ADA1_CLKA_posedge,
          TestSignal              => ADA1_ipd,
          TestSignalName          => "ADA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA1_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA1_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA2_CLKA_posedge,
          TimingData              => Tmkr_ADA2_CLKA_posedge,
          TestSignal              => ADA2_ipd,
          TestSignalName          => "ADA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA2_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA2_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA3_CLKA_posedge,
          TimingData              => Tmkr_ADA3_CLKA_posedge,
          TestSignal              => ADA3_ipd,
          TestSignalName          => "ADA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA3_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA3_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA4_CLKA_posedge,
          TimingData              => Tmkr_ADA4_CLKA_posedge,
          TestSignal              => ADA4_ipd,
          TestSignalName          => "ADA4",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA4_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA4_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA4_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA4_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA5_CLKA_posedge,
          TimingData              => Tmkr_ADA5_CLKA_posedge,
          TestSignal              => ADA5_ipd,
          TestSignalName          => "ADA5",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA5_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA5_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA5_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA5_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA6_CLKA_posedge,
          TimingData              => Tmkr_ADA6_CLKA_posedge,
          TestSignal              => ADA6_ipd,
          TestSignalName          => "ADA6",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA6_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA6_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA6_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA6_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA7_CLKA_posedge,
          TimingData              => Tmkr_ADA7_CLKA_posedge,
          TestSignal              => ADA7_ipd,
          TestSignalName          => "ADA7",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA7_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA7_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA7_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA7_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA8_CLKA_posedge,
          TimingData              => Tmkr_ADA8_CLKA_posedge,
          TestSignal              => ADA8_ipd,
          TestSignalName          => "ADA8",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA8_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA8_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA8_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA8_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA9_CLKA_posedge,
          TimingData              => Tmkr_ADA9_CLKA_posedge,
          TestSignal              => ADA9_ipd,
          TestSignalName          => "ADA9",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA9_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA9_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA9_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA9_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA10_CLKA_posedge,
          TimingData              => Tmkr_ADA10_CLKA_posedge,
          TestSignal              => ADA10_ipd,
          TestSignalName          => "ADA10",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA10_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA10_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA10_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA10_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA11_CLKA_posedge,
          TimingData              => Tmkr_ADA11_CLKA_posedge,
          TestSignal              => ADA11_ipd,
          TestSignalName          => "ADA11",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA11_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA11_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA11_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA11_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB0_CLKB_posedge,
          TimingData              => Tmkr_DIB0_CLKB_posedge,
          TestSignal              => DIB0_ipd,
          TestSignalName          => "DIB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB0_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB0_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB1_CLKB_posedge,
          TimingData              => Tmkr_DIB1_CLKB_posedge,
          TestSignal              => DIB1_ipd,
          TestSignalName          => "DIB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB1_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB1_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB0_CLKB_posedge,
          TimingData              => Tmkr_ADB0_CLKB_posedge,
          TestSignal              => ADB0_ipd,
          TestSignalName          => "ADB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB0_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB0_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB1_CLKB_posedge,
          TimingData              => Tmkr_ADB1_CLKB_posedge,
          TestSignal              => ADB1_ipd,
          TestSignalName          => "ADB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB1_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB1_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB2_CLKB_posedge,
          TimingData              => Tmkr_ADB2_CLKB_posedge,
          TestSignal              => ADB2_ipd,
          TestSignalName          => "ADB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB2_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB2_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB3_CLKB_posedge,
          TimingData              => Tmkr_ADB3_CLKB_posedge,
          TestSignal              => ADB3_ipd,
          TestSignalName          => "ADB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB3_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB3_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB4_CLKB_posedge,
          TimingData              => Tmkr_ADB4_CLKB_posedge,
          TestSignal              => ADB4_ipd,
          TestSignalName          => "ADB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB4_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB4_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB5_CLKB_posedge,
          TimingData              => Tmkr_ADB5_CLKB_posedge,
          TestSignal              => ADB5_ipd,
          TestSignalName          => "ADB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB5_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB5_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB6_CLKB_posedge,
          TimingData              => Tmkr_ADB6_CLKB_posedge,
          TestSignal              => ADB6_ipd,
          TestSignalName          => "ADB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB6_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB6_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB7_CLKB_posedge,
          TimingData              => Tmkr_ADB7_CLKB_posedge,
          TestSignal              => ADB7_ipd,
          TestSignalName          => "ADB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB7_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB7_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB8_CLKB_posedge,
          TimingData              => Tmkr_ADB8_CLKB_posedge,
          TestSignal              => ADB8_ipd,
          TestSignalName          => "ADB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB8_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB8_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB9_CLKB_posedge,
          TimingData              => Tmkr_ADB9_CLKB_posedge,
          TestSignal              => ADB9_ipd,
          TestSignalName          => "ADB9",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB9_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB9_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB9_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB9_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB10_CLKB_posedge,
          TimingData              => Tmkr_ADB10_CLKB_posedge,
          TestSignal              => ADB10_ipd,
          TestSignalName          => "ADB10",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB10_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB10_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB10_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB10_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB11_CLKB_posedge,
          TimingData              => Tmkr_ADB11_CLKB_posedge,
          TestSignal              => ADB11_ipd,
          TestSignalName          => "ADB11",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB11_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB11_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB11_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB11_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKA,
          PeriodData              => PInfo_CLKA,
          TestSignal              => CLKA_ipd,
          TestSignalName          => "CLKA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKA_posedge,
          PulseWidthLow           => tpw_CLKA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKB,
          PeriodData              => PInfo_CLKB,
          TestSignal              => CLKB_ipd,
          TestSignalName          => "CLKB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKB_posedge,
          PulseWidthLow           => tpw_CLKB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTA,
          PeriodData              => PInfo_RSTA,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTA_posedge,
          PulseWidthLow           => tpw_RSTA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTB,
          PeriodData              => PInfo_RSTB,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTB_posedge,
          PulseWidthLow           => tpw_RSTB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X2_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTA_CLKA_posedge_posedge,
          TimingData              => Tmkr_RSTA_CLKA_posedge_posedge,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName          => "CLKA",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTA_CLKA_posedge_posedge,
          Removal                 => thold_RSTA_CLKA_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTB_CLKB_posedge_posedge,
          TimingData              => Tmkr_RSTB_CLKB_posedge_posedge,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName          => "CLKB",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTB_CLKB_posedge_posedge,
          Removal                 => thold_RSTB_CLKB_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CENA_CLKA_posedge or Tviol_WRA_CLKA_posedge or 
                 Tviol_CSA0_CLKA_posedge or Tviol_CSA1_CLKA_posedge or 
                 Tviol_ADA0_CLKA_posedge or Tviol_ADA1_CLKA_posedge or 
                 Tviol_ADA2_CLKA_posedge or Tviol_ADA3_CLKA_posedge or 
                 Tviol_ADA4_CLKA_posedge or Tviol_ADA5_CLKA_posedge or 
                 Tviol_ADA6_CLKA_posedge or Tviol_ADA7_CLKA_posedge or 
                 Tviol_ADA8_CLKA_posedge or Tviol_ADA9_CLKA_posedge or 
                 Tviol_ADA10_CLKA_posedge or Tviol_ADA11_CLKA_posedge or 
		 Tviol_DIA0_CLKA_posedge or  Tviol_DIA1_CLKA_posedge or
                 Tviol_ADB0_CLKB_posedge or Tviol_ADB1_CLKB_posedge or 
                 Tviol_ADB2_CLKB_posedge or Tviol_ADB3_CLKB_posedge or 
                 Tviol_ADB4_CLKB_posedge or Tviol_ADB5_CLKB_posedge or 
                 Tviol_ADB6_CLKB_posedge or Tviol_ADB7_CLKB_posedge or 
                 Tviol_ADB8_CLKB_posedge or Tviol_ADB9_CLKB_posedge or 
                 Tviol_ADB10_CLKB_posedge or Tviol_ADB11_CLKB_posedge or
 		 Tviol_DIB0_CLKB_posedge or  Tviol_DIB1_CLKB_posedge or 
                 Pviol_CLKA or Pviol_CLKB or Pviol_RSTA or Pviol_RSTB;

    -------------------------
    --  Functionality Section
    -------------------------

wait on CENA_ipd, CLKA_ipd, WRA_ipd, CSA, RSTA_ipd, DIA, ADA, CENB_ipd, CLKB_ipd, WRB_ipd, CSB, RSTB_ipd, DIB, ADB;

      end process VITALBehavior;

    VitalBehavior_DOA0  : process
      variable DOA0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA0_zd := DOA(0);

    VitalPathDelay01 (
      OutSignal => DOA0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA0",
      OutTemp => DOA0_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA0, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(0);
      end process;

    VitalBehavior_DOA1  : process
      variable DOA1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA1_zd := DOA(1);

    VitalPathDelay01 (
      OutSignal => DOA1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA1",
      OutTemp => DOA1_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA1, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(1);
      end process;

    VitalBehavior_DOB0  : process
      variable DOB0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB0_zd := DOB(0);

    VitalPathDelay01 (
      OutSignal => DOB0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB0",
      OutTemp => DOB0_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB0, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(0);
      end process;

    VitalBehavior_DOB1  : process
      variable DOB1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB1_zd := DOB(1);

    VitalPathDelay01 (
      OutSignal => DOB1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB1",
      OutTemp => DOB1_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB1, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(1);
      end process;



	DPRAM_INST: SC_DPRAM_16K
	   generic map(
		ADDR_WIDTH_A => 12,
		DATA_WIDTH_A => 2,
		ADDR_WIDTH_B => 12,
		DATA_WIDTH_B => 2,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CENA => CENA_ipd,
	        CLKA => CLKA_ipd,
	        WRA  => WRA_ipd,
	        CSA  => CSA,
	        RSTA => RSTA_ipd,
	        DIA  => DIA,
	        ADA  => ADA,
	        DOA  => DOA,

	        CENB => CENB_ipd,
	        CLKB => CLKB_ipd,
	        WRB  => WRB_ipd,
	        CSB  => CSB,
	        RSTB => RSTB_ipd,
	        DIB  => DIB,
	        ADB  => ADB,
	        DOB  => DOB);

end VITAL;

configuration CFG_RAMB8K_X2_X2_VITAL of RAMB8K_X2_X2 is
   for VITAL
   end for;
end CFG_RAMB8K_X2_X2_VITAL;



----- CELL RAMB8K_X2_X4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB8K_X2_X4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "dummy";
      tpd_CLKA_DOA0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_CLKB_DOB0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTA_DOA0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTB_DOB0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_CENA_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENA_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRA_CLKA_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRA_CLKA_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CENB_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENB_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRB_CLKB_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRB_CLKB_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_DIA0_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA1_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;


      tsetup_DIB0_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB1_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB2_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB3_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA2_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA3_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA4_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA4_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA5_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA5_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA6_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA6_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA7_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA7_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA8_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA8_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA9_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA9_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA10_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA10_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_ADA11_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA11_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB2_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB3_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB4_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB5_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB6_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB7_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB8_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB9_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB9_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB10_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADB10_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RSTA_CLKA_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTA_CLKA_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTB_CLKB_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTB_CLKB_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLKA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_CLKB_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTB_posedge                   :	VitalDelayType   := 2.0 ns;
      tipd_CENA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRA                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CENB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRB                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CENA                            :	in    STD_ULOGIC;
      CLKA                            :	in    STD_ULOGIC;
      WRA                             :	in    STD_ULOGIC;
      CSA0                            :	in    STD_ULOGIC;
      CSA1                            :	in    STD_ULOGIC;
      RSTA                            :	in    STD_ULOGIC;
      CENB                            :	in    STD_ULOGIC;
      CLKB                            :	in    STD_ULOGIC;
      WRB                             :	in    STD_ULOGIC;
      CSB0                            :	in    STD_ULOGIC;
      CSB1                            :	in    STD_ULOGIC;
      RSTB                            :	in    STD_ULOGIC;
      DIA0                            :	in    STD_ULOGIC;
      DIA1                            :	in    STD_ULOGIC;
      ADA0                            :	in    STD_ULOGIC;
      ADA1                            :	in    STD_ULOGIC;
      ADA2                            :	in    STD_ULOGIC;
      ADA3                            :	in    STD_ULOGIC;
      ADA4                            :	in    STD_ULOGIC;
      ADA5                            :	in    STD_ULOGIC;
      ADA6                            :	in    STD_ULOGIC;
      ADA7                            :	in    STD_ULOGIC;
      ADA8                            :	in    STD_ULOGIC;
      ADA9                            :	in    STD_ULOGIC;
      ADA10                           :	in    STD_ULOGIC;
      ADA11                           :	in    STD_ULOGIC;
      DIB0                            :	in    STD_ULOGIC;
      DIB1                            :	in    STD_ULOGIC;
      DIB2                            :	in    STD_ULOGIC;
      DIB3                            :	in    STD_ULOGIC;
      ADB0                            :	in    STD_ULOGIC;
      ADB1                            :	in    STD_ULOGIC;
      ADB2                            :	in    STD_ULOGIC;
      ADB3                            :	in    STD_ULOGIC;
      ADB4                            :	in    STD_ULOGIC;
      ADB5                            :	in    STD_ULOGIC;
      ADB6                            :	in    STD_ULOGIC;
      ADB7                            :	in    STD_ULOGIC;
      ADB8                            :	in    STD_ULOGIC;
      ADB9                            :	in    STD_ULOGIC;
      ADB10                           :	in    STD_ULOGIC;
      DOA0                            :	out   STD_ULOGIC;
      DOA1                            :	out   STD_ULOGIC;
      DOB0                            :	out   STD_ULOGIC;
      DOB1                            :	out   STD_ULOGIC;
      DOB2                            :	out   STD_ULOGIC;
      DOB3                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB8K_X2_X4 : entity is FALSE;
end RAMB8K_X2_X4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB8K_X2_X4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_DPRAM_16K
	   generic (
		ADDR_WIDTH_A    : integer := 12;
		DATA_WIDTH_A    : integer := 2;
		ADDR_WIDTH_B    : integer := 11;
		DATA_WIDTH_B    : integer := 4;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CENA : in  STD_LOGIC ;
		CLKA : in  STD_LOGIC ;
		WRA  : in  STD_LOGIC ;
		CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTA : in  STD_LOGIC ;
		DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
		ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
		DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

		CENB : in  STD_LOGIC ;
		CLKB : in  STD_LOGIC ;
		WRB  : in  STD_LOGIC ;
		CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTB : in  STD_LOGIC ;
		DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
		ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
		DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
		);
	end component ;

      signal CENA_ipd      : std_ulogic := 'X';
      signal CLKA_ipd      : std_ulogic := 'X';
      signal WRA_ipd       : std_ulogic := 'X';
      signal CSA0_ipd      : std_ulogic := 'X';
      signal CSA1_ipd      : std_ulogic := 'X';
      signal RSTA_ipd      : std_ulogic := 'X';

      signal CENB_ipd      : std_ulogic := 'X';
      signal CLKB_ipd      : std_ulogic := 'X';
      signal WRB_ipd       : std_ulogic := 'X';
      signal CSB0_ipd      : std_ulogic := 'X';
      signal CSB1_ipd      : std_ulogic := 'X';
      signal RSTB_ipd      : std_ulogic := 'X';

      signal DIA0_ipd      : std_ulogic := 'X';
      signal DIA1_ipd      : std_ulogic := 'X';

      signal ADA0_ipd      : std_ulogic := 'X';
      signal ADA1_ipd      : std_ulogic := 'X';
      signal ADA2_ipd      : std_ulogic := 'X';
      signal ADA3_ipd      : std_ulogic := 'X';
      signal ADA4_ipd      : std_ulogic := 'X';
      signal ADA5_ipd      : std_ulogic := 'X';
      signal ADA6_ipd      : std_ulogic := 'X';
      signal ADA7_ipd      : std_ulogic := 'X';
      signal ADA8_ipd      : std_ulogic := 'X';
      signal ADA9_ipd      : std_ulogic := 'X';
      signal ADA10_ipd     : std_ulogic := 'X';
      signal ADA11_ipd     : std_ulogic := 'X';

      signal DIB0_ipd       : std_ulogic := 'X';
      signal DIB1_ipd       : std_ulogic := 'X';
      signal DIB2_ipd       : std_ulogic := 'X';
      signal DIB3_ipd       : std_ulogic := 'X';

      signal ADB0_ipd      : std_ulogic := 'X';
      signal ADB1_ipd      : std_ulogic := 'X';
      signal ADB2_ipd      : std_ulogic := 'X';
      signal ADB3_ipd      : std_ulogic := 'X';
      signal ADB4_ipd      : std_ulogic := 'X';
      signal ADB5_ipd      : std_ulogic := 'X';
      signal ADB6_ipd      : std_ulogic := 'X';
      signal ADB7_ipd      : std_ulogic := 'X';
      signal ADB8_ipd      : std_ulogic := 'X';
      signal ADB9_ipd      : std_ulogic := 'X';
      signal ADB10_ipd     : std_ulogic := 'X';

	signal CSA : std_logic_vector (1 downto 0);
	signal CSB : std_logic_vector (1 downto 0);
	signal DIA : std_logic_vector (1 downto 0);
	signal DOA : std_logic_vector (1 downto 0);
	signal DIB : std_logic_vector (3 downto 0);
	signal DOB : std_logic_vector (3 downto 0);
	signal ADA : std_logic_vector (11 downto 0);
	signal ADB : std_logic_vector (10 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);

begin 

	CSA <= CSA1_ipd & CSA0_ipd;
	CSB <= CSB1_ipd & CSB0_ipd;
	DIA <= DIA1_ipd & DIA0_ipd;
	DIB <= DIB3_ipd & DIB2_ipd & DIB1_ipd & DIB0_ipd;
	ADA <= ADA11_ipd & ADA10_ipd & ADA9_ipd & ADA8_ipd & ADA7_ipd & ADA6_ipd & ADA5_ipd & ADA4_ipd & ADA3_ipd & ADA2_ipd & ADA1_ipd & ADA0_ipd;
	ADB <= ADB10_ipd & ADB9_ipd & ADB8_ipd & ADB7_ipd & ADB6_ipd & ADB5_ipd & ADB4_ipd & ADB3_ipd & ADB2_ipd & ADB1_ipd & ADB0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CENA_ipd, CENA, tipd_CENA);
        VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
        VitalWireDelay (CSA0_ipd, CSA0, tipd_CSA0);
        VitalWireDelay (CSA1_ipd, CSA1, tipd_CSA1);
        VitalWireDelay (WRA_ipd, WRA, tipd_WRA);
        VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);

        VitalWireDelay (CENB_ipd, CENB, tipd_CENB);
        VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
        VitalWireDelay (CSB0_ipd, CSB0, tipd_CSB0);
        VitalWireDelay (CSB1_ipd, CSB1, tipd_CSB1);
        VitalWireDelay (WRB_ipd, WRB, tipd_WRB);
        VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);

        VitalWireDelay (DIA0_ipd, DIA0, tipd_DIA0);
        VitalWireDelay (DIA1_ipd, DIA1, tipd_DIA1);


        VitalWireDelay (ADA0_ipd, ADA0, tipd_ADA0);
        VitalWireDelay (ADA1_ipd, ADA1, tipd_ADA1);
        VitalWireDelay (ADA2_ipd, ADA2, tipd_ADA2);
        VitalWireDelay (ADA3_ipd, ADA3, tipd_ADA3);
        VitalWireDelay (ADA4_ipd, ADA4, tipd_ADA4);
        VitalWireDelay (ADA5_ipd, ADA5, tipd_ADA5);
        VitalWireDelay (ADA6_ipd, ADA6, tipd_ADA6);
        VitalWireDelay (ADA7_ipd, ADA7, tipd_ADA7);
        VitalWireDelay (ADA8_ipd, ADA8, tipd_ADA8);
        VitalWireDelay (ADA9_ipd, ADA9, tipd_ADA9);
        VitalWireDelay (ADA10_ipd, ADA10, tipd_ADA10);
        VitalWireDelay (ADA11_ipd, ADA11, tipd_ADA11);

        VitalWireDelay (DIB0_ipd, DIB0, tipd_DIB0);
        VitalWireDelay (DIB1_ipd, DIB1, tipd_DIB1);
        VitalWireDelay (DIB2_ipd, DIB2, tipd_DIB2);
        VitalWireDelay (DIB3_ipd, DIB3, tipd_DIB3);

        VitalWireDelay (ADB0_ipd, ADB0, tipd_ADB0);
        VitalWireDelay (ADB1_ipd, ADB1, tipd_ADB1);
        VitalWireDelay (ADB2_ipd, ADB2, tipd_ADB2);
        VitalWireDelay (ADB3_ipd, ADB3, tipd_ADB3);
        VitalWireDelay (ADB4_ipd, ADB4, tipd_ADB4);
        VitalWireDelay (ADB5_ipd, ADB5, tipd_ADB5);
        VitalWireDelay (ADB6_ipd, ADB6, tipd_ADB6);
        VitalWireDelay (ADB7_ipd, ADB7, tipd_ADB7);
        VitalWireDelay (ADB8_ipd, ADB8, tipd_ADB8);
        VitalWireDelay (ADB9_ipd, ADB9, tipd_ADB9);
        VitalWireDelay (ADB10_ipd, ADB10, tipd_ADB10);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CENA_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_WRA_CLKA_posedge     : std_ulogic  := '0';

        variable Tviol_CENB_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_WRB_CLKB_posedge      : std_ulogic  := '0';


        variable Tviol_DIA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA1_CLKA_posedge    : std_ulogic  := '0';

        variable Tviol_ADA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA3_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA4_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA5_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA6_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA7_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA8_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA9_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA10_CLKA_posedge   : std_ulogic  := '0';
        variable Tviol_ADA11_CLKA_posedge   : std_ulogic  := '0';

        variable Tviol_DIB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB3_CLKB_posedge    : std_ulogic  := '0';

        variable Tviol_ADB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB8_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB9_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB10_CLKB_posedge   : std_ulogic  := '0';

        variable Tviol_RSTA_CLKA_posedge_posedge : std_ulogic  := '0';
        variable Tviol_RSTB_CLKB_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CENA_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRA_CLKA_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CENB_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRB_CLKB_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA4_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA5_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA6_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA7_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA8_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA9_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA10_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA11_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB9_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB10_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RSTA_CLKA_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RSTB_CLKB_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLKA       : std_ulogic := '0';
        variable PInfo_CLKA       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_CLKB       : std_ulogic := '0';
        variable PInfo_CLkB       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTA        : std_ulogic := '0';
        variable PInfo_RSTA        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTB        : std_ulogic := '0';
        variable PInfo_RSTB        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DOA0_zd         : std_ulogic := 'X';
        variable DOA1_zd         : std_ulogic := 'X';
        variable DOB0_zd         : std_ulogic := 'X';
        variable DOB1_zd         : std_ulogic := 'X';
        variable DOB2_zd         : std_ulogic := 'X';
        variable DOB3_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CENA_CLKA_posedge,
          TimingData              => Tmkr_CENA_CLKA_posedge,
          TestSignal              => CENA_ipd,
          TestSignalName          => "CENA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENA_CLKA_noedge_posedge,
          SetupLow                => tsetup_CENA_CLKA_noedge_posedge,
          HoldLow                 => thold_CENA_CLKA_noedge_posedge,
          HoldHigh                => thold_CENA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRA_CLKA_posedge,
          TimingData              => Tmkr_WRA_CLKA_posedge,
          TestSignal              => WRA_ipd,
          TestSignalName          => "WRA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRA_CLKA_noedge_posedge,
          SetupLow                => tsetup_WRA_CLKA_noedge_posedge,
          HoldLow                 => thold_WRA_CLKA_noedge_posedge,
          HoldHigh                => thold_WRA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA0_CLKA_posedge,
          TimingData              => Tmkr_CSA0_CLKA_posedge,
          TestSignal              => CSA0_ipd,
          TestSignalName          => "CSA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA0_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA0_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA1_CLKA_posedge,
          TimingData              => Tmkr_CSA1_CLKA_posedge,
          TestSignal              => CSA1_ipd,
          TestSignalName          => "CSA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA1_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA1_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CENB_CLKB_posedge,
          TimingData              => Tmkr_CENB_CLKB_posedge,
          TestSignal              => CENB_ipd,
          TestSignalName          => "CENB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENB_CLKB_noedge_posedge,
          SetupLow                => tsetup_CENB_CLKB_noedge_posedge,
          HoldLow                 => thold_CENB_CLKB_noedge_posedge,
          HoldHigh                => thold_CENB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRB_CLKB_posedge,
          TimingData              => Tmkr_WRB_CLKB_posedge,
          TestSignal              => WRB_ipd,
          TestSignalName          => "WRB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRB_CLKB_noedge_posedge,
          SetupLow                => tsetup_WRB_CLKB_noedge_posedge,
          HoldLow                 => thold_WRB_CLKB_noedge_posedge,
          HoldHigh                => thold_WRB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB0_CLKB_posedge,
          TimingData              => Tmkr_CSB0_CLKB_posedge,
          TestSignal              => CSB0_ipd,
          TestSignalName          => "CSB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB0_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB0_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB1_CLKB_posedge,
          TimingData              => Tmkr_CSB1_CLKB_posedge,
          TestSignal              => CSB1_ipd,
          TestSignalName          => "CSB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB1_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB1_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA0_CLKA_posedge,
          TimingData              => Tmkr_DIA0_CLKA_posedge,
          TestSignal              => DIA0_ipd,
          TestSignalName          => "DIA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA0_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA0_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA1_CLKA_posedge,
          TimingData              => Tmkr_DIA1_CLKA_posedge,
          TestSignal              => DIA1_ipd,
          TestSignalName          => "DIA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA1_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA1_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA0_CLKA_posedge,
          TimingData              => Tmkr_ADA0_CLKA_posedge,
          TestSignal              => ADA0_ipd,
          TestSignalName          => "ADA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA0_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA0_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA1_CLKA_posedge,
          TimingData              => Tmkr_ADA1_CLKA_posedge,
          TestSignal              => ADA1_ipd,
          TestSignalName          => "ADA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA1_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA1_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA2_CLKA_posedge,
          TimingData              => Tmkr_ADA2_CLKA_posedge,
          TestSignal              => ADA2_ipd,
          TestSignalName          => "ADA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA2_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA2_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA3_CLKA_posedge,
          TimingData              => Tmkr_ADA3_CLKA_posedge,
          TestSignal              => ADA3_ipd,
          TestSignalName          => "ADA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA3_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA3_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA4_CLKA_posedge,
          TimingData              => Tmkr_ADA4_CLKA_posedge,
          TestSignal              => ADA4_ipd,
          TestSignalName          => "ADA4",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA4_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA4_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA4_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA4_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA5_CLKA_posedge,
          TimingData              => Tmkr_ADA5_CLKA_posedge,
          TestSignal              => ADA5_ipd,
          TestSignalName          => "ADA5",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA5_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA5_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA5_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA5_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA6_CLKA_posedge,
          TimingData              => Tmkr_ADA6_CLKA_posedge,
          TestSignal              => ADA6_ipd,
          TestSignalName          => "ADA6",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA6_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA6_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA6_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA6_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA7_CLKA_posedge,
          TimingData              => Tmkr_ADA7_CLKA_posedge,
          TestSignal              => ADA7_ipd,
          TestSignalName          => "ADA7",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA7_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA7_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA7_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA7_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA8_CLKA_posedge,
          TimingData              => Tmkr_ADA8_CLKA_posedge,
          TestSignal              => ADA8_ipd,
          TestSignalName          => "ADA8",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA8_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA8_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA8_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA8_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA9_CLKA_posedge,
          TimingData              => Tmkr_ADA9_CLKA_posedge,
          TestSignal              => ADA9_ipd,
          TestSignalName          => "ADA9",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA9_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA9_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA9_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA9_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA10_CLKA_posedge,
          TimingData              => Tmkr_ADA10_CLKA_posedge,
          TestSignal              => ADA10_ipd,
          TestSignalName          => "ADA10",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA10_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA10_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA10_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA10_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA11_CLKA_posedge,
          TimingData              => Tmkr_ADA11_CLKA_posedge,
          TestSignal              => ADA11_ipd,
          TestSignalName          => "ADA11",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA11_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA11_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA11_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA11_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB0_CLKB_posedge,
          TimingData              => Tmkr_DIB0_CLKB_posedge,
          TestSignal              => DIB0_ipd,
          TestSignalName          => "DIB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB0_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB0_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB1_CLKB_posedge,
          TimingData              => Tmkr_DIB1_CLKB_posedge,
          TestSignal              => DIB1_ipd,
          TestSignalName          => "DIB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB1_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB1_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB2_CLKB_posedge,
          TimingData              => Tmkr_DIB2_CLKB_posedge,
          TestSignal              => DIB2_ipd,
          TestSignalName          => "DIB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB2_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB2_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB3_CLKB_posedge,
          TimingData              => Tmkr_DIB3_CLKB_posedge,
          TestSignal              => DIB3_ipd,
          TestSignalName          => "DIB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB3_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB3_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB0_CLKB_posedge,
          TimingData              => Tmkr_ADB0_CLKB_posedge,
          TestSignal              => ADB0_ipd,
          TestSignalName          => "ADB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB0_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB0_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB1_CLKB_posedge,
          TimingData              => Tmkr_ADB1_CLKB_posedge,
          TestSignal              => ADB1_ipd,
          TestSignalName          => "ADB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB1_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB1_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB2_CLKB_posedge,
          TimingData              => Tmkr_ADB2_CLKB_posedge,
          TestSignal              => ADB2_ipd,
          TestSignalName          => "ADB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB2_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB2_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB3_CLKB_posedge,
          TimingData              => Tmkr_ADB3_CLKB_posedge,
          TestSignal              => ADB3_ipd,
          TestSignalName          => "ADB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB3_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB3_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB4_CLKB_posedge,
          TimingData              => Tmkr_ADB4_CLKB_posedge,
          TestSignal              => ADB4_ipd,
          TestSignalName          => "ADB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB4_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB4_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB5_CLKB_posedge,
          TimingData              => Tmkr_ADB5_CLKB_posedge,
          TestSignal              => ADB5_ipd,
          TestSignalName          => "ADB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB5_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB5_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB6_CLKB_posedge,
          TimingData              => Tmkr_ADB6_CLKB_posedge,
          TestSignal              => ADB6_ipd,
          TestSignalName          => "ADB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB6_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB6_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB7_CLKB_posedge,
          TimingData              => Tmkr_ADB7_CLKB_posedge,
          TestSignal              => ADB7_ipd,
          TestSignalName          => "ADB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB7_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB7_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB8_CLKB_posedge,
          TimingData              => Tmkr_ADB8_CLKB_posedge,
          TestSignal              => ADB8_ipd,
          TestSignalName          => "ADB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB8_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB8_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB9_CLKB_posedge,
          TimingData              => Tmkr_ADB9_CLKB_posedge,
          TestSignal              => ADB9_ipd,
          TestSignalName          => "ADB9",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB9_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB9_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB9_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB9_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB10_CLKB_posedge,
          TimingData              => Tmkr_ADB10_CLKB_posedge,
          TestSignal              => ADB10_ipd,
          TestSignalName          => "ADB10",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB10_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB10_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB10_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB10_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKA,
          PeriodData              => PInfo_CLKA,
          TestSignal              => CLKA_ipd,
          TestSignalName          => "CLKA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKA_posedge,
          PulseWidthLow           => tpw_CLKA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKB,
          PeriodData              => PInfo_CLKB,
          TestSignal              => CLKB_ipd,
          TestSignalName          => "CLKB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKB_posedge,
          PulseWidthLow           => tpw_CLKB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTA,
          PeriodData              => PInfo_RSTA,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTA_posedge,
          PulseWidthLow           => tpw_RSTA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTB,
          PeriodData              => PInfo_RSTB,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTB_posedge,
          PulseWidthLow           => tpw_RSTB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X2_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTA_CLKA_posedge_posedge,
          TimingData              => Tmkr_RSTA_CLKA_posedge_posedge,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName          => "CLKA",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTA_CLKA_posedge_posedge,
          Removal                 => thold_RSTA_CLKA_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTB_CLKB_posedge_posedge,
          TimingData              => Tmkr_RSTB_CLKB_posedge_posedge,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName          => "CLKB",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTB_CLKB_posedge_posedge,
          Removal                 => thold_RSTB_CLKB_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CENA_CLKA_posedge or Tviol_WRA_CLKA_posedge or 
                 Tviol_CSA0_CLKA_posedge or Tviol_CSA1_CLKA_posedge or 
                 Tviol_ADA0_CLKA_posedge or Tviol_ADA1_CLKA_posedge or 
                 Tviol_ADA2_CLKA_posedge or Tviol_ADA3_CLKA_posedge or 
                 Tviol_ADA4_CLKA_posedge or Tviol_ADA5_CLKA_posedge or 
                 Tviol_ADA6_CLKA_posedge or Tviol_ADA7_CLKA_posedge or 
                 Tviol_ADA8_CLKA_posedge or Tviol_ADA9_CLKA_posedge or 
                 Tviol_ADA10_CLKA_posedge or Tviol_ADA11_CLKA_posedge or 
                 Tviol_DIA0_CLKA_posedge or Tviol_DIA1_CLKA_posedge or
                 Tviol_ADB0_CLKB_posedge or Tviol_ADB1_CLKB_posedge or 
                 Tviol_ADB2_CLKB_posedge or Tviol_ADB3_CLKB_posedge or 
                 Tviol_ADB4_CLKB_posedge or Tviol_ADB5_CLKB_posedge or 
                 Tviol_ADB6_CLKB_posedge or Tviol_ADB7_CLKB_posedge or 
                 Tviol_ADB8_CLKB_posedge or Tviol_ADB9_CLKB_posedge or 
                 Tviol_ADB10_CLKB_posedge or 
 		 Tviol_DIB0_CLKB_posedge or  Tviol_DIB1_CLKB_posedge or 
 		 Tviol_DIB2_CLKB_posedge or  Tviol_DIB3_CLKB_posedge or 
                 Pviol_CLKA or Pviol_CLKB or Pviol_RSTA or Pviol_RSTB;

    -------------------------
    --  Functionality Section
    -------------------------

wait on CENA_ipd, CLKA_ipd, WRA_ipd, CSA, RSTA_ipd, DIA, ADA, CENB_ipd, CLKB_ipd, WRB_ipd, CSB, RSTB_ipd, DIB, ADB;

      end process VITALBehavior;

    VitalBehavior_DOA0  : process
      variable DOA0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA0_zd := DOA(0);

    VitalPathDelay01 (
      OutSignal => DOA0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA0",
      OutTemp => DOA0_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA0, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(0);
      end process;

    VitalBehavior_DOA1  : process
      variable DOA1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA1_zd := DOA(1);

    VitalPathDelay01 (
      OutSignal => DOA1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA1",
      OutTemp => DOA1_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA1, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(1);
      end process;

    VitalBehavior_DOB0  : process
      variable DOB0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB0_zd := DOB(0);

    VitalPathDelay01 (
      OutSignal => DOB0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB0",
      OutTemp => DOB0_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB0, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(0);
      end process;

    VitalBehavior_DOB1  : process
      variable DOB1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB1_zd := DOB(1);

    VitalPathDelay01 (
      OutSignal => DOB1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB1",
      OutTemp => DOB1_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB1, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(1);
      end process;

    VitalBehavior_DOB2  : process
      variable DOB2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB2_zd := DOB(2);

    VitalPathDelay01 (
      OutSignal => DOB2,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB2",
      OutTemp => DOB2_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB2, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(2);
      end process;

    VitalBehavior_DOB3  : process
      variable DOB3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB3_zd := DOB(3);

    VitalPathDelay01 (
      OutSignal => DOB3,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB3",
      OutTemp => DOB3_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB3, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(3);
      end process;



	DPRAM_INST: SC_DPRAM_16K
	   generic map(
		ADDR_WIDTH_A => 12,
		DATA_WIDTH_A => 2,
		ADDR_WIDTH_B => 11,
		DATA_WIDTH_B => 4,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CENA => CENA_ipd,
	        CLKA => CLKA_ipd,
	        WRA  => WRA_ipd,
	        CSA  => CSA,
	        RSTA => RSTA_ipd,
	        DIA  => DIA,
	        ADA  => ADA,
	        DOA  => DOA,

	        CENB => CENB_ipd,
	        CLKB => CLKB_ipd,
	        WRB  => WRB_ipd,
	        CSB  => CSB,
	        RSTB => RSTB_ipd,
	        DIB  => DIB,
	        ADB  => ADB,
	        DOB  => DOB);
end VITAL;

configuration CFG_RAMB8K_X2_X4_VITAL of RAMB8K_X2_X4 is
   for VITAL
   end for;
end CFG_RAMB8K_X2_X4_VITAL;



----- CELL RAMB8K_X2_X8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB8K_X2_X8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "dummy";
      tpd_CLKA_DOA0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_CLKB_DOB0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTA_DOA0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTB_DOB0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_CENA_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENA_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRA_CLKA_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRA_CLKA_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CENB_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENB_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRB_CLKB_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRB_CLKB_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_DIA0_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA1_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_DIB0_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB1_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB2_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB3_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB4_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB5_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB6_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB7_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA2_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA3_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA4_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA4_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA5_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA5_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA6_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA6_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA7_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA7_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA8_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA8_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA9_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA9_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA10_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA10_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_ADA11_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA11_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB2_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB3_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB4_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB5_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB6_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB7_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB8_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB9_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB9_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTA_CLKA_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTA_CLKA_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTB_CLKB_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTB_CLKB_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLKA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_CLKB_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTB_posedge                   :	VitalDelayType   := 2.0 ns;
      tipd_CENA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRA                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CENB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRB                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CENA                            :	in    STD_ULOGIC;
      CLKA                            :	in    STD_ULOGIC;
      WRA                             :	in    STD_ULOGIC;
      CSA0                            :	in    STD_ULOGIC;
      CSA1                            :	in    STD_ULOGIC;
      RSTA                            :	in    STD_ULOGIC;
      CENB                            :	in    STD_ULOGIC;
      CLKB                            :	in    STD_ULOGIC;
      WRB                             :	in    STD_ULOGIC;
      CSB0                            :	in    STD_ULOGIC;
      CSB1                            :	in    STD_ULOGIC;
      RSTB                            :	in    STD_ULOGIC;
      DIA0                            :	in    STD_ULOGIC;
      DIA1                            :	in    STD_ULOGIC;
      ADA0                            :	in    STD_ULOGIC;
      ADA1                            :	in    STD_ULOGIC;
      ADA2                            :	in    STD_ULOGIC;
      ADA3                            :	in    STD_ULOGIC;
      ADA4                            :	in    STD_ULOGIC;
      ADA5                            :	in    STD_ULOGIC;
      ADA6                            :	in    STD_ULOGIC;
      ADA7                            :	in    STD_ULOGIC;
      ADA8                            :	in    STD_ULOGIC;
      ADA9                            :	in    STD_ULOGIC;
      ADA10                           :	in    STD_ULOGIC;
      ADA11                           :	in    STD_ULOGIC;
      DIB0                            :	in    STD_ULOGIC;
      DIB1                            :	in    STD_ULOGIC;
      DIB2                            :	in    STD_ULOGIC;
      DIB3                            :	in    STD_ULOGIC;
      DIB4                            :	in    STD_ULOGIC;
      DIB5                            :	in    STD_ULOGIC;
      DIB6                            :	in    STD_ULOGIC;
      DIB7                            :	in    STD_ULOGIC;
      ADB0                            :	in    STD_ULOGIC;
      ADB1                            :	in    STD_ULOGIC;
      ADB2                            :	in    STD_ULOGIC;
      ADB3                            :	in    STD_ULOGIC;
      ADB4                            :	in    STD_ULOGIC;
      ADB5                            :	in    STD_ULOGIC;
      ADB6                            :	in    STD_ULOGIC;
      ADB7                            :	in    STD_ULOGIC;
      ADB8                            :	in    STD_ULOGIC;
      ADB9                            :	in    STD_ULOGIC;
      DOA0                            :	out   STD_ULOGIC;
      DOA1                            :	out   STD_ULOGIC;
      DOB0                            :	out   STD_ULOGIC;
      DOB1                            :	out   STD_ULOGIC;
      DOB2                            :	out   STD_ULOGIC;
      DOB3                            :	out   STD_ULOGIC;
      DOB4                            :	out   STD_ULOGIC;
      DOB5                            :	out   STD_ULOGIC;
      DOB6                            :	out   STD_ULOGIC;
      DOB7                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB8K_X2_X8 : entity is FALSE;
end RAMB8K_X2_X8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB8K_X2_X8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_DPRAM_16K
	   generic (
		ADDR_WIDTH_A    : integer := 12;
		DATA_WIDTH_A    : integer := 2;
		ADDR_WIDTH_B    : integer := 10;
		DATA_WIDTH_B    : integer := 8;
	        MEM_INIT_FLAG   : integer := 0;  
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CENA : in  STD_LOGIC ;
		CLKA : in  STD_LOGIC ;
		WRA  : in  STD_LOGIC ;
		CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTA : in  STD_LOGIC ;
		DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
		ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
		DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

		CENB : in  STD_LOGIC ;
		CLKB : in  STD_LOGIC ;
		WRB  : in  STD_LOGIC ;
		CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTB : in  STD_LOGIC ;
		DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
		ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
		DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0)
		);
	end component ;

      signal CENA_ipd      : std_ulogic := 'X';
      signal CLKA_ipd      : std_ulogic := 'X';
      signal WRA_ipd       : std_ulogic := 'X';
      signal CSA0_ipd      : std_ulogic := 'X';
      signal CSA1_ipd      : std_ulogic := 'X';
      signal RSTA_ipd      : std_ulogic := 'X';

      signal CENB_ipd      : std_ulogic := 'X';
      signal CLKB_ipd      : std_ulogic := 'X';
      signal WRB_ipd       : std_ulogic := 'X';
      signal CSB0_ipd      : std_ulogic := 'X';
      signal CSB1_ipd      : std_ulogic := 'X';
      signal RSTB_ipd      : std_ulogic := 'X';

      signal DIA0_ipd      : std_ulogic := 'X';
      signal DIA1_ipd      : std_ulogic := 'X';

      signal ADA0_ipd      : std_ulogic := 'X';
      signal ADA1_ipd      : std_ulogic := 'X';
      signal ADA2_ipd      : std_ulogic := 'X';
      signal ADA3_ipd      : std_ulogic := 'X';
      signal ADA4_ipd      : std_ulogic := 'X';
      signal ADA5_ipd      : std_ulogic := 'X';
      signal ADA6_ipd      : std_ulogic := 'X';
      signal ADA7_ipd      : std_ulogic := 'X';
      signal ADA8_ipd      : std_ulogic := 'X';
      signal ADA9_ipd      : std_ulogic := 'X';
      signal ADA10_ipd     : std_ulogic := 'X';
      signal ADA11_ipd     : std_ulogic := 'X';

      signal DIB0_ipd       : std_ulogic := 'X';
      signal DIB1_ipd       : std_ulogic := 'X';
      signal DIB2_ipd       : std_ulogic := 'X';
      signal DIB3_ipd       : std_ulogic := 'X';
      signal DIB4_ipd       : std_ulogic := 'X';
      signal DIB5_ipd       : std_ulogic := 'X';
      signal DIB6_ipd       : std_ulogic := 'X';
      signal DIB7_ipd       : std_ulogic := 'X';

      signal ADB0_ipd      : std_ulogic := 'X';
      signal ADB1_ipd      : std_ulogic := 'X';
      signal ADB2_ipd      : std_ulogic := 'X';
      signal ADB3_ipd      : std_ulogic := 'X';
      signal ADB4_ipd      : std_ulogic := 'X';
      signal ADB5_ipd      : std_ulogic := 'X';
      signal ADB6_ipd      : std_ulogic := 'X';
      signal ADB7_ipd      : std_ulogic := 'X';
      signal ADB8_ipd      : std_ulogic := 'X';
      signal ADB9_ipd      : std_ulogic := 'X';

      signal CSA : std_logic_vector (1 downto 0); 
      signal CSB : std_logic_vector (1 downto 0); 
      signal DIA : std_logic_vector (1 downto 0); 
      signal DOA : std_logic_vector (1 downto 0); 
      signal DIB : std_logic_vector (7 downto 0); 
      signal DOB : std_logic_vector (7 downto 0); 
      signal ADA : std_logic_vector (11 downto 0); 
      signal ADB : std_logic_vector (9 downto 0); 
      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);

begin 

      CSA <= CSA1_ipd & CSA0_ipd;
      DIA <= DIA1_ipd & DIA0_ipd;
      ADA <= ADA11_ipd & ADA10_ipd & ADA9_ipd & ADA8_ipd & ADA7_ipd & ADA6_ipd & ADA5_ipd & ADA4_ipd & ADA3_ipd & ADA2_ipd & ADA1_ipd & ADA0_ipd;

      CSB <= CSB1_ipd & CSB0_ipd;
      DIB <= DIB7_ipd & DIB6_ipd & DIB5_ipd & DIB4_ipd & DIB3_ipd & DIB2_ipd & DIB1_ipd & DIB0_ipd;
      ADB <= ADB9_ipd & ADB8_ipd & ADB7_ipd & ADB6_ipd & ADB5_ipd & ADB4_ipd & ADB3_ipd & ADB2_ipd & ADB1_ipd & ADB0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CENA_ipd, CENA, tipd_CENA);
        VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
        VitalWireDelay (CSA0_ipd, CSA0, tipd_CSA0);
        VitalWireDelay (CSA1_ipd, CSA1, tipd_CSA1);
        VitalWireDelay (WRA_ipd, WRA, tipd_WRA);
        VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);

        VitalWireDelay (CENB_ipd, CENB, tipd_CENB);
        VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
        VitalWireDelay (CSB0_ipd, CSB0, tipd_CSB0);
        VitalWireDelay (CSB1_ipd, CSB1, tipd_CSB1);
        VitalWireDelay (WRB_ipd, WRB, tipd_WRB);
        VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);

        VitalWireDelay (DIA0_ipd, DIA0, tipd_DIA0);
        VitalWireDelay (DIA1_ipd, DIA1, tipd_DIA1);

        VitalWireDelay (ADA0_ipd, ADA0, tipd_ADA0);
        VitalWireDelay (ADA1_ipd, ADA1, tipd_ADA1);
        VitalWireDelay (ADA2_ipd, ADA2, tipd_ADA2);
        VitalWireDelay (ADA3_ipd, ADA3, tipd_ADA3);
        VitalWireDelay (ADA4_ipd, ADA4, tipd_ADA4);
        VitalWireDelay (ADA5_ipd, ADA5, tipd_ADA5);
        VitalWireDelay (ADA6_ipd, ADA6, tipd_ADA6);
        VitalWireDelay (ADA7_ipd, ADA7, tipd_ADA7);
        VitalWireDelay (ADA8_ipd, ADA8, tipd_ADA8);
        VitalWireDelay (ADA9_ipd, ADA9, tipd_ADA9);
        VitalWireDelay (ADA10_ipd, ADA10, tipd_ADA10);
        VitalWireDelay (ADA11_ipd, ADA11, tipd_ADA11);

        VitalWireDelay (DIB0_ipd, DIB0, tipd_DIB0);
        VitalWireDelay (DIB1_ipd, DIB1, tipd_DIB1);
        VitalWireDelay (DIB2_ipd, DIB2, tipd_DIB2);
        VitalWireDelay (DIB3_ipd, DIB3, tipd_DIB3);
        VitalWireDelay (DIB4_ipd, DIB4, tipd_DIB4);
        VitalWireDelay (DIB5_ipd, DIB5, tipd_DIB5);
        VitalWireDelay (DIB6_ipd, DIB6, tipd_DIB6);
        VitalWireDelay (DIB7_ipd, DIB7, tipd_DIB7);


        VitalWireDelay (ADB0_ipd, ADB0, tipd_ADB0);
        VitalWireDelay (ADB1_ipd, ADB1, tipd_ADB1);
        VitalWireDelay (ADB2_ipd, ADB2, tipd_ADB2);
        VitalWireDelay (ADB3_ipd, ADB3, tipd_ADB3);
        VitalWireDelay (ADB4_ipd, ADB4, tipd_ADB4);
        VitalWireDelay (ADB5_ipd, ADB5, tipd_ADB5);
        VitalWireDelay (ADB6_ipd, ADB6, tipd_ADB6);
        VitalWireDelay (ADB7_ipd, ADB7, tipd_ADB7);
        VitalWireDelay (ADB8_ipd, ADB8, tipd_ADB8);
        VitalWireDelay (ADB9_ipd, ADB9, tipd_ADB9);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CENA_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_WRA_CLKA_posedge     : std_ulogic  := '0';

        variable Tviol_CENB_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_WRB_CLKB_posedge      : std_ulogic  := '0';

        variable Tviol_DIA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA1_CLKA_posedge    : std_ulogic  := '0';

        variable Tviol_ADA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA3_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA4_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA5_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA6_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA7_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA8_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA9_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA10_CLKA_posedge   : std_ulogic  := '0';
        variable Tviol_ADA11_CLKA_posedge   : std_ulogic  := '0';

        variable Tviol_DIB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB7_CLKB_posedge    : std_ulogic  := '0';

        variable Tviol_ADB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB8_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB9_CLKB_posedge    : std_ulogic  := '0';

        variable Tviol_RSTA_CLKA_posedge_posedge : std_ulogic  := '0';
        variable Tviol_RSTB_CLKB_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CENA_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRA_CLKA_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CENB_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRB_CLKB_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA4_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA5_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA6_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA7_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA8_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA9_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA10_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA11_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB9_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RSTA_CLKA_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RSTB_CLKB_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLKA       : std_ulogic := '0';
        variable PInfo_CLKA       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_CLKB       : std_ulogic := '0';
        variable PInfo_CLkB       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTA        : std_ulogic := '0';
        variable PInfo_RSTA        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTB        : std_ulogic := '0';
        variable PInfo_RSTB        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DOA0_zd         : std_ulogic := 'X';
        variable DOA1_zd         : std_ulogic := 'X';
        variable DOB0_zd         : std_ulogic := 'X';
        variable DOB1_zd         : std_ulogic := 'X';
        variable DOB2_zd         : std_ulogic := 'X';
        variable DOB3_zd         : std_ulogic := 'X';
        variable DOB4_zd         : std_ulogic := 'X';
        variable DOB5_zd         : std_ulogic := 'X';
        variable DOB6_zd         : std_ulogic := 'X';
        variable DOB7_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CENA_CLKA_posedge,
          TimingData              => Tmkr_CENA_CLKA_posedge,
          TestSignal              => CENA_ipd,
          TestSignalName          => "CENA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENA_CLKA_noedge_posedge,
          SetupLow                => tsetup_CENA_CLKA_noedge_posedge,
          HoldLow                 => thold_CENA_CLKA_noedge_posedge,
          HoldHigh                => thold_CENA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRA_CLKA_posedge,
          TimingData              => Tmkr_WRA_CLKA_posedge,
          TestSignal              => WRA_ipd,
          TestSignalName          => "WRA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRA_CLKA_noedge_posedge,
          SetupLow                => tsetup_WRA_CLKA_noedge_posedge,
          HoldLow                 => thold_WRA_CLKA_noedge_posedge,
          HoldHigh                => thold_WRA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA0_CLKA_posedge,
          TimingData              => Tmkr_CSA0_CLKA_posedge,
          TestSignal              => CSA0_ipd,
          TestSignalName          => "CSA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA0_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA0_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA1_CLKA_posedge,
          TimingData              => Tmkr_CSA1_CLKA_posedge,
          TestSignal              => CSA1_ipd,
          TestSignalName          => "CSA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA1_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA1_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CENB_CLKB_posedge,
          TimingData              => Tmkr_CENB_CLKB_posedge,
          TestSignal              => CENB_ipd,
          TestSignalName          => "CENB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENB_CLKB_noedge_posedge,
          SetupLow                => tsetup_CENB_CLKB_noedge_posedge,
          HoldLow                 => thold_CENB_CLKB_noedge_posedge,
          HoldHigh                => thold_CENB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRB_CLKB_posedge,
          TimingData              => Tmkr_WRB_CLKB_posedge,
          TestSignal              => WRB_ipd,
          TestSignalName          => "WRB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRB_CLKB_noedge_posedge,
          SetupLow                => tsetup_WRB_CLKB_noedge_posedge,
          HoldLow                 => thold_WRB_CLKB_noedge_posedge,
          HoldHigh                => thold_WRB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB0_CLKB_posedge,
          TimingData              => Tmkr_CSB0_CLKB_posedge,
          TestSignal              => CSB0_ipd,
          TestSignalName          => "CSB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB0_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB0_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB1_CLKB_posedge,
          TimingData              => Tmkr_CSB1_CLKB_posedge,
          TestSignal              => CSB1_ipd,
          TestSignalName          => "CSB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB1_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB1_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA0_CLKA_posedge,
          TimingData              => Tmkr_DIA0_CLKA_posedge,
          TestSignal              => DIA0_ipd,
          TestSignalName          => "DIA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA0_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA0_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA1_CLKA_posedge,
          TimingData              => Tmkr_DIA1_CLKA_posedge,
          TestSignal              => DIA1_ipd,
          TestSignalName          => "DIA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA1_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA1_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA0_CLKA_posedge,
          TimingData              => Tmkr_ADA0_CLKA_posedge,
          TestSignal              => ADA0_ipd,
          TestSignalName          => "ADA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA0_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA0_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA1_CLKA_posedge,
          TimingData              => Tmkr_ADA1_CLKA_posedge,
          TestSignal              => ADA1_ipd,
          TestSignalName          => "ADA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA1_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA1_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA2_CLKA_posedge,
          TimingData              => Tmkr_ADA2_CLKA_posedge,
          TestSignal              => ADA2_ipd,
          TestSignalName          => "ADA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA2_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA2_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA3_CLKA_posedge,
          TimingData              => Tmkr_ADA3_CLKA_posedge,
          TestSignal              => ADA3_ipd,
          TestSignalName          => "ADA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA3_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA3_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA4_CLKA_posedge,
          TimingData              => Tmkr_ADA4_CLKA_posedge,
          TestSignal              => ADA4_ipd,
          TestSignalName          => "ADA4",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA4_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA4_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA4_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA4_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA5_CLKA_posedge,
          TimingData              => Tmkr_ADA5_CLKA_posedge,
          TestSignal              => ADA5_ipd,
          TestSignalName          => "ADA5",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA5_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA5_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA5_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA5_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA6_CLKA_posedge,
          TimingData              => Tmkr_ADA6_CLKA_posedge,
          TestSignal              => ADA6_ipd,
          TestSignalName          => "ADA6",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA6_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA6_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA6_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA6_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA7_CLKA_posedge,
          TimingData              => Tmkr_ADA7_CLKA_posedge,
          TestSignal              => ADA7_ipd,
          TestSignalName          => "ADA7",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA7_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA7_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA7_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA7_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA8_CLKA_posedge,
          TimingData              => Tmkr_ADA8_CLKA_posedge,
          TestSignal              => ADA8_ipd,
          TestSignalName          => "ADA8",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA8_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA8_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA8_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA8_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA9_CLKA_posedge,
          TimingData              => Tmkr_ADA9_CLKA_posedge,
          TestSignal              => ADA9_ipd,
          TestSignalName          => "ADA9",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA9_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA9_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA9_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA9_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA10_CLKA_posedge,
          TimingData              => Tmkr_ADA10_CLKA_posedge,
          TestSignal              => ADA10_ipd,
          TestSignalName          => "ADA10",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA10_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA10_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA10_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA10_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA11_CLKA_posedge,
          TimingData              => Tmkr_ADA11_CLKA_posedge,
          TestSignal              => ADA11_ipd,
          TestSignalName          => "ADA11",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA11_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA11_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA11_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA11_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB0_CLKB_posedge,
          TimingData              => Tmkr_DIB0_CLKB_posedge,
          TestSignal              => DIB0_ipd,
          TestSignalName          => "DIB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB0_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB0_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB1_CLKB_posedge,
          TimingData              => Tmkr_DIB1_CLKB_posedge,
          TestSignal              => DIB1_ipd,
          TestSignalName          => "DIB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB1_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB1_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB2_CLKB_posedge,
          TimingData              => Tmkr_DIB2_CLKB_posedge,
          TestSignal              => DIB2_ipd,
          TestSignalName          => "DIB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB2_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB2_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB3_CLKB_posedge,
          TimingData              => Tmkr_DIB3_CLKB_posedge,
          TestSignal              => DIB3_ipd,
          TestSignalName          => "DIB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB3_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB3_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB4_CLKB_posedge,
          TimingData              => Tmkr_DIB4_CLKB_posedge,
          TestSignal              => DIB4_ipd,
          TestSignalName          => "DIB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB4_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB4_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB5_CLKB_posedge,
          TimingData              => Tmkr_DIB5_CLKB_posedge,
          TestSignal              => DIB5_ipd,
          TestSignalName          => "DIB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB5_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB5_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB6_CLKB_posedge,
          TimingData              => Tmkr_DIB6_CLKB_posedge,
          TestSignal              => DIB6_ipd,
          TestSignalName          => "DIB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB6_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB6_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB7_CLKB_posedge,
          TimingData              => Tmkr_DIB7_CLKB_posedge,
          TestSignal              => DIB7_ipd,
          TestSignalName          => "DIB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB7_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB7_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB0_CLKB_posedge,
          TimingData              => Tmkr_ADB0_CLKB_posedge,
          TestSignal              => ADB0_ipd,
          TestSignalName          => "ADB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB0_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB0_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB1_CLKB_posedge,
          TimingData              => Tmkr_ADB1_CLKB_posedge,
          TestSignal              => ADB1_ipd,
          TestSignalName          => "ADB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB1_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB1_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB2_CLKB_posedge,
          TimingData              => Tmkr_ADB2_CLKB_posedge,
          TestSignal              => ADB2_ipd,
          TestSignalName          => "ADB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB2_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB2_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB3_CLKB_posedge,
          TimingData              => Tmkr_ADB3_CLKB_posedge,
          TestSignal              => ADB3_ipd,
          TestSignalName          => "ADB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB3_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB3_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB4_CLKB_posedge,
          TimingData              => Tmkr_ADB4_CLKB_posedge,
          TestSignal              => ADB4_ipd,
          TestSignalName          => "ADB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB4_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB4_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB5_CLKB_posedge,
          TimingData              => Tmkr_ADB5_CLKB_posedge,
          TestSignal              => ADB5_ipd,
          TestSignalName          => "ADB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB5_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB5_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB6_CLKB_posedge,
          TimingData              => Tmkr_ADB6_CLKB_posedge,
          TestSignal              => ADB6_ipd,
          TestSignalName          => "ADB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB6_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB6_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB7_CLKB_posedge,
          TimingData              => Tmkr_ADB7_CLKB_posedge,
          TestSignal              => ADB7_ipd,
          TestSignalName          => "ADB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB7_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB7_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB8_CLKB_posedge,
          TimingData              => Tmkr_ADB8_CLKB_posedge,
          TestSignal              => ADB8_ipd,
          TestSignalName          => "ADB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB8_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB8_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB9_CLKB_posedge,
          TimingData              => Tmkr_ADB9_CLKB_posedge,
          TestSignal              => ADB9_ipd,
          TestSignalName          => "ADB9",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB9_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB9_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB9_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB9_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKA,
          PeriodData              => PInfo_CLKA,
          TestSignal              => CLKA_ipd,
          TestSignalName          => "CLKA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKA_posedge,
          PulseWidthLow           => tpw_CLKA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKB,
          PeriodData              => PInfo_CLKB,
          TestSignal              => CLKB_ipd,
          TestSignalName          => "CLKB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKB_posedge,
          PulseWidthLow           => tpw_CLKB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTA,
          PeriodData              => PInfo_RSTA,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTA_posedge,
          PulseWidthLow           => tpw_RSTA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTB,
          PeriodData              => PInfo_RSTB,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTB_posedge,
          PulseWidthLow           => tpw_RSTB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X2_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTA_CLKA_posedge_posedge,
          TimingData              => Tmkr_RSTA_CLKA_posedge_posedge,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName          => "CLKA",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTA_CLKA_posedge_posedge,
          Removal                 => thold_RSTA_CLKA_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTB_CLKB_posedge_posedge,
          TimingData              => Tmkr_RSTB_CLKB_posedge_posedge,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName          => "CLKB",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTB_CLKB_posedge_posedge,
          Removal                 => thold_RSTB_CLKB_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CENA_CLKA_posedge or Tviol_WRA_CLKA_posedge or 
                 Tviol_CSA0_CLKA_posedge or Tviol_CSA1_CLKA_posedge or 
                 Tviol_ADA0_CLKA_posedge or Tviol_ADA1_CLKA_posedge or 
                 Tviol_ADA2_CLKA_posedge or Tviol_ADA3_CLKA_posedge or 
                 Tviol_ADA4_CLKA_posedge or Tviol_ADA5_CLKA_posedge or 
                 Tviol_ADA6_CLKA_posedge or Tviol_ADA7_CLKA_posedge or 
                 Tviol_ADA8_CLKA_posedge or Tviol_ADA9_CLKA_posedge or 
                 Tviol_ADA10_CLKA_posedge or Tviol_ADA11_CLKA_posedge or 
                 Tviol_DIA0_CLKA_posedge or Tviol_DIA1_CLKA_posedge or
                 Tviol_ADB0_CLKB_posedge or Tviol_ADB1_CLKB_posedge or 
                 Tviol_ADB2_CLKB_posedge or Tviol_ADB3_CLKB_posedge or 
                 Tviol_ADB4_CLKB_posedge or Tviol_ADB5_CLKB_posedge or 
                 Tviol_ADB6_CLKB_posedge or Tviol_ADB7_CLKB_posedge or 
                 Tviol_ADB8_CLKB_posedge or Tviol_ADB9_CLKB_posedge or 
 		 Tviol_DIB0_CLKB_posedge or  Tviol_DIB1_CLKB_posedge or 
 		 Tviol_DIB2_CLKB_posedge or  Tviol_DIB3_CLKB_posedge or 
 		 Tviol_DIB4_CLKB_posedge or  Tviol_DIB5_CLKB_posedge or 
 		 Tviol_DIB6_CLKB_posedge or  Tviol_DIB7_CLKB_posedge or 
                 Pviol_CLKA or Pviol_CLKB or Pviol_RSTA or Pviol_RSTB;

    -------------------------
    --  Functionality Section
    -------------------------

     wait on CENA_ipd, CLKA_ipd, WRA_ipd, CSA, RSTA_ipd, DIA, ADA, CENB_ipd, CLKB_ipd, WRB_ipd, CSB, RSTB_ipd, DIB, ADB;

      end process VITALBehavior;

    VitalBehavior_DOA0  : process
      variable DOA0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA0_zd := DOA(0);

    VitalPathDelay01 (
      OutSignal => DOA0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA0",
      OutTemp => DOA0_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA0, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(0);
      end process;

    VitalBehavior_DOA1  : process
      variable DOA1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA1_zd := DOA(1);

    VitalPathDelay01 (
      OutSignal => DOA1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA1",
      OutTemp => DOA1_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA1, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(1);
      end process;

    VitalBehavior_DOB0  : process
      variable DOB0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB0_zd := DOB(0);

    VitalPathDelay01 (
      OutSignal => DOB0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB0",
      OutTemp => DOB0_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB0, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(0);
      end process;

    VitalBehavior_DOB1  : process
      variable DOB1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB1_zd := DOB(1);

    VitalPathDelay01 (
      OutSignal => DOB1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB1",
      OutTemp => DOB1_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB1, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(1);
      end process;

    VitalBehavior_DOB2  : process
      variable DOB2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB2_zd := DOB(2);

    VitalPathDelay01 (
      OutSignal => DOB2,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB2",
      OutTemp => DOB2_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB2, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(2);
      end process;

    VitalBehavior_DOB3  : process
      variable DOB3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB3_zd := DOB(3);

    VitalPathDelay01 (
      OutSignal => DOB3,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB3",
      OutTemp => DOB3_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB3, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(3);
      end process;

    VitalBehavior_DOB4  : process
      variable DOB4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB4_zd := DOB(4);

    VitalPathDelay01 (
      OutSignal => DOB4,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB4",
      OutTemp => DOB4_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB4, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(4);
      end process;

    VitalBehavior_DOB5  : process
      variable DOB5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB5_zd := DOB(5);

    VitalPathDelay01 (
      OutSignal => DOB5,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB5",
      OutTemp => DOB5_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB5, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(5);
      end process;

    VitalBehavior_DOB6  : process
      variable DOB6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB6_zd := DOB(6);

    VitalPathDelay01 (
      OutSignal => DOB6,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB6",
      OutTemp => DOB6_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB6, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(6);
      end process;

    VitalBehavior_DOB7  : process
      variable DOB7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB7_zd := DOB(7);

    VitalPathDelay01 (
      OutSignal => DOB7,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB7",
      OutTemp => DOB7_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB7, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(7);
      end process;



  DPRAM_INST: SC_DPRAM_16K
    generic map(
        ADDR_WIDTH_A => 12,
        DATA_WIDTH_A => 2, 
        ADDR_WIDTH_B => 10,
        DATA_WIDTH_B => 8, 
        MEM_INIT_FLAG => RAM_INIT_FLAG,  
	MEM_INIT_FILE => RAM_INIT_FILE
       )
	   port map (
		CENA => CENA_ipd,
	        CLKA => CLKA_ipd,
	        WRA  => WRA_ipd,
	        CSA  => CSA,
	        RSTA => RSTA_ipd,
	        DIA  => DIA,
	        ADA  => ADA,
	        DOA  => DOA,

	        CENB => CENB_ipd,
	        CLKB => CLKB_ipd,
	        WRB  => WRB_ipd,
	        CSB  => CSB,
	        RSTB => RSTB_ipd,
	        DIB  => DIB,
	        ADB  => ADB,
	        DOB  => DOB);
end VITAL;

configuration CFG_RAMB8K_X2_X8_VITAL of RAMB8K_X2_X8 is
   for VITAL
   end for;
end CFG_RAMB8K_X2_X8_VITAL;



----- CELL RAMB8K_X2_X16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB8K_X2_X16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "dummy";
      tpd_CLKA_DOA0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_CLKB_DOB0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTA_DOA0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTB_DOB0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_CENA_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENA_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRA_CLKA_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRA_CLKA_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CENB_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENB_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRB_CLKB_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRB_CLKB_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_DIA0_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA1_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_DIB0_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB1_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB2_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB3_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB4_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB5_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB6_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB7_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB8_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB9_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB9_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB10_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB10_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB11_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB11_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB12_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB12_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB13_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB13_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB14_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB14_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB15_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB15_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA2_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA3_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA4_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA4_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA5_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA5_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA6_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA6_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA7_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA7_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA8_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA8_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA9_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA9_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA10_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA10_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_ADA11_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA11_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB2_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB3_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB4_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB5_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB6_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB7_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB8_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTA_CLKA_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTA_CLKA_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTB_CLKB_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTB_CLKB_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLKA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_CLKB_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTB_posedge                   :	VitalDelayType   := 2.0 ns;
      tipd_CENA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRA                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CENB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRB                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CENA                            :	in    STD_ULOGIC;
      CLKA                            :	in    STD_ULOGIC;
      WRA                             :	in    STD_ULOGIC;
      CSA0                            :	in    STD_ULOGIC;
      CSA1                            :	in    STD_ULOGIC;
      RSTA                            :	in    STD_ULOGIC;
      CENB                            :	in    STD_ULOGIC;
      CLKB                            :	in    STD_ULOGIC;
      WRB                             :	in    STD_ULOGIC;
      CSB0                            :	in    STD_ULOGIC;
      CSB1                            :	in    STD_ULOGIC;
      RSTB                            :	in    STD_ULOGIC;
      DIA0                            :	in    STD_ULOGIC;
      DIA1                            :	in    STD_ULOGIC;
      ADA0                            :	in    STD_ULOGIC;
      ADA1                            :	in    STD_ULOGIC;
      ADA2                            :	in    STD_ULOGIC;
      ADA3                            :	in    STD_ULOGIC;
      ADA4                            :	in    STD_ULOGIC;
      ADA5                            :	in    STD_ULOGIC;
      ADA6                            :	in    STD_ULOGIC;
      ADA7                            :	in    STD_ULOGIC;
      ADA8                            :	in    STD_ULOGIC;
      ADA9                            :	in    STD_ULOGIC;
      ADA10                           :	in    STD_ULOGIC;
      ADA11                           :	in    STD_ULOGIC;
      DIB0                            :	in    STD_ULOGIC;
      DIB1                            :	in    STD_ULOGIC;
      DIB2                            :	in    STD_ULOGIC;
      DIB3                            :	in    STD_ULOGIC;
      DIB4                            :	in    STD_ULOGIC;
      DIB5                            :	in    STD_ULOGIC;
      DIB6                            :	in    STD_ULOGIC;
      DIB7                            :	in    STD_ULOGIC;
      DIB8                            :	in    STD_ULOGIC;
      DIB9                            :	in    STD_ULOGIC;
      DIB10                           :	in    STD_ULOGIC;
      DIB11                           :	in    STD_ULOGIC;
      DIB12                           :	in    STD_ULOGIC;
      DIB13                           :	in    STD_ULOGIC;
      DIB14                           :	in    STD_ULOGIC;
      DIB15                           :	in    STD_ULOGIC;
      ADB0                            :	in    STD_ULOGIC;
      ADB1                            :	in    STD_ULOGIC;
      ADB2                            :	in    STD_ULOGIC;
      ADB3                            :	in    STD_ULOGIC;
      ADB4                            :	in    STD_ULOGIC;
      ADB5                            :	in    STD_ULOGIC;
      ADB6                            :	in    STD_ULOGIC;
      ADB7                            :	in    STD_ULOGIC;
      ADB8                            :	in    STD_ULOGIC;
      DOA0                            :	out   STD_ULOGIC;
      DOA1                            :	out   STD_ULOGIC;
      DOB0                            :	out   STD_ULOGIC;
      DOB1                            :	out   STD_ULOGIC;
      DOB2                            :	out   STD_ULOGIC;
      DOB3                            :	out   STD_ULOGIC;
      DOB4                            :	out   STD_ULOGIC;
      DOB5                            :	out   STD_ULOGIC;
      DOB6                            :	out   STD_ULOGIC;
      DOB7                            :	out   STD_ULOGIC;
      DOB8                            :	out   STD_ULOGIC;
      DOB9                            :	out   STD_ULOGIC;
      DOB10                           :	out   STD_ULOGIC;
      DOB11                           :	out   STD_ULOGIC;
      DOB12                           :	out   STD_ULOGIC;
      DOB13                           :	out   STD_ULOGIC;
      DOB14                           :	out   STD_ULOGIC;
      DOB15                           :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB8K_X2_X16 : entity is FALSE;
end RAMB8K_X2_X16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB8K_X2_X16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_DPRAM_16K
	   generic (
		ADDR_WIDTH_A    : integer := 12;
		DATA_WIDTH_A    : integer := 2;
		ADDR_WIDTH_B    : integer := 9;
		DATA_WIDTH_B    : integer := 16;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CENA : in  STD_LOGIC ;
		CLKA : in  STD_LOGIC ;
		WRA  : in  STD_LOGIC ;
		CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTA : in  STD_LOGIC ;
		DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
		ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
		DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

		CENB : in  STD_LOGIC ;
		CLKB : in  STD_LOGIC ;
		WRB  : in  STD_LOGIC ;
		CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTB : in  STD_LOGIC ;
		DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
		ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
		DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
		);
	end component ;

      signal CENA_ipd      : std_ulogic := 'X';
      signal CLKA_ipd      : std_ulogic := 'X';
      signal WRA_ipd       : std_ulogic := 'X';
      signal CSA0_ipd      : std_ulogic := 'X';
      signal CSA1_ipd      : std_ulogic := 'X';
      signal RSTA_ipd      : std_ulogic := 'X';

      signal CENB_ipd      : std_ulogic := 'X';
      signal CLKB_ipd      : std_ulogic := 'X';
      signal WRB_ipd       : std_ulogic := 'X';
      signal CSB0_ipd      : std_ulogic := 'X';
      signal CSB1_ipd      : std_ulogic := 'X';
      signal RSTB_ipd      : std_ulogic := 'X';

      signal DIA0_ipd      : std_ulogic := 'X';
      signal DIA1_ipd      : std_ulogic := 'X';

      signal ADA0_ipd      : std_ulogic := 'X';
      signal ADA1_ipd      : std_ulogic := 'X';
      signal ADA2_ipd      : std_ulogic := 'X';
      signal ADA3_ipd      : std_ulogic := 'X';
      signal ADA4_ipd      : std_ulogic := 'X';
      signal ADA5_ipd      : std_ulogic := 'X';
      signal ADA6_ipd      : std_ulogic := 'X';
      signal ADA7_ipd      : std_ulogic := 'X';
      signal ADA8_ipd      : std_ulogic := 'X';
      signal ADA9_ipd      : std_ulogic := 'X';
      signal ADA10_ipd     : std_ulogic := 'X';
      signal ADA11_ipd     : std_ulogic := 'X';

      signal DIB0_ipd       : std_ulogic := 'X';
      signal DIB1_ipd       : std_ulogic := 'X';
      signal DIB2_ipd       : std_ulogic := 'X';
      signal DIB3_ipd       : std_ulogic := 'X';
      signal DIB4_ipd       : std_ulogic := 'X';
      signal DIB5_ipd       : std_ulogic := 'X';
      signal DIB6_ipd       : std_ulogic := 'X';
      signal DIB7_ipd       : std_ulogic := 'X';
      signal DIB8_ipd       : std_ulogic := 'X';
      signal DIB9_ipd       : std_ulogic := 'X';
      signal DIB10_ipd      : std_ulogic := 'X';
      signal DIB11_ipd      : std_ulogic := 'X';
      signal DIB12_ipd      : std_ulogic := 'X';
      signal DIB13_ipd      : std_ulogic := 'X';
      signal DIB14_ipd      : std_ulogic := 'X';
      signal DIB15_ipd      : std_ulogic := 'X';

      signal ADB0_ipd      : std_ulogic := 'X';
      signal ADB1_ipd      : std_ulogic := 'X';
      signal ADB2_ipd      : std_ulogic := 'X';
      signal ADB3_ipd      : std_ulogic := 'X';
      signal ADB4_ipd      : std_ulogic := 'X';
      signal ADB5_ipd      : std_ulogic := 'X';
      signal ADB6_ipd      : std_ulogic := 'X';
      signal ADB7_ipd      : std_ulogic := 'X';
      signal ADB8_ipd      : std_ulogic := 'X';

	signal CSA : std_logic_vector (1 downto 0);
	signal CSB : std_logic_vector (1 downto 0);
	signal DIA : std_logic_vector (1 downto 0);
	signal DOA : std_logic_vector (1 downto 0);
	signal DIB : std_logic_vector (15 downto 0);
	signal DOB : std_logic_vector (15 downto 0);
	signal ADA : std_logic_vector (11 downto 0);
	signal ADB : std_logic_vector (8 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);

begin 

	CSA <= CSA1_ipd & CSA0_ipd;
	CSB <= CSB1_ipd & CSB0_ipd;
	DIA <= DIA1_ipd & DIA0_ipd;
	DIB <= DIB15_ipd & DIB14_ipd & DIB13_ipd & DIB12_ipd & DIB11_ipd & DIB10_ipd & DIB9_ipd & DIB8_ipd & DIB7_ipd & DIB6_ipd & DIB5_ipd & DIB4_ipd & DIB3_ipd & DIB2_ipd & DIB1_ipd & DIB0_ipd;
	ADA <= ADA11_ipd & ADA10_ipd & ADA9_ipd & ADA8_ipd & ADA7_ipd & ADA6_ipd & ADA5_ipd & ADA4_ipd & ADA3_ipd & ADA2_ipd & ADA1_ipd & ADA0_ipd;
	ADB <= ADB8_ipd & ADB7_ipd & ADB6_ipd & ADB5_ipd & ADB4_ipd & ADB3_ipd & ADB2_ipd & ADB1_ipd & ADB0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CENA_ipd, CENA, tipd_CENA);
        VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
        VitalWireDelay (CSA0_ipd, CSA0, tipd_CSA0);
        VitalWireDelay (CSA1_ipd, CSA1, tipd_CSA1);
        VitalWireDelay (WRA_ipd, WRA, tipd_WRA);
        VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);

        VitalWireDelay (CENB_ipd, CENB, tipd_CENB);
        VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
        VitalWireDelay (CSB0_ipd, CSB0, tipd_CSB0);
        VitalWireDelay (CSB1_ipd, CSB1, tipd_CSB1);
        VitalWireDelay (WRB_ipd, WRB, tipd_WRB);
        VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);

        VitalWireDelay (DIA0_ipd, DIA0, tipd_DIA0);
        VitalWireDelay (DIA1_ipd, DIA1, tipd_DIA1);

        VitalWireDelay (ADA0_ipd, ADA0, tipd_ADA0);
        VitalWireDelay (ADA1_ipd, ADA1, tipd_ADA1);
        VitalWireDelay (ADA2_ipd, ADA2, tipd_ADA2);
        VitalWireDelay (ADA3_ipd, ADA3, tipd_ADA3);
        VitalWireDelay (ADA4_ipd, ADA4, tipd_ADA4);
        VitalWireDelay (ADA5_ipd, ADA5, tipd_ADA5);
        VitalWireDelay (ADA6_ipd, ADA6, tipd_ADA6);
        VitalWireDelay (ADA7_ipd, ADA7, tipd_ADA7);
        VitalWireDelay (ADA8_ipd, ADA8, tipd_ADA8);
        VitalWireDelay (ADA9_ipd, ADA9, tipd_ADA9);
        VitalWireDelay (ADA10_ipd, ADA10, tipd_ADA10);
        VitalWireDelay (ADA11_ipd, ADA11, tipd_ADA11);

        VitalWireDelay (DIB0_ipd, DIB0, tipd_DIB0);
        VitalWireDelay (DIB1_ipd, DIB1, tipd_DIB1);
        VitalWireDelay (DIB2_ipd, DIB2, tipd_DIB2);
        VitalWireDelay (DIB3_ipd, DIB3, tipd_DIB3);
        VitalWireDelay (DIB4_ipd, DIB4, tipd_DIB4);
        VitalWireDelay (DIB5_ipd, DIB5, tipd_DIB5);
        VitalWireDelay (DIB6_ipd, DIB6, tipd_DIB6);
        VitalWireDelay (DIB7_ipd, DIB7, tipd_DIB7);
        VitalWireDelay (DIB8_ipd, DIB8, tipd_DIB8);
        VitalWireDelay (DIB9_ipd, DIB9, tipd_DIB9);
        VitalWireDelay (DIB10_ipd, DIB10, tipd_DIB10);
        VitalWireDelay (DIB11_ipd, DIB11, tipd_DIB11);
        VitalWireDelay (DIB12_ipd, DIB12, tipd_DIB12);
        VitalWireDelay (DIB13_ipd, DIB13, tipd_DIB13);
        VitalWireDelay (DIB14_ipd, DIB14, tipd_DIB14);
        VitalWireDelay (DIB15_ipd, DIB15, tipd_DIB15);


        VitalWireDelay (ADB0_ipd, ADB0, tipd_ADB0);
        VitalWireDelay (ADB1_ipd, ADB1, tipd_ADB1);
        VitalWireDelay (ADB2_ipd, ADB2, tipd_ADB2);
        VitalWireDelay (ADB3_ipd, ADB3, tipd_ADB3);
        VitalWireDelay (ADB4_ipd, ADB4, tipd_ADB4);
        VitalWireDelay (ADB5_ipd, ADB5, tipd_ADB5);
        VitalWireDelay (ADB6_ipd, ADB6, tipd_ADB6);
        VitalWireDelay (ADB7_ipd, ADB7, tipd_ADB7);
        VitalWireDelay (ADB8_ipd, ADB8, tipd_ADB8);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CENA_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_WRA_CLKA_posedge     : std_ulogic  := '0';

        variable Tviol_CENB_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_WRB_CLKB_posedge      : std_ulogic  := '0';


        variable Tviol_DIA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA1_CLKA_posedge    : std_ulogic  := '0';

        variable Tviol_ADA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA3_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA4_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA5_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA6_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA7_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA8_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA9_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA10_CLKA_posedge   : std_ulogic  := '0';
        variable Tviol_ADA11_CLKA_posedge   : std_ulogic  := '0';

        variable Tviol_DIB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB8_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB9_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB10_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB11_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB12_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB13_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB14_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB15_CLKB_posedge    : std_ulogic  := '0';


        variable Tviol_ADB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB8_CLKB_posedge    : std_ulogic  := '0';

        variable Tviol_RSTA_CLKA_posedge_posedge : std_ulogic  := '0';
        variable Tviol_RSTB_CLKB_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CENA_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRA_CLKA_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CENB_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRB_CLKB_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB9_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB10_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB11_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB12_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB13_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB14_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB15_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA4_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA5_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA6_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA7_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA8_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA9_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA10_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA11_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RSTA_CLKA_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RSTB_CLKB_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLKA       : std_ulogic := '0';
        variable PInfo_CLKA       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_CLKB       : std_ulogic := '0';
        variable PInfo_CLkB       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTA        : std_ulogic := '0';
        variable PInfo_RSTA        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTB        : std_ulogic := '0';
        variable PInfo_RSTB        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DOA0_zd         : std_ulogic := 'X';
        variable DOA1_zd         : std_ulogic := 'X';
        variable DOB0_zd         : std_ulogic := 'X';
        variable DOB1_zd         : std_ulogic := 'X';
        variable DOB2_zd         : std_ulogic := 'X';
        variable DOB3_zd         : std_ulogic := 'X';
        variable DOB4_zd         : std_ulogic := 'X';
        variable DOB5_zd         : std_ulogic := 'X';
        variable DOB6_zd         : std_ulogic := 'X';
        variable DOB7_zd         : std_ulogic := 'X';
        variable DOB8_zd         : std_ulogic := 'X';
        variable DOB9_zd         : std_ulogic := 'X';
        variable DOB10_zd         : std_ulogic := 'X';
        variable DOB11_zd         : std_ulogic := 'X';
        variable DOB12_zd         : std_ulogic := 'X';
        variable DOB13_zd         : std_ulogic := 'X';
        variable DOB14_zd         : std_ulogic := 'X';
        variable DOB15_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CENA_CLKA_posedge,
          TimingData              => Tmkr_CENA_CLKA_posedge,
          TestSignal              => CENA_ipd,
          TestSignalName          => "CENA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENA_CLKA_noedge_posedge,
          SetupLow                => tsetup_CENA_CLKA_noedge_posedge,
          HoldLow                 => thold_CENA_CLKA_noedge_posedge,
          HoldHigh                => thold_CENA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRA_CLKA_posedge,
          TimingData              => Tmkr_WRA_CLKA_posedge,
          TestSignal              => WRA_ipd,
          TestSignalName          => "WRA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRA_CLKA_noedge_posedge,
          SetupLow                => tsetup_WRA_CLKA_noedge_posedge,
          HoldLow                 => thold_WRA_CLKA_noedge_posedge,
          HoldHigh                => thold_WRA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA0_CLKA_posedge,
          TimingData              => Tmkr_CSA0_CLKA_posedge,
          TestSignal              => CSA0_ipd,
          TestSignalName          => "CSA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA0_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA0_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA1_CLKA_posedge,
          TimingData              => Tmkr_CSA1_CLKA_posedge,
          TestSignal              => CSA1_ipd,
          TestSignalName          => "CSA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA1_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA1_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CENB_CLKB_posedge,
          TimingData              => Tmkr_CENB_CLKB_posedge,
          TestSignal              => CENB_ipd,
          TestSignalName          => "CENB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENB_CLKB_noedge_posedge,
          SetupLow                => tsetup_CENB_CLKB_noedge_posedge,
          HoldLow                 => thold_CENB_CLKB_noedge_posedge,
          HoldHigh                => thold_CENB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRB_CLKB_posedge,
          TimingData              => Tmkr_WRB_CLKB_posedge,
          TestSignal              => WRB_ipd,
          TestSignalName          => "WRB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRB_CLKB_noedge_posedge,
          SetupLow                => tsetup_WRB_CLKB_noedge_posedge,
          HoldLow                 => thold_WRB_CLKB_noedge_posedge,
          HoldHigh                => thold_WRB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB0_CLKB_posedge,
          TimingData              => Tmkr_CSB0_CLKB_posedge,
          TestSignal              => CSB0_ipd,
          TestSignalName          => "CSB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB0_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB0_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB1_CLKB_posedge,
          TimingData              => Tmkr_CSB1_CLKB_posedge,
          TestSignal              => CSB1_ipd,
          TestSignalName          => "CSB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB1_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB1_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA0_CLKA_posedge,
          TimingData              => Tmkr_DIA0_CLKA_posedge,
          TestSignal              => DIA0_ipd,
          TestSignalName          => "DIA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA0_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA0_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA1_CLKA_posedge,
          TimingData              => Tmkr_DIA1_CLKA_posedge,
          TestSignal              => DIA1_ipd,
          TestSignalName          => "DIA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA1_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA1_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA0_CLKA_posedge,
          TimingData              => Tmkr_ADA0_CLKA_posedge,
          TestSignal              => ADA0_ipd,
          TestSignalName          => "ADA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA0_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA0_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA1_CLKA_posedge,
          TimingData              => Tmkr_ADA1_CLKA_posedge,
          TestSignal              => ADA1_ipd,
          TestSignalName          => "ADA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA1_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA1_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA2_CLKA_posedge,
          TimingData              => Tmkr_ADA2_CLKA_posedge,
          TestSignal              => ADA2_ipd,
          TestSignalName          => "ADA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA2_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA2_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA3_CLKA_posedge,
          TimingData              => Tmkr_ADA3_CLKA_posedge,
          TestSignal              => ADA3_ipd,
          TestSignalName          => "ADA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA3_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA3_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA4_CLKA_posedge,
          TimingData              => Tmkr_ADA4_CLKA_posedge,
          TestSignal              => ADA4_ipd,
          TestSignalName          => "ADA4",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA4_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA4_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA4_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA4_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA5_CLKA_posedge,
          TimingData              => Tmkr_ADA5_CLKA_posedge,
          TestSignal              => ADA5_ipd,
          TestSignalName          => "ADA5",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA5_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA5_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA5_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA5_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA6_CLKA_posedge,
          TimingData              => Tmkr_ADA6_CLKA_posedge,
          TestSignal              => ADA6_ipd,
          TestSignalName          => "ADA6",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA6_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA6_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA6_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA6_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA7_CLKA_posedge,
          TimingData              => Tmkr_ADA7_CLKA_posedge,
          TestSignal              => ADA7_ipd,
          TestSignalName          => "ADA7",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA7_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA7_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA7_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA7_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA8_CLKA_posedge,
          TimingData              => Tmkr_ADA8_CLKA_posedge,
          TestSignal              => ADA8_ipd,
          TestSignalName          => "ADA8",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA8_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA8_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA8_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA8_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA9_CLKA_posedge,
          TimingData              => Tmkr_ADA9_CLKA_posedge,
          TestSignal              => ADA9_ipd,
          TestSignalName          => "ADA9",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA9_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA9_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA9_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA9_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA10_CLKA_posedge,
          TimingData              => Tmkr_ADA10_CLKA_posedge,
          TestSignal              => ADA10_ipd,
          TestSignalName          => "ADA10",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA10_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA10_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA10_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA10_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA11_CLKA_posedge,
          TimingData              => Tmkr_ADA11_CLKA_posedge,
          TestSignal              => ADA11_ipd,
          TestSignalName          => "ADA11",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA11_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA11_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA11_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA11_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB0_CLKB_posedge,
          TimingData              => Tmkr_DIB0_CLKB_posedge,
          TestSignal              => DIB0_ipd,
          TestSignalName          => "DIB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB0_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB0_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB1_CLKB_posedge,
          TimingData              => Tmkr_DIB1_CLKB_posedge,
          TestSignal              => DIB1_ipd,
          TestSignalName          => "DIB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB1_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB1_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB2_CLKB_posedge,
          TimingData              => Tmkr_DIB2_CLKB_posedge,
          TestSignal              => DIB2_ipd,
          TestSignalName          => "DIB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB2_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB2_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB3_CLKB_posedge,
          TimingData              => Tmkr_DIB3_CLKB_posedge,
          TestSignal              => DIB3_ipd,
          TestSignalName          => "DIB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB3_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB3_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB4_CLKB_posedge,
          TimingData              => Tmkr_DIB4_CLKB_posedge,
          TestSignal              => DIB4_ipd,
          TestSignalName          => "DIB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB4_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB4_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB5_CLKB_posedge,
          TimingData              => Tmkr_DIB5_CLKB_posedge,
          TestSignal              => DIB5_ipd,
          TestSignalName          => "DIB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB5_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB5_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB6_CLKB_posedge,
          TimingData              => Tmkr_DIB6_CLKB_posedge,
          TestSignal              => DIB6_ipd,
          TestSignalName          => "DIB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB6_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB6_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB7_CLKB_posedge,
          TimingData              => Tmkr_DIB7_CLKB_posedge,
          TestSignal              => DIB7_ipd,
          TestSignalName          => "DIB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB7_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB7_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB8_CLKB_posedge,
          TimingData              => Tmkr_DIB8_CLKB_posedge,
          TestSignal              => DIB8_ipd,
          TestSignalName          => "DIB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB8_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB8_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB9_CLKB_posedge,
          TimingData              => Tmkr_DIB9_CLKB_posedge,
          TestSignal              => DIB9_ipd,
          TestSignalName          => "DIB9",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB9_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB9_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB9_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB9_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB10_CLKB_posedge,
          TimingData              => Tmkr_DIB10_CLKB_posedge,
          TestSignal              => DIB10_ipd,
          TestSignalName          => "DIB10",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB10_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB10_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB10_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB10_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB11_CLKB_posedge,
          TimingData              => Tmkr_DIB11_CLKB_posedge,
          TestSignal              => DIB11_ipd,
          TestSignalName          => "DIB11",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB11_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB11_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB11_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB11_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB12_CLKB_posedge,
          TimingData              => Tmkr_DIB12_CLKB_posedge,
          TestSignal              => DIB12_ipd,
          TestSignalName          => "DIB12",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB12_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB12_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB12_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB12_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB13_CLKB_posedge,
          TimingData              => Tmkr_DIB13_CLKB_posedge,
          TestSignal              => DIB13_ipd,
          TestSignalName          => "DIB13",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB13_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB13_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB13_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB13_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB14_CLKB_posedge,
          TimingData              => Tmkr_DIB14_CLKB_posedge,
          TestSignal              => DIB14_ipd,
          TestSignalName          => "DIB14",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB14_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB14_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB14_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB14_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB15_CLKB_posedge,
          TimingData              => Tmkr_DIB15_CLKB_posedge,
          TestSignal              => DIB15_ipd,
          TestSignalName          => "DIB15",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB15_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB15_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB15_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB15_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB0_CLKB_posedge,
          TimingData              => Tmkr_ADB0_CLKB_posedge,
          TestSignal              => ADB0_ipd,
          TestSignalName          => "ADB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB0_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB0_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB1_CLKB_posedge,
          TimingData              => Tmkr_ADB1_CLKB_posedge,
          TestSignal              => ADB1_ipd,
          TestSignalName          => "ADB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB1_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB1_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB2_CLKB_posedge,
          TimingData              => Tmkr_ADB2_CLKB_posedge,
          TestSignal              => ADB2_ipd,
          TestSignalName          => "ADB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB2_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB2_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB3_CLKB_posedge,
          TimingData              => Tmkr_ADB3_CLKB_posedge,
          TestSignal              => ADB3_ipd,
          TestSignalName          => "ADB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB3_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB3_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB4_CLKB_posedge,
          TimingData              => Tmkr_ADB4_CLKB_posedge,
          TestSignal              => ADB4_ipd,
          TestSignalName          => "ADB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB4_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB4_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB5_CLKB_posedge,
          TimingData              => Tmkr_ADB5_CLKB_posedge,
          TestSignal              => ADB5_ipd,
          TestSignalName          => "ADB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB5_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB5_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB6_CLKB_posedge,
          TimingData              => Tmkr_ADB6_CLKB_posedge,
          TestSignal              => ADB6_ipd,
          TestSignalName          => "ADB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB6_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB6_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB7_CLKB_posedge,
          TimingData              => Tmkr_ADB7_CLKB_posedge,
          TestSignal              => ADB7_ipd,
          TestSignalName          => "ADB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB7_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB7_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB8_CLKB_posedge,
          TimingData              => Tmkr_ADB8_CLKB_posedge,
          TestSignal              => ADB8_ipd,
          TestSignalName          => "ADB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB8_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB8_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKA,
          PeriodData              => PInfo_CLKA,
          TestSignal              => CLKA_ipd,
          TestSignalName          => "CLKA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKA_posedge,
          PulseWidthLow           => tpw_CLKA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKB,
          PeriodData              => PInfo_CLKB,
          TestSignal              => CLKB_ipd,
          TestSignalName          => "CLKB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKB_posedge,
          PulseWidthLow           => tpw_CLKB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTA,
          PeriodData              => PInfo_RSTA,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTA_posedge,
          PulseWidthLow           => tpw_RSTA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTB,
          PeriodData              => PInfo_RSTB,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTB_posedge,
          PulseWidthLow           => tpw_RSTB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X2_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTA_CLKA_posedge_posedge,
          TimingData              => Tmkr_RSTA_CLKA_posedge_posedge,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName          => "CLKA",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTA_CLKA_posedge_posedge,
          Removal                 => thold_RSTA_CLKA_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTB_CLKB_posedge_posedge,
          TimingData              => Tmkr_RSTB_CLKB_posedge_posedge,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName          => "CLKB",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTB_CLKB_posedge_posedge,
          Removal                 => thold_RSTB_CLKB_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CENA_CLKA_posedge or Tviol_WRA_CLKA_posedge or 
                 Tviol_CSA0_CLKA_posedge or Tviol_CSA1_CLKA_posedge or 
                 Tviol_ADA0_CLKA_posedge or Tviol_ADA1_CLKA_posedge or 
                 Tviol_ADA2_CLKA_posedge or Tviol_ADA3_CLKA_posedge or 
                 Tviol_ADA4_CLKA_posedge or Tviol_ADA5_CLKA_posedge or 
                 Tviol_ADA6_CLKA_posedge or Tviol_ADA7_CLKA_posedge or 
                 Tviol_ADA8_CLKA_posedge or Tviol_ADA9_CLKA_posedge or 
                 Tviol_ADA10_CLKA_posedge or Tviol_ADA11_CLKA_posedge or 
                 Tviol_DIA0_CLKA_posedge or Tviol_DIA1_CLKA_posedge or
                 Tviol_ADB0_CLKB_posedge or Tviol_ADB1_CLKB_posedge or 
                 Tviol_ADB2_CLKB_posedge or Tviol_ADB3_CLKB_posedge or 
                 Tviol_ADB4_CLKB_posedge or Tviol_ADB5_CLKB_posedge or 
                 Tviol_ADB6_CLKB_posedge or Tviol_ADB7_CLKB_posedge or 
                 Tviol_ADB8_CLKB_posedge or
 		 Tviol_DIB0_CLKB_posedge or  Tviol_DIB1_CLKB_posedge or 
 		 Tviol_DIB2_CLKB_posedge or  Tviol_DIB3_CLKB_posedge or 
 		 Tviol_DIB4_CLKB_posedge or  Tviol_DIB5_CLKB_posedge or 
 		 Tviol_DIB6_CLKB_posedge or  Tviol_DIB7_CLKB_posedge or 
 		 Tviol_DIB8_CLKB_posedge or  Tviol_DIB9_CLKB_posedge or 
 		 Tviol_DIB10_CLKB_posedge or  Tviol_DIB11_CLKB_posedge or
 		 Tviol_DIB12_CLKB_posedge or  Tviol_DIB13_CLKB_posedge or 
 		 Tviol_DIB14_CLKB_posedge or  Tviol_DIB15_CLKB_posedge or
                 Pviol_CLKA or Pviol_CLKB or Pviol_RSTA or Pviol_RSTB;

    -------------------------
    --  Functionality Section
    -------------------------

wait on CENA_ipd, CLKA_ipd, WRA_ipd, CSA, RSTA_ipd, DIA, ADA, CENB_ipd, CLKB_ipd, WRB_ipd, CSB, RSTB_ipd, DIB, ADB;

      end process VITALBehavior;

    VitalBehavior_DOA0  : process
      variable DOA0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA0_zd := DOA(0);

    VitalPathDelay01 (
      OutSignal => DOA0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA0",
      OutTemp => DOA0_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA0, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(0);
      end process;

    VitalBehavior_DOA1  : process
      variable DOA1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA1_zd := DOA(1);

    VitalPathDelay01 (
      OutSignal => DOA1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA1",
      OutTemp => DOA1_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA1, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(1);
      end process;

    VitalBehavior_DOB0  : process
      variable DOB0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB0_zd := DOB(0);

    VitalPathDelay01 (
      OutSignal => DOB0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB0",
      OutTemp => DOB0_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB0, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(0);
      end process;

    VitalBehavior_DOB1  : process
      variable DOB1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB1_zd := DOB(1);

    VitalPathDelay01 (
      OutSignal => DOB1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB1",
      OutTemp => DOB1_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB1, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(1);
      end process;

    VitalBehavior_DOB2  : process
      variable DOB2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB2_zd := DOB(2);

    VitalPathDelay01 (
      OutSignal => DOB2,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB2",
      OutTemp => DOB2_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB2, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(2);
      end process;

    VitalBehavior_DOB3  : process
      variable DOB3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB3_zd := DOB(3);

    VitalPathDelay01 (
      OutSignal => DOB3,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB3",
      OutTemp => DOB3_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB3, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(3);
      end process;

    VitalBehavior_DOB4  : process
      variable DOB4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB4_zd := DOB(4);

    VitalPathDelay01 (
      OutSignal => DOB4,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB4",
      OutTemp => DOB4_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB4, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(4);
      end process;

    VitalBehavior_DOB5  : process
      variable DOB5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB5_zd := DOB(5);

    VitalPathDelay01 (
      OutSignal => DOB5,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB5",
      OutTemp => DOB5_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB5, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(5);
      end process;

    VitalBehavior_DOB6  : process
      variable DOB6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB6_zd := DOB(6);

    VitalPathDelay01 (
      OutSignal => DOB6,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB6",
      OutTemp => DOB6_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB6, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(6);
      end process;

    VitalBehavior_DOB7  : process
      variable DOB7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB7_zd := DOB(7);

    VitalPathDelay01 (
      OutSignal => DOB7,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB7",
      OutTemp => DOB7_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB7, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(7);
      end process;

    VitalBehavior_DOB8  : process
      variable DOB8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB8_zd := DOB(8);

    VitalPathDelay01 (
      OutSignal => DOB8,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB8",
      OutTemp => DOB8_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB8, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(8);
      end process;

    VitalBehavior_DOB9  : process
      variable DOB9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB9_zd := DOB(9);

    VitalPathDelay01 (
      OutSignal => DOB9,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB9",
      OutTemp => DOB9_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB9, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(9);
      end process;

    VitalBehavior_DOB10  : process
      variable DOB10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB10_zd := DOB(10);

    VitalPathDelay01 (
      OutSignal => DOB10,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB10",
      OutTemp => DOB10_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB10, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(10);
      end process;

    VitalBehavior_DOB11  : process
      variable DOB11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB11_zd := DOB(11);

    VitalPathDelay01 (
      OutSignal => DOB11,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB11",
      OutTemp => DOB11_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB11, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(11);
      end process;

    VitalBehavior_DOB12  : process
      variable DOB12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB12_zd := DOB(12);

    VitalPathDelay01 (
      OutSignal => DOB12,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB12",
      OutTemp => DOB12_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB12, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(12);
      end process;

    VitalBehavior_DOB13  : process
      variable DOB13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB13_zd := DOB(13);

    VitalPathDelay01 (
      OutSignal => DOB13,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB13",
      OutTemp => DOB13_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB13, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(13);
      end process;

    VitalBehavior_DOB14  : process
      variable DOB14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB14_zd := DOB(14);

    VitalPathDelay01 (
      OutSignal => DOB14,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB14",
      OutTemp => DOB14_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB14, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(14);
      end process;

    VitalBehavior_DOB15  : process
      variable DOB15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB15_zd := DOB(15);

    VitalPathDelay01 (
      OutSignal => DOB15,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB15",
      OutTemp => DOB15_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB15, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(15);
      end process;



	DPRAM_INST: SC_DPRAM_16K
	   generic map(
		ADDR_WIDTH_A => 12,
		DATA_WIDTH_A => 2,
		ADDR_WIDTH_B => 9,
		DATA_WIDTH_B => 16,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CENA => CENA_ipd,
	        CLKA => CLKA_ipd,
	        WRA  => WRA_ipd,
	        CSA  => CSA,
	        RSTA => RSTA_ipd,
	        DIA  => DIA,
	        ADA  => ADA,
	        DOA  => DOA,

	        CENB => CENB_ipd,
	        CLKB => CLKB_ipd,
	        WRB  => WRB_ipd,
	        CSB  => CSB,
	        RSTB => RSTB_ipd,
	        DIB  => DIB,
	        ADB  => ADB,
	        DOB  => DOB);

end VITAL;

configuration CFG_RAMB8K_X2_X16_VITAL of RAMB8K_X2_X16 is
   for VITAL
   end for;
end CFG_RAMB8K_X2_X16_VITAL;



----- CELL RAMB8K_X4_X4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB8K_X4_X4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "dummy";
      tpd_CLKA_DOA0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_CLKB_DOB0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTA_DOA0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTB_DOB0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_CENA_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENA_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRA_CLKA_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRA_CLKA_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CENB_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENB_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRB_CLKB_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRB_CLKB_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_DIA0_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA1_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA2_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA3_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_DIB0_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB1_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB2_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB3_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA2_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA3_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA4_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA4_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA5_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA5_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA6_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA6_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA7_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA7_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA8_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA8_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA9_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA9_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA10_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA10_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB2_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB3_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB4_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB5_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB6_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB7_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB8_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB9_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB9_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB10_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADB10_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RSTA_CLKA_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTA_CLKA_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTB_CLKB_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTB_CLKB_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLKA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_CLKB_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTB_posedge                   :	VitalDelayType   := 2.0 ns;
      tipd_CENA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRA                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CENB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRB                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CENA                            :	in    STD_ULOGIC;
      CLKA                            :	in    STD_ULOGIC;
      WRA                             :	in    STD_ULOGIC;
      CSA0                            :	in    STD_ULOGIC;
      CSA1                            :	in    STD_ULOGIC;
      RSTA                            :	in    STD_ULOGIC;
      CENB                            :	in    STD_ULOGIC;
      CLKB                            :	in    STD_ULOGIC;
      WRB                             :	in    STD_ULOGIC;
      CSB0                            :	in    STD_ULOGIC;
      CSB1                            :	in    STD_ULOGIC;
      RSTB                            :	in    STD_ULOGIC;
      DIA0                            :	in    STD_ULOGIC;
      DIA1                            :	in    STD_ULOGIC;
      DIA2                            :	in    STD_ULOGIC;
      DIA3                            :	in    STD_ULOGIC;
      ADA0                            :	in    STD_ULOGIC;
      ADA1                            :	in    STD_ULOGIC;
      ADA2                            :	in    STD_ULOGIC;
      ADA3                            :	in    STD_ULOGIC;
      ADA4                            :	in    STD_ULOGIC;
      ADA5                            :	in    STD_ULOGIC;
      ADA6                            :	in    STD_ULOGIC;
      ADA7                            :	in    STD_ULOGIC;
      ADA8                            :	in    STD_ULOGIC;
      ADA9                            :	in    STD_ULOGIC;
      ADA10                           :	in    STD_ULOGIC;
      DIB0                            :	in    STD_ULOGIC;
      DIB1                            :	in    STD_ULOGIC;
      DIB2                            :	in    STD_ULOGIC;
      DIB3                            :	in    STD_ULOGIC;
      ADB0                            :	in    STD_ULOGIC;
      ADB1                            :	in    STD_ULOGIC;
      ADB2                            :	in    STD_ULOGIC;
      ADB3                            :	in    STD_ULOGIC;
      ADB4                            :	in    STD_ULOGIC;
      ADB5                            :	in    STD_ULOGIC;
      ADB6                            :	in    STD_ULOGIC;
      ADB7                            :	in    STD_ULOGIC;
      ADB8                            :	in    STD_ULOGIC;
      ADB9                            :	in    STD_ULOGIC;
      ADB10                           :	in    STD_ULOGIC;
      DOA0                            :	out   STD_ULOGIC;
      DOA1                            :	out   STD_ULOGIC;
      DOA2                            :	out   STD_ULOGIC;
      DOA3                            :	out   STD_ULOGIC;
      DOB0                            :	out   STD_ULOGIC;
      DOB1                            :	out   STD_ULOGIC;
      DOB2                            :	out   STD_ULOGIC;
      DOB3                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB8K_X4_X4 : entity is FALSE;
end RAMB8K_X4_X4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB8K_X4_X4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_DPRAM_16K
	   generic (
		ADDR_WIDTH_A    : integer := 11;
		DATA_WIDTH_A    : integer := 4;
		ADDR_WIDTH_B    : integer := 11;
		DATA_WIDTH_B    : integer := 4;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CENA : in  STD_LOGIC ;
		CLKA : in  STD_LOGIC ;
		WRA  : in  STD_LOGIC ;
		CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTA : in  STD_LOGIC ;
		DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
		ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
		DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

		CENB : in  STD_LOGIC ;
		CLKB : in  STD_LOGIC ;
		WRB  : in  STD_LOGIC ;
		CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTB : in  STD_LOGIC ;
		DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
		ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
		DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
		);
	end component ;

      signal CENA_ipd      : std_ulogic := 'X';
      signal CLKA_ipd      : std_ulogic := 'X';
      signal WRA_ipd       : std_ulogic := 'X';
      signal CSA0_ipd      : std_ulogic := 'X';
      signal CSA1_ipd      : std_ulogic := 'X';
      signal RSTA_ipd      : std_ulogic := 'X';

      signal CENB_ipd      : std_ulogic := 'X';
      signal CLKB_ipd      : std_ulogic := 'X';
      signal WRB_ipd       : std_ulogic := 'X';
      signal CSB0_ipd      : std_ulogic := 'X';
      signal CSB1_ipd      : std_ulogic := 'X';
      signal RSTB_ipd      : std_ulogic := 'X';

      signal DIA0_ipd      : std_ulogic := 'X';
      signal DIA1_ipd      : std_ulogic := 'X';
      signal DIA2_ipd      : std_ulogic := 'X';
      signal DIA3_ipd      : std_ulogic := 'X';

      signal ADA0_ipd      : std_ulogic := 'X';
      signal ADA1_ipd      : std_ulogic := 'X';
      signal ADA2_ipd      : std_ulogic := 'X';
      signal ADA3_ipd      : std_ulogic := 'X';
      signal ADA4_ipd      : std_ulogic := 'X';
      signal ADA5_ipd      : std_ulogic := 'X';
      signal ADA6_ipd      : std_ulogic := 'X';
      signal ADA7_ipd      : std_ulogic := 'X';
      signal ADA8_ipd      : std_ulogic := 'X';
      signal ADA9_ipd      : std_ulogic := 'X';
      signal ADA10_ipd     : std_ulogic := 'X';

      signal DIB0_ipd       : std_ulogic := 'X';
      signal DIB1_ipd       : std_ulogic := 'X';
      signal DIB2_ipd       : std_ulogic := 'X';
      signal DIB3_ipd       : std_ulogic := 'X';

      signal ADB0_ipd      : std_ulogic := 'X';
      signal ADB1_ipd      : std_ulogic := 'X';
      signal ADB2_ipd      : std_ulogic := 'X';
      signal ADB3_ipd      : std_ulogic := 'X';
      signal ADB4_ipd      : std_ulogic := 'X';
      signal ADB5_ipd      : std_ulogic := 'X';
      signal ADB6_ipd      : std_ulogic := 'X';
      signal ADB7_ipd      : std_ulogic := 'X';
      signal ADB8_ipd      : std_ulogic := 'X';
      signal ADB9_ipd      : std_ulogic := 'X';
      signal ADB10_ipd     : std_ulogic := 'X';

	signal CSA : std_logic_vector (1 downto 0);
	signal CSB : std_logic_vector (1 downto 0);
	signal DIA : std_logic_vector (3 downto 0);
	signal DOA : std_logic_vector (3 downto 0);
	signal DIB : std_logic_vector (3 downto 0);
	signal DOB : std_logic_vector (3 downto 0);
	signal ADA : std_logic_vector (10 downto 0);
	signal ADB : std_logic_vector (10 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);

begin 

	CSA <= CSA1_ipd & CSA0_ipd;
	CSB <= CSB1_ipd & CSB0_ipd;
	DIA <= DIA3_ipd & DIA2_ipd & DIA1_ipd & DIA0_ipd;
	DIB <= DIB3_ipd & DIB2_ipd & DIB1_ipd & DIB0_ipd;
	ADA <= ADA10_ipd & ADA9_ipd & ADA8_ipd & ADA7_ipd & ADA6_ipd & ADA5_ipd & ADA4_ipd & ADA3_ipd & ADA2_ipd & ADA1_ipd & ADA0_ipd;
	ADB <= ADB10_ipd & ADB9_ipd & ADB8_ipd & ADB7_ipd & ADB6_ipd & ADB5_ipd & ADB4_ipd & ADB3_ipd & ADB2_ipd & ADB1_ipd & ADB0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CENA_ipd, CENA, tipd_CENA);
        VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
        VitalWireDelay (CSA0_ipd, CSA0, tipd_CSA0);
        VitalWireDelay (CSA1_ipd, CSA1, tipd_CSA1);
        VitalWireDelay (WRA_ipd, WRA, tipd_WRA);
        VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);

        VitalWireDelay (CENB_ipd, CENB, tipd_CENB);
        VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
        VitalWireDelay (CSB0_ipd, CSB0, tipd_CSB0);
        VitalWireDelay (CSB1_ipd, CSB1, tipd_CSB1);
        VitalWireDelay (WRB_ipd, WRB, tipd_WRB);
        VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);

        VitalWireDelay (DIA0_ipd, DIA0, tipd_DIA0);
        VitalWireDelay (DIA1_ipd, DIA1, tipd_DIA1);
        VitalWireDelay (DIA2_ipd, DIA2, tipd_DIA2);
        VitalWireDelay (DIA3_ipd, DIA3, tipd_DIA3);

        VitalWireDelay (ADA0_ipd, ADA0, tipd_ADA0);
        VitalWireDelay (ADA1_ipd, ADA1, tipd_ADA1);
        VitalWireDelay (ADA2_ipd, ADA2, tipd_ADA2);
        VitalWireDelay (ADA3_ipd, ADA3, tipd_ADA3);
        VitalWireDelay (ADA4_ipd, ADA4, tipd_ADA4);
        VitalWireDelay (ADA5_ipd, ADA5, tipd_ADA5);
        VitalWireDelay (ADA6_ipd, ADA6, tipd_ADA6);
        VitalWireDelay (ADA7_ipd, ADA7, tipd_ADA7);
        VitalWireDelay (ADA8_ipd, ADA8, tipd_ADA8);
        VitalWireDelay (ADA9_ipd, ADA9, tipd_ADA9);
        VitalWireDelay (ADA10_ipd, ADA10, tipd_ADA10);

        VitalWireDelay (DIB0_ipd, DIB0, tipd_DIB0);
        VitalWireDelay (DIB1_ipd, DIB1, tipd_DIB1);
        VitalWireDelay (DIB2_ipd, DIB2, tipd_DIB2);
        VitalWireDelay (DIB3_ipd, DIB3, tipd_DIB3);

        VitalWireDelay (ADB0_ipd, ADB0, tipd_ADB0);
        VitalWireDelay (ADB1_ipd, ADB1, tipd_ADB1);
        VitalWireDelay (ADB2_ipd, ADB2, tipd_ADB2);
        VitalWireDelay (ADB3_ipd, ADB3, tipd_ADB3);
        VitalWireDelay (ADB4_ipd, ADB4, tipd_ADB4);
        VitalWireDelay (ADB5_ipd, ADB5, tipd_ADB5);
        VitalWireDelay (ADB6_ipd, ADB6, tipd_ADB6);
        VitalWireDelay (ADB7_ipd, ADB7, tipd_ADB7);
        VitalWireDelay (ADB8_ipd, ADB8, tipd_ADB8);
        VitalWireDelay (ADB9_ipd, ADB9, tipd_ADB9);
        VitalWireDelay (ADB10_ipd, ADB10, tipd_ADB10);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CENA_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_WRA_CLKA_posedge     : std_ulogic  := '0';

        variable Tviol_CENB_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_WRB_CLKB_posedge      : std_ulogic  := '0';


        variable Tviol_DIA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA3_CLKA_posedge    : std_ulogic  := '0';

        variable Tviol_ADA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA3_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA4_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA5_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA6_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA7_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA8_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA9_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA10_CLKA_posedge   : std_ulogic  := '0';

        variable Tviol_DIB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB3_CLKB_posedge    : std_ulogic  := '0';

        variable Tviol_ADB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB8_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB9_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB10_CLKB_posedge   : std_ulogic  := '0';

        variable Tviol_RSTA_CLKA_posedge_posedge : std_ulogic  := '0';
        variable Tviol_RSTB_CLKB_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CENA_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRA_CLKA_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CENB_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRB_CLKB_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA4_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA5_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA6_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA7_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA8_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA9_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA10_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB9_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB10_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RSTA_CLKA_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RSTB_CLKB_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLKA       : std_ulogic := '0';
        variable PInfo_CLKA       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_CLKB       : std_ulogic := '0';
        variable PInfo_CLkB       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTA        : std_ulogic := '0';
        variable PInfo_RSTA        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTB        : std_ulogic := '0';
        variable PInfo_RSTB        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DOA0_zd         : std_ulogic := 'X';
        variable DOA1_zd         : std_ulogic := 'X';
        variable DOA2_zd         : std_ulogic := 'X';
        variable DOA3_zd         : std_ulogic := 'X';
        variable DOB0_zd         : std_ulogic := 'X';
        variable DOB1_zd         : std_ulogic := 'X';
        variable DOB2_zd         : std_ulogic := 'X';
        variable DOB3_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CENA_CLKA_posedge,
          TimingData              => Tmkr_CENA_CLKA_posedge,
          TestSignal              => CENA_ipd,
          TestSignalName          => "CENA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENA_CLKA_noedge_posedge,
          SetupLow                => tsetup_CENA_CLKA_noedge_posedge,
          HoldLow                 => thold_CENA_CLKA_noedge_posedge,
          HoldHigh                => thold_CENA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRA_CLKA_posedge,
          TimingData              => Tmkr_WRA_CLKA_posedge,
          TestSignal              => WRA_ipd,
          TestSignalName          => "WRA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRA_CLKA_noedge_posedge,
          SetupLow                => tsetup_WRA_CLKA_noedge_posedge,
          HoldLow                 => thold_WRA_CLKA_noedge_posedge,
          HoldHigh                => thold_WRA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA0_CLKA_posedge,
          TimingData              => Tmkr_CSA0_CLKA_posedge,
          TestSignal              => CSA0_ipd,
          TestSignalName          => "CSA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA0_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA0_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA1_CLKA_posedge,
          TimingData              => Tmkr_CSA1_CLKA_posedge,
          TestSignal              => CSA1_ipd,
          TestSignalName          => "CSA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA1_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA1_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CENB_CLKB_posedge,
          TimingData              => Tmkr_CENB_CLKB_posedge,
          TestSignal              => CENB_ipd,
          TestSignalName          => "CENB",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENB_CLKB_noedge_posedge,
          SetupLow                => tsetup_CENB_CLKB_noedge_posedge,
          HoldLow                 => thold_CENB_CLKB_noedge_posedge,
          HoldHigh                => thold_CENB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRB_CLKB_posedge,
          TimingData              => Tmkr_WRB_CLKB_posedge,
          TestSignal              => WRB_ipd,
          TestSignalName          => "WRB",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRB_CLKB_noedge_posedge,
          SetupLow                => tsetup_WRB_CLKB_noedge_posedge,
          HoldLow                 => thold_WRB_CLKB_noedge_posedge,
          HoldHigh                => thold_WRB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB0_CLKB_posedge,
          TimingData              => Tmkr_CSB0_CLKB_posedge,
          TestSignal              => CSB0_ipd,
          TestSignalName          => "CSB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB0_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB0_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB1_CLKB_posedge,
          TimingData              => Tmkr_CSB1_CLKB_posedge,
          TestSignal              => CSB1_ipd,
          TestSignalName          => "CSB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB1_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB1_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA0_CLKA_posedge,
          TimingData              => Tmkr_DIA0_CLKA_posedge,
          TestSignal              => DIA0_ipd,
          TestSignalName          => "DIA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA0_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA0_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA1_CLKA_posedge,
          TimingData              => Tmkr_DIA1_CLKA_posedge,
          TestSignal              => DIA1_ipd,
          TestSignalName          => "DIA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA1_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA1_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA2_CLKA_posedge,
          TimingData              => Tmkr_DIA2_CLKA_posedge,
          TestSignal              => DIA2_ipd,
          TestSignalName          => "DIA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA2_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA2_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA3_CLKA_posedge,
          TimingData              => Tmkr_DIA3_CLKA_posedge,
          TestSignal              => DIA3_ipd,
          TestSignalName          => "DIA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA3_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA3_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA0_CLKA_posedge,
          TimingData              => Tmkr_ADA0_CLKA_posedge,
          TestSignal              => ADA0_ipd,
          TestSignalName          => "ADA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA0_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA0_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA1_CLKA_posedge,
          TimingData              => Tmkr_ADA1_CLKA_posedge,
          TestSignal              => ADA1_ipd,
          TestSignalName          => "ADA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA1_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA1_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA2_CLKA_posedge,
          TimingData              => Tmkr_ADA2_CLKA_posedge,
          TestSignal              => ADA2_ipd,
          TestSignalName          => "ADA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA2_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA2_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA3_CLKA_posedge,
          TimingData              => Tmkr_ADA3_CLKA_posedge,
          TestSignal              => ADA3_ipd,
          TestSignalName          => "ADA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA3_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA3_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA4_CLKA_posedge,
          TimingData              => Tmkr_ADA4_CLKA_posedge,
          TestSignal              => ADA4_ipd,
          TestSignalName          => "ADA4",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA4_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA4_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA4_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA4_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA5_CLKA_posedge,
          TimingData              => Tmkr_ADA5_CLKA_posedge,
          TestSignal              => ADA5_ipd,
          TestSignalName          => "ADA5",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA5_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA5_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA5_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA5_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA6_CLKA_posedge,
          TimingData              => Tmkr_ADA6_CLKA_posedge,
          TestSignal              => ADA6_ipd,
          TestSignalName          => "ADA6",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA6_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA6_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA6_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA6_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA7_CLKA_posedge,
          TimingData              => Tmkr_ADA7_CLKA_posedge,
          TestSignal              => ADA7_ipd,
          TestSignalName          => "ADA7",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA7_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA7_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA7_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA7_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA8_CLKA_posedge,
          TimingData              => Tmkr_ADA8_CLKA_posedge,
          TestSignal              => ADA8_ipd,
          TestSignalName          => "ADA8",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA8_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA8_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA8_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA8_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA9_CLKA_posedge,
          TimingData              => Tmkr_ADA9_CLKA_posedge,
          TestSignal              => ADA9_ipd,
          TestSignalName          => "ADA9",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA9_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA9_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA9_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA9_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA10_CLKA_posedge,
          TimingData              => Tmkr_ADA10_CLKA_posedge,
          TestSignal              => ADA10_ipd,
          TestSignalName          => "ADA10",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA10_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA10_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA10_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA10_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB0_CLKB_posedge,
          TimingData              => Tmkr_DIB0_CLKB_posedge,
          TestSignal              => DIB0_ipd,
          TestSignalName          => "DIB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB0_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB0_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB1_CLKB_posedge,
          TimingData              => Tmkr_DIB1_CLKB_posedge,
          TestSignal              => DIB1_ipd,
          TestSignalName          => "DIB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB1_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB1_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB2_CLKB_posedge,
          TimingData              => Tmkr_DIB2_CLKB_posedge,
          TestSignal              => DIB2_ipd,
          TestSignalName          => "DIB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB2_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB2_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB3_CLKB_posedge,
          TimingData              => Tmkr_DIB3_CLKB_posedge,
          TestSignal              => DIB3_ipd,
          TestSignalName          => "DIB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB3_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB3_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB0_CLKB_posedge,
          TimingData              => Tmkr_ADB0_CLKB_posedge,
          TestSignal              => ADB0_ipd,
          TestSignalName          => "ADB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB0_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB0_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB1_CLKB_posedge,
          TimingData              => Tmkr_ADB1_CLKB_posedge,
          TestSignal              => ADB1_ipd,
          TestSignalName          => "ADB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB1_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB1_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB2_CLKB_posedge,
          TimingData              => Tmkr_ADB2_CLKB_posedge,
          TestSignal              => ADB2_ipd,
          TestSignalName          => "ADB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB2_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB2_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB3_CLKB_posedge,
          TimingData              => Tmkr_ADB3_CLKB_posedge,
          TestSignal              => ADB3_ipd,
          TestSignalName          => "ADB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB3_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB3_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB4_CLKB_posedge,
          TimingData              => Tmkr_ADB4_CLKB_posedge,
          TestSignal              => ADB4_ipd,
          TestSignalName          => "ADB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB4_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB4_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB5_CLKB_posedge,
          TimingData              => Tmkr_ADB5_CLKB_posedge,
          TestSignal              => ADB5_ipd,
          TestSignalName          => "ADB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB5_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB5_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB6_CLKB_posedge,
          TimingData              => Tmkr_ADB6_CLKB_posedge,
          TestSignal              => ADB6_ipd,
          TestSignalName          => "ADB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB6_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB6_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB7_CLKB_posedge,
          TimingData              => Tmkr_ADB7_CLKB_posedge,
          TestSignal              => ADB7_ipd,
          TestSignalName          => "ADB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB7_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB7_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB8_CLKB_posedge,
          TimingData              => Tmkr_ADB8_CLKB_posedge,
          TestSignal              => ADB8_ipd,
          TestSignalName          => "ADB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB8_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB8_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB9_CLKB_posedge,
          TimingData              => Tmkr_ADB9_CLKB_posedge,
          TestSignal              => ADB9_ipd,
          TestSignalName          => "ADB9",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB9_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB9_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB9_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB9_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB10_CLKB_posedge,
          TimingData              => Tmkr_ADB10_CLKB_posedge,
          TestSignal              => ADB10_ipd,
          TestSignalName          => "ADB10",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB10_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB10_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB10_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB10_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKA,
          PeriodData              => PInfo_CLKA,
          TestSignal              => CLKA_ipd,
          TestSignalName          => "CLKA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKA_posedge,
          PulseWidthLow           => tpw_CLKA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKB,
          PeriodData              => PInfo_CLKB,
          TestSignal              => CLKB_ipd,
          TestSignalName          => "CLKB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKB_posedge,
          PulseWidthLow           => tpw_CLKB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTA,
          PeriodData              => PInfo_RSTA,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTA_posedge,
          PulseWidthLow           => tpw_RSTA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTB,
          PeriodData              => PInfo_RSTB,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTB_posedge,
          PulseWidthLow           => tpw_RSTB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X4_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTA_CLKA_posedge_posedge,
          TimingData              => Tmkr_RSTA_CLKA_posedge_posedge,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName          => "CLKA",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTA_CLKA_posedge_posedge,
          Removal                 => thold_RSTA_CLKA_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTB_CLKB_posedge_posedge,
          TimingData              => Tmkr_RSTB_CLKB_posedge_posedge,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName          => "CLKB",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTB_CLKB_posedge_posedge,
          Removal                 => thold_RSTB_CLKB_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CENA_CLKA_posedge or Tviol_WRA_CLKA_posedge or 
                 Tviol_CSA0_CLKA_posedge or Tviol_CSA1_CLKA_posedge or 
                 Tviol_ADA0_CLKA_posedge or Tviol_ADA1_CLKA_posedge or 
                 Tviol_ADA2_CLKA_posedge or Tviol_ADA3_CLKA_posedge or 
                 Tviol_ADA4_CLKA_posedge or Tviol_ADA5_CLKA_posedge or 
                 Tviol_ADA6_CLKA_posedge or Tviol_ADA7_CLKA_posedge or 
                 Tviol_ADA8_CLKA_posedge or Tviol_ADA9_CLKA_posedge or 
                 Tviol_ADA10_CLKA_posedge or 
                 Tviol_DIA0_CLKA_posedge or Tviol_DIA1_CLKA_posedge or
                 Tviol_DIA2_CLKA_posedge or Tviol_DIA3_CLKA_posedge or
                 Tviol_ADB0_CLKB_posedge or Tviol_ADB1_CLKB_posedge or 
                 Tviol_ADB2_CLKB_posedge or Tviol_ADB3_CLKB_posedge or 
                 Tviol_ADB4_CLKB_posedge or Tviol_ADB5_CLKB_posedge or 
                 Tviol_ADB6_CLKB_posedge or Tviol_ADB7_CLKB_posedge or 
                 Tviol_ADB8_CLKB_posedge or Tviol_ADB9_CLKB_posedge or 
                 Tviol_ADB10_CLKB_posedge or 
 		 Tviol_DIB0_CLKB_posedge or  Tviol_DIB1_CLKB_posedge or 
 		 Tviol_DIB2_CLKB_posedge or  Tviol_DIB3_CLKB_posedge or 
                 Pviol_CLKA or Pviol_CLKB or Pviol_RSTA or Pviol_RSTB;

    -------------------------
    --  Functionality Section
    -------------------------

wait on CENA_ipd, CLKA_ipd, WRA_ipd, CSA, RSTA_ipd, DIA, ADA, CENB_ipd, CLKB_ipd, WRB_ipd, CSB, RSTB_ipd, DIB, ADB;

      end process VITALBehavior;

    VitalBehavior_DOA0  : process
      variable DOA0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA0_zd := DOA(0);

    VitalPathDelay01 (
      OutSignal => DOA0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA0",
      OutTemp => DOA0_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA0, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(0);
      end process;

    VitalBehavior_DOA1  : process
      variable DOA1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA1_zd := DOA(1);

    VitalPathDelay01 (
      OutSignal => DOA1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA1",
      OutTemp => DOA1_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA1, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(1);
      end process;

    VitalBehavior_DOA2  : process
      variable DOA2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA2_zd := DOA(2);

    VitalPathDelay01 (
      OutSignal => DOA2,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA2",
      OutTemp => DOA2_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA2, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(2);
      end process;

    VitalBehavior_DOA3  : process
      variable DOA3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA3_zd := DOA(3);

    VitalPathDelay01 (
      OutSignal => DOA3,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA3",
      OutTemp => DOA3_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA3, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(3);
      end process;

    VitalBehavior_DOB0  : process
      variable DOB0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB0_zd := DOB(0);

    VitalPathDelay01 (
      OutSignal => DOB0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB0",
      OutTemp => DOB0_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB0, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(0);
      end process;

    VitalBehavior_DOB1  : process
      variable DOB1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB1_zd := DOB(1);

    VitalPathDelay01 (
      OutSignal => DOB1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB1",
      OutTemp => DOB1_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB1, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(1);
      end process;

    VitalBehavior_DOB2  : process
      variable DOB2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB2_zd := DOB(2);

    VitalPathDelay01 (
      OutSignal => DOB2,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB2",
      OutTemp => DOB2_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB2, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(2);
      end process;

    VitalBehavior_DOB3  : process
      variable DOB3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB3_zd := DOB(3);

    VitalPathDelay01 (
      OutSignal => DOB3,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB3",
      OutTemp => DOB3_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB3, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(3);
      end process;



	DPRAM_INST: SC_DPRAM_16K
	   generic map(
		ADDR_WIDTH_A => 11,
		DATA_WIDTH_A => 4,
		ADDR_WIDTH_B => 11,
		DATA_WIDTH_B => 4,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CENA => CENA_ipd,
	        CLKA => CLKA_ipd,
	        WRA  => WRA_ipd,
	        CSA  => CSA,
	        RSTA => RSTA_ipd,
	        DIA  => DIA,
	        ADA  => ADA,
	        DOA  => DOA,

	        CENB => CENB_ipd,
	        CLKB => CLKB_ipd,
	        WRB  => WRB_ipd,
	        CSB  => CSB,
	        RSTB => RSTB_ipd,
	        DIB  => DIB,
	        ADB  => ADB,
	        DOB  => DOB);

end VITAL;

configuration CFG_RAMB8K_X4_X4_VITAL of RAMB8K_X4_X4 is
   for VITAL
   end for;
end CFG_RAMB8K_X4_X4_VITAL;



----- CELL RAMB8K_X4_X8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB8K_X4_X8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "dummy";
      tpd_CLKA_DOA0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_CLKB_DOB0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTA_DOA0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTB_DOB0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_CENA_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENA_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRA_CLKA_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRA_CLKA_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CENB_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENB_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRB_CLKB_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRB_CLKB_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_DIA0_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA1_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA2_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA3_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_DIB0_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB1_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB2_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB3_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB4_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB5_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB6_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB7_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA2_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA3_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA4_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA4_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA5_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA5_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA6_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA6_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA7_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA7_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA8_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA8_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA9_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA9_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA10_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA10_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB2_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB3_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB4_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB5_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB6_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB7_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB8_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB9_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB9_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTA_CLKA_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTA_CLKA_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTB_CLKB_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTB_CLKB_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLKA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_CLKB_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTB_posedge                   :	VitalDelayType   := 2.0 ns;
      tipd_CENA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRA                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CENB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRB                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CENA                            :	in    STD_ULOGIC;
      CLKA                            :	in    STD_ULOGIC;
      WRA                             :	in    STD_ULOGIC;
      CSA0                            :	in    STD_ULOGIC;
      CSA1                            :	in    STD_ULOGIC;
      RSTA                            :	in    STD_ULOGIC;
      CENB                            :	in    STD_ULOGIC;
      CLKB                            :	in    STD_ULOGIC;
      WRB                             :	in    STD_ULOGIC;
      CSB0                            :	in    STD_ULOGIC;
      CSB1                            :	in    STD_ULOGIC;
      RSTB                            :	in    STD_ULOGIC;
      DIA0                            :	in    STD_ULOGIC;
      DIA1                            :	in    STD_ULOGIC;
      DIA2                            :	in    STD_ULOGIC;
      DIA3                            :	in    STD_ULOGIC;
      ADA0                            :	in    STD_ULOGIC;
      ADA1                            :	in    STD_ULOGIC;
      ADA2                            :	in    STD_ULOGIC;
      ADA3                            :	in    STD_ULOGIC;
      ADA4                            :	in    STD_ULOGIC;
      ADA5                            :	in    STD_ULOGIC;
      ADA6                            :	in    STD_ULOGIC;
      ADA7                            :	in    STD_ULOGIC;
      ADA8                            :	in    STD_ULOGIC;
      ADA9                            :	in    STD_ULOGIC;
      ADA10                           :	in    STD_ULOGIC;
      DIB0                            :	in    STD_ULOGIC;
      DIB1                            :	in    STD_ULOGIC;
      DIB2                            :	in    STD_ULOGIC;
      DIB3                            :	in    STD_ULOGIC;
      DIB4                            :	in    STD_ULOGIC;
      DIB5                            :	in    STD_ULOGIC;
      DIB6                            :	in    STD_ULOGIC;
      DIB7                            :	in    STD_ULOGIC;
      ADB0                            :	in    STD_ULOGIC;
      ADB1                            :	in    STD_ULOGIC;
      ADB2                            :	in    STD_ULOGIC;
      ADB3                            :	in    STD_ULOGIC;
      ADB4                            :	in    STD_ULOGIC;
      ADB5                            :	in    STD_ULOGIC;
      ADB6                            :	in    STD_ULOGIC;
      ADB7                            :	in    STD_ULOGIC;
      ADB8                            :	in    STD_ULOGIC;
      ADB9                            :	in    STD_ULOGIC;
      DOA0                            :	out   STD_ULOGIC;
      DOA1                            :	out   STD_ULOGIC;
      DOA2                            :	out   STD_ULOGIC;
      DOA3                            :	out   STD_ULOGIC;
      DOB0                            :	out   STD_ULOGIC;
      DOB1                            :	out   STD_ULOGIC;
      DOB2                            :	out   STD_ULOGIC;
      DOB3                            :	out   STD_ULOGIC;
      DOB4                            :	out   STD_ULOGIC;
      DOB5                            :	out   STD_ULOGIC;
      DOB6                            :	out   STD_ULOGIC;
      DOB7                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB8K_X4_X8 : entity is FALSE;
end RAMB8K_X4_X8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB8K_X4_X8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_DPRAM_16K
	   generic (
		ADDR_WIDTH_A    : integer := 11;
		DATA_WIDTH_A    : integer := 4;
		ADDR_WIDTH_B    : integer := 10;
		DATA_WIDTH_B    : integer := 8;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CENA : in  STD_LOGIC ;
		CLKA : in  STD_LOGIC ;
		WRA  : in  STD_LOGIC ;
		CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTA : in  STD_LOGIC ;
		DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
		ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
		DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

		CENB : in  STD_LOGIC ;
		CLKB : in  STD_LOGIC ;
		WRB  : in  STD_LOGIC ;
		CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTB : in  STD_LOGIC ;
		DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
		ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
		DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
		);
	end component ;

      signal CENA_ipd      : std_ulogic := 'X';
      signal CLKA_ipd      : std_ulogic := 'X';
      signal WRA_ipd       : std_ulogic := 'X';
      signal CSA0_ipd      : std_ulogic := 'X';
      signal CSA1_ipd      : std_ulogic := 'X';
      signal RSTA_ipd      : std_ulogic := 'X';

      signal CENB_ipd      : std_ulogic := 'X';
      signal CLKB_ipd      : std_ulogic := 'X';
      signal WRB_ipd       : std_ulogic := 'X';
      signal CSB0_ipd      : std_ulogic := 'X';
      signal CSB1_ipd      : std_ulogic := 'X';
      signal RSTB_ipd      : std_ulogic := 'X';

      signal DIA0_ipd      : std_ulogic := 'X';
      signal DIA1_ipd      : std_ulogic := 'X';
      signal DIA2_ipd      : std_ulogic := 'X';
      signal DIA3_ipd      : std_ulogic := 'X';

      signal ADA0_ipd      : std_ulogic := 'X';
      signal ADA1_ipd      : std_ulogic := 'X';
      signal ADA2_ipd      : std_ulogic := 'X';
      signal ADA3_ipd      : std_ulogic := 'X';
      signal ADA4_ipd      : std_ulogic := 'X';
      signal ADA5_ipd      : std_ulogic := 'X';
      signal ADA6_ipd      : std_ulogic := 'X';
      signal ADA7_ipd      : std_ulogic := 'X';
      signal ADA8_ipd      : std_ulogic := 'X';
      signal ADA9_ipd      : std_ulogic := 'X';
      signal ADA10_ipd     : std_ulogic := 'X';

      signal DIB0_ipd       : std_ulogic := 'X';
      signal DIB1_ipd       : std_ulogic := 'X';
      signal DIB2_ipd       : std_ulogic := 'X';
      signal DIB3_ipd       : std_ulogic := 'X';
      signal DIB4_ipd       : std_ulogic := 'X';
      signal DIB5_ipd       : std_ulogic := 'X';
      signal DIB6_ipd       : std_ulogic := 'X';
      signal DIB7_ipd       : std_ulogic := 'X';

      signal ADB0_ipd      : std_ulogic := 'X';
      signal ADB1_ipd      : std_ulogic := 'X';
      signal ADB2_ipd      : std_ulogic := 'X';
      signal ADB3_ipd      : std_ulogic := 'X';
      signal ADB4_ipd      : std_ulogic := 'X';
      signal ADB5_ipd      : std_ulogic := 'X';
      signal ADB6_ipd      : std_ulogic := 'X';
      signal ADB7_ipd      : std_ulogic := 'X';
      signal ADB8_ipd      : std_ulogic := 'X';
      signal ADB9_ipd      : std_ulogic := 'X';

	signal CSA : std_logic_vector (1 downto 0);
	signal CSB : std_logic_vector (1 downto 0);
	signal DIA : std_logic_vector (3 downto 0);
	signal DOA : std_logic_vector (3 downto 0);
	signal DIB : std_logic_vector (7 downto 0);
	signal DOB : std_logic_vector (7 downto 0);
	signal ADA : std_logic_vector (10 downto 0);
	signal ADB : std_logic_vector (9 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);

begin 

	CSA <= CSA1_ipd & CSA0_ipd;
	CSB <= CSB1_ipd & CSB0_ipd;
	DIA <= DIA3_ipd & DIA2_ipd & DIA1_ipd & DIA0_ipd;
	DIB <= DIB7_ipd & DIB6_ipd & DIB5_ipd & DIB4_ipd & DIB3_ipd & DIB2_ipd & DIB1_ipd & DIB0_ipd;
	ADA <= ADA10_ipd & ADA9_ipd & ADA8_ipd & ADA7_ipd & ADA6_ipd & ADA5_ipd & ADA4_ipd & ADA3_ipd & ADA2_ipd & ADA1_ipd & ADA0_ipd;
	ADB <= ADB9_ipd & ADB8_ipd & ADB7_ipd & ADB6_ipd & ADB5_ipd & ADB4_ipd & ADB3_ipd & ADB2_ipd & ADB1_ipd & ADB0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CENA_ipd, CENA, tipd_CENA);
        VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
        VitalWireDelay (CSA0_ipd, CSA0, tipd_CSA0);
        VitalWireDelay (CSA1_ipd, CSA1, tipd_CSA1);
        VitalWireDelay (WRA_ipd, WRA, tipd_WRA);
        VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);

        VitalWireDelay (CENB_ipd, CENB, tipd_CENB);
        VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
        VitalWireDelay (CSB0_ipd, CSB0, tipd_CSB0);
        VitalWireDelay (CSB1_ipd, CSB1, tipd_CSB1);
        VitalWireDelay (WRB_ipd, WRB, tipd_WRB);
        VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);

        VitalWireDelay (DIA0_ipd, DIA0, tipd_DIA0);
        VitalWireDelay (DIA1_ipd, DIA1, tipd_DIA1);
        VitalWireDelay (DIA2_ipd, DIA2, tipd_DIA2);
        VitalWireDelay (DIA3_ipd, DIA3, tipd_DIA3);

        VitalWireDelay (ADA0_ipd, ADA0, tipd_ADA0);
        VitalWireDelay (ADA1_ipd, ADA1, tipd_ADA1);
        VitalWireDelay (ADA2_ipd, ADA2, tipd_ADA2);
        VitalWireDelay (ADA3_ipd, ADA3, tipd_ADA3);
        VitalWireDelay (ADA4_ipd, ADA4, tipd_ADA4);
        VitalWireDelay (ADA5_ipd, ADA5, tipd_ADA5);
        VitalWireDelay (ADA6_ipd, ADA6, tipd_ADA6);
        VitalWireDelay (ADA7_ipd, ADA7, tipd_ADA7);
        VitalWireDelay (ADA8_ipd, ADA8, tipd_ADA8);
        VitalWireDelay (ADA9_ipd, ADA9, tipd_ADA9);
        VitalWireDelay (ADA10_ipd, ADA10, tipd_ADA10);

        VitalWireDelay (DIB0_ipd, DIB0, tipd_DIB0);
        VitalWireDelay (DIB1_ipd, DIB1, tipd_DIB1);
        VitalWireDelay (DIB2_ipd, DIB2, tipd_DIB2);
        VitalWireDelay (DIB3_ipd, DIB3, tipd_DIB3);
        VitalWireDelay (DIB4_ipd, DIB4, tipd_DIB4);
        VitalWireDelay (DIB5_ipd, DIB5, tipd_DIB5);
        VitalWireDelay (DIB6_ipd, DIB6, tipd_DIB6);
        VitalWireDelay (DIB7_ipd, DIB7, tipd_DIB7);


        VitalWireDelay (ADB0_ipd, ADB0, tipd_ADB0);
        VitalWireDelay (ADB1_ipd, ADB1, tipd_ADB1);
        VitalWireDelay (ADB2_ipd, ADB2, tipd_ADB2);
        VitalWireDelay (ADB3_ipd, ADB3, tipd_ADB3);
        VitalWireDelay (ADB4_ipd, ADB4, tipd_ADB4);
        VitalWireDelay (ADB5_ipd, ADB5, tipd_ADB5);
        VitalWireDelay (ADB6_ipd, ADB6, tipd_ADB6);
        VitalWireDelay (ADB7_ipd, ADB7, tipd_ADB7);
        VitalWireDelay (ADB8_ipd, ADB8, tipd_ADB8);
        VitalWireDelay (ADB9_ipd, ADB9, tipd_ADB9);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CENA_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_WRA_CLKA_posedge     : std_ulogic  := '0';

        variable Tviol_CENB_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_WRB_CLKB_posedge      : std_ulogic  := '0';

        variable Tviol_DIA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA3_CLKA_posedge    : std_ulogic  := '0';

        variable Tviol_ADA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA3_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA4_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA5_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA6_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA7_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA8_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA9_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA10_CLKA_posedge   : std_ulogic  := '0';

        variable Tviol_DIB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB7_CLKB_posedge    : std_ulogic  := '0';

        variable Tviol_ADB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB8_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB9_CLKB_posedge    : std_ulogic  := '0';

        variable Tviol_RSTA_CLKA_posedge_posedge : std_ulogic  := '0';
        variable Tviol_RSTB_CLKB_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CENA_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRA_CLKA_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CENB_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRB_CLKB_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA4_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA5_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA6_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA7_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA8_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA9_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA10_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB9_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RSTA_CLKA_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RSTB_CLKB_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLKA       : std_ulogic := '0';
        variable PInfo_CLKA       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_CLKB       : std_ulogic := '0';
        variable PInfo_CLkB       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTA        : std_ulogic := '0';
        variable PInfo_RSTA        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTB        : std_ulogic := '0';
        variable PInfo_RSTB        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DOA0_zd         : std_ulogic := 'X';
        variable DOA1_zd         : std_ulogic := 'X';
        variable DOA2_zd         : std_ulogic := 'X';
        variable DOA3_zd         : std_ulogic := 'X';
        variable DOB0_zd         : std_ulogic := 'X';
        variable DOB1_zd         : std_ulogic := 'X';
        variable DOB2_zd         : std_ulogic := 'X';
        variable DOB3_zd         : std_ulogic := 'X';
        variable DOB4_zd         : std_ulogic := 'X';
        variable DOB5_zd         : std_ulogic := 'X';
        variable DOB6_zd         : std_ulogic := 'X';
        variable DOB7_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CENA_CLKA_posedge,
          TimingData              => Tmkr_CENA_CLKA_posedge,
          TestSignal              => CENA_ipd,
          TestSignalName          => "CENA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENA_CLKA_noedge_posedge,
          SetupLow                => tsetup_CENA_CLKA_noedge_posedge,
          HoldLow                 => thold_CENA_CLKA_noedge_posedge,
          HoldHigh                => thold_CENA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRA_CLKA_posedge,
          TimingData              => Tmkr_WRA_CLKA_posedge,
          TestSignal              => WRA_ipd,
          TestSignalName          => "WRA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRA_CLKA_noedge_posedge,
          SetupLow                => tsetup_WRA_CLKA_noedge_posedge,
          HoldLow                 => thold_WRA_CLKA_noedge_posedge,
          HoldHigh                => thold_WRA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA0_CLKA_posedge,
          TimingData              => Tmkr_CSA0_CLKA_posedge,
          TestSignal              => CSA0_ipd,
          TestSignalName          => "CSA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA0_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA0_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA1_CLKA_posedge,
          TimingData              => Tmkr_CSA1_CLKA_posedge,
          TestSignal              => CSA1_ipd,
          TestSignalName          => "CSA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA1_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA1_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CENB_CLKB_posedge,
          TimingData              => Tmkr_CENB_CLKB_posedge,
          TestSignal              => CENB_ipd,
          TestSignalName          => "CENB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENB_CLKB_noedge_posedge,
          SetupLow                => tsetup_CENB_CLKB_noedge_posedge,
          HoldLow                 => thold_CENB_CLKB_noedge_posedge,
          HoldHigh                => thold_CENB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRB_CLKB_posedge,
          TimingData              => Tmkr_WRB_CLKB_posedge,
          TestSignal              => WRB_ipd,
          TestSignalName          => "WRB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRB_CLKB_noedge_posedge,
          SetupLow                => tsetup_WRB_CLKB_noedge_posedge,
          HoldLow                 => thold_WRB_CLKB_noedge_posedge,
          HoldHigh                => thold_WRB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB0_CLKB_posedge,
          TimingData              => Tmkr_CSB0_CLKB_posedge,
          TestSignal              => CSB0_ipd,
          TestSignalName          => "CSB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB0_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB0_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB1_CLKB_posedge,
          TimingData              => Tmkr_CSB1_CLKB_posedge,
          TestSignal              => CSB1_ipd,
          TestSignalName          => "CSB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB1_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB1_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA0_CLKA_posedge,
          TimingData              => Tmkr_DIA0_CLKA_posedge,
          TestSignal              => DIA0_ipd,
          TestSignalName          => "DIA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA0_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA0_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA1_CLKA_posedge,
          TimingData              => Tmkr_DIA1_CLKA_posedge,
          TestSignal              => DIA1_ipd,
          TestSignalName          => "DIA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA1_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA1_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA2_CLKA_posedge,
          TimingData              => Tmkr_DIA2_CLKA_posedge,
          TestSignal              => DIA2_ipd,
          TestSignalName          => "DIA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA2_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA2_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA3_CLKA_posedge,
          TimingData              => Tmkr_DIA3_CLKA_posedge,
          TestSignal              => DIA3_ipd,
          TestSignalName          => "DIA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA3_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA3_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA0_CLKA_posedge,
          TimingData              => Tmkr_ADA0_CLKA_posedge,
          TestSignal              => ADA0_ipd,
          TestSignalName          => "ADA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA0_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA0_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA1_CLKA_posedge,
          TimingData              => Tmkr_ADA1_CLKA_posedge,
          TestSignal              => ADA1_ipd,
          TestSignalName          => "ADA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA1_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA1_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA2_CLKA_posedge,
          TimingData              => Tmkr_ADA2_CLKA_posedge,
          TestSignal              => ADA2_ipd,
          TestSignalName          => "ADA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA2_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA2_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA3_CLKA_posedge,
          TimingData              => Tmkr_ADA3_CLKA_posedge,
          TestSignal              => ADA3_ipd,
          TestSignalName          => "ADA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA3_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA3_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA4_CLKA_posedge,
          TimingData              => Tmkr_ADA4_CLKA_posedge,
          TestSignal              => ADA4_ipd,
          TestSignalName          => "ADA4",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA4_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA4_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA4_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA4_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA5_CLKA_posedge,
          TimingData              => Tmkr_ADA5_CLKA_posedge,
          TestSignal              => ADA5_ipd,
          TestSignalName          => "ADA5",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA5_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA5_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA5_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA5_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA6_CLKA_posedge,
          TimingData              => Tmkr_ADA6_CLKA_posedge,
          TestSignal              => ADA6_ipd,
          TestSignalName          => "ADA6",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA6_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA6_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA6_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA6_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA7_CLKA_posedge,
          TimingData              => Tmkr_ADA7_CLKA_posedge,
          TestSignal              => ADA7_ipd,
          TestSignalName          => "ADA7",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA7_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA7_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA7_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA7_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA8_CLKA_posedge,
          TimingData              => Tmkr_ADA8_CLKA_posedge,
          TestSignal              => ADA8_ipd,
          TestSignalName          => "ADA8",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA8_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA8_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA8_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA8_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA9_CLKA_posedge,
          TimingData              => Tmkr_ADA9_CLKA_posedge,
          TestSignal              => ADA9_ipd,
          TestSignalName          => "ADA9",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA9_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA9_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA9_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA9_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA10_CLKA_posedge,
          TimingData              => Tmkr_ADA10_CLKA_posedge,
          TestSignal              => ADA10_ipd,
          TestSignalName          => "ADA10",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA10_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA10_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA10_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA10_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB0_CLKB_posedge,
          TimingData              => Tmkr_DIB0_CLKB_posedge,
          TestSignal              => DIB0_ipd,
          TestSignalName          => "DIB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB0_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB0_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB1_CLKB_posedge,
          TimingData              => Tmkr_DIB1_CLKB_posedge,
          TestSignal              => DIB1_ipd,
          TestSignalName          => "DIB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB1_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB1_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB2_CLKB_posedge,
          TimingData              => Tmkr_DIB2_CLKB_posedge,
          TestSignal              => DIB2_ipd,
          TestSignalName          => "DIB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB2_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB2_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB3_CLKB_posedge,
          TimingData              => Tmkr_DIB3_CLKB_posedge,
          TestSignal              => DIB3_ipd,
          TestSignalName          => "DIB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB3_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB3_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB4_CLKB_posedge,
          TimingData              => Tmkr_DIB4_CLKB_posedge,
          TestSignal              => DIB4_ipd,
          TestSignalName          => "DIB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB4_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB4_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB5_CLKB_posedge,
          TimingData              => Tmkr_DIB5_CLKB_posedge,
          TestSignal              => DIB5_ipd,
          TestSignalName          => "DIB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB5_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB5_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB6_CLKB_posedge,
          TimingData              => Tmkr_DIB6_CLKB_posedge,
          TestSignal              => DIB6_ipd,
          TestSignalName          => "DIB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB6_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB6_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB7_CLKB_posedge,
          TimingData              => Tmkr_DIB7_CLKB_posedge,
          TestSignal              => DIB7_ipd,
          TestSignalName          => "DIB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB7_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB7_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB0_CLKB_posedge,
          TimingData              => Tmkr_ADB0_CLKB_posedge,
          TestSignal              => ADB0_ipd,
          TestSignalName          => "ADB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB0_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB0_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB1_CLKB_posedge,
          TimingData              => Tmkr_ADB1_CLKB_posedge,
          TestSignal              => ADB1_ipd,
          TestSignalName          => "ADB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB1_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB1_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB2_CLKB_posedge,
          TimingData              => Tmkr_ADB2_CLKB_posedge,
          TestSignal              => ADB2_ipd,
          TestSignalName          => "ADB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB2_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB2_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB3_CLKB_posedge,
          TimingData              => Tmkr_ADB3_CLKB_posedge,
          TestSignal              => ADB3_ipd,
          TestSignalName          => "ADB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB3_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB3_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB4_CLKB_posedge,
          TimingData              => Tmkr_ADB4_CLKB_posedge,
          TestSignal              => ADB4_ipd,
          TestSignalName          => "ADB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB4_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB4_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB5_CLKB_posedge,
          TimingData              => Tmkr_ADB5_CLKB_posedge,
          TestSignal              => ADB5_ipd,
          TestSignalName          => "ADB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB5_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB5_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB6_CLKB_posedge,
          TimingData              => Tmkr_ADB6_CLKB_posedge,
          TestSignal              => ADB6_ipd,
          TestSignalName          => "ADB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB6_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB6_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB7_CLKB_posedge,
          TimingData              => Tmkr_ADB7_CLKB_posedge,
          TestSignal              => ADB7_ipd,
          TestSignalName          => "ADB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB7_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB7_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB8_CLKB_posedge,
          TimingData              => Tmkr_ADB8_CLKB_posedge,
          TestSignal              => ADB8_ipd,
          TestSignalName          => "ADB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB8_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB8_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB9_CLKB_posedge,
          TimingData              => Tmkr_ADB9_CLKB_posedge,
          TestSignal              => ADB9_ipd,
          TestSignalName          => "ADB9",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB9_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB9_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB9_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB9_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKA,
          PeriodData              => PInfo_CLKA,
          TestSignal              => CLKA_ipd,
          TestSignalName          => "CLKA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKA_posedge,
          PulseWidthLow           => tpw_CLKA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKB,
          PeriodData              => PInfo_CLKB,
          TestSignal              => CLKB_ipd,
          TestSignalName          => "CLKB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKB_posedge,
          PulseWidthLow           => tpw_CLKB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTA,
          PeriodData              => PInfo_RSTA,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTA_posedge,
          PulseWidthLow           => tpw_RSTA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTB,
          PeriodData              => PInfo_RSTB,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTB_posedge,
          PulseWidthLow           => tpw_RSTB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X4_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTA_CLKA_posedge_posedge,
          TimingData              => Tmkr_RSTA_CLKA_posedge_posedge,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName          => "CLKA",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTA_CLKA_posedge_posedge,
          Removal                 => thold_RSTA_CLKA_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTB_CLKB_posedge_posedge,
          TimingData              => Tmkr_RSTB_CLKB_posedge_posedge,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName          => "CLKB",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTB_CLKB_posedge_posedge,
          Removal                 => thold_RSTB_CLKB_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CENA_CLKA_posedge or Tviol_WRA_CLKA_posedge or 
                 Tviol_CSA0_CLKA_posedge or Tviol_CSA1_CLKA_posedge or 
                 Tviol_ADA0_CLKA_posedge or Tviol_ADA1_CLKA_posedge or 
                 Tviol_ADA2_CLKA_posedge or Tviol_ADA3_CLKA_posedge or 
                 Tviol_ADA4_CLKA_posedge or Tviol_ADA5_CLKA_posedge or 
                 Tviol_ADA6_CLKA_posedge or Tviol_ADA7_CLKA_posedge or 
                 Tviol_ADA8_CLKA_posedge or Tviol_ADA9_CLKA_posedge or 
                 Tviol_ADA10_CLKA_posedge or
                 Tviol_DIA0_CLKA_posedge or Tviol_DIA1_CLKA_posedge or
                 Tviol_DIA2_CLKA_posedge or Tviol_DIA3_CLKA_posedge or
                 Tviol_ADB0_CLKB_posedge or Tviol_ADB1_CLKB_posedge or 
                 Tviol_ADB2_CLKB_posedge or Tviol_ADB3_CLKB_posedge or 
                 Tviol_ADB4_CLKB_posedge or Tviol_ADB5_CLKB_posedge or 
                 Tviol_ADB6_CLKB_posedge or Tviol_ADB7_CLKB_posedge or 
                 Tviol_ADB8_CLKB_posedge or Tviol_ADB9_CLKB_posedge or 
 		 Tviol_DIB0_CLKB_posedge or  Tviol_DIB1_CLKB_posedge or 
 		 Tviol_DIB2_CLKB_posedge or  Tviol_DIB3_CLKB_posedge or 
 		 Tviol_DIB4_CLKB_posedge or  Tviol_DIB5_CLKB_posedge or 
 		 Tviol_DIB6_CLKB_posedge or  Tviol_DIB7_CLKB_posedge or 
                 Pviol_CLKA or Pviol_CLKB or Pviol_RSTA or Pviol_RSTB;

    -------------------------
    --  Functionality Section
    -------------------------

wait on CENA_ipd, CLKA_ipd, WRA_ipd, CSA, RSTA_ipd, DIA, ADA, CENB_ipd, CLKB_ipd, WRB_ipd, CSB, RSTB_ipd, DIB, ADB;

      end process VITALBehavior;

    VitalBehavior_DOA0  : process
      variable DOA0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA0_zd := DOA(0);

    VitalPathDelay01 (
      OutSignal => DOA0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA0",
      OutTemp => DOA0_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA0, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(0);
      end process;

    VitalBehavior_DOA1  : process
      variable DOA1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA1_zd := DOA(1);

    VitalPathDelay01 (
      OutSignal => DOA1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA1",
      OutTemp => DOA1_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA1, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(1);
      end process;

    VitalBehavior_DOA2  : process
      variable DOA2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA2_zd := DOA(2);

    VitalPathDelay01 (
      OutSignal => DOA2,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA2",
      OutTemp => DOA2_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA2, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(2);
      end process;

    VitalBehavior_DOA3  : process
      variable DOA3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA3_zd := DOA(3);

    VitalPathDelay01 (
      OutSignal => DOA3,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA3",
      OutTemp => DOA3_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA3, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(3);
      end process;

    VitalBehavior_DOB0  : process
      variable DOB0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB0_zd := DOB(0);

    VitalPathDelay01 (
      OutSignal => DOB0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB0",
      OutTemp => DOB0_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB0, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(0);
      end process;

    VitalBehavior_DOB1  : process
      variable DOB1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB1_zd := DOB(1);

    VitalPathDelay01 (
      OutSignal => DOB1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB1",
      OutTemp => DOB1_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB1, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(1);
      end process;

    VitalBehavior_DOB2  : process
      variable DOB2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB2_zd := DOB(2);

    VitalPathDelay01 (
      OutSignal => DOB2,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB2",
      OutTemp => DOB2_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB2, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(2);
      end process;

    VitalBehavior_DOB3  : process
      variable DOB3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB3_zd := DOB(3);

    VitalPathDelay01 (
      OutSignal => DOB3,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB3",
      OutTemp => DOB3_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB3, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(3);
      end process;

    VitalBehavior_DOB4  : process
      variable DOB4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB4_zd := DOB(4);

    VitalPathDelay01 (
      OutSignal => DOB4,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB4",
      OutTemp => DOB4_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB4, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(4);
      end process;

    VitalBehavior_DOB5  : process
      variable DOB5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB5_zd := DOB(5);

    VitalPathDelay01 (
      OutSignal => DOB5,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB5",
      OutTemp => DOB5_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB5, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(5);
      end process;

    VitalBehavior_DOB6  : process
      variable DOB6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB6_zd := DOB(6);

    VitalPathDelay01 (
      OutSignal => DOB6,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB6",
      OutTemp => DOB6_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB6, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(6);
      end process;

    VitalBehavior_DOB7  : process
      variable DOB7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB7_zd := DOB(7);

    VitalPathDelay01 (
      OutSignal => DOB7,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB7",
      OutTemp => DOB7_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB7, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(7);
      end process;



	DPRAM_INST: SC_DPRAM_16K
	   generic map(
		ADDR_WIDTH_A => 11,
		DATA_WIDTH_A => 4,
		ADDR_WIDTH_B => 10,
		DATA_WIDTH_B => 8,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CENA => CENA_ipd,
	        CLKA => CLKA_ipd,
	        WRA  => WRA_ipd,
	        CSA  => CSA,
	        RSTA => RSTA_ipd,
	        DIA  => DIA,
	        ADA  => ADA,
	        DOA  => DOA,

	        CENB => CENB_ipd,
	        CLKB => CLKB_ipd,
	        WRB  => WRB_ipd,
	        CSB  => CSB,
	        RSTB => RSTB_ipd,
	        DIB  => DIB,
	        ADB  => ADB,
	        DOB  => DOB);

end VITAL;

configuration CFG_RAMB8K_X4_X8_VITAL of RAMB8K_X4_X8 is
   for VITAL
   end for;
end CFG_RAMB8K_X4_X8_VITAL;



----- CELL RAMB8K_X4_X16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB8K_X4_X16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "dummy";
      tpd_CLKA_DOA0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_CLKB_DOB0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTA_DOA0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTB_DOB0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_CENA_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENA_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRA_CLKA_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRA_CLKA_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CENB_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENB_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRB_CLKB_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRB_CLKB_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_DIA0_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA1_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA2_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA3_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_DIB0_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB1_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB2_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB3_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB4_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB5_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB6_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB7_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB8_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB9_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB9_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB10_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB10_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB11_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB11_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB12_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB12_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB13_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB13_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB14_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB14_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB15_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB15_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA2_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA3_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA4_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA4_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA5_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA5_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA6_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA6_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA7_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA7_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA8_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA8_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA9_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA9_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA10_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_ADA10_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB2_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB3_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB4_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB5_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB6_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB7_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB8_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTA_CLKA_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTA_CLKA_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTB_CLKB_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTB_CLKB_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLKA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_CLKB_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTB_posedge                   :	VitalDelayType   := 2.0 ns;
      tipd_CENA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRA                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CENB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRB                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CENA                            :	in    STD_ULOGIC;
      CLKA                            :	in    STD_ULOGIC;
      WRA                             :	in    STD_ULOGIC;
      CSA0                            :	in    STD_ULOGIC;
      CSA1                            :	in    STD_ULOGIC;
      RSTA                            :	in    STD_ULOGIC;
      CENB                            :	in    STD_ULOGIC;
      CLKB                            :	in    STD_ULOGIC;
      WRB                             :	in    STD_ULOGIC;
      CSB0                            :	in    STD_ULOGIC;
      CSB1                            :	in    STD_ULOGIC;
      RSTB                            :	in    STD_ULOGIC;
      DIA0                            :	in    STD_ULOGIC;
      DIA1                            :	in    STD_ULOGIC;
      DIA2                            :	in    STD_ULOGIC;
      DIA3                            :	in    STD_ULOGIC;
      ADA0                            :	in    STD_ULOGIC;
      ADA1                            :	in    STD_ULOGIC;
      ADA2                            :	in    STD_ULOGIC;
      ADA3                            :	in    STD_ULOGIC;
      ADA4                            :	in    STD_ULOGIC;
      ADA5                            :	in    STD_ULOGIC;
      ADA6                            :	in    STD_ULOGIC;
      ADA7                            :	in    STD_ULOGIC;
      ADA8                            :	in    STD_ULOGIC;
      ADA9                            :	in    STD_ULOGIC;
      ADA10                           :	in    STD_ULOGIC;
      DIB0                            :	in    STD_ULOGIC;
      DIB1                            :	in    STD_ULOGIC;
      DIB2                            :	in    STD_ULOGIC;
      DIB3                            :	in    STD_ULOGIC;
      DIB4                            :	in    STD_ULOGIC;
      DIB5                            :	in    STD_ULOGIC;
      DIB6                            :	in    STD_ULOGIC;
      DIB7                            :	in    STD_ULOGIC;
      DIB8                            :	in    STD_ULOGIC;
      DIB9                            :	in    STD_ULOGIC;
      DIB10                           :	in    STD_ULOGIC;
      DIB11                           :	in    STD_ULOGIC;
      DIB12                           :	in    STD_ULOGIC;
      DIB13                           :	in    STD_ULOGIC;
      DIB14                           :	in    STD_ULOGIC;
      DIB15                           :	in    STD_ULOGIC;
      ADB0                            :	in    STD_ULOGIC;
      ADB1                            :	in    STD_ULOGIC;
      ADB2                            :	in    STD_ULOGIC;
      ADB3                            :	in    STD_ULOGIC;
      ADB4                            :	in    STD_ULOGIC;
      ADB5                            :	in    STD_ULOGIC;
      ADB6                            :	in    STD_ULOGIC;
      ADB7                            :	in    STD_ULOGIC;
      ADB8                            :	in    STD_ULOGIC;
      DOA0                            :	out   STD_ULOGIC;
      DOA1                            :	out   STD_ULOGIC;
      DOA2                            :	out   STD_ULOGIC;
      DOA3                            :	out   STD_ULOGIC;
      DOB0                            :	out   STD_ULOGIC;
      DOB1                            :	out   STD_ULOGIC;
      DOB2                            :	out   STD_ULOGIC;
      DOB3                            :	out   STD_ULOGIC;
      DOB4                            :	out   STD_ULOGIC;
      DOB5                            :	out   STD_ULOGIC;
      DOB6                            :	out   STD_ULOGIC;
      DOB7                            :	out   STD_ULOGIC;
      DOB8                            :	out   STD_ULOGIC;
      DOB9                            :	out   STD_ULOGIC;
      DOB10                           :	out   STD_ULOGIC;
      DOB11                           :	out   STD_ULOGIC;
      DOB12                           :	out   STD_ULOGIC;
      DOB13                           :	out   STD_ULOGIC;
      DOB14                           :	out   STD_ULOGIC;
      DOB15                           :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB8K_X4_X16 : entity is FALSE;
end RAMB8K_X4_X16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB8K_X4_X16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_DPRAM_16K
	   generic (
		ADDR_WIDTH_A    : integer := 11;
		DATA_WIDTH_A    : integer := 4;
		ADDR_WIDTH_B    : integer := 9;
		DATA_WIDTH_B    : integer := 16;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CENA : in  STD_LOGIC ;
		CLKA : in  STD_LOGIC ;
		WRA  : in  STD_LOGIC ;
		CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTA : in  STD_LOGIC ;
		DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
		ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
		DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

		CENB : in  STD_LOGIC ;
		CLKB : in  STD_LOGIC ;
		WRB  : in  STD_LOGIC ;
		CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTB : in  STD_LOGIC ;
		DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
		ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
		DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
		);
	end component ;

      signal CENA_ipd      : std_ulogic := 'X';
      signal CLKA_ipd      : std_ulogic := 'X';
      signal WRA_ipd       : std_ulogic := 'X';
      signal CSA0_ipd      : std_ulogic := 'X';
      signal CSA1_ipd      : std_ulogic := 'X';
      signal RSTA_ipd      : std_ulogic := 'X';

      signal CENB_ipd      : std_ulogic := 'X';
      signal CLKB_ipd      : std_ulogic := 'X';
      signal WRB_ipd       : std_ulogic := 'X';
      signal CSB0_ipd      : std_ulogic := 'X';
      signal CSB1_ipd      : std_ulogic := 'X';
      signal RSTB_ipd      : std_ulogic := 'X';

      signal DIA0_ipd      : std_ulogic := 'X';
      signal DIA1_ipd      : std_ulogic := 'X';
      signal DIA2_ipd      : std_ulogic := 'X';
      signal DIA3_ipd      : std_ulogic := 'X';

      signal ADA0_ipd      : std_ulogic := 'X';
      signal ADA1_ipd      : std_ulogic := 'X';
      signal ADA2_ipd      : std_ulogic := 'X';
      signal ADA3_ipd      : std_ulogic := 'X';
      signal ADA4_ipd      : std_ulogic := 'X';
      signal ADA5_ipd      : std_ulogic := 'X';
      signal ADA6_ipd      : std_ulogic := 'X';
      signal ADA7_ipd      : std_ulogic := 'X';
      signal ADA8_ipd      : std_ulogic := 'X';
      signal ADA9_ipd      : std_ulogic := 'X';
      signal ADA10_ipd     : std_ulogic := 'X';

      signal DIB0_ipd       : std_ulogic := 'X';
      signal DIB1_ipd       : std_ulogic := 'X';
      signal DIB2_ipd       : std_ulogic := 'X';
      signal DIB3_ipd       : std_ulogic := 'X';
      signal DIB4_ipd       : std_ulogic := 'X';
      signal DIB5_ipd       : std_ulogic := 'X';
      signal DIB6_ipd       : std_ulogic := 'X';
      signal DIB7_ipd       : std_ulogic := 'X';
      signal DIB8_ipd       : std_ulogic := 'X';
      signal DIB9_ipd       : std_ulogic := 'X';
      signal DIB10_ipd      : std_ulogic := 'X';
      signal DIB11_ipd      : std_ulogic := 'X';
      signal DIB12_ipd      : std_ulogic := 'X';
      signal DIB13_ipd      : std_ulogic := 'X';
      signal DIB14_ipd      : std_ulogic := 'X';
      signal DIB15_ipd      : std_ulogic := 'X';

      signal ADB0_ipd      : std_ulogic := 'X';
      signal ADB1_ipd      : std_ulogic := 'X';
      signal ADB2_ipd      : std_ulogic := 'X';
      signal ADB3_ipd      : std_ulogic := 'X';
      signal ADB4_ipd      : std_ulogic := 'X';
      signal ADB5_ipd      : std_ulogic := 'X';
      signal ADB6_ipd      : std_ulogic := 'X';
      signal ADB7_ipd      : std_ulogic := 'X';
      signal ADB8_ipd      : std_ulogic := 'X';

	signal CSA : std_logic_vector (1 downto 0);
	signal CSB : std_logic_vector (1 downto 0);
	signal DIA : std_logic_vector (3 downto 0);
	signal DOA : std_logic_vector (3 downto 0);
	signal DIB : std_logic_vector (15 downto 0);
	signal DOB : std_logic_vector (15 downto 0);
	signal ADA : std_logic_vector (10 downto 0);
	signal ADB : std_logic_vector (8 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);

begin 

	CSA <= CSA1_ipd & CSA0_ipd;
	CSB <= CSB1_ipd & CSB0_ipd;
	DIA <= DIA3_ipd & DIA2_ipd & DIA1_ipd & DIA0_ipd;
	DIB <= DIB15_ipd & DIB14_ipd & DIB13_ipd & DIB12_ipd & DIB11_ipd & DIB10_ipd & DIB9_ipd & DIB8_ipd & DIB7_ipd & DIB6_ipd & DIB5_ipd & DIB4_ipd & DIB3_ipd & DIB2_ipd & DIB1_ipd & DIB0_ipd;
	ADA <= ADA10_ipd & ADA9_ipd & ADA8_ipd & ADA7_ipd & ADA6_ipd & ADA5_ipd & ADA4_ipd & ADA3_ipd & ADA2_ipd & ADA1_ipd & ADA0_ipd;
	ADB <= ADB8_ipd & ADB7_ipd & ADB6_ipd & ADB5_ipd & ADB4_ipd & ADB3_ipd & ADB2_ipd & ADB1_ipd & ADB0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CENA_ipd, CENA, tipd_CENA);
        VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
        VitalWireDelay (CSA0_ipd, CSA0, tipd_CSA0);
        VitalWireDelay (CSA1_ipd, CSA1, tipd_CSA1);
        VitalWireDelay (WRA_ipd, WRA, tipd_WRA);
        VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);

        VitalWireDelay (CENB_ipd, CENB, tipd_CENB);
        VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
        VitalWireDelay (CSB0_ipd, CSB0, tipd_CSB0);
        VitalWireDelay (CSB1_ipd, CSB1, tipd_CSB1);
        VitalWireDelay (WRB_ipd, WRB, tipd_WRB);
        VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);

        VitalWireDelay (DIA0_ipd, DIA0, tipd_DIA0);
        VitalWireDelay (DIA1_ipd, DIA1, tipd_DIA1);
        VitalWireDelay (DIA2_ipd, DIA2, tipd_DIA2);
        VitalWireDelay (DIA3_ipd, DIA3, tipd_DIA3);

        VitalWireDelay (ADA0_ipd, ADA0, tipd_ADA0);
        VitalWireDelay (ADA1_ipd, ADA1, tipd_ADA1);
        VitalWireDelay (ADA2_ipd, ADA2, tipd_ADA2);
        VitalWireDelay (ADA3_ipd, ADA3, tipd_ADA3);
        VitalWireDelay (ADA4_ipd, ADA4, tipd_ADA4);
        VitalWireDelay (ADA5_ipd, ADA5, tipd_ADA5);
        VitalWireDelay (ADA6_ipd, ADA6, tipd_ADA6);
        VitalWireDelay (ADA7_ipd, ADA7, tipd_ADA7);
        VitalWireDelay (ADA8_ipd, ADA8, tipd_ADA8);
        VitalWireDelay (ADA9_ipd, ADA9, tipd_ADA9);
        VitalWireDelay (ADA10_ipd, ADA10, tipd_ADA10);

        VitalWireDelay (DIB0_ipd, DIB0, tipd_DIB0);
        VitalWireDelay (DIB1_ipd, DIB1, tipd_DIB1);
        VitalWireDelay (DIB2_ipd, DIB2, tipd_DIB2);
        VitalWireDelay (DIB3_ipd, DIB3, tipd_DIB3);
        VitalWireDelay (DIB4_ipd, DIB4, tipd_DIB4);
        VitalWireDelay (DIB5_ipd, DIB5, tipd_DIB5);
        VitalWireDelay (DIB6_ipd, DIB6, tipd_DIB6);
        VitalWireDelay (DIB7_ipd, DIB7, tipd_DIB7);
        VitalWireDelay (DIB8_ipd, DIB8, tipd_DIB8);
        VitalWireDelay (DIB9_ipd, DIB9, tipd_DIB9);
        VitalWireDelay (DIB10_ipd, DIB10, tipd_DIB10);
        VitalWireDelay (DIB11_ipd, DIB11, tipd_DIB11);
        VitalWireDelay (DIB12_ipd, DIB12, tipd_DIB12);
        VitalWireDelay (DIB13_ipd, DIB13, tipd_DIB13);
        VitalWireDelay (DIB14_ipd, DIB14, tipd_DIB14);
        VitalWireDelay (DIB15_ipd, DIB15, tipd_DIB15);


        VitalWireDelay (ADB0_ipd, ADB0, tipd_ADB0);
        VitalWireDelay (ADB1_ipd, ADB1, tipd_ADB1);
        VitalWireDelay (ADB2_ipd, ADB2, tipd_ADB2);
        VitalWireDelay (ADB3_ipd, ADB3, tipd_ADB3);
        VitalWireDelay (ADB4_ipd, ADB4, tipd_ADB4);
        VitalWireDelay (ADB5_ipd, ADB5, tipd_ADB5);
        VitalWireDelay (ADB6_ipd, ADB6, tipd_ADB6);
        VitalWireDelay (ADB7_ipd, ADB7, tipd_ADB7);
        VitalWireDelay (ADB8_ipd, ADB8, tipd_ADB8);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CENA_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_WRA_CLKA_posedge     : std_ulogic  := '0';

        variable Tviol_CENB_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_WRB_CLKB_posedge      : std_ulogic  := '0';


        variable Tviol_DIA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA3_CLKA_posedge    : std_ulogic  := '0';

        variable Tviol_ADA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA3_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA4_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA5_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA6_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA7_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA8_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA9_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA10_CLKA_posedge   : std_ulogic  := '0';

        variable Tviol_DIB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB8_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB9_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB10_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB11_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB12_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB13_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB14_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB15_CLKB_posedge    : std_ulogic  := '0';


        variable Tviol_ADB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB8_CLKB_posedge    : std_ulogic  := '0';

        variable Tviol_RSTA_CLKA_posedge_posedge : std_ulogic  := '0';
        variable Tviol_RSTB_CLKB_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CENA_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRA_CLKA_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CENB_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRB_CLKB_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB9_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB10_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB11_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB12_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB13_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB14_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB15_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA4_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA5_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA6_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA7_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA8_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA9_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA10_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RSTA_CLKA_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RSTB_CLKB_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLKA       : std_ulogic := '0';
        variable PInfo_CLKA       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_CLKB       : std_ulogic := '0';
        variable PInfo_CLkB       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTA        : std_ulogic := '0';
        variable PInfo_RSTA        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTB        : std_ulogic := '0';
        variable PInfo_RSTB        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DOA0_zd         : std_ulogic := 'X';
        variable DOA1_zd         : std_ulogic := 'X';
        variable DOA2_zd         : std_ulogic := 'X';
        variable DOA3_zd         : std_ulogic := 'X';
        variable DOB0_zd         : std_ulogic := 'X';
        variable DOB1_zd         : std_ulogic := 'X';
        variable DOB2_zd         : std_ulogic := 'X';
        variable DOB3_zd         : std_ulogic := 'X';
        variable DOB4_zd         : std_ulogic := 'X';
        variable DOB5_zd         : std_ulogic := 'X';
        variable DOB6_zd         : std_ulogic := 'X';
        variable DOB7_zd         : std_ulogic := 'X';
        variable DOB8_zd         : std_ulogic := 'X';
        variable DOB9_zd         : std_ulogic := 'X';
        variable DOB10_zd         : std_ulogic := 'X';
        variable DOB11_zd         : std_ulogic := 'X';
        variable DOB12_zd         : std_ulogic := 'X';
        variable DOB13_zd         : std_ulogic := 'X';
        variable DOB14_zd         : std_ulogic := 'X';
        variable DOB15_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CENA_CLKA_posedge,
          TimingData              => Tmkr_CENA_CLKA_posedge,
          TestSignal              => CENA_ipd,
          TestSignalName          => "CENA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENA_CLKA_noedge_posedge,
          SetupLow                => tsetup_CENA_CLKA_noedge_posedge,
          HoldLow                 => thold_CENA_CLKA_noedge_posedge,
          HoldHigh                => thold_CENA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRA_CLKA_posedge,
          TimingData              => Tmkr_WRA_CLKA_posedge,
          TestSignal              => WRA_ipd,
          TestSignalName          => "WRA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRA_CLKA_noedge_posedge,
          SetupLow                => tsetup_WRA_CLKA_noedge_posedge,
          HoldLow                 => thold_WRA_CLKA_noedge_posedge,
          HoldHigh                => thold_WRA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA0_CLKA_posedge,
          TimingData              => Tmkr_CSA0_CLKA_posedge,
          TestSignal              => CSA0_ipd,
          TestSignalName          => "CSA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA0_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA0_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA1_CLKA_posedge,
          TimingData              => Tmkr_CSA1_CLKA_posedge,
          TestSignal              => CSA1_ipd,
          TestSignalName          => "CSA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA1_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA1_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CENB_CLKB_posedge,
          TimingData              => Tmkr_CENB_CLKB_posedge,
          TestSignal              => CENB_ipd,
          TestSignalName          => "CENB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENB_CLKB_noedge_posedge,
          SetupLow                => tsetup_CENB_CLKB_noedge_posedge,
          HoldLow                 => thold_CENB_CLKB_noedge_posedge,
          HoldHigh                => thold_CENB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRB_CLKB_posedge,
          TimingData              => Tmkr_WRB_CLKB_posedge,
          TestSignal              => WRB_ipd,
          TestSignalName          => "WRB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRB_CLKB_noedge_posedge,
          SetupLow                => tsetup_WRB_CLKB_noedge_posedge,
          HoldLow                 => thold_WRB_CLKB_noedge_posedge,
          HoldHigh                => thold_WRB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB0_CLKB_posedge,
          TimingData              => Tmkr_CSB0_CLKB_posedge,
          TestSignal              => CSB0_ipd,
          TestSignalName          => "CSB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB0_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB0_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB1_CLKB_posedge,
          TimingData              => Tmkr_CSB1_CLKB_posedge,
          TestSignal              => CSB1_ipd,
          TestSignalName          => "CSB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB1_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB1_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA0_CLKA_posedge,
          TimingData              => Tmkr_DIA0_CLKA_posedge,
          TestSignal              => DIA0_ipd,
          TestSignalName          => "DIA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA0_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA0_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA1_CLKA_posedge,
          TimingData              => Tmkr_DIA1_CLKA_posedge,
          TestSignal              => DIA1_ipd,
          TestSignalName          => "DIA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA1_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA1_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA2_CLKA_posedge,
          TimingData              => Tmkr_DIA2_CLKA_posedge,
          TestSignal              => DIA2_ipd,
          TestSignalName          => "DIA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA2_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA2_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA3_CLKA_posedge,
          TimingData              => Tmkr_DIA3_CLKA_posedge,
          TestSignal              => DIA3_ipd,
          TestSignalName          => "DIA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA3_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA3_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA0_CLKA_posedge,
          TimingData              => Tmkr_ADA0_CLKA_posedge,
          TestSignal              => ADA0_ipd,
          TestSignalName          => "ADA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA0_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA0_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA1_CLKA_posedge,
          TimingData              => Tmkr_ADA1_CLKA_posedge,
          TestSignal              => ADA1_ipd,
          TestSignalName          => "ADA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA1_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA1_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA2_CLKA_posedge,
          TimingData              => Tmkr_ADA2_CLKA_posedge,
          TestSignal              => ADA2_ipd,
          TestSignalName          => "ADA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA2_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA2_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA3_CLKA_posedge,
          TimingData              => Tmkr_ADA3_CLKA_posedge,
          TestSignal              => ADA3_ipd,
          TestSignalName          => "ADA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA3_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA3_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA4_CLKA_posedge,
          TimingData              => Tmkr_ADA4_CLKA_posedge,
          TestSignal              => ADA4_ipd,
          TestSignalName          => "ADA4",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA4_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA4_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA4_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA4_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA5_CLKA_posedge,
          TimingData              => Tmkr_ADA5_CLKA_posedge,
          TestSignal              => ADA5_ipd,
          TestSignalName          => "ADA5",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA5_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA5_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA5_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA5_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA6_CLKA_posedge,
          TimingData              => Tmkr_ADA6_CLKA_posedge,
          TestSignal              => ADA6_ipd,
          TestSignalName          => "ADA6",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA6_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA6_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA6_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA6_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA7_CLKA_posedge,
          TimingData              => Tmkr_ADA7_CLKA_posedge,
          TestSignal              => ADA7_ipd,
          TestSignalName          => "ADA7",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA7_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA7_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA7_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA7_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA8_CLKA_posedge,
          TimingData              => Tmkr_ADA8_CLKA_posedge,
          TestSignal              => ADA8_ipd,
          TestSignalName          => "ADA8",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA8_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA8_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA8_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA8_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA9_CLKA_posedge,
          TimingData              => Tmkr_ADA9_CLKA_posedge,
          TestSignal              => ADA9_ipd,
          TestSignalName          => "ADA9",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA9_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA9_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA9_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA9_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA10_CLKA_posedge,
          TimingData              => Tmkr_ADA10_CLKA_posedge,
          TestSignal              => ADA10_ipd,
          TestSignalName          => "ADA10",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA10_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA10_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA10_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA10_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB0_CLKB_posedge,
          TimingData              => Tmkr_DIB0_CLKB_posedge,
          TestSignal              => DIB0_ipd,
          TestSignalName          => "DIB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB0_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB0_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB1_CLKB_posedge,
          TimingData              => Tmkr_DIB1_CLKB_posedge,
          TestSignal              => DIB1_ipd,
          TestSignalName          => "DIB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB1_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB1_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB2_CLKB_posedge,
          TimingData              => Tmkr_DIB2_CLKB_posedge,
          TestSignal              => DIB2_ipd,
          TestSignalName          => "DIB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB2_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB2_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB3_CLKB_posedge,
          TimingData              => Tmkr_DIB3_CLKB_posedge,
          TestSignal              => DIB3_ipd,
          TestSignalName          => "DIB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB3_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB3_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB4_CLKB_posedge,
          TimingData              => Tmkr_DIB4_CLKB_posedge,
          TestSignal              => DIB4_ipd,
          TestSignalName          => "DIB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB4_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB4_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB5_CLKB_posedge,
          TimingData              => Tmkr_DIB5_CLKB_posedge,
          TestSignal              => DIB5_ipd,
          TestSignalName          => "DIB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB5_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB5_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB6_CLKB_posedge,
          TimingData              => Tmkr_DIB6_CLKB_posedge,
          TestSignal              => DIB6_ipd,
          TestSignalName          => "DIB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB6_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB6_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB7_CLKB_posedge,
          TimingData              => Tmkr_DIB7_CLKB_posedge,
          TestSignal              => DIB7_ipd,
          TestSignalName          => "DIB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB7_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB7_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB8_CLKB_posedge,
          TimingData              => Tmkr_DIB8_CLKB_posedge,
          TestSignal              => DIB8_ipd,
          TestSignalName          => "DIB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB8_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB8_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB9_CLKB_posedge,
          TimingData              => Tmkr_DIB9_CLKB_posedge,
          TestSignal              => DIB9_ipd,
          TestSignalName          => "DIB9",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB9_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB9_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB9_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB9_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB10_CLKB_posedge,
          TimingData              => Tmkr_DIB10_CLKB_posedge,
          TestSignal              => DIB10_ipd,
          TestSignalName          => "DIB10",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB10_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB10_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB10_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB10_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB11_CLKB_posedge,
          TimingData              => Tmkr_DIB11_CLKB_posedge,
          TestSignal              => DIB11_ipd,
          TestSignalName          => "DIB11",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB11_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB11_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB11_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB11_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB12_CLKB_posedge,
          TimingData              => Tmkr_DIB12_CLKB_posedge,
          TestSignal              => DIB12_ipd,
          TestSignalName          => "DIB12",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB12_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB12_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB12_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB12_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB13_CLKB_posedge,
          TimingData              => Tmkr_DIB13_CLKB_posedge,
          TestSignal              => DIB13_ipd,
          TestSignalName          => "DIB13",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB13_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB13_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB13_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB13_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB14_CLKB_posedge,
          TimingData              => Tmkr_DIB14_CLKB_posedge,
          TestSignal              => DIB14_ipd,
          TestSignalName          => "DIB14",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB14_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB14_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB14_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB14_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB15_CLKB_posedge,
          TimingData              => Tmkr_DIB15_CLKB_posedge,
          TestSignal              => DIB15_ipd,
          TestSignalName          => "DIB15",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB15_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB15_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB15_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB15_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB0_CLKB_posedge,
          TimingData              => Tmkr_ADB0_CLKB_posedge,
          TestSignal              => ADB0_ipd,
          TestSignalName          => "ADB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB0_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB0_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB1_CLKB_posedge,
          TimingData              => Tmkr_ADB1_CLKB_posedge,
          TestSignal              => ADB1_ipd,
          TestSignalName          => "ADB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB1_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB1_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB2_CLKB_posedge,
          TimingData              => Tmkr_ADB2_CLKB_posedge,
          TestSignal              => ADB2_ipd,
          TestSignalName          => "ADB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB2_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB2_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB3_CLKB_posedge,
          TimingData              => Tmkr_ADB3_CLKB_posedge,
          TestSignal              => ADB3_ipd,
          TestSignalName          => "ADB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB3_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB3_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB4_CLKB_posedge,
          TimingData              => Tmkr_ADB4_CLKB_posedge,
          TestSignal              => ADB4_ipd,
          TestSignalName          => "ADB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB4_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB4_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB5_CLKB_posedge,
          TimingData              => Tmkr_ADB5_CLKB_posedge,
          TestSignal              => ADB5_ipd,
          TestSignalName          => "ADB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB5_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB5_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB6_CLKB_posedge,
          TimingData              => Tmkr_ADB6_CLKB_posedge,
          TestSignal              => ADB6_ipd,
          TestSignalName          => "ADB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB6_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB6_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB7_CLKB_posedge,
          TimingData              => Tmkr_ADB7_CLKB_posedge,
          TestSignal              => ADB7_ipd,
          TestSignalName          => "ADB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB7_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB7_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB8_CLKB_posedge,
          TimingData              => Tmkr_ADB8_CLKB_posedge,
          TestSignal              => ADB8_ipd,
          TestSignalName          => "ADB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB8_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB8_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKA,
          PeriodData              => PInfo_CLKA,
          TestSignal              => CLKA_ipd,
          TestSignalName          => "CLKA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKA_posedge,
          PulseWidthLow           => tpw_CLKA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKB,
          PeriodData              => PInfo_CLKB,
          TestSignal              => CLKB_ipd,
          TestSignalName          => "CLKB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKB_posedge,
          PulseWidthLow           => tpw_CLKB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTA,
          PeriodData              => PInfo_RSTA,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTA_posedge,
          PulseWidthLow           => tpw_RSTA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTB,
          PeriodData              => PInfo_RSTB,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTB_posedge,
          PulseWidthLow           => tpw_RSTB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X4_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTA_CLKA_posedge_posedge,
          TimingData              => Tmkr_RSTA_CLKA_posedge_posedge,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName          => "CLKA",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTA_CLKA_posedge_posedge,
          Removal                 => thold_RSTA_CLKA_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTB_CLKB_posedge_posedge,
          TimingData              => Tmkr_RSTB_CLKB_posedge_posedge,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName          => "CLKB",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTB_CLKB_posedge_posedge,
          Removal                 => thold_RSTB_CLKB_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CENA_CLKA_posedge or Tviol_WRA_CLKA_posedge or 
                 Tviol_CSA0_CLKA_posedge or Tviol_CSA1_CLKA_posedge or 
                 Tviol_ADA0_CLKA_posedge or Tviol_ADA1_CLKA_posedge or 
                 Tviol_ADA2_CLKA_posedge or Tviol_ADA3_CLKA_posedge or 
                 Tviol_ADA4_CLKA_posedge or Tviol_ADA5_CLKA_posedge or 
                 Tviol_ADA6_CLKA_posedge or Tviol_ADA7_CLKA_posedge or 
                 Tviol_ADA8_CLKA_posedge or Tviol_ADA9_CLKA_posedge or 
                 Tviol_ADA10_CLKA_posedge or 
                 Tviol_DIA0_CLKA_posedge or Tviol_DIA1_CLKA_posedge or
                 Tviol_DIA2_CLKA_posedge or Tviol_DIA3_CLKA_posedge or
                 Tviol_ADB0_CLKB_posedge or Tviol_ADB1_CLKB_posedge or 
                 Tviol_ADB2_CLKB_posedge or Tviol_ADB3_CLKB_posedge or 
                 Tviol_ADB4_CLKB_posedge or Tviol_ADB5_CLKB_posedge or 
                 Tviol_ADB6_CLKB_posedge or Tviol_ADB7_CLKB_posedge or 
                 Tviol_ADB8_CLKB_posedge or
 		 Tviol_DIB0_CLKB_posedge or  Tviol_DIB1_CLKB_posedge or 
 		 Tviol_DIB2_CLKB_posedge or  Tviol_DIB3_CLKB_posedge or 
 		 Tviol_DIB4_CLKB_posedge or  Tviol_DIB5_CLKB_posedge or 
 		 Tviol_DIB6_CLKB_posedge or  Tviol_DIB7_CLKB_posedge or 
 		 Tviol_DIB8_CLKB_posedge or  Tviol_DIB9_CLKB_posedge or 
 		 Tviol_DIB10_CLKB_posedge or  Tviol_DIB11_CLKB_posedge or
 		 Tviol_DIB12_CLKB_posedge or  Tviol_DIB13_CLKB_posedge or 
 		 Tviol_DIB14_CLKB_posedge or  Tviol_DIB15_CLKB_posedge or
                 Pviol_CLKA or Pviol_CLKB or Pviol_RSTA or Pviol_RSTB;

    -------------------------
    --  Functionality Section
    -------------------------

wait on CENA_ipd, CLKA_ipd, WRA_ipd, CSA, RSTA_ipd, DIA, ADA, CENB_ipd, CLKB_ipd, WRB_ipd, CSB, RSTB_ipd, DIB, ADB;

      end process VITALBehavior;

    VitalBehavior_DOA0  : process
      variable DOA0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA0_zd := DOA(0);

    VitalPathDelay01 (
      OutSignal => DOA0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA0",
      OutTemp => DOA0_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA0, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(0);
      end process;

    VitalBehavior_DOA1  : process
      variable DOA1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA1_zd := DOA(1);

    VitalPathDelay01 (
      OutSignal => DOA1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA1",
      OutTemp => DOA1_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA1, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(1);
      end process;

    VitalBehavior_DOA2  : process
      variable DOA2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA2_zd := DOA(2);

    VitalPathDelay01 (
      OutSignal => DOA2,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA2",
      OutTemp => DOA2_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA2, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(2);
      end process;

    VitalBehavior_DOA3  : process
      variable DOA3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA3_zd := DOA(3);

    VitalPathDelay01 (
      OutSignal => DOA3,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA3",
      OutTemp => DOA3_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA3, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(3);
      end process;

    VitalBehavior_DOB0  : process
      variable DOB0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB0_zd := DOB(0);

    VitalPathDelay01 (
      OutSignal => DOB0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB0",
      OutTemp => DOB0_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB0, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(0);
      end process;

    VitalBehavior_DOB1  : process
      variable DOB1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB1_zd := DOB(1);

    VitalPathDelay01 (
      OutSignal => DOB1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB1",
      OutTemp => DOB1_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB1, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(1);
      end process;

    VitalBehavior_DOB2  : process
      variable DOB2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB2_zd := DOB(2);

    VitalPathDelay01 (
      OutSignal => DOB2,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB2",
      OutTemp => DOB2_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB2, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(2);
      end process;

    VitalBehavior_DOB3  : process
      variable DOB3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB3_zd := DOB(3);

    VitalPathDelay01 (
      OutSignal => DOB3,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB3",
      OutTemp => DOB3_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB3, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(3);
      end process;

    VitalBehavior_DOB4  : process
      variable DOB4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB4_zd := DOB(4);

    VitalPathDelay01 (
      OutSignal => DOB4,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB4",
      OutTemp => DOB4_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB4, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(4);
      end process;

    VitalBehavior_DOB5  : process
      variable DOB5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB5_zd := DOB(5);

    VitalPathDelay01 (
      OutSignal => DOB5,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB5",
      OutTemp => DOB5_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB5, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(5);
      end process;

    VitalBehavior_DOB6  : process
      variable DOB6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB6_zd := DOB(6);

    VitalPathDelay01 (
      OutSignal => DOB6,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB6",
      OutTemp => DOB6_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB6, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(6);
      end process;

    VitalBehavior_DOB7  : process
      variable DOB7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB7_zd := DOB(7);

    VitalPathDelay01 (
      OutSignal => DOB7,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB7",
      OutTemp => DOB7_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB7, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(7);
      end process;

    VitalBehavior_DOB8  : process
      variable DOB8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB8_zd := DOB(8);

    VitalPathDelay01 (
      OutSignal => DOB8,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB8",
      OutTemp => DOB8_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB8, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(8);
      end process;

    VitalBehavior_DOB9  : process
      variable DOB9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB9_zd := DOB(9);

    VitalPathDelay01 (
      OutSignal => DOB9,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB9",
      OutTemp => DOB9_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB9, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(9);
      end process;

    VitalBehavior_DOB10  : process
      variable DOB10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB10_zd := DOB(10);

    VitalPathDelay01 (
      OutSignal => DOB10,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB10",
      OutTemp => DOB10_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB10, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(10);
      end process;

    VitalBehavior_DOB11  : process
      variable DOB11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB11_zd := DOB(11);

    VitalPathDelay01 (
      OutSignal => DOB11,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB11",
      OutTemp => DOB11_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB11, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(11);
      end process;

    VitalBehavior_DOB12  : process
      variable DOB12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB12_zd := DOB(12);

    VitalPathDelay01 (
      OutSignal => DOB12,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB12",
      OutTemp => DOB12_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB12, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(12);
      end process;

    VitalBehavior_DOB13  : process
      variable DOB13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB13_zd := DOB(13);

    VitalPathDelay01 (
      OutSignal => DOB13,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB13",
      OutTemp => DOB13_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB13, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(13);
      end process;

    VitalBehavior_DOB14  : process
      variable DOB14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB14_zd := DOB(14);

    VitalPathDelay01 (
      OutSignal => DOB14,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB14",
      OutTemp => DOB14_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB14, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(14);
      end process;

    VitalBehavior_DOB15  : process
      variable DOB15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB15_zd := DOB(15);

    VitalPathDelay01 (
      OutSignal => DOB15,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB15",
      OutTemp => DOB15_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB15, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(15);
      end process;



	DPRAM_INST: SC_DPRAM_16K
	   generic map(
		ADDR_WIDTH_A => 11,
		DATA_WIDTH_A => 4,
		ADDR_WIDTH_B => 9,
		DATA_WIDTH_B => 16,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CENA => CENA_ipd,
	        CLKA => CLKA_ipd,
	        WRA  => WRA_ipd,
	        CSA  => CSA,
	        RSTA => RSTA_ipd,
	        DIA  => DIA,
	        ADA  => ADA,
	        DOA  => DOA,

	        CENB => CENB_ipd,
	        CLKB => CLKB_ipd,
	        WRB  => WRB_ipd,
	        CSB  => CSB,
	        RSTB => RSTB_ipd,
	        DIB  => DIB,
	        ADB  => ADB,
	        DOB  => DOB);

end VITAL;

configuration CFG_RAMB8K_X4_X16_VITAL of RAMB8K_X4_X16 is
   for VITAL
   end for;
end CFG_RAMB8K_X4_X16_VITAL;



----- CELL RAMB8K_X8_X8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB8K_X8_X8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "dummy";
      tpd_CLKA_DOA0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_CLKB_DOB0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTA_DOA0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTB_DOB0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_CENA_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENA_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRA_CLKA_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRA_CLKA_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CENB_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENB_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRB_CLKB_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRB_CLKB_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_DIA0_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA1_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA2_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA3_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA4_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA4_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA5_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA5_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA6_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA6_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA7_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA7_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_DIB0_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB1_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB2_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB3_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB4_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB5_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB6_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB7_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA2_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA3_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA4_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA4_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA5_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA5_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA6_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA6_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA7_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA7_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA8_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA8_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA9_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA9_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB2_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB3_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB4_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB5_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB6_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB7_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB8_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB9_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB9_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTA_CLKA_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTA_CLKA_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTB_CLKB_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTB_CLKB_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLKA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_CLKB_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTB_posedge                   :	VitalDelayType   := 2.0 ns;
      tipd_CENA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRA                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CENB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRB                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CENA                            :	in    STD_ULOGIC;
      CLKA                            :	in    STD_ULOGIC;
      WRA                             :	in    STD_ULOGIC;
      CSA0                            :	in    STD_ULOGIC;
      CSA1                            :	in    STD_ULOGIC;
      RSTA                            :	in    STD_ULOGIC;
      CENB                            :	in    STD_ULOGIC;
      CLKB                            :	in    STD_ULOGIC;
      WRB                             :	in    STD_ULOGIC;
      CSB0                            :	in    STD_ULOGIC;
      CSB1                            :	in    STD_ULOGIC;
      RSTB                            :	in    STD_ULOGIC;
      DIA0                            :	in    STD_ULOGIC;
      DIA1                            :	in    STD_ULOGIC;
      DIA2                            :	in    STD_ULOGIC;
      DIA3                            :	in    STD_ULOGIC;
      DIA4                            :	in    STD_ULOGIC;
      DIA5                            :	in    STD_ULOGIC;
      DIA6                            :	in    STD_ULOGIC;
      DIA7                            :	in    STD_ULOGIC;
      ADA0                            :	in    STD_ULOGIC;
      ADA1                            :	in    STD_ULOGIC;
      ADA2                            :	in    STD_ULOGIC;
      ADA3                            :	in    STD_ULOGIC;
      ADA4                            :	in    STD_ULOGIC;
      ADA5                            :	in    STD_ULOGIC;
      ADA6                            :	in    STD_ULOGIC;
      ADA7                            :	in    STD_ULOGIC;
      ADA8                            :	in    STD_ULOGIC;
      ADA9                            :	in    STD_ULOGIC;
      DIB0                            :	in    STD_ULOGIC;
      DIB1                            :	in    STD_ULOGIC;
      DIB2                            :	in    STD_ULOGIC;
      DIB3                            :	in    STD_ULOGIC;
      DIB4                            :	in    STD_ULOGIC;
      DIB5                            :	in    STD_ULOGIC;
      DIB6                            :	in    STD_ULOGIC;
      DIB7                            :	in    STD_ULOGIC;
      ADB0                            :	in    STD_ULOGIC;
      ADB1                            :	in    STD_ULOGIC;
      ADB2                            :	in    STD_ULOGIC;
      ADB3                            :	in    STD_ULOGIC;
      ADB4                            :	in    STD_ULOGIC;
      ADB5                            :	in    STD_ULOGIC;
      ADB6                            :	in    STD_ULOGIC;
      ADB7                            :	in    STD_ULOGIC;
      ADB8                            :	in    STD_ULOGIC;
      ADB9                            :	in    STD_ULOGIC;
      DOA0                            :	out   STD_ULOGIC;
      DOA1                            :	out   STD_ULOGIC;
      DOA2                            :	out   STD_ULOGIC;
      DOA3                            :	out   STD_ULOGIC;
      DOA4                            :	out   STD_ULOGIC;
      DOA5                            :	out   STD_ULOGIC;
      DOA6                            :	out   STD_ULOGIC;
      DOA7                            :	out   STD_ULOGIC;
      DOB0                            :	out   STD_ULOGIC;
      DOB1                            :	out   STD_ULOGIC;
      DOB2                            :	out   STD_ULOGIC;
      DOB3                            :	out   STD_ULOGIC;
      DOB4                            :	out   STD_ULOGIC;
      DOB5                            :	out   STD_ULOGIC;
      DOB6                            :	out   STD_ULOGIC;
      DOB7                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB8K_X8_X8 : entity is FALSE;
end RAMB8K_X8_X8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB8K_X8_X8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_DPRAM_16K
	   generic (
		ADDR_WIDTH_A    : integer := 10;
		DATA_WIDTH_A    : integer := 8;
		ADDR_WIDTH_B    : integer := 10;
		DATA_WIDTH_B    : integer := 8;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CENA : in  STD_LOGIC ;
		CLKA : in  STD_LOGIC ;
		WRA  : in  STD_LOGIC ;
		CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTA : in  STD_LOGIC ;
		DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
		ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
		DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

		CENB : in  STD_LOGIC ;
		CLKB : in  STD_LOGIC ;
		WRB  : in  STD_LOGIC ;
		CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTB : in  STD_LOGIC ;
		DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
		ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
		DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
		);
	end component ;

      signal CENA_ipd      : std_ulogic := 'X';
      signal CLKA_ipd      : std_ulogic := 'X';
      signal WRA_ipd       : std_ulogic := 'X';
      signal CSA0_ipd      : std_ulogic := 'X';
      signal CSA1_ipd      : std_ulogic := 'X';
      signal RSTA_ipd      : std_ulogic := 'X';

      signal CENB_ipd      : std_ulogic := 'X';
      signal CLKB_ipd      : std_ulogic := 'X';
      signal WRB_ipd       : std_ulogic := 'X';
      signal CSB0_ipd      : std_ulogic := 'X';
      signal CSB1_ipd      : std_ulogic := 'X';
      signal RSTB_ipd      : std_ulogic := 'X';

      signal DIA0_ipd      : std_ulogic := 'X';
      signal DIA1_ipd      : std_ulogic := 'X';
      signal DIA2_ipd      : std_ulogic := 'X';
      signal DIA3_ipd      : std_ulogic := 'X';
      signal DIA4_ipd      : std_ulogic := 'X';
      signal DIA5_ipd      : std_ulogic := 'X';
      signal DIA6_ipd      : std_ulogic := 'X';
      signal DIA7_ipd      : std_ulogic := 'X';

      signal ADA0_ipd      : std_ulogic := 'X';
      signal ADA1_ipd      : std_ulogic := 'X';
      signal ADA2_ipd      : std_ulogic := 'X';
      signal ADA3_ipd      : std_ulogic := 'X';
      signal ADA4_ipd      : std_ulogic := 'X';
      signal ADA5_ipd      : std_ulogic := 'X';
      signal ADA6_ipd      : std_ulogic := 'X';
      signal ADA7_ipd      : std_ulogic := 'X';
      signal ADA8_ipd      : std_ulogic := 'X';
      signal ADA9_ipd      : std_ulogic := 'X';

      signal DIB0_ipd       : std_ulogic := 'X';
      signal DIB1_ipd       : std_ulogic := 'X';
      signal DIB2_ipd       : std_ulogic := 'X';
      signal DIB3_ipd       : std_ulogic := 'X';
      signal DIB4_ipd       : std_ulogic := 'X';
      signal DIB5_ipd       : std_ulogic := 'X';
      signal DIB6_ipd       : std_ulogic := 'X';
      signal DIB7_ipd       : std_ulogic := 'X';

      signal ADB0_ipd      : std_ulogic := 'X';
      signal ADB1_ipd      : std_ulogic := 'X';
      signal ADB2_ipd      : std_ulogic := 'X';
      signal ADB3_ipd      : std_ulogic := 'X';
      signal ADB4_ipd      : std_ulogic := 'X';
      signal ADB5_ipd      : std_ulogic := 'X';
      signal ADB6_ipd      : std_ulogic := 'X';
      signal ADB7_ipd      : std_ulogic := 'X';
      signal ADB8_ipd      : std_ulogic := 'X';
      signal ADB9_ipd      : std_ulogic := 'X';

	signal CSA : std_logic_vector (1 downto 0);
	signal CSB : std_logic_vector (1 downto 0);
	signal DIA : std_logic_vector (7 downto 0);
	signal DOA : std_logic_vector (7 downto 0);
	signal DIB : std_logic_vector (7 downto 0);
	signal DOB : std_logic_vector (7 downto 0);
	signal ADA : std_logic_vector (9 downto 0);
	signal ADB : std_logic_vector (9 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);

begin 

	CSA <= CSA1_ipd & CSA0_ipd;
	CSB <= CSB1_ipd & CSB0_ipd;
	DIA <= DIA7_ipd & DIA6_ipd & DIA5_ipd & DIA4_ipd & DIA3_ipd & DIA2_ipd & DIA1_ipd & DIA0_ipd;
	DIB <= DIB7_ipd & DIB6_ipd & DIB5_ipd & DIB4_ipd & DIB3_ipd & DIB2_ipd & DIB1_ipd & DIB0_ipd;
	ADA <= ADA9_ipd & ADA8_ipd & ADA7_ipd & ADA6_ipd & ADA5_ipd & ADA4_ipd & ADA3_ipd & ADA2_ipd & ADA1_ipd & ADA0_ipd;
	ADB <= ADB9_ipd & ADB8_ipd & ADB7_ipd & ADB6_ipd & ADB5_ipd & ADB4_ipd & ADB3_ipd & ADB2_ipd & ADB1_ipd & ADB0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CENA_ipd, CENA, tipd_CENA);
        VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
        VitalWireDelay (CSA0_ipd, CSA0, tipd_CSA0);
        VitalWireDelay (CSA1_ipd, CSA1, tipd_CSA1);
        VitalWireDelay (WRA_ipd, WRA, tipd_WRA);
        VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);

        VitalWireDelay (CENB_ipd, CENB, tipd_CENB);
        VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
        VitalWireDelay (CSB0_ipd, CSB0, tipd_CSB0);
        VitalWireDelay (CSB1_ipd, CSB1, tipd_CSB1);
        VitalWireDelay (WRB_ipd, WRB, tipd_WRB);
        VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);

        VitalWireDelay (DIA0_ipd, DIA0, tipd_DIA0);
        VitalWireDelay (DIA1_ipd, DIA1, tipd_DIA1);
        VitalWireDelay (DIA2_ipd, DIA2, tipd_DIA2);
        VitalWireDelay (DIA3_ipd, DIA3, tipd_DIA3);
        VitalWireDelay (DIA4_ipd, DIA4, tipd_DIA4);
        VitalWireDelay (DIA5_ipd, DIA5, tipd_DIA5);
        VitalWireDelay (DIA6_ipd, DIA6, tipd_DIA6);
        VitalWireDelay (DIA7_ipd, DIA7, tipd_DIA7);

        VitalWireDelay (ADA0_ipd, ADA0, tipd_ADA0);
        VitalWireDelay (ADA1_ipd, ADA1, tipd_ADA1);
        VitalWireDelay (ADA2_ipd, ADA2, tipd_ADA2);
        VitalWireDelay (ADA3_ipd, ADA3, tipd_ADA3);
        VitalWireDelay (ADA4_ipd, ADA4, tipd_ADA4);
        VitalWireDelay (ADA5_ipd, ADA5, tipd_ADA5);
        VitalWireDelay (ADA6_ipd, ADA6, tipd_ADA6);
        VitalWireDelay (ADA7_ipd, ADA7, tipd_ADA7);
        VitalWireDelay (ADA8_ipd, ADA8, tipd_ADA8);
        VitalWireDelay (ADA9_ipd, ADA9, tipd_ADA9);

        VitalWireDelay (DIB0_ipd, DIB0, tipd_DIB0);
        VitalWireDelay (DIB1_ipd, DIB1, tipd_DIB1);
        VitalWireDelay (DIB2_ipd, DIB2, tipd_DIB2);
        VitalWireDelay (DIB3_ipd, DIB3, tipd_DIB3);
        VitalWireDelay (DIB4_ipd, DIB4, tipd_DIB4);
        VitalWireDelay (DIB5_ipd, DIB5, tipd_DIB5);
        VitalWireDelay (DIB6_ipd, DIB6, tipd_DIB6);
        VitalWireDelay (DIB7_ipd, DIB7, tipd_DIB7);


        VitalWireDelay (ADB0_ipd, ADB0, tipd_ADB0);
        VitalWireDelay (ADB1_ipd, ADB1, tipd_ADB1);
        VitalWireDelay (ADB2_ipd, ADB2, tipd_ADB2);
        VitalWireDelay (ADB3_ipd, ADB3, tipd_ADB3);
        VitalWireDelay (ADB4_ipd, ADB4, tipd_ADB4);
        VitalWireDelay (ADB5_ipd, ADB5, tipd_ADB5);
        VitalWireDelay (ADB6_ipd, ADB6, tipd_ADB6);
        VitalWireDelay (ADB7_ipd, ADB7, tipd_ADB7);
        VitalWireDelay (ADB8_ipd, ADB8, tipd_ADB8);
        VitalWireDelay (ADB9_ipd, ADB9, tipd_ADB9);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CENA_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_WRA_CLKA_posedge     : std_ulogic  := '0';

        variable Tviol_CENB_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_WRB_CLKB_posedge      : std_ulogic  := '0';

        variable Tviol_DIA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA3_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA4_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA5_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA6_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA7_CLKA_posedge    : std_ulogic  := '0';

        variable Tviol_ADA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA3_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA4_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA5_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA6_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA7_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA8_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA9_CLKA_posedge    : std_ulogic  := '0';

        variable Tviol_DIB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB7_CLKB_posedge    : std_ulogic  := '0';

        variable Tviol_ADB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB8_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB9_CLKB_posedge    : std_ulogic  := '0';

        variable Tviol_RSTA_CLKA_posedge_posedge : std_ulogic  := '0';
        variable Tviol_RSTB_CLKB_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CENA_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRA_CLKA_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CENB_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRB_CLKB_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA4_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA5_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA6_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA7_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA4_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA5_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA6_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA7_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA8_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA9_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB9_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RSTA_CLKA_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RSTB_CLKB_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLKA       : std_ulogic := '0';
        variable PInfo_CLKA       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_CLKB       : std_ulogic := '0';
        variable PInfo_CLkB       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTA        : std_ulogic := '0';
        variable PInfo_RSTA        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTB        : std_ulogic := '0';
        variable PInfo_RSTB        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DOA0_zd         : std_ulogic := 'X';
        variable DOA1_zd         : std_ulogic := 'X';
        variable DOA2_zd         : std_ulogic := 'X';
        variable DOA3_zd         : std_ulogic := 'X';
        variable DOA4_zd         : std_ulogic := 'X';
        variable DOA5_zd         : std_ulogic := 'X';
        variable DOA6_zd         : std_ulogic := 'X';
        variable DOA7_zd         : std_ulogic := 'X';
        variable DOB0_zd         : std_ulogic := 'X';
        variable DOB1_zd         : std_ulogic := 'X';
        variable DOB2_zd         : std_ulogic := 'X';
        variable DOB3_zd         : std_ulogic := 'X';
        variable DOB4_zd         : std_ulogic := 'X';
        variable DOB5_zd         : std_ulogic := 'X';
        variable DOB6_zd         : std_ulogic := 'X';
        variable DOB7_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CENA_CLKA_posedge,
          TimingData              => Tmkr_CENA_CLKA_posedge,
          TestSignal              => CENA_ipd,
          TestSignalName          => "CENA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENA_CLKA_noedge_posedge,
          SetupLow                => tsetup_CENA_CLKA_noedge_posedge,
          HoldLow                 => thold_CENA_CLKA_noedge_posedge,
          HoldHigh                => thold_CENA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRA_CLKA_posedge,
          TimingData              => Tmkr_WRA_CLKA_posedge,
          TestSignal              => WRA_ipd,
          TestSignalName          => "WRA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRA_CLKA_noedge_posedge,
          SetupLow                => tsetup_WRA_CLKA_noedge_posedge,
          HoldLow                 => thold_WRA_CLKA_noedge_posedge,
          HoldHigh                => thold_WRA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA0_CLKA_posedge,
          TimingData              => Tmkr_CSA0_CLKA_posedge,
          TestSignal              => CSA0_ipd,
          TestSignalName          => "CSA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA0_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA0_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA1_CLKA_posedge,
          TimingData              => Tmkr_CSA1_CLKA_posedge,
          TestSignal              => CSA1_ipd,
          TestSignalName          => "CSA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA1_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA1_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CENB_CLKB_posedge,
          TimingData              => Tmkr_CENB_CLKB_posedge,
          TestSignal              => CENB_ipd,
          TestSignalName          => "CENB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENB_CLKB_noedge_posedge,
          SetupLow                => tsetup_CENB_CLKB_noedge_posedge,
          HoldLow                 => thold_CENB_CLKB_noedge_posedge,
          HoldHigh                => thold_CENB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRB_CLKB_posedge,
          TimingData              => Tmkr_WRB_CLKB_posedge,
          TestSignal              => WRB_ipd,
          TestSignalName          => "WRB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRB_CLKB_noedge_posedge,
          SetupLow                => tsetup_WRB_CLKB_noedge_posedge,
          HoldLow                 => thold_WRB_CLKB_noedge_posedge,
          HoldHigh                => thold_WRB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB0_CLKB_posedge,
          TimingData              => Tmkr_CSB0_CLKB_posedge,
          TestSignal              => CSB0_ipd,
          TestSignalName          => "CSB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB0_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB0_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB1_CLKB_posedge,
          TimingData              => Tmkr_CSB1_CLKB_posedge,
          TestSignal              => CSB1_ipd,
          TestSignalName          => "CSB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB1_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB1_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA0_CLKA_posedge,
          TimingData              => Tmkr_DIA0_CLKA_posedge,
          TestSignal              => DIA0_ipd,
          TestSignalName          => "DIA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA0_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA0_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA1_CLKA_posedge,
          TimingData              => Tmkr_DIA1_CLKA_posedge,
          TestSignal              => DIA1_ipd,
          TestSignalName          => "DIA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA1_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA1_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA2_CLKA_posedge,
          TimingData              => Tmkr_DIA2_CLKA_posedge,
          TestSignal              => DIA2_ipd,
          TestSignalName          => "DIA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA2_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA2_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA3_CLKA_posedge,
          TimingData              => Tmkr_DIA3_CLKA_posedge,
          TestSignal              => DIA3_ipd,
          TestSignalName          => "DIA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA3_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA3_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA4_CLKA_posedge,
          TimingData              => Tmkr_DIA4_CLKA_posedge,
          TestSignal              => DIA4_ipd,
          TestSignalName          => "DIA4",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA4_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA4_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA4_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA4_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA5_CLKA_posedge,
          TimingData              => Tmkr_DIA5_CLKA_posedge,
          TestSignal              => DIA5_ipd,
          TestSignalName          => "DIA5",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA5_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA5_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA5_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA5_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA6_CLKA_posedge,
          TimingData              => Tmkr_DIA6_CLKA_posedge,
          TestSignal              => DIA6_ipd,
          TestSignalName          => "DIA6",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA6_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA6_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA6_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA6_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA7_CLKA_posedge,
          TimingData              => Tmkr_DIA7_CLKA_posedge,
          TestSignal              => DIA7_ipd,
          TestSignalName          => "DIA7",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA7_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA7_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA7_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA7_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA0_CLKA_posedge,
          TimingData              => Tmkr_ADA0_CLKA_posedge,
          TestSignal              => ADA0_ipd,
          TestSignalName          => "ADA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA0_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA0_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA1_CLKA_posedge,
          TimingData              => Tmkr_ADA1_CLKA_posedge,
          TestSignal              => ADA1_ipd,
          TestSignalName          => "ADA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA1_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA1_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA2_CLKA_posedge,
          TimingData              => Tmkr_ADA2_CLKA_posedge,
          TestSignal              => ADA2_ipd,
          TestSignalName          => "ADA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA2_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA2_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA3_CLKA_posedge,
          TimingData              => Tmkr_ADA3_CLKA_posedge,
          TestSignal              => ADA3_ipd,
          TestSignalName          => "ADA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA3_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA3_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA4_CLKA_posedge,
          TimingData              => Tmkr_ADA4_CLKA_posedge,
          TestSignal              => ADA4_ipd,
          TestSignalName          => "ADA4",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA4_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA4_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA4_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA4_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA5_CLKA_posedge,
          TimingData              => Tmkr_ADA5_CLKA_posedge,
          TestSignal              => ADA5_ipd,
          TestSignalName          => "ADA5",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA5_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA5_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA5_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA5_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA6_CLKA_posedge,
          TimingData              => Tmkr_ADA6_CLKA_posedge,
          TestSignal              => ADA6_ipd,
          TestSignalName          => "ADA6",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA6_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA6_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA6_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA6_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA7_CLKA_posedge,
          TimingData              => Tmkr_ADA7_CLKA_posedge,
          TestSignal              => ADA7_ipd,
          TestSignalName          => "ADA7",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA7_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA7_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA7_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA7_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA8_CLKA_posedge,
          TimingData              => Tmkr_ADA8_CLKA_posedge,
          TestSignal              => ADA8_ipd,
          TestSignalName          => "ADA8",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA8_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA8_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA8_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA8_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA9_CLKA_posedge,
          TimingData              => Tmkr_ADA9_CLKA_posedge,
          TestSignal              => ADA9_ipd,
          TestSignalName          => "ADA9",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA9_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA9_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA9_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA9_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB0_CLKB_posedge,
          TimingData              => Tmkr_DIB0_CLKB_posedge,
          TestSignal              => DIB0_ipd,
          TestSignalName          => "DIB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB0_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB0_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB1_CLKB_posedge,
          TimingData              => Tmkr_DIB1_CLKB_posedge,
          TestSignal              => DIB1_ipd,
          TestSignalName          => "DIB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB1_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB1_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB2_CLKB_posedge,
          TimingData              => Tmkr_DIB2_CLKB_posedge,
          TestSignal              => DIB2_ipd,
          TestSignalName          => "DIB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB2_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB2_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB3_CLKB_posedge,
          TimingData              => Tmkr_DIB3_CLKB_posedge,
          TestSignal              => DIB3_ipd,
          TestSignalName          => "DIB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB3_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB3_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB4_CLKB_posedge,
          TimingData              => Tmkr_DIB4_CLKB_posedge,
          TestSignal              => DIB4_ipd,
          TestSignalName          => "DIB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB4_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB4_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB5_CLKB_posedge,
          TimingData              => Tmkr_DIB5_CLKB_posedge,
          TestSignal              => DIB5_ipd,
          TestSignalName          => "DIB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB5_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB5_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB6_CLKB_posedge,
          TimingData              => Tmkr_DIB6_CLKB_posedge,
          TestSignal              => DIB6_ipd,
          TestSignalName          => "DIB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB6_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB6_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB7_CLKB_posedge,
          TimingData              => Tmkr_DIB7_CLKB_posedge,
          TestSignal              => DIB7_ipd,
          TestSignalName          => "DIB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB7_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB7_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB0_CLKB_posedge,
          TimingData              => Tmkr_ADB0_CLKB_posedge,
          TestSignal              => ADB0_ipd,
          TestSignalName          => "ADB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB0_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB0_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB1_CLKB_posedge,
          TimingData              => Tmkr_ADB1_CLKB_posedge,
          TestSignal              => ADB1_ipd,
          TestSignalName          => "ADB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB1_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB1_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB2_CLKB_posedge,
          TimingData              => Tmkr_ADB2_CLKB_posedge,
          TestSignal              => ADB2_ipd,
          TestSignalName          => "ADB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB2_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB2_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB3_CLKB_posedge,
          TimingData              => Tmkr_ADB3_CLKB_posedge,
          TestSignal              => ADB3_ipd,
          TestSignalName          => "ADB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB3_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB3_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB4_CLKB_posedge,
          TimingData              => Tmkr_ADB4_CLKB_posedge,
          TestSignal              => ADB4_ipd,
          TestSignalName          => "ADB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB4_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB4_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB5_CLKB_posedge,
          TimingData              => Tmkr_ADB5_CLKB_posedge,
          TestSignal              => ADB5_ipd,
          TestSignalName          => "ADB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB5_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB5_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB6_CLKB_posedge,
          TimingData              => Tmkr_ADB6_CLKB_posedge,
          TestSignal              => ADB6_ipd,
          TestSignalName          => "ADB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB6_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB6_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB7_CLKB_posedge,
          TimingData              => Tmkr_ADB7_CLKB_posedge,
          TestSignal              => ADB7_ipd,
          TestSignalName          => "ADB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB7_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB7_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB8_CLKB_posedge,
          TimingData              => Tmkr_ADB8_CLKB_posedge,
          TestSignal              => ADB8_ipd,
          TestSignalName          => "ADB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB8_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB8_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB9_CLKB_posedge,
          TimingData              => Tmkr_ADB9_CLKB_posedge,
          TestSignal              => ADB9_ipd,
          TestSignalName          => "ADB9",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB9_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB9_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB9_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB9_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKA,
          PeriodData              => PInfo_CLKA,
          TestSignal              => CLKA_ipd,
          TestSignalName          => "CLKA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKA_posedge,
          PulseWidthLow           => tpw_CLKA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKB,
          PeriodData              => PInfo_CLKB,
          TestSignal              => CLKB_ipd,
          TestSignalName          => "CLKB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKB_posedge,
          PulseWidthLow           => tpw_CLKB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTA,
          PeriodData              => PInfo_RSTA,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTA_posedge,
          PulseWidthLow           => tpw_RSTA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTB,
          PeriodData              => PInfo_RSTB,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTB_posedge,
          PulseWidthLow           => tpw_RSTB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X8_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTA_CLKA_posedge_posedge,
          TimingData              => Tmkr_RSTA_CLKA_posedge_posedge,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName          => "CLKA",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTA_CLKA_posedge_posedge,
          Removal                 => thold_RSTA_CLKA_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTB_CLKB_posedge_posedge,
          TimingData              => Tmkr_RSTB_CLKB_posedge_posedge,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName          => "CLKB",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTB_CLKB_posedge_posedge,
          Removal                 => thold_RSTB_CLKB_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CENA_CLKA_posedge or Tviol_WRA_CLKA_posedge or 
                 Tviol_CSA0_CLKA_posedge or Tviol_CSA1_CLKA_posedge or 
                 Tviol_ADA0_CLKA_posedge or Tviol_ADA1_CLKA_posedge or 
                 Tviol_ADA2_CLKA_posedge or Tviol_ADA3_CLKA_posedge or 
                 Tviol_ADA4_CLKA_posedge or Tviol_ADA5_CLKA_posedge or 
                 Tviol_ADA6_CLKA_posedge or Tviol_ADA7_CLKA_posedge or 
                 Tviol_ADA8_CLKA_posedge or Tviol_ADA9_CLKA_posedge or 
                 Tviol_DIA0_CLKA_posedge or Tviol_DIA1_CLKA_posedge or
                 Tviol_DIA2_CLKA_posedge or Tviol_DIA3_CLKA_posedge or
                 Tviol_DIA4_CLKA_posedge or Tviol_DIA5_CLKA_posedge or
                 Tviol_DIA6_CLKA_posedge or Tviol_DIA7_CLKA_posedge or
                 Tviol_ADB0_CLKB_posedge or Tviol_ADB1_CLKB_posedge or 
                 Tviol_ADB2_CLKB_posedge or Tviol_ADB3_CLKB_posedge or 
                 Tviol_ADB4_CLKB_posedge or Tviol_ADB5_CLKB_posedge or 
                 Tviol_ADB6_CLKB_posedge or Tviol_ADB7_CLKB_posedge or 
                 Tviol_ADB8_CLKB_posedge or Tviol_ADB9_CLKB_posedge or 
 		 Tviol_DIB0_CLKB_posedge or  Tviol_DIB1_CLKB_posedge or 
 		 Tviol_DIB2_CLKB_posedge or  Tviol_DIB3_CLKB_posedge or 
 		 Tviol_DIB4_CLKB_posedge or  Tviol_DIB5_CLKB_posedge or 
 		 Tviol_DIB6_CLKB_posedge or  Tviol_DIB7_CLKB_posedge or 
                 Pviol_CLKA or Pviol_CLKB or Pviol_RSTA or Pviol_RSTB;

    -------------------------
    --  Functionality Section
    -------------------------

wait on CENA_ipd, CLKA_ipd, WRA_ipd, CSA, RSTA_ipd, DIA, ADA, CENB_ipd, CLKB_ipd, WRB_ipd, CSB, RSTB_ipd, DIB, ADB;

      end process VITALBehavior;

    VitalBehavior_DOA0  : process
      variable DOA0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA0_zd := DOA(0);

    VitalPathDelay01 (
      OutSignal => DOA0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA0",
      OutTemp => DOA0_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA0, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(0);
      end process;

    VitalBehavior_DOA1  : process
      variable DOA1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA1_zd := DOA(1);

    VitalPathDelay01 (
      OutSignal => DOA1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA1",
      OutTemp => DOA1_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA1, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(1);
      end process;

    VitalBehavior_DOA2  : process
      variable DOA2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA2_zd := DOA(2);

    VitalPathDelay01 (
      OutSignal => DOA2,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA2",
      OutTemp => DOA2_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA2, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(2);
      end process;

    VitalBehavior_DOA3  : process
      variable DOA3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA3_zd := DOA(3);

    VitalPathDelay01 (
      OutSignal => DOA3,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA3",
      OutTemp => DOA3_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA3, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(3);
      end process;

    VitalBehavior_DOA4  : process
      variable DOA4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA4_zd := DOA(4);

    VitalPathDelay01 (
      OutSignal => DOA4,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA4",
      OutTemp => DOA4_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA4, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(4);
      end process;

    VitalBehavior_DOA5  : process
      variable DOA5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA5_zd := DOA(5);

    VitalPathDelay01 (
      OutSignal => DOA5,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA5",
      OutTemp => DOA5_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA5, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(5);
      end process;

    VitalBehavior_DOA6  : process
      variable DOA6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA6_zd := DOA(6);

    VitalPathDelay01 (
      OutSignal => DOA6,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA6",
      OutTemp => DOA6_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA6, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(6);
      end process;

    VitalBehavior_DOA7  : process
      variable DOA7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA7_zd := DOA(7);

    VitalPathDelay01 (
      OutSignal => DOA7,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA7",
      OutTemp => DOA7_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA7, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(7);
      end process;

    VitalBehavior_DOB0  : process
      variable DOB0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB0_zd := DOB(0);

    VitalPathDelay01 (
      OutSignal => DOB0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB0",
      OutTemp => DOB0_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB0, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(0);
      end process;

    VitalBehavior_DOB1  : process
      variable DOB1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB1_zd := DOB(1);

    VitalPathDelay01 (
      OutSignal => DOB1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB1",
      OutTemp => DOB1_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB1, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(1);
      end process;

    VitalBehavior_DOB2  : process
      variable DOB2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB2_zd := DOB(2);

    VitalPathDelay01 (
      OutSignal => DOB2,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB2",
      OutTemp => DOB2_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB2, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(2);
      end process;

    VitalBehavior_DOB3  : process
      variable DOB3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB3_zd := DOB(3);

    VitalPathDelay01 (
      OutSignal => DOB3,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB3",
      OutTemp => DOB3_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB3, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(3);
      end process;

    VitalBehavior_DOB4  : process
      variable DOB4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB4_zd := DOB(4);

    VitalPathDelay01 (
      OutSignal => DOB4,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB4",
      OutTemp => DOB4_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB4, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(4);
      end process;

    VitalBehavior_DOB5  : process
      variable DOB5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB5_zd := DOB(5);

    VitalPathDelay01 (
      OutSignal => DOB5,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB5",
      OutTemp => DOB5_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB5, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(5);
      end process;

    VitalBehavior_DOB6  : process
      variable DOB6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB6_zd := DOB(6);

    VitalPathDelay01 (
      OutSignal => DOB6,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB6",
      OutTemp => DOB6_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB6, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(6);
      end process;

    VitalBehavior_DOB7  : process
      variable DOB7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB7_zd := DOB(7);

    VitalPathDelay01 (
      OutSignal => DOB7,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB7",
      OutTemp => DOB7_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB7, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(7);
      end process;



	DPRAM_INST: SC_DPRAM_16K
	   generic map(
		ADDR_WIDTH_A => 10,
		DATA_WIDTH_A => 8,
		ADDR_WIDTH_B => 10,
		DATA_WIDTH_B => 8,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CENA => CENA_ipd,
	        CLKA => CLKA_ipd,
	        WRA  => WRA_ipd,
	        CSA  => CSA,
	        RSTA => RSTA_ipd,
	        DIA  => DIA,
	        ADA  => ADA,
	        DOA  => DOA,

	        CENB => CENB_ipd,
	        CLKB => CLKB_ipd,
	        WRB  => WRB_ipd,
	        CSB  => CSB,
	        RSTB => RSTB_ipd,
	        DIB  => DIB,
	        ADB  => ADB,
	        DOB  => DOB);

end VITAL;

configuration CFG_RAMB8K_X8_X8_VITAL of RAMB8K_X8_X8 is
   for VITAL
   end for;
end CFG_RAMB8K_X8_X8_VITAL;



----- CELL RAMB8K_X8_X16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB8K_X8_X16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "dummy";
      tpd_CLKA_DOA0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_CLKB_DOB0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTA_DOA0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTB_DOB0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_CENA_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENA_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRA_CLKA_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRA_CLKA_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CENB_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENB_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRB_CLKB_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRB_CLKB_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_DIA0_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA1_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA2_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA3_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA4_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA4_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA5_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA5_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA6_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA6_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA7_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA7_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_DIB0_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB1_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB2_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB3_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB4_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB5_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB6_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB7_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB8_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB9_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB9_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB10_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB10_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB11_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB11_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB12_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB12_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB13_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB13_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB14_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB14_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB15_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB15_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA2_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA3_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA4_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA4_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA5_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA5_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA6_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA6_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA7_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA7_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA8_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA8_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA9_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA9_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB2_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB3_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB4_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB5_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB6_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB7_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB8_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTA_CLKA_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTA_CLKA_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTB_CLKB_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTB_CLKB_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLKA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_CLKB_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTB_posedge                   :	VitalDelayType   := 2.0 ns;
      tipd_CENA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRA                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CENB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRB                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CENA                            :	in    STD_ULOGIC;
      CLKA                            :	in    STD_ULOGIC;
      WRA                             :	in    STD_ULOGIC;
      CSA0                            :	in    STD_ULOGIC;
      CSA1                            :	in    STD_ULOGIC;
      RSTA                            :	in    STD_ULOGIC;
      CENB                            :	in    STD_ULOGIC;
      CLKB                            :	in    STD_ULOGIC;
      WRB                             :	in    STD_ULOGIC;
      CSB0                            :	in    STD_ULOGIC;
      CSB1                            :	in    STD_ULOGIC;
      RSTB                            :	in    STD_ULOGIC;
      DIA0                            :	in    STD_ULOGIC;
      DIA1                            :	in    STD_ULOGIC;
      DIA2                            :	in    STD_ULOGIC;
      DIA3                            :	in    STD_ULOGIC;
      DIA4                            :	in    STD_ULOGIC;
      DIA5                            :	in    STD_ULOGIC;
      DIA6                            :	in    STD_ULOGIC;
      DIA7                            :	in    STD_ULOGIC;
      ADA0                            :	in    STD_ULOGIC;
      ADA1                            :	in    STD_ULOGIC;
      ADA2                            :	in    STD_ULOGIC;
      ADA3                            :	in    STD_ULOGIC;
      ADA4                            :	in    STD_ULOGIC;
      ADA5                            :	in    STD_ULOGIC;
      ADA6                            :	in    STD_ULOGIC;
      ADA7                            :	in    STD_ULOGIC;
      ADA8                            :	in    STD_ULOGIC;
      ADA9                            :	in    STD_ULOGIC;
      DIB0                            :	in    STD_ULOGIC;
      DIB1                            :	in    STD_ULOGIC;
      DIB2                            :	in    STD_ULOGIC;
      DIB3                            :	in    STD_ULOGIC;
      DIB4                            :	in    STD_ULOGIC;
      DIB5                            :	in    STD_ULOGIC;
      DIB6                            :	in    STD_ULOGIC;
      DIB7                            :	in    STD_ULOGIC;
      DIB8                            :	in    STD_ULOGIC;
      DIB9                            :	in    STD_ULOGIC;
      DIB10                           :	in    STD_ULOGIC;
      DIB11                           :	in    STD_ULOGIC;
      DIB12                           :	in    STD_ULOGIC;
      DIB13                           :	in    STD_ULOGIC;
      DIB14                           :	in    STD_ULOGIC;
      DIB15                           :	in    STD_ULOGIC;
      ADB0                            :	in    STD_ULOGIC;
      ADB1                            :	in    STD_ULOGIC;
      ADB2                            :	in    STD_ULOGIC;
      ADB3                            :	in    STD_ULOGIC;
      ADB4                            :	in    STD_ULOGIC;
      ADB5                            :	in    STD_ULOGIC;
      ADB6                            :	in    STD_ULOGIC;
      ADB7                            :	in    STD_ULOGIC;
      ADB8                            :	in    STD_ULOGIC;
      DOA0                            :	out   STD_ULOGIC;
      DOA1                            :	out   STD_ULOGIC;
      DOA2                            :	out   STD_ULOGIC;
      DOA3                            :	out   STD_ULOGIC;
      DOA4                            :	out   STD_ULOGIC;
      DOA5                            :	out   STD_ULOGIC;
      DOA6                            :	out   STD_ULOGIC;
      DOA7                            :	out   STD_ULOGIC;
      DOB0                            :	out   STD_ULOGIC;
      DOB1                            :	out   STD_ULOGIC;
      DOB2                            :	out   STD_ULOGIC;
      DOB3                            :	out   STD_ULOGIC;
      DOB4                            :	out   STD_ULOGIC;
      DOB5                            :	out   STD_ULOGIC;
      DOB6                            :	out   STD_ULOGIC;
      DOB7                            :	out   STD_ULOGIC;
      DOB8                            :	out   STD_ULOGIC;
      DOB9                            :	out   STD_ULOGIC;
      DOB10                           :	out   STD_ULOGIC;
      DOB11                           :	out   STD_ULOGIC;
      DOB12                           :	out   STD_ULOGIC;
      DOB13                           :	out   STD_ULOGIC;
      DOB14                           :	out   STD_ULOGIC;
      DOB15                           :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB8K_X8_X16 : entity is FALSE;
end RAMB8K_X8_X16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB8K_X8_X16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_DPRAM_16K
	   generic (
		ADDR_WIDTH_A    : integer := 10;
		DATA_WIDTH_A    : integer := 8;
		ADDR_WIDTH_B    : integer := 9;
		DATA_WIDTH_B    : integer := 16;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CENA : in  STD_LOGIC ;
		CLKA : in  STD_LOGIC ;
		WRA  : in  STD_LOGIC ;
		CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTA : in  STD_LOGIC ;
		DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
		ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
		DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

		CENB : in  STD_LOGIC ;
		CLKB : in  STD_LOGIC ;
		WRB  : in  STD_LOGIC ;
		CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTB : in  STD_LOGIC ;
		DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
		ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
		DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
		);
	end component ;

      signal CENA_ipd      : std_ulogic := 'X';
      signal CLKA_ipd      : std_ulogic := 'X';
      signal WRA_ipd       : std_ulogic := 'X';
      signal CSA0_ipd      : std_ulogic := 'X';
      signal CSA1_ipd      : std_ulogic := 'X';
      signal RSTA_ipd      : std_ulogic := 'X';

      signal CENB_ipd      : std_ulogic := 'X';
      signal CLKB_ipd      : std_ulogic := 'X';
      signal WRB_ipd       : std_ulogic := 'X';
      signal CSB0_ipd      : std_ulogic := 'X';
      signal CSB1_ipd      : std_ulogic := 'X';
      signal RSTB_ipd      : std_ulogic := 'X';

      signal DIA0_ipd      : std_ulogic := 'X';
      signal DIA1_ipd      : std_ulogic := 'X';
      signal DIA2_ipd      : std_ulogic := 'X';
      signal DIA3_ipd      : std_ulogic := 'X';
      signal DIA4_ipd      : std_ulogic := 'X';
      signal DIA5_ipd      : std_ulogic := 'X';
      signal DIA6_ipd      : std_ulogic := 'X';
      signal DIA7_ipd      : std_ulogic := 'X';

      signal ADA0_ipd      : std_ulogic := 'X';
      signal ADA1_ipd      : std_ulogic := 'X';
      signal ADA2_ipd      : std_ulogic := 'X';
      signal ADA3_ipd      : std_ulogic := 'X';
      signal ADA4_ipd      : std_ulogic := 'X';
      signal ADA5_ipd      : std_ulogic := 'X';
      signal ADA6_ipd      : std_ulogic := 'X';
      signal ADA7_ipd      : std_ulogic := 'X';
      signal ADA8_ipd      : std_ulogic := 'X';
      signal ADA9_ipd      : std_ulogic := 'X';

      signal DIB0_ipd       : std_ulogic := 'X';
      signal DIB1_ipd       : std_ulogic := 'X';
      signal DIB2_ipd       : std_ulogic := 'X';
      signal DIB3_ipd       : std_ulogic := 'X';
      signal DIB4_ipd       : std_ulogic := 'X';
      signal DIB5_ipd       : std_ulogic := 'X';
      signal DIB6_ipd       : std_ulogic := 'X';
      signal DIB7_ipd       : std_ulogic := 'X';
      signal DIB8_ipd       : std_ulogic := 'X';
      signal DIB9_ipd       : std_ulogic := 'X';
      signal DIB10_ipd      : std_ulogic := 'X';
      signal DIB11_ipd      : std_ulogic := 'X';
      signal DIB12_ipd      : std_ulogic := 'X';
      signal DIB13_ipd      : std_ulogic := 'X';
      signal DIB14_ipd      : std_ulogic := 'X';
      signal DIB15_ipd      : std_ulogic := 'X';

      signal ADB0_ipd      : std_ulogic := 'X';
      signal ADB1_ipd      : std_ulogic := 'X';
      signal ADB2_ipd      : std_ulogic := 'X';
      signal ADB3_ipd      : std_ulogic := 'X';
      signal ADB4_ipd      : std_ulogic := 'X';
      signal ADB5_ipd      : std_ulogic := 'X';
      signal ADB6_ipd      : std_ulogic := 'X';
      signal ADB7_ipd      : std_ulogic := 'X';
      signal ADB8_ipd      : std_ulogic := 'X';

	signal CSA : std_logic_vector (1 downto 0);
	signal CSB : std_logic_vector (1 downto 0);
	signal DIA : std_logic_vector (7 downto 0);
	signal DOA : std_logic_vector (7 downto 0);
	signal DIB : std_logic_vector (15 downto 0);
	signal DOB : std_logic_vector (15 downto 0);
	signal ADA : std_logic_vector (9 downto 0);
	signal ADB : std_logic_vector (8 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);

begin 

	CSA <= CSA1_ipd & CSA0_ipd;
	CSB <= CSB1_ipd & CSB0_ipd;
	DIA <= DIA7_ipd & DIA6_ipd & DIA5_ipd & DIA4_ipd & DIA3_ipd & DIA2_ipd & DIA1_ipd & DIA0_ipd;
	DIB <= DIB15_ipd & DIB14_ipd & DIB13_ipd & DIB12_ipd & DIB11_ipd & DIB10_ipd & DIB9_ipd & DIB8_ipd & DIB7_ipd & DIB6_ipd & DIB5_ipd & DIB4_ipd & DIB3_ipd & DIB2_ipd & DIB1_ipd & DIB0_ipd;
	ADA <= ADA9_ipd & ADA8_ipd & ADA7_ipd & ADA6_ipd & ADA5_ipd & ADA4_ipd & ADA3_ipd & ADA2_ipd & ADA1_ipd & ADA0_ipd;
	ADB <= ADB8_ipd & ADB7_ipd & ADB6_ipd & ADB5_ipd & ADB4_ipd & ADB3_ipd & ADB2_ipd & ADB1_ipd & ADB0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CENA_ipd, CENA, tipd_CENA);
        VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
        VitalWireDelay (CSA0_ipd, CSA0, tipd_CSA0);
        VitalWireDelay (CSA1_ipd, CSA1, tipd_CSA1);
        VitalWireDelay (WRA_ipd, WRA, tipd_WRA);
        VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);

        VitalWireDelay (CENB_ipd, CENB, tipd_CENB);
        VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
        VitalWireDelay (CSB0_ipd, CSB0, tipd_CSB0);
        VitalWireDelay (CSB1_ipd, CSB1, tipd_CSB1);
        VitalWireDelay (WRB_ipd, WRB, tipd_WRB);
        VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);

        VitalWireDelay (DIA0_ipd, DIA0, tipd_DIA0);
        VitalWireDelay (DIA1_ipd, DIA1, tipd_DIA1);
        VitalWireDelay (DIA2_ipd, DIA2, tipd_DIA2);
        VitalWireDelay (DIA3_ipd, DIA3, tipd_DIA3);
        VitalWireDelay (DIA4_ipd, DIA4, tipd_DIA4);
        VitalWireDelay (DIA5_ipd, DIA5, tipd_DIA5);
        VitalWireDelay (DIA6_ipd, DIA6, tipd_DIA6);
        VitalWireDelay (DIA7_ipd, DIA7, tipd_DIA7);

        VitalWireDelay (ADA0_ipd, ADA0, tipd_ADA0);
        VitalWireDelay (ADA1_ipd, ADA1, tipd_ADA1);
        VitalWireDelay (ADA2_ipd, ADA2, tipd_ADA2);
        VitalWireDelay (ADA3_ipd, ADA3, tipd_ADA3);
        VitalWireDelay (ADA4_ipd, ADA4, tipd_ADA4);
        VitalWireDelay (ADA5_ipd, ADA5, tipd_ADA5);
        VitalWireDelay (ADA6_ipd, ADA6, tipd_ADA6);
        VitalWireDelay (ADA7_ipd, ADA7, tipd_ADA7);
        VitalWireDelay (ADA8_ipd, ADA8, tipd_ADA8);
        VitalWireDelay (ADA9_ipd, ADA9, tipd_ADA9);

        VitalWireDelay (DIB0_ipd, DIB0, tipd_DIB0);
        VitalWireDelay (DIB1_ipd, DIB1, tipd_DIB1);
        VitalWireDelay (DIB2_ipd, DIB2, tipd_DIB2);
        VitalWireDelay (DIB3_ipd, DIB3, tipd_DIB3);
        VitalWireDelay (DIB4_ipd, DIB4, tipd_DIB4);
        VitalWireDelay (DIB5_ipd, DIB5, tipd_DIB5);
        VitalWireDelay (DIB6_ipd, DIB6, tipd_DIB6);
        VitalWireDelay (DIB7_ipd, DIB7, tipd_DIB7);
        VitalWireDelay (DIB8_ipd, DIB8, tipd_DIB8);
        VitalWireDelay (DIB9_ipd, DIB9, tipd_DIB9);
        VitalWireDelay (DIB10_ipd, DIB10, tipd_DIB10);
        VitalWireDelay (DIB11_ipd, DIB11, tipd_DIB11);
        VitalWireDelay (DIB12_ipd, DIB12, tipd_DIB12);
        VitalWireDelay (DIB13_ipd, DIB13, tipd_DIB13);
        VitalWireDelay (DIB14_ipd, DIB14, tipd_DIB14);
        VitalWireDelay (DIB15_ipd, DIB15, tipd_DIB15);


        VitalWireDelay (ADB0_ipd, ADB0, tipd_ADB0);
        VitalWireDelay (ADB1_ipd, ADB1, tipd_ADB1);
        VitalWireDelay (ADB2_ipd, ADB2, tipd_ADB2);
        VitalWireDelay (ADB3_ipd, ADB3, tipd_ADB3);
        VitalWireDelay (ADB4_ipd, ADB4, tipd_ADB4);
        VitalWireDelay (ADB5_ipd, ADB5, tipd_ADB5);
        VitalWireDelay (ADB6_ipd, ADB6, tipd_ADB6);
        VitalWireDelay (ADB7_ipd, ADB7, tipd_ADB7);
        VitalWireDelay (ADB8_ipd, ADB8, tipd_ADB8);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CENA_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_WRA_CLKA_posedge     : std_ulogic  := '0';

        variable Tviol_CENB_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_WRB_CLKB_posedge      : std_ulogic  := '0';


        variable Tviol_DIA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA3_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA4_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA5_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA6_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA7_CLKA_posedge    : std_ulogic  := '0';

        variable Tviol_ADA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA3_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA4_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA5_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA6_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA7_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA8_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA9_CLKA_posedge    : std_ulogic  := '0';

        variable Tviol_DIB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB8_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB9_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB10_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB11_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB12_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB13_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB14_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB15_CLKB_posedge    : std_ulogic  := '0';


        variable Tviol_ADB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB8_CLKB_posedge    : std_ulogic  := '0';

        variable Tviol_RSTA_CLKA_posedge_posedge : std_ulogic  := '0';
        variable Tviol_RSTB_CLKB_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CENA_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRA_CLKA_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CENB_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRB_CLKB_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA4_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA5_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA6_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA7_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB9_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB10_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB11_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB12_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB13_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB14_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB15_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA4_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA5_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA6_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA7_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA8_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA9_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RSTA_CLKA_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RSTB_CLKB_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLKA       : std_ulogic := '0';
        variable PInfo_CLKA       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_CLKB       : std_ulogic := '0';
        variable PInfo_CLkB       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTA        : std_ulogic := '0';
        variable PInfo_RSTA        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTB        : std_ulogic := '0';
        variable PInfo_RSTB        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DOA0_zd         : std_ulogic := 'X';
        variable DOA1_zd         : std_ulogic := 'X';
        variable DOA2_zd         : std_ulogic := 'X';
        variable DOA3_zd         : std_ulogic := 'X';
        variable DOA4_zd         : std_ulogic := 'X';
        variable DOA5_zd         : std_ulogic := 'X';
        variable DOA6_zd         : std_ulogic := 'X';
        variable DOA7_zd         : std_ulogic := 'X';
        variable DOB0_zd         : std_ulogic := 'X';
        variable DOB1_zd         : std_ulogic := 'X';
        variable DOB2_zd         : std_ulogic := 'X';
        variable DOB3_zd         : std_ulogic := 'X';
        variable DOB4_zd         : std_ulogic := 'X';
        variable DOB5_zd         : std_ulogic := 'X';
        variable DOB6_zd         : std_ulogic := 'X';
        variable DOB7_zd         : std_ulogic := 'X';
        variable DOB8_zd         : std_ulogic := 'X';
        variable DOB9_zd         : std_ulogic := 'X';
        variable DOB10_zd         : std_ulogic := 'X';
        variable DOB11_zd         : std_ulogic := 'X';
        variable DOB12_zd         : std_ulogic := 'X';
        variable DOB13_zd         : std_ulogic := 'X';
        variable DOB14_zd         : std_ulogic := 'X';
        variable DOB15_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CENA_CLKA_posedge,
          TimingData              => Tmkr_CENA_CLKA_posedge,
          TestSignal              => CENA_ipd,
          TestSignalName          => "CENA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENA_CLKA_noedge_posedge,
          SetupLow                => tsetup_CENA_CLKA_noedge_posedge,
          HoldLow                 => thold_CENA_CLKA_noedge_posedge,
          HoldHigh                => thold_CENA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRA_CLKA_posedge,
          TimingData              => Tmkr_WRA_CLKA_posedge,
          TestSignal              => WRA_ipd,
          TestSignalName          => "WRA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRA_CLKA_noedge_posedge,
          SetupLow                => tsetup_WRA_CLKA_noedge_posedge,
          HoldLow                 => thold_WRA_CLKA_noedge_posedge,
          HoldHigh                => thold_WRA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA0_CLKA_posedge,
          TimingData              => Tmkr_CSA0_CLKA_posedge,
          TestSignal              => CSA0_ipd,
          TestSignalName          => "CSA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA0_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA0_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA1_CLKA_posedge,
          TimingData              => Tmkr_CSA1_CLKA_posedge,
          TestSignal              => CSA1_ipd,
          TestSignalName          => "CSA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA1_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA1_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CENB_CLKB_posedge,
          TimingData              => Tmkr_CENB_CLKB_posedge,
          TestSignal              => CENB_ipd,
          TestSignalName          => "CENB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENB_CLKB_noedge_posedge,
          SetupLow                => tsetup_CENB_CLKB_noedge_posedge,
          HoldLow                 => thold_CENB_CLKB_noedge_posedge,
          HoldHigh                => thold_CENB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRB_CLKB_posedge,
          TimingData              => Tmkr_WRB_CLKB_posedge,
          TestSignal              => WRB_ipd,
          TestSignalName          => "WRB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRB_CLKB_noedge_posedge,
          SetupLow                => tsetup_WRB_CLKB_noedge_posedge,
          HoldLow                 => thold_WRB_CLKB_noedge_posedge,
          HoldHigh                => thold_WRB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB0_CLKB_posedge,
          TimingData              => Tmkr_CSB0_CLKB_posedge,
          TestSignal              => CSB0_ipd,
          TestSignalName          => "CSB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB0_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB0_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB1_CLKB_posedge,
          TimingData              => Tmkr_CSB1_CLKB_posedge,
          TestSignal              => CSB1_ipd,
          TestSignalName          => "CSB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB1_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB1_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA0_CLKA_posedge,
          TimingData              => Tmkr_DIA0_CLKA_posedge,
          TestSignal              => DIA0_ipd,
          TestSignalName          => "DIA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA0_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA0_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA1_CLKA_posedge,
          TimingData              => Tmkr_DIA1_CLKA_posedge,
          TestSignal              => DIA1_ipd,
          TestSignalName          => "DIA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA1_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA1_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA2_CLKA_posedge,
          TimingData              => Tmkr_DIA2_CLKA_posedge,
          TestSignal              => DIA2_ipd,
          TestSignalName          => "DIA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA2_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA2_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA3_CLKA_posedge,
          TimingData              => Tmkr_DIA3_CLKA_posedge,
          TestSignal              => DIA3_ipd,
          TestSignalName          => "DIA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA3_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA3_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA4_CLKA_posedge,
          TimingData              => Tmkr_DIA4_CLKA_posedge,
          TestSignal              => DIA4_ipd,
          TestSignalName          => "DIA4",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA4_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA4_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA4_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA4_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA5_CLKA_posedge,
          TimingData              => Tmkr_DIA5_CLKA_posedge,
          TestSignal              => DIA5_ipd,
          TestSignalName          => "DIA5",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA5_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA5_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA5_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA5_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA6_CLKA_posedge,
          TimingData              => Tmkr_DIA6_CLKA_posedge,
          TestSignal              => DIA6_ipd,
          TestSignalName          => "DIA6",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA6_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA6_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA6_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA6_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA7_CLKA_posedge,
          TimingData              => Tmkr_DIA7_CLKA_posedge,
          TestSignal              => DIA7_ipd,
          TestSignalName          => "DIA7",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA7_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA7_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA7_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA7_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_ADA0_CLKA_posedge,
          TimingData              => Tmkr_ADA0_CLKA_posedge,
          TestSignal              => ADA0_ipd,
          TestSignalName          => "ADA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA0_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA0_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA1_CLKA_posedge,
          TimingData              => Tmkr_ADA1_CLKA_posedge,
          TestSignal              => ADA1_ipd,
          TestSignalName          => "ADA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA1_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA1_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA2_CLKA_posedge,
          TimingData              => Tmkr_ADA2_CLKA_posedge,
          TestSignal              => ADA2_ipd,
          TestSignalName          => "ADA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA2_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA2_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA3_CLKA_posedge,
          TimingData              => Tmkr_ADA3_CLKA_posedge,
          TestSignal              => ADA3_ipd,
          TestSignalName          => "ADA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA3_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA3_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA4_CLKA_posedge,
          TimingData              => Tmkr_ADA4_CLKA_posedge,
          TestSignal              => ADA4_ipd,
          TestSignalName          => "ADA4",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA4_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA4_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA4_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA4_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA5_CLKA_posedge,
          TimingData              => Tmkr_ADA5_CLKA_posedge,
          TestSignal              => ADA5_ipd,
          TestSignalName          => "ADA5",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA5_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA5_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA5_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA5_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA6_CLKA_posedge,
          TimingData              => Tmkr_ADA6_CLKA_posedge,
          TestSignal              => ADA6_ipd,
          TestSignalName          => "ADA6",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA6_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA6_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA6_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA6_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA7_CLKA_posedge,
          TimingData              => Tmkr_ADA7_CLKA_posedge,
          TestSignal              => ADA7_ipd,
          TestSignalName          => "ADA7",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA7_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA7_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA7_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA7_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA8_CLKA_posedge,
          TimingData              => Tmkr_ADA8_CLKA_posedge,
          TestSignal              => ADA8_ipd,
          TestSignalName          => "ADA8",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA8_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA8_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA8_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA8_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA9_CLKA_posedge,
          TimingData              => Tmkr_ADA9_CLKA_posedge,
          TestSignal              => ADA9_ipd,
          TestSignalName          => "ADA9",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA9_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA9_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA9_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA9_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB0_CLKB_posedge,
          TimingData              => Tmkr_DIB0_CLKB_posedge,
          TestSignal              => DIB0_ipd,
          TestSignalName          => "DIB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB0_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB0_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB1_CLKB_posedge,
          TimingData              => Tmkr_DIB1_CLKB_posedge,
          TestSignal              => DIB1_ipd,
          TestSignalName          => "DIB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB1_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB1_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB2_CLKB_posedge,
          TimingData              => Tmkr_DIB2_CLKB_posedge,
          TestSignal              => DIB2_ipd,
          TestSignalName          => "DIB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB2_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB2_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB3_CLKB_posedge,
          TimingData              => Tmkr_DIB3_CLKB_posedge,
          TestSignal              => DIB3_ipd,
          TestSignalName          => "DIB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB3_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB3_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB4_CLKB_posedge,
          TimingData              => Tmkr_DIB4_CLKB_posedge,
          TestSignal              => DIB4_ipd,
          TestSignalName          => "DIB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB4_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB4_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB5_CLKB_posedge,
          TimingData              => Tmkr_DIB5_CLKB_posedge,
          TestSignal              => DIB5_ipd,
          TestSignalName          => "DIB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB5_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB5_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB6_CLKB_posedge,
          TimingData              => Tmkr_DIB6_CLKB_posedge,
          TestSignal              => DIB6_ipd,
          TestSignalName          => "DIB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB6_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB6_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB7_CLKB_posedge,
          TimingData              => Tmkr_DIB7_CLKB_posedge,
          TestSignal              => DIB7_ipd,
          TestSignalName          => "DIB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB7_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB7_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB8_CLKB_posedge,
          TimingData              => Tmkr_DIB8_CLKB_posedge,
          TestSignal              => DIB8_ipd,
          TestSignalName          => "DIB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB8_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB8_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB9_CLKB_posedge,
          TimingData              => Tmkr_DIB9_CLKB_posedge,
          TestSignal              => DIB9_ipd,
          TestSignalName          => "DIB9",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB9_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB9_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB9_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB9_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB10_CLKB_posedge,
          TimingData              => Tmkr_DIB10_CLKB_posedge,
          TestSignal              => DIB10_ipd,
          TestSignalName          => "DIB10",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB10_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB10_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB10_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB10_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB11_CLKB_posedge,
          TimingData              => Tmkr_DIB11_CLKB_posedge,
          TestSignal              => DIB11_ipd,
          TestSignalName          => "DIB11",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB11_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB11_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB11_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB11_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB12_CLKB_posedge,
          TimingData              => Tmkr_DIB12_CLKB_posedge,
          TestSignal              => DIB12_ipd,
          TestSignalName          => "DIB12",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB12_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB12_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB12_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB12_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB13_CLKB_posedge,
          TimingData              => Tmkr_DIB13_CLKB_posedge,
          TestSignal              => DIB13_ipd,
          TestSignalName          => "DIB13",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB13_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB13_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB13_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB13_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB14_CLKB_posedge,
          TimingData              => Tmkr_DIB14_CLKB_posedge,
          TestSignal              => DIB14_ipd,
          TestSignalName          => "DIB14",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB14_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB14_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB14_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB14_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB15_CLKB_posedge,
          TimingData              => Tmkr_DIB15_CLKB_posedge,
          TestSignal              => DIB15_ipd,
          TestSignalName          => "DIB15",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB15_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB15_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB15_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB15_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB0_CLKB_posedge,
          TimingData              => Tmkr_ADB0_CLKB_posedge,
          TestSignal              => ADB0_ipd,
          TestSignalName          => "ADB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB0_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB0_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB1_CLKB_posedge,
          TimingData              => Tmkr_ADB1_CLKB_posedge,
          TestSignal              => ADB1_ipd,
          TestSignalName          => "ADB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB1_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB1_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB2_CLKB_posedge,
          TimingData              => Tmkr_ADB2_CLKB_posedge,
          TestSignal              => ADB2_ipd,
          TestSignalName          => "ADB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB2_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB2_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB3_CLKB_posedge,
          TimingData              => Tmkr_ADB3_CLKB_posedge,
          TestSignal              => ADB3_ipd,
          TestSignalName          => "ADB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB3_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB3_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB4_CLKB_posedge,
          TimingData              => Tmkr_ADB4_CLKB_posedge,
          TestSignal              => ADB4_ipd,
          TestSignalName          => "ADB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB4_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB4_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB5_CLKB_posedge,
          TimingData              => Tmkr_ADB5_CLKB_posedge,
          TestSignal              => ADB5_ipd,
          TestSignalName          => "ADB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB5_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB5_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB6_CLKB_posedge,
          TimingData              => Tmkr_ADB6_CLKB_posedge,
          TestSignal              => ADB6_ipd,
          TestSignalName          => "ADB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB6_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB6_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB7_CLKB_posedge,
          TimingData              => Tmkr_ADB7_CLKB_posedge,
          TestSignal              => ADB7_ipd,
          TestSignalName          => "ADB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB7_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB7_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB8_CLKB_posedge,
          TimingData              => Tmkr_ADB8_CLKB_posedge,
          TestSignal              => ADB8_ipd,
          TestSignalName          => "ADB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB8_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB8_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKA,
          PeriodData              => PInfo_CLKA,
          TestSignal              => CLKA_ipd,
          TestSignalName          => "CLKA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKA_posedge,
          PulseWidthLow           => tpw_CLKA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKB,
          PeriodData              => PInfo_CLKB,
          TestSignal              => CLKB_ipd,
          TestSignalName          => "CLKB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKB_posedge,
          PulseWidthLow           => tpw_CLKB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTA,
          PeriodData              => PInfo_RSTA,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTA_posedge,
          PulseWidthLow           => tpw_RSTA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTB,
          PeriodData              => PInfo_RSTB,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTB_posedge,
          PulseWidthLow           => tpw_RSTB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X8_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTA_CLKA_posedge_posedge,
          TimingData              => Tmkr_RSTA_CLKA_posedge_posedge,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName          => "CLKA",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTA_CLKA_posedge_posedge,
          Removal                 => thold_RSTA_CLKA_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTB_CLKB_posedge_posedge,
          TimingData              => Tmkr_RSTB_CLKB_posedge_posedge,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName          => "CLKB",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTB_CLKB_posedge_posedge,
          Removal                 => thold_RSTB_CLKB_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CENA_CLKA_posedge or Tviol_WRA_CLKA_posedge or 
                 Tviol_CSA0_CLKA_posedge or Tviol_CSA1_CLKA_posedge or 
                 Tviol_ADA0_CLKA_posedge or Tviol_ADA1_CLKA_posedge or 
                 Tviol_ADA2_CLKA_posedge or Tviol_ADA3_CLKA_posedge or 
                 Tviol_ADA4_CLKA_posedge or Tviol_ADA5_CLKA_posedge or 
                 Tviol_ADA6_CLKA_posedge or Tviol_ADA7_CLKA_posedge or 
                 Tviol_ADA8_CLKA_posedge or Tviol_ADA9_CLKA_posedge or 
                 Tviol_DIA0_CLKA_posedge or Tviol_DIA1_CLKA_posedge or
                 Tviol_DIA2_CLKA_posedge or Tviol_DIA3_CLKA_posedge or
                 Tviol_DIA4_CLKA_posedge or Tviol_DIA5_CLKA_posedge or
                 Tviol_DIA6_CLKA_posedge or Tviol_DIA7_CLKA_posedge or
                 Tviol_ADB0_CLKB_posedge or Tviol_ADB1_CLKB_posedge or 
                 Tviol_ADB2_CLKB_posedge or Tviol_ADB3_CLKB_posedge or 
                 Tviol_ADB4_CLKB_posedge or Tviol_ADB5_CLKB_posedge or 
                 Tviol_ADB6_CLKB_posedge or Tviol_ADB7_CLKB_posedge or 
                 Tviol_ADB8_CLKB_posedge or
 		 Tviol_DIB0_CLKB_posedge or  Tviol_DIB1_CLKB_posedge or 
 		 Tviol_DIB2_CLKB_posedge or  Tviol_DIB3_CLKB_posedge or 
 		 Tviol_DIB4_CLKB_posedge or  Tviol_DIB5_CLKB_posedge or 
 		 Tviol_DIB6_CLKB_posedge or  Tviol_DIB7_CLKB_posedge or 
 		 Tviol_DIB8_CLKB_posedge or  Tviol_DIB9_CLKB_posedge or 
 		 Tviol_DIB10_CLKB_posedge or  Tviol_DIB11_CLKB_posedge or
 		 Tviol_DIB12_CLKB_posedge or  Tviol_DIB13_CLKB_posedge or 
 		 Tviol_DIB14_CLKB_posedge or  Tviol_DIB15_CLKB_posedge or
                 Pviol_CLKA or Pviol_CLKB or Pviol_RSTA or Pviol_RSTB;

    -------------------------
    --  Functionality Section
    -------------------------

wait on CENA_ipd, CLKA_ipd, WRA_ipd, CSA, RSTA_ipd, DIA, ADA, CENB_ipd, CLKB_ipd, WRB_ipd, CSB, RSTB_ipd, DIB, ADB;

      end process VITALBehavior;

    VitalBehavior_DOA0  : process
      variable DOA0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA0_zd := DOA(0);

    VitalPathDelay01 (
      OutSignal => DOA0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA0",
      OutTemp => DOA0_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA0, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(0);
      end process;

    VitalBehavior_DOA1  : process
      variable DOA1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA1_zd := DOA(1);

    VitalPathDelay01 (
      OutSignal => DOA1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA1",
      OutTemp => DOA1_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA1, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(1);
      end process;

    VitalBehavior_DOA2  : process
      variable DOA2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA2_zd := DOA(2);

    VitalPathDelay01 (
      OutSignal => DOA2,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA2",
      OutTemp => DOA2_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA2, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(2);
      end process;

    VitalBehavior_DOA3  : process
      variable DOA3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA3_zd := DOA(3);

    VitalPathDelay01 (
      OutSignal => DOA3,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA3",
      OutTemp => DOA3_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA3, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(3);
      end process;

    VitalBehavior_DOA4  : process
      variable DOA4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA4_zd := DOA(4);

    VitalPathDelay01 (
      OutSignal => DOA4,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA4",
      OutTemp => DOA4_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA4, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(4);
      end process;

    VitalBehavior_DOA5  : process
      variable DOA5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA5_zd := DOA(5);

    VitalPathDelay01 (
      OutSignal => DOA5,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA5",
      OutTemp => DOA5_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA5, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(5);
      end process;

    VitalBehavior_DOA6  : process
      variable DOA6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA6_zd := DOA(6);

    VitalPathDelay01 (
      OutSignal => DOA6,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA6",
      OutTemp => DOA6_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA6, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(6);
      end process;

    VitalBehavior_DOA7  : process
      variable DOA7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA7_zd := DOA(7);

    VitalPathDelay01 (
      OutSignal => DOA7,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA7",
      OutTemp => DOA7_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA7, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(7);
      end process;

    VitalBehavior_DOB0  : process
      variable DOB0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB0_zd := DOB(0);

    VitalPathDelay01 (
      OutSignal => DOB0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB0",
      OutTemp => DOB0_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB0, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(0);
      end process;

    VitalBehavior_DOB1  : process
      variable DOB1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB1_zd := DOB(1);

    VitalPathDelay01 (
      OutSignal => DOB1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB1",
      OutTemp => DOB1_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB1, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(1);
      end process;

    VitalBehavior_DOB2  : process
      variable DOB2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB2_zd := DOB(2);

    VitalPathDelay01 (
      OutSignal => DOB2,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB2",
      OutTemp => DOB2_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB2, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(2);
      end process;

    VitalBehavior_DOB3  : process
      variable DOB3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB3_zd := DOB(3);

    VitalPathDelay01 (
      OutSignal => DOB3,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB3",
      OutTemp => DOB3_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB3, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(3);
      end process;

    VitalBehavior_DOB4  : process
      variable DOB4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB4_zd := DOB(4);

    VitalPathDelay01 (
      OutSignal => DOB4,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB4",
      OutTemp => DOB4_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB4, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(4);
      end process;

    VitalBehavior_DOB5  : process
      variable DOB5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB5_zd := DOB(5);

    VitalPathDelay01 (
      OutSignal => DOB5,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB5",
      OutTemp => DOB5_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB5, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(5);
      end process;

    VitalBehavior_DOB6  : process
      variable DOB6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB6_zd := DOB(6);

    VitalPathDelay01 (
      OutSignal => DOB6,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB6",
      OutTemp => DOB6_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB6, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(6);
      end process;

    VitalBehavior_DOB7  : process
      variable DOB7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB7_zd := DOB(7);

    VitalPathDelay01 (
      OutSignal => DOB7,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB7",
      OutTemp => DOB7_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB7, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(7);
      end process;

    VitalBehavior_DOB8  : process
      variable DOB8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB8_zd := DOB(8);

    VitalPathDelay01 (
      OutSignal => DOB8,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB8",
      OutTemp => DOB8_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB8, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(8);
      end process;

    VitalBehavior_DOB9  : process
      variable DOB9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB9_zd := DOB(9);

    VitalPathDelay01 (
      OutSignal => DOB9,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB9",
      OutTemp => DOB9_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB9, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(9);
      end process;

    VitalBehavior_DOB10  : process
      variable DOB10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB10_zd := DOB(10);

    VitalPathDelay01 (
      OutSignal => DOB10,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB10",
      OutTemp => DOB10_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB10, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(10);
      end process;

    VitalBehavior_DOB11  : process
      variable DOB11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB11_zd := DOB(11);

    VitalPathDelay01 (
      OutSignal => DOB11,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB11",
      OutTemp => DOB11_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB11, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(11);
      end process;

    VitalBehavior_DOB12  : process
      variable DOB12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB12_zd := DOB(12);

    VitalPathDelay01 (
      OutSignal => DOB12,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB12",
      OutTemp => DOB12_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB12, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(12);
      end process;

    VitalBehavior_DOB13  : process
      variable DOB13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB13_zd := DOB(13);

    VitalPathDelay01 (
      OutSignal => DOB13,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB13",
      OutTemp => DOB13_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB13, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(13);
      end process;

    VitalBehavior_DOB14  : process
      variable DOB14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB14_zd := DOB(14);

    VitalPathDelay01 (
      OutSignal => DOB14,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB14",
      OutTemp => DOB14_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB14, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(14);
      end process;

    VitalBehavior_DOB15  : process
      variable DOB15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB15_zd := DOB(15);

    VitalPathDelay01 (
      OutSignal => DOB15,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB15",
      OutTemp => DOB15_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB15, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(15);
      end process;



	DPRAM_INST: SC_DPRAM_16K
	   generic map(
		ADDR_WIDTH_A => 10,
		DATA_WIDTH_A => 8,
		ADDR_WIDTH_B => 9,
		DATA_WIDTH_B => 16,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CENA => CENA_ipd,
	        CLKA => CLKA_ipd,
	        WRA  => WRA_ipd,
	        CSA  => CSA,
	        RSTA => RSTA_ipd,
	        DIA  => DIA,
	        ADA  => ADA,
	        DOA  => DOA,

	        CENB => CENB_ipd,
	        CLKB => CLKB_ipd,
	        WRB  => WRB_ipd,
	        CSB  => CSB,
	        RSTB => RSTB_ipd,
	        DIB  => DIB,
	        ADB  => ADB,
	        DOB  => DOB);

end VITAL;

configuration CFG_RAMB8K_X8_X16_VITAL of RAMB8K_X8_X16 is
   for VITAL
   end for;
end CFG_RAMB8K_X8_X16_VITAL;



----- CELL RAMB8K_X16_X16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB8K_X16_X16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "dummy";
      tpd_CLKA_DOA0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA10                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA11                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA12                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA13                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA14                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKA_DOA15                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_CLKB_DOB0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLKB_DOB15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTA_DOA0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTA_DOA15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RSTB_DOB0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RSTB_DOB15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_CENA_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENA_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRA_CLKA_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRA_CLKA_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CENB_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CENB_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CSB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CSB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WRB_CLKB_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WRB_CLKB_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_DIA0_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA1_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA2_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA3_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA4_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA4_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA5_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA5_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA6_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA6_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA7_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA7_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA8_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA8_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA9_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA9_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA10_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA10_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA11_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA11_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA12_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA12_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA13_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA13_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA14_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA14_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIA15_CLKA_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIA15_CLKA_noedge_posedge    :	VitalDelayType   := 0.0 ns;


      tsetup_DIB0_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB1_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB2_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB3_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB4_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB5_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB6_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB7_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB8_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB9_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB9_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB10_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB10_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB11_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB11_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB12_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB12_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB13_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB13_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB14_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB14_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_DIB15_CLKB_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_DIB15_CLKB_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADA0_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA0_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA1_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA1_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA2_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA2_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA3_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA3_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA4_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA4_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA5_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA5_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA6_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA6_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA7_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA7_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADA8_CLKA_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADA8_CLKA_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADB0_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB0_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB1_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB1_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB2_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB2_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB3_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB3_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB4_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB4_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB5_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB5_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB6_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB6_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB7_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB7_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_ADB8_CLKB_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_ADB8_CLKB_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTA_CLKA_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTA_CLKA_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RSTB_CLKB_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RSTB_CLKB_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLKA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_CLKB_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTA_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RSTB_posedge                   :	VitalDelayType   := 2.0 ns;
      tipd_CENA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRA                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTA                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CENB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLKB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WRB                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CSB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RSTB                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIA15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DIB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DIB15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CENA                            :	in    STD_ULOGIC;
      CLKA                            :	in    STD_ULOGIC;
      WRA                             :	in    STD_ULOGIC;
      CSA0                            :	in    STD_ULOGIC;
      CSA1                            :	in    STD_ULOGIC;
      RSTA                            :	in    STD_ULOGIC;
      CENB                            :	in    STD_ULOGIC;
      CLKB                            :	in    STD_ULOGIC;
      WRB                             :	in    STD_ULOGIC;
      CSB0                            :	in    STD_ULOGIC;
      CSB1                            :	in    STD_ULOGIC;
      RSTB                            :	in    STD_ULOGIC;
      DIA0                            :	in    STD_ULOGIC;
      DIA1                            :	in    STD_ULOGIC;
      DIA2                            :	in    STD_ULOGIC;
      DIA3                            :	in    STD_ULOGIC;
      DIA4                            :	in    STD_ULOGIC;
      DIA5                            :	in    STD_ULOGIC;
      DIA6                            :	in    STD_ULOGIC;
      DIA7                            :	in    STD_ULOGIC;
      DIA8                            :	in    STD_ULOGIC;
      DIA9                            :	in    STD_ULOGIC;
      DIA10                           :	in    STD_ULOGIC;
      DIA11                           :	in    STD_ULOGIC;
      DIA12                           :	in    STD_ULOGIC;
      DIA13                           :	in    STD_ULOGIC;
      DIA14                           :	in    STD_ULOGIC;
      DIA15                           :	in    STD_ULOGIC;
      ADA0                            :	in    STD_ULOGIC;
      ADA1                            :	in    STD_ULOGIC;
      ADA2                            :	in    STD_ULOGIC;
      ADA3                            :	in    STD_ULOGIC;
      ADA4                            :	in    STD_ULOGIC;
      ADA5                            :	in    STD_ULOGIC;
      ADA6                            :	in    STD_ULOGIC;
      ADA7                            :	in    STD_ULOGIC;
      ADA8                            :	in    STD_ULOGIC;
      DIB0                            :	in    STD_ULOGIC;
      DIB1                            :	in    STD_ULOGIC;
      DIB2                            :	in    STD_ULOGIC;
      DIB3                            :	in    STD_ULOGIC;
      DIB4                            :	in    STD_ULOGIC;
      DIB5                            :	in    STD_ULOGIC;
      DIB6                            :	in    STD_ULOGIC;
      DIB7                            :	in    STD_ULOGIC;
      DIB8                            :	in    STD_ULOGIC;
      DIB9                            :	in    STD_ULOGIC;
      DIB10                           :	in    STD_ULOGIC;
      DIB11                           :	in    STD_ULOGIC;
      DIB12                           :	in    STD_ULOGIC;
      DIB13                           :	in    STD_ULOGIC;
      DIB14                           :	in    STD_ULOGIC;
      DIB15                           :	in    STD_ULOGIC;
      ADB0                            :	in    STD_ULOGIC;
      ADB1                            :	in    STD_ULOGIC;
      ADB2                            :	in    STD_ULOGIC;
      ADB3                            :	in    STD_ULOGIC;
      ADB4                            :	in    STD_ULOGIC;
      ADB5                            :	in    STD_ULOGIC;
      ADB6                            :	in    STD_ULOGIC;
      ADB7                            :	in    STD_ULOGIC;
      ADB8                            :	in    STD_ULOGIC;
      DOA0                            :	out   STD_ULOGIC;
      DOA1                            :	out   STD_ULOGIC;
      DOA2                            :	out   STD_ULOGIC;
      DOA3                            :	out   STD_ULOGIC;
      DOA4                            :	out   STD_ULOGIC;
      DOA5                            :	out   STD_ULOGIC;
      DOA6                            :	out   STD_ULOGIC;
      DOA7                            :	out   STD_ULOGIC;
      DOA8                            :	out   STD_ULOGIC;
      DOA9                            :	out   STD_ULOGIC;
      DOA10                           :	out   STD_ULOGIC;
      DOA11                           :	out   STD_ULOGIC;
      DOA12                           :	out   STD_ULOGIC;
      DOA13                           :	out   STD_ULOGIC;
      DOA14                           :	out   STD_ULOGIC;
      DOA15                           :	out   STD_ULOGIC;
      DOB0                            :	out   STD_ULOGIC;
      DOB1                            :	out   STD_ULOGIC;
      DOB2                            :	out   STD_ULOGIC;
      DOB3                            :	out   STD_ULOGIC;
      DOB4                            :	out   STD_ULOGIC;
      DOB5                            :	out   STD_ULOGIC;
      DOB6                            :	out   STD_ULOGIC;
      DOB7                            :	out   STD_ULOGIC;
      DOB8                            :	out   STD_ULOGIC;
      DOB9                            :	out   STD_ULOGIC;
      DOB10                           :	out   STD_ULOGIC;
      DOB11                           :	out   STD_ULOGIC;
      DOB12                           :	out   STD_ULOGIC;
      DOB13                           :	out   STD_ULOGIC;
      DOB14                           :	out   STD_ULOGIC;
      DOB15                           :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB8K_X16_X16 : entity is FALSE;
end RAMB8K_X16_X16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB8K_X16_X16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_DPRAM_16K
	   generic (
		ADDR_WIDTH_A    : integer := 9;
		DATA_WIDTH_A    : integer := 16;
		ADDR_WIDTH_B    : integer := 9;
		DATA_WIDTH_B    : integer := 16;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CENA : in  STD_LOGIC ;
		CLKA : in  STD_LOGIC ;
		WRA  : in  STD_LOGIC ;
		CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTA : in  STD_LOGIC ;
		DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
		ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
		DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

		CENB : in  STD_LOGIC ;
		CLKB : in  STD_LOGIC ;
		WRB  : in  STD_LOGIC ;
		CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
		RSTB : in  STD_LOGIC ;
		DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
		ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
		DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
		);
	end component ;

      signal CENA_ipd      : std_ulogic := 'X';
      signal CLKA_ipd      : std_ulogic := 'X';
      signal WRA_ipd       : std_ulogic := 'X';
      signal CSA0_ipd      : std_ulogic := 'X';
      signal CSA1_ipd      : std_ulogic := 'X';
      signal RSTA_ipd      : std_ulogic := 'X';

      signal CENB_ipd      : std_ulogic := 'X';
      signal CLKB_ipd      : std_ulogic := 'X';
      signal WRB_ipd       : std_ulogic := 'X';
      signal CSB0_ipd      : std_ulogic := 'X';
      signal CSB1_ipd      : std_ulogic := 'X';
      signal RSTB_ipd      : std_ulogic := 'X';

      signal DIA0_ipd      : std_ulogic := 'X';
      signal DIA1_ipd      : std_ulogic := 'X';
      signal DIA2_ipd      : std_ulogic := 'X';
      signal DIA3_ipd      : std_ulogic := 'X';
      signal DIA4_ipd      : std_ulogic := 'X';
      signal DIA5_ipd      : std_ulogic := 'X';
      signal DIA6_ipd      : std_ulogic := 'X';
      signal DIA7_ipd      : std_ulogic := 'X';
      signal DIA8_ipd      : std_ulogic := 'X';
      signal DIA9_ipd      : std_ulogic := 'X';
      signal DIA10_ipd      : std_ulogic := 'X';
      signal DIA11_ipd      : std_ulogic := 'X';
      signal DIA12_ipd      : std_ulogic := 'X';
      signal DIA13_ipd      : std_ulogic := 'X';
      signal DIA14_ipd      : std_ulogic := 'X';
      signal DIA15_ipd      : std_ulogic := 'X';

      signal ADA0_ipd      : std_ulogic := 'X';
      signal ADA1_ipd      : std_ulogic := 'X';
      signal ADA2_ipd      : std_ulogic := 'X';
      signal ADA3_ipd      : std_ulogic := 'X';
      signal ADA4_ipd      : std_ulogic := 'X';
      signal ADA5_ipd      : std_ulogic := 'X';
      signal ADA6_ipd      : std_ulogic := 'X';
      signal ADA7_ipd      : std_ulogic := 'X';
      signal ADA8_ipd      : std_ulogic := 'X';

      signal DIB0_ipd       : std_ulogic := 'X';
      signal DIB1_ipd       : std_ulogic := 'X';
      signal DIB2_ipd       : std_ulogic := 'X';
      signal DIB3_ipd       : std_ulogic := 'X';
      signal DIB4_ipd       : std_ulogic := 'X';
      signal DIB5_ipd       : std_ulogic := 'X';
      signal DIB6_ipd       : std_ulogic := 'X';
      signal DIB7_ipd       : std_ulogic := 'X';
      signal DIB8_ipd       : std_ulogic := 'X';
      signal DIB9_ipd       : std_ulogic := 'X';
      signal DIB10_ipd      : std_ulogic := 'X';
      signal DIB11_ipd      : std_ulogic := 'X';
      signal DIB12_ipd      : std_ulogic := 'X';
      signal DIB13_ipd      : std_ulogic := 'X';
      signal DIB14_ipd      : std_ulogic := 'X';
      signal DIB15_ipd      : std_ulogic := 'X';

      signal ADB0_ipd      : std_ulogic := 'X';
      signal ADB1_ipd      : std_ulogic := 'X';
      signal ADB2_ipd      : std_ulogic := 'X';
      signal ADB3_ipd      : std_ulogic := 'X';
      signal ADB4_ipd      : std_ulogic := 'X';
      signal ADB5_ipd      : std_ulogic := 'X';
      signal ADB6_ipd      : std_ulogic := 'X';
      signal ADB7_ipd      : std_ulogic := 'X';
      signal ADB8_ipd      : std_ulogic := 'X';

	signal CSA : std_logic_vector (1 downto 0);
	signal CSB : std_logic_vector (1 downto 0);
	signal DIA : std_logic_vector (15 downto 0);
	signal DOA : std_logic_vector (15 downto 0);
	signal DIB : std_logic_vector (15 downto 0);
	signal DOB : std_logic_vector (15 downto 0);
	signal ADA : std_logic_vector (8 downto 0);
	signal ADB : std_logic_vector (8 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);

begin 

	CSA <= CSA1_ipd & CSA0_ipd;
	CSB <= CSB1_ipd & CSB0_ipd;
	DIA <= DIA15_ipd & DIA14_ipd & DIA13_ipd & DIA12_ipd & DIA11_ipd & DIA10_ipd & DIA9_ipd & DIA8_ipd & DIA7_ipd & DIA6_ipd & DIA5_ipd & DIA4_ipd & DIA3_ipd & DIA2_ipd & DIA1_ipd & DIA0_ipd;
	DIB <= DIB15_ipd & DIB14_ipd & DIB13_ipd & DIB12_ipd & DIB11_ipd & DIB10_ipd & DIB9_ipd & DIB8_ipd & DIB7_ipd & DIB6_ipd & DIB5_ipd & DIB4_ipd & DIB3_ipd & DIB2_ipd & DIB1_ipd & DIB0_ipd;
	ADA <= ADA8_ipd & ADA7_ipd & ADA6_ipd & ADA5_ipd & ADA4_ipd & ADA3_ipd & ADA2_ipd & ADA1_ipd & ADA0_ipd;
	ADB <= ADB8_ipd & ADB7_ipd & ADB6_ipd & ADB5_ipd & ADB4_ipd & ADB3_ipd & ADB2_ipd & ADB1_ipd & ADB0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CENA_ipd, CENA, tipd_CENA);
        VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
        VitalWireDelay (CSA0_ipd, CSA0, tipd_CSA0);
        VitalWireDelay (CSA1_ipd, CSA1, tipd_CSA1);
        VitalWireDelay (WRA_ipd, WRA, tipd_WRA);
        VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);

        VitalWireDelay (CENB_ipd, CENB, tipd_CENB);
        VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
        VitalWireDelay (CSB0_ipd, CSB0, tipd_CSB0);
        VitalWireDelay (CSB1_ipd, CSB1, tipd_CSB1);
        VitalWireDelay (WRB_ipd, WRB, tipd_WRB);
        VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);

        VitalWireDelay (DIA0_ipd, DIA0, tipd_DIA0);
        VitalWireDelay (DIA1_ipd, DIA1, tipd_DIA1);
        VitalWireDelay (DIA2_ipd, DIA2, tipd_DIA2);
        VitalWireDelay (DIA3_ipd, DIA3, tipd_DIA3);
        VitalWireDelay (DIA4_ipd, DIA4, tipd_DIA4);
        VitalWireDelay (DIA5_ipd, DIA5, tipd_DIA5);
        VitalWireDelay (DIA6_ipd, DIA6, tipd_DIA6);
        VitalWireDelay (DIA7_ipd, DIA7, tipd_DIA7);
        VitalWireDelay (DIA8_ipd, DIA8, tipd_DIA8);
        VitalWireDelay (DIA9_ipd, DIA9, tipd_DIA9);
        VitalWireDelay (DIA10_ipd, DIA10, tipd_DIA10);
        VitalWireDelay (DIA11_ipd, DIA11, tipd_DIA11);
        VitalWireDelay (DIA12_ipd, DIA12, tipd_DIA12);
        VitalWireDelay (DIA13_ipd, DIA13, tipd_DIA13);
        VitalWireDelay (DIA14_ipd, DIA14, tipd_DIA14);
        VitalWireDelay (DIA15_ipd, DIA15, tipd_DIA15);

        VitalWireDelay (ADA0_ipd, ADA0, tipd_ADA0);
        VitalWireDelay (ADA1_ipd, ADA1, tipd_ADA1);
        VitalWireDelay (ADA2_ipd, ADA2, tipd_ADA2);
        VitalWireDelay (ADA3_ipd, ADA3, tipd_ADA3);
        VitalWireDelay (ADA4_ipd, ADA4, tipd_ADA4);
        VitalWireDelay (ADA5_ipd, ADA5, tipd_ADA5);
        VitalWireDelay (ADA6_ipd, ADA6, tipd_ADA6);
        VitalWireDelay (ADA7_ipd, ADA7, tipd_ADA7);
        VitalWireDelay (ADA8_ipd, ADA8, tipd_ADA8);

        VitalWireDelay (DIB0_ipd, DIB0, tipd_DIB0);
        VitalWireDelay (DIB1_ipd, DIB1, tipd_DIB1);
        VitalWireDelay (DIB2_ipd, DIB2, tipd_DIB2);
        VitalWireDelay (DIB3_ipd, DIB3, tipd_DIB3);
        VitalWireDelay (DIB4_ipd, DIB4, tipd_DIB4);
        VitalWireDelay (DIB5_ipd, DIB5, tipd_DIB5);
        VitalWireDelay (DIB6_ipd, DIB6, tipd_DIB6);
        VitalWireDelay (DIB7_ipd, DIB7, tipd_DIB7);
        VitalWireDelay (DIB8_ipd, DIB8, tipd_DIB8);
        VitalWireDelay (DIB9_ipd, DIB9, tipd_DIB9);
        VitalWireDelay (DIB10_ipd, DIB10, tipd_DIB10);
        VitalWireDelay (DIB11_ipd, DIB11, tipd_DIB11);
        VitalWireDelay (DIB12_ipd, DIB12, tipd_DIB12);
        VitalWireDelay (DIB13_ipd, DIB13, tipd_DIB13);
        VitalWireDelay (DIB14_ipd, DIB14, tipd_DIB14);
        VitalWireDelay (DIB15_ipd, DIB15, tipd_DIB15);


        VitalWireDelay (ADB0_ipd, ADB0, tipd_ADB0);
        VitalWireDelay (ADB1_ipd, ADB1, tipd_ADB1);
        VitalWireDelay (ADB2_ipd, ADB2, tipd_ADB2);
        VitalWireDelay (ADB3_ipd, ADB3, tipd_ADB3);
        VitalWireDelay (ADB4_ipd, ADB4, tipd_ADB4);
        VitalWireDelay (ADB5_ipd, ADB5, tipd_ADB5);
        VitalWireDelay (ADB6_ipd, ADB6, tipd_ADB6);
        VitalWireDelay (ADB7_ipd, ADB7, tipd_ADB7);
        VitalWireDelay (ADB8_ipd, ADB8, tipd_ADB8);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CENA_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_CSA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_WRA_CLKA_posedge     : std_ulogic  := '0';

        variable Tviol_CENB_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_CSB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_WRB_CLKB_posedge      : std_ulogic  := '0';


        variable Tviol_DIA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA3_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA4_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA5_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA6_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA7_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA8_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA9_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA10_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA11_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA12_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA13_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA14_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_DIA15_CLKA_posedge    : std_ulogic  := '0';

        variable Tviol_ADA0_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA1_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA2_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA3_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA4_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA5_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA6_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA7_CLKA_posedge    : std_ulogic  := '0';
        variable Tviol_ADA8_CLKA_posedge    : std_ulogic  := '0';

        variable Tviol_DIB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB8_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB9_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB10_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB11_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB12_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB13_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB14_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_DIB15_CLKB_posedge    : std_ulogic  := '0';


        variable Tviol_ADB0_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB1_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB2_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB3_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB4_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB5_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB6_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB7_CLKB_posedge    : std_ulogic  := '0';
        variable Tviol_ADB8_CLKB_posedge    : std_ulogic  := '0';

        variable Tviol_RSTA_CLKA_posedge_posedge : std_ulogic  := '0';
        variable Tviol_RSTB_CLKB_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CENA_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRA_CLKA_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CENB_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CSB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WRB_CLKB_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA4_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA5_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA6_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA7_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA8_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA9_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA10_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA11_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA12_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA13_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA14_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIA15_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DIB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB9_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB10_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB11_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB12_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB13_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB14_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DIB15_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADA0_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA1_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA2_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA3_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA4_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA5_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA6_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA7_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADA8_CLKA_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADB0_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB1_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB2_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB3_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB4_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB5_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB6_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB7_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADB8_CLKB_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RSTA_CLKA_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RSTB_CLKB_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLKA       : std_ulogic := '0';
        variable PInfo_CLKA       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_CLKB       : std_ulogic := '0';
        variable PInfo_CLkB       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTA        : std_ulogic := '0';
        variable PInfo_RSTA        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RSTB        : std_ulogic := '0';
        variable PInfo_RSTB        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DOA0_zd         : std_ulogic := 'X';
        variable DOA1_zd         : std_ulogic := 'X';
        variable DOA2_zd         : std_ulogic := 'X';
        variable DOA3_zd         : std_ulogic := 'X';
        variable DOA4_zd         : std_ulogic := 'X';
        variable DOA5_zd         : std_ulogic := 'X';
        variable DOA6_zd         : std_ulogic := 'X';
        variable DOA7_zd         : std_ulogic := 'X';
        variable DOA8_zd         : std_ulogic := 'X';
        variable DOA9_zd         : std_ulogic := 'X';
        variable DOA10_zd         : std_ulogic := 'X';
        variable DOA11_zd         : std_ulogic := 'X';
        variable DOA12_zd         : std_ulogic := 'X';
        variable DOA13_zd         : std_ulogic := 'X';
        variable DOA14_zd         : std_ulogic := 'X';
        variable DOA15_zd         : std_ulogic := 'X';
        variable DOB0_zd         : std_ulogic := 'X';
        variable DOB1_zd         : std_ulogic := 'X';
        variable DOB2_zd         : std_ulogic := 'X';
        variable DOB3_zd         : std_ulogic := 'X';
        variable DOB4_zd         : std_ulogic := 'X';
        variable DOB5_zd         : std_ulogic := 'X';
        variable DOB6_zd         : std_ulogic := 'X';
        variable DOB7_zd         : std_ulogic := 'X';
        variable DOB8_zd         : std_ulogic := 'X';
        variable DOB9_zd         : std_ulogic := 'X';
        variable DOB10_zd         : std_ulogic := 'X';
        variable DOB11_zd         : std_ulogic := 'X';
        variable DOB12_zd         : std_ulogic := 'X';
        variable DOB13_zd         : std_ulogic := 'X';
        variable DOB14_zd         : std_ulogic := 'X';
        variable DOB15_zd         : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CENA_CLKA_posedge,
          TimingData              => Tmkr_CENA_CLKA_posedge,
          TestSignal              => CENA_ipd,
          TestSignalName          => "CENA",
          TestDelay               => 0 ns,
          RefSignal               => CENA_ipd,
          RefSignalName           => "CENA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENA_CLKA_noedge_posedge,
          SetupLow                => tsetup_CENA_CLKA_noedge_posedge,
          HoldLow                 => thold_CENA_CLKA_noedge_posedge,
          HoldHigh                => thold_CENA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRA_CLKA_posedge,
          TimingData              => Tmkr_WRA_CLKA_posedge,
          TestSignal              => WRA_ipd,
          TestSignalName          => "WRA",
          TestDelay               => 0 ns,
          RefSignal               => WRA_ipd,
          RefSignalName           => "WRA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRA_CLKA_noedge_posedge,
          SetupLow                => tsetup_WRA_CLKA_noedge_posedge,
          HoldLow                 => thold_WRA_CLKA_noedge_posedge,
          HoldHigh                => thold_WRA_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA0_CLKA_posedge,
          TimingData              => Tmkr_CSA0_CLKA_posedge,
          TestSignal              => CSA0_ipd,
          TestSignalName          => "CSA0",
          TestDelay               => 0 ns,
          RefSignal               => CSA0_ipd,
          RefSignalName           => "CSA0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA0_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA0_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSA1_CLKA_posedge,
          TimingData              => Tmkr_CSA1_CLKA_posedge,
          TestSignal              => CSA1_ipd,
          TestSignalName          => "CSA1",
          TestDelay               => 0 ns,
          RefSignal               => CSA1_ipd,
          RefSignalName           => "CSA1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_CSA1_CLKA_noedge_posedge,
          HoldLow                 => thold_CSA1_CLKA_noedge_posedge,
          HoldHigh                => thold_CSA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CENB_CLKB_posedge,
          TimingData              => Tmkr_CENB_CLKB_posedge,
          TestSignal              => CENB_ipd,
          TestSignalName          => "CENB",
          TestDelay               => 0 ns,
          RefSignal               => CENB_ipd,
          RefSignalName           => "CENB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CENB_CLKB_noedge_posedge,
          SetupLow                => tsetup_CENB_CLKB_noedge_posedge,
          HoldLow                 => thold_CENB_CLKB_noedge_posedge,
          HoldHigh                => thold_CENB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WRB_CLKB_posedge,
          TimingData              => Tmkr_WRB_CLKB_posedge,
          TestSignal              => WRB_ipd,
          TestSignalName          => "WRB",
          TestDelay               => 0 ns,
          RefSignal               => WRB_ipd,
          RefSignalName           => "WRB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WRB_CLKB_noedge_posedge,
          SetupLow                => tsetup_WRB_CLKB_noedge_posedge,
          HoldLow                 => thold_WRB_CLKB_noedge_posedge,
          HoldHigh                => thold_WRB_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB0_CLKB_posedge,
          TimingData              => Tmkr_CSB0_CLKB_posedge,
          TestSignal              => CSB0_ipd,
          TestSignalName          => "CSB0",
          TestDelay               => 0 ns,
          RefSignal               => CSB0_ipd,
          RefSignalName           => "CSB0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB0_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB0_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CSB1_CLKB_posedge,
          TimingData              => Tmkr_CSB1_CLKB_posedge,
          TestSignal              => CSB1_ipd,
          TestSignalName          => "CSB1",
          TestDelay               => 0 ns,
          RefSignal               => CSB1_ipd,
          RefSignalName           => "CSB1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CSB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_CSB1_CLKB_noedge_posedge,
          HoldLow                 => thold_CSB1_CLKB_noedge_posedge,
          HoldHigh                => thold_CSB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA0_CLKA_posedge,
          TimingData              => Tmkr_DIA0_CLKA_posedge,
          TestSignal              => DIA0_ipd,
          TestSignalName          => "DIA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA0_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA0_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA1_CLKA_posedge,
          TimingData              => Tmkr_DIA1_CLKA_posedge,
          TestSignal              => DIA1_ipd,
          TestSignalName          => "DIA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA1_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA1_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA2_CLKA_posedge,
          TimingData              => Tmkr_DIA2_CLKA_posedge,
          TestSignal              => DIA2_ipd,
          TestSignalName          => "DIA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA2_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA2_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA3_CLKA_posedge,
          TimingData              => Tmkr_DIA3_CLKA_posedge,
          TestSignal              => DIA3_ipd,
          TestSignalName          => "DIA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA3_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA3_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA4_CLKA_posedge,
          TimingData              => Tmkr_DIA4_CLKA_posedge,
          TestSignal              => DIA4_ipd,
          TestSignalName          => "DIA4",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA4_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA4_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA4_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA4_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA5_CLKA_posedge,
          TimingData              => Tmkr_DIA5_CLKA_posedge,
          TestSignal              => DIA5_ipd,
          TestSignalName          => "DIA5",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA5_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA5_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA5_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA5_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA6_CLKA_posedge,
          TimingData              => Tmkr_DIA6_CLKA_posedge,
          TestSignal              => DIA6_ipd,
          TestSignalName          => "DIA6",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA6_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA6_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA6_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA6_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA7_CLKA_posedge,
          TimingData              => Tmkr_DIA7_CLKA_posedge,
          TestSignal              => DIA7_ipd,
          TestSignalName          => "DIA7",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA7_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA7_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA7_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA7_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA8_CLKA_posedge,
          TimingData              => Tmkr_DIA8_CLKA_posedge,
          TestSignal              => DIA8_ipd,
          TestSignalName          => "DIA8",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA8_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA8_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA8_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA8_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA9_CLKA_posedge,
          TimingData              => Tmkr_DIA9_CLKA_posedge,
          TestSignal              => DIA9_ipd,
          TestSignalName          => "DIA9",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA9_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA9_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA9_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA9_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA10_CLKA_posedge,
          TimingData              => Tmkr_DIA10_CLKA_posedge,
          TestSignal              => DIA10_ipd,
          TestSignalName          => "DIA10",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA10_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA10_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA10_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA10_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA11_CLKA_posedge,
          TimingData              => Tmkr_DIA11_CLKA_posedge,
          TestSignal              => DIA11_ipd,
          TestSignalName          => "DIA11",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA11_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA11_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA11_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA11_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA12_CLKA_posedge,
          TimingData              => Tmkr_DIA12_CLKA_posedge,
          TestSignal              => DIA12_ipd,
          TestSignalName          => "DIA12",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA12_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA12_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA12_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA12_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA13_CLKA_posedge,
          TimingData              => Tmkr_DIA13_CLKA_posedge,
          TestSignal              => DIA13_ipd,
          TestSignalName          => "DIA13",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA13_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA13_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA13_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA13_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA14_CLKA_posedge,
          TimingData              => Tmkr_DIA14_CLKA_posedge,
          TestSignal              => DIA14_ipd,
          TestSignalName          => "DIA14",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA14_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA14_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA14_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA14_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIA15_CLKA_posedge,
          TimingData              => Tmkr_DIA15_CLKA_posedge,
          TestSignal              => DIA15_ipd,
          TestSignalName          => "DIA15",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIA15_CLKA_noedge_posedge,
          SetupLow                => tsetup_DIA15_CLKA_noedge_posedge,
          HoldLow                 => thold_DIA15_CLKA_noedge_posedge,
          HoldHigh                => thold_DIA15_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_ADA0_CLKA_posedge,
          TimingData              => Tmkr_ADA0_CLKA_posedge,
          TestSignal              => ADA0_ipd,
          TestSignalName          => "ADA0",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA0_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA0_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA0_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA0_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA1_CLKA_posedge,
          TimingData              => Tmkr_ADA1_CLKA_posedge,
          TestSignal              => ADA1_ipd,
          TestSignalName          => "ADA1",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA1_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA1_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA1_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA1_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA2_CLKA_posedge,
          TimingData              => Tmkr_ADA2_CLKA_posedge,
          TestSignal              => ADA2_ipd,
          TestSignalName          => "ADA2",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA2_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA2_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA2_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA2_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA3_CLKA_posedge,
          TimingData              => Tmkr_ADA3_CLKA_posedge,
          TestSignal              => ADA3_ipd,
          TestSignalName          => "ADA3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA3_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA3_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA3_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA3_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA4_CLKA_posedge,
          TimingData              => Tmkr_ADA4_CLKA_posedge,
          TestSignal              => ADA4_ipd,
          TestSignalName          => "ADA4",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA4_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA4_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA4_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA4_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA5_CLKA_posedge,
          TimingData              => Tmkr_ADA5_CLKA_posedge,
          TestSignal              => ADA5_ipd,
          TestSignalName          => "ADA5",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA5_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA5_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA5_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA5_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA6_CLKA_posedge,
          TimingData              => Tmkr_ADA6_CLKA_posedge,
          TestSignal              => ADA6_ipd,
          TestSignalName          => "ADA6",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA6_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA6_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA6_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA6_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA7_CLKA_posedge,
          TimingData              => Tmkr_ADA7_CLKA_posedge,
          TestSignal              => ADA7_ipd,
          TestSignalName          => "ADA7",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA7_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA7_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA7_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA7_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADA8_CLKA_posedge,
          TimingData              => Tmkr_ADA8_CLKA_posedge,
          TestSignal              => ADA8_ipd,
          TestSignalName          => "ADA8",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKA",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADA8_CLKA_noedge_posedge,
          SetupLow                => tsetup_ADA8_CLKA_noedge_posedge,
          HoldLow                 => thold_ADA8_CLKA_noedge_posedge,
          HoldHigh                => thold_ADA8_CLKA_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB0_CLKB_posedge,
          TimingData              => Tmkr_DIB0_CLKB_posedge,
          TestSignal              => DIB0_ipd,
          TestSignalName          => "DIB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB0_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB0_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB1_CLKB_posedge,
          TimingData              => Tmkr_DIB1_CLKB_posedge,
          TestSignal              => DIB1_ipd,
          TestSignalName          => "DIB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB1_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB1_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB2_CLKB_posedge,
          TimingData              => Tmkr_DIB2_CLKB_posedge,
          TestSignal              => DIB2_ipd,
          TestSignalName          => "DIB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB2_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB2_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB3_CLKB_posedge,
          TimingData              => Tmkr_DIB3_CLKB_posedge,
          TestSignal              => DIB3_ipd,
          TestSignalName          => "DIB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB3_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB3_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB4_CLKB_posedge,
          TimingData              => Tmkr_DIB4_CLKB_posedge,
          TestSignal              => DIB4_ipd,
          TestSignalName          => "DIB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB4_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB4_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB5_CLKB_posedge,
          TimingData              => Tmkr_DIB5_CLKB_posedge,
          TestSignal              => DIB5_ipd,
          TestSignalName          => "DIB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB5_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB5_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB6_CLKB_posedge,
          TimingData              => Tmkr_DIB6_CLKB_posedge,
          TestSignal              => DIB6_ipd,
          TestSignalName          => "DIB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB6_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB6_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB7_CLKB_posedge,
          TimingData              => Tmkr_DIB7_CLKB_posedge,
          TestSignal              => DIB7_ipd,
          TestSignalName          => "DIB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB7_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB7_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB8_CLKB_posedge,
          TimingData              => Tmkr_DIB8_CLKB_posedge,
          TestSignal              => DIB8_ipd,
          TestSignalName          => "DIB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB8_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB8_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB9_CLKB_posedge,
          TimingData              => Tmkr_DIB9_CLKB_posedge,
          TestSignal              => DIB9_ipd,
          TestSignalName          => "DIB9",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB9_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB9_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB9_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB9_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB10_CLKB_posedge,
          TimingData              => Tmkr_DIB10_CLKB_posedge,
          TestSignal              => DIB10_ipd,
          TestSignalName          => "DIB10",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB10_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB10_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB10_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB10_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB11_CLKB_posedge,
          TimingData              => Tmkr_DIB11_CLKB_posedge,
          TestSignal              => DIB11_ipd,
          TestSignalName          => "DIB11",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB11_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB11_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB11_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB11_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB12_CLKB_posedge,
          TimingData              => Tmkr_DIB12_CLKB_posedge,
          TestSignal              => DIB12_ipd,
          TestSignalName          => "DIB12",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB12_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB12_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB12_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB12_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB13_CLKB_posedge,
          TimingData              => Tmkr_DIB13_CLKB_posedge,
          TestSignal              => DIB13_ipd,
          TestSignalName          => "DIB13",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB13_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB13_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB13_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB13_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB14_CLKB_posedge,
          TimingData              => Tmkr_DIB14_CLKB_posedge,
          TestSignal              => DIB14_ipd,
          TestSignalName          => "DIB14",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB14_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB14_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB14_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB14_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DIB15_CLKB_posedge,
          TimingData              => Tmkr_DIB15_CLKB_posedge,
          TestSignal              => DIB15_ipd,
          TestSignalName          => "DIB15",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DIB15_CLKB_noedge_posedge,
          SetupLow                => tsetup_DIB15_CLKB_noedge_posedge,
          HoldLow                 => thold_DIB15_CLKB_noedge_posedge,
          HoldHigh                => thold_DIB15_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB0_CLKB_posedge,
          TimingData              => Tmkr_ADB0_CLKB_posedge,
          TestSignal              => ADB0_ipd,
          TestSignalName          => "ADB0",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB0_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB0_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB0_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB0_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB1_CLKB_posedge,
          TimingData              => Tmkr_ADB1_CLKB_posedge,
          TestSignal              => ADB1_ipd,
          TestSignalName          => "ADB1",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB1_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB1_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB1_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB1_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB2_CLKB_posedge,
          TimingData              => Tmkr_ADB2_CLKB_posedge,
          TestSignal              => ADB2_ipd,
          TestSignalName          => "ADB2",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB2_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB2_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB2_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB2_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB3_CLKB_posedge,
          TimingData              => Tmkr_ADB3_CLKB_posedge,
          TestSignal              => ADB3_ipd,
          TestSignalName          => "ADB3",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB3_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB3_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB3_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB3_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB4_CLKB_posedge,
          TimingData              => Tmkr_ADB4_CLKB_posedge,
          TestSignal              => ADB4_ipd,
          TestSignalName          => "ADB4",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB4_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB4_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB4_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB4_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB5_CLKB_posedge,
          TimingData              => Tmkr_ADB5_CLKB_posedge,
          TestSignal              => ADB5_ipd,
          TestSignalName          => "ADB5",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB5_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB5_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB5_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB5_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB6_CLKB_posedge,
          TimingData              => Tmkr_ADB6_CLKB_posedge,
          TestSignal              => ADB6_ipd,
          TestSignalName          => "ADB6",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB6_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB6_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB6_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB6_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB7_CLKB_posedge,
          TimingData              => Tmkr_ADB7_CLKB_posedge,
          TestSignal              => ADB7_ipd,
          TestSignalName          => "ADB7",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB7_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB7_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB7_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB7_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADB8_CLKB_posedge,
          TimingData              => Tmkr_ADB8_CLKB_posedge,
          TestSignal              => ADB8_ipd,
          TestSignalName          => "ADB8",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName           => "CLKB",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADB8_CLKB_noedge_posedge,
          SetupLow                => tsetup_ADB8_CLKB_noedge_posedge,
          HoldLow                 => thold_ADB8_CLKB_noedge_posedge,
          HoldHigh                => thold_ADB8_CLKB_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKA,
          PeriodData              => PInfo_CLKA,
          TestSignal              => CLKA_ipd,
          TestSignalName          => "CLKA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKA_posedge,
          PulseWidthLow           => tpw_CLKA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLKB,
          PeriodData              => PInfo_CLKB,
          TestSignal              => CLKB_ipd,
          TestSignalName          => "CLKB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLKB_posedge,
          PulseWidthLow           => tpw_CLKB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTA,
          PeriodData              => PInfo_RSTA,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTA_posedge,
          PulseWidthLow           => tpw_RSTA_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RSTB,
          PeriodData              => PInfo_RSTB,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RSTB_posedge,
          PulseWidthLow           => tpw_RSTB_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB8K_X16_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTA_CLKA_posedge_posedge,
          TimingData              => Tmkr_RSTA_CLKA_posedge_posedge,
          TestSignal              => RSTA_ipd,
          TestSignalName          => "RSTA",
          TestDelay               => 0 ns,
          RefSignal               => CLKA_ipd,
          RefSignalName          => "CLKA",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTA_CLKA_posedge_posedge,
          Removal                 => thold_RSTA_CLKA_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RSTB_CLKB_posedge_posedge,
          TimingData              => Tmkr_RSTB_CLKB_posedge_posedge,
          TestSignal              => RSTB_ipd,
          TestSignalName          => "RSTB",
          TestDelay               => 0 ns,
          RefSignal               => CLKB_ipd,
          RefSignalName          => "CLKB",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RSTB_CLKB_posedge_posedge,
          Removal                 => thold_RSTB_CLKB_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CENA_CLKA_posedge or Tviol_WRA_CLKA_posedge or 
                 Tviol_CSA0_CLKA_posedge or Tviol_CSA1_CLKA_posedge or 
                 Tviol_ADA0_CLKA_posedge or Tviol_ADA1_CLKA_posedge or 
                 Tviol_ADA2_CLKA_posedge or Tviol_ADA3_CLKA_posedge or 
                 Tviol_ADA4_CLKA_posedge or Tviol_ADA5_CLKA_posedge or 
                 Tviol_ADA6_CLKA_posedge or Tviol_ADA7_CLKA_posedge or 
                 Tviol_ADA8_CLKA_posedge or 
                 Tviol_DIA0_CLKA_posedge or Tviol_DIA1_CLKA_posedge or
                 Tviol_DIA2_CLKA_posedge or Tviol_DIA3_CLKA_posedge or
                 Tviol_DIA4_CLKA_posedge or Tviol_DIA5_CLKA_posedge or
                 Tviol_DIA6_CLKA_posedge or Tviol_DIA7_CLKA_posedge or
                 Tviol_DIA8_CLKA_posedge or Tviol_DIA9_CLKA_posedge or
                 Tviol_DIA10_CLKA_posedge or Tviol_DIA11_CLKA_posedge or
                 Tviol_DIA12_CLKA_posedge or Tviol_DIA13_CLKA_posedge or
                 Tviol_DIA14_CLKA_posedge or Tviol_DIA15_CLKA_posedge or
                 Tviol_ADB0_CLKB_posedge or Tviol_ADB1_CLKB_posedge or 
                 Tviol_ADB2_CLKB_posedge or Tviol_ADB3_CLKB_posedge or 
                 Tviol_ADB4_CLKB_posedge or Tviol_ADB5_CLKB_posedge or 
                 Tviol_ADB6_CLKB_posedge or Tviol_ADB7_CLKB_posedge or 
                 Tviol_ADB8_CLKB_posedge or
 		 Tviol_DIB0_CLKB_posedge or  Tviol_DIB1_CLKB_posedge or 
 		 Tviol_DIB2_CLKB_posedge or  Tviol_DIB3_CLKB_posedge or 
 		 Tviol_DIB4_CLKB_posedge or  Tviol_DIB5_CLKB_posedge or 
 		 Tviol_DIB6_CLKB_posedge or  Tviol_DIB7_CLKB_posedge or 
 		 Tviol_DIB8_CLKB_posedge or  Tviol_DIB9_CLKB_posedge or 
 		 Tviol_DIB10_CLKB_posedge or  Tviol_DIB11_CLKB_posedge or
 		 Tviol_DIB12_CLKB_posedge or  Tviol_DIB13_CLKB_posedge or 
 		 Tviol_DIB14_CLKB_posedge or  Tviol_DIB15_CLKB_posedge or
                 Pviol_CLKA or Pviol_CLKB or Pviol_RSTA or Pviol_RSTB;

    -------------------------
    --  Functionality Section
    -------------------------

wait on CENA_ipd, CLKA_ipd, WRA_ipd, CSA, RSTA_ipd, DIA, ADA, CENB_ipd, CLKB_ipd, WRB_ipd, CSB, RSTB_ipd, DIB, ADB;

      end process VITALBehavior;

    VitalBehavior_DOA0  : process
      variable DOA0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA0_zd := DOA(0);

    VitalPathDelay01 (
      OutSignal => DOA0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA0",
      OutTemp => DOA0_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA0, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(0);
      end process;

    VitalBehavior_DOA1  : process
      variable DOA1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA1_zd := DOA(1);

    VitalPathDelay01 (
      OutSignal => DOA1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA1",
      OutTemp => DOA1_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA1, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(1);
      end process;

    VitalBehavior_DOA2  : process
      variable DOA2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA2_zd := DOA(2);

    VitalPathDelay01 (
      OutSignal => DOA2,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA2",
      OutTemp => DOA2_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA2, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(2);
      end process;

    VitalBehavior_DOA3  : process
      variable DOA3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA3_zd := DOA(3);

    VitalPathDelay01 (
      OutSignal => DOA3,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA3",
      OutTemp => DOA3_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA3, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(3);
      end process;

    VitalBehavior_DOA4  : process
      variable DOA4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA4_zd := DOA(4);

    VitalPathDelay01 (
      OutSignal => DOA4,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA4",
      OutTemp => DOA4_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA4, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(4);
      end process;

    VitalBehavior_DOA5  : process
      variable DOA5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA5_zd := DOA(5);

    VitalPathDelay01 (
      OutSignal => DOA5,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA5",
      OutTemp => DOA5_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA5, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(5);
      end process;

    VitalBehavior_DOA6  : process
      variable DOA6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA6_zd := DOA(6);

    VitalPathDelay01 (
      OutSignal => DOA6,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA6",
      OutTemp => DOA6_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA6, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(6);
      end process;

    VitalBehavior_DOA7  : process
      variable DOA7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA7_zd := DOA(7);

    VitalPathDelay01 (
      OutSignal => DOA7,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA7",
      OutTemp => DOA7_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA7, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(7);
      end process;

    VitalBehavior_DOA8  : process
      variable DOA8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA8_zd := DOA(8);

    VitalPathDelay01 (
      OutSignal => DOA8,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA8",
      OutTemp => DOA8_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA8, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(8);
      end process;

    VitalBehavior_DOA9  : process
      variable DOA9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA9_zd := DOA(9);

    VitalPathDelay01 (
      OutSignal => DOA9,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA9",
      OutTemp => DOA9_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA9, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(9);
      end process;

    VitalBehavior_DOA10  : process
      variable DOA10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA10_zd := DOA(10);

    VitalPathDelay01 (
      OutSignal => DOA10,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA10",
      OutTemp => DOA10_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA10, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(10);
      end process;

    VitalBehavior_DOA11  : process
      variable DOA11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA11_zd := DOA(11);

    VitalPathDelay01 (
      OutSignal => DOA11,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA11",
      OutTemp => DOA11_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA11, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(11);
      end process;

    VitalBehavior_DOA12  : process
      variable DOA12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA12_zd := DOA(12);

    VitalPathDelay01 (
      OutSignal => DOA12,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA12",
      OutTemp => DOA12_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA12, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(12);
      end process;

    VitalBehavior_DOA13  : process
      variable DOA13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA13_zd := DOA(13);

    VitalPathDelay01 (
      OutSignal => DOA13,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA13",
      OutTemp => DOA13_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA13, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(13);
      end process;

    VitalBehavior_DOA14  : process
      variable DOA14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA14_zd := DOA(14);

    VitalPathDelay01 (
      OutSignal => DOA14,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA14",
      OutTemp => DOA14_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA14, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(14);
      end process;

    VitalBehavior_DOA15  : process
      variable DOA15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOA15_zd := DOA(15);

    VitalPathDelay01 (
      OutSignal => DOA15,
      GlitchData => O_GlitchData,
      OutSignalName => "DOA15",
      OutTemp => DOA15_zd,
      Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA15, TRUE),
                1 => (RSTA_ipd'last_event, tpd_RSTA_DOA15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOA(15);
      end process;

    VitalBehavior_DOB0  : process
      variable DOB0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB0_zd := DOB(0);

    VitalPathDelay01 (
      OutSignal => DOB0,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB0",
      OutTemp => DOB0_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB0, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(0);
      end process;

    VitalBehavior_DOB1  : process
      variable DOB1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB1_zd := DOB(1);

    VitalPathDelay01 (
      OutSignal => DOB1,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB1",
      OutTemp => DOB1_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB1, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(1);
      end process;

    VitalBehavior_DOB2  : process
      variable DOB2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB2_zd := DOB(2);

    VitalPathDelay01 (
      OutSignal => DOB2,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB2",
      OutTemp => DOB2_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB2, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(2);
      end process;

    VitalBehavior_DOB3  : process
      variable DOB3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB3_zd := DOB(3);

    VitalPathDelay01 (
      OutSignal => DOB3,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB3",
      OutTemp => DOB3_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB3, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(3);
      end process;

    VitalBehavior_DOB4  : process
      variable DOB4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB4_zd := DOB(4);

    VitalPathDelay01 (
      OutSignal => DOB4,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB4",
      OutTemp => DOB4_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB4, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(4);
      end process;

    VitalBehavior_DOB5  : process
      variable DOB5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB5_zd := DOB(5);

    VitalPathDelay01 (
      OutSignal => DOB5,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB5",
      OutTemp => DOB5_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB5, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(5);
      end process;

    VitalBehavior_DOB6  : process
      variable DOB6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB6_zd := DOB(6);

    VitalPathDelay01 (
      OutSignal => DOB6,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB6",
      OutTemp => DOB6_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB6, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(6);
      end process;

    VitalBehavior_DOB7  : process
      variable DOB7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB7_zd := DOB(7);

    VitalPathDelay01 (
      OutSignal => DOB7,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB7",
      OutTemp => DOB7_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB7, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(7);
      end process;

    VitalBehavior_DOB8  : process
      variable DOB8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB8_zd := DOB(8);

    VitalPathDelay01 (
      OutSignal => DOB8,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB8",
      OutTemp => DOB8_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB8, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(8);
      end process;

    VitalBehavior_DOB9  : process
      variable DOB9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB9_zd := DOB(9);

    VitalPathDelay01 (
      OutSignal => DOB9,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB9",
      OutTemp => DOB9_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB9, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(9);
      end process;

    VitalBehavior_DOB10  : process
      variable DOB10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB10_zd := DOB(10);

    VitalPathDelay01 (
      OutSignal => DOB10,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB10",
      OutTemp => DOB10_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB10, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(10);
      end process;

    VitalBehavior_DOB11  : process
      variable DOB11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB11_zd := DOB(11);

    VitalPathDelay01 (
      OutSignal => DOB11,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB11",
      OutTemp => DOB11_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB11, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(11);
      end process;

    VitalBehavior_DOB12  : process
      variable DOB12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB12_zd := DOB(12);

    VitalPathDelay01 (
      OutSignal => DOB12,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB12",
      OutTemp => DOB12_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB12, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(12);
      end process;

    VitalBehavior_DOB13  : process
      variable DOB13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB13_zd := DOB(13);

    VitalPathDelay01 (
      OutSignal => DOB13,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB13",
      OutTemp => DOB13_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB13, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(13);
      end process;

    VitalBehavior_DOB14  : process
      variable DOB14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB14_zd := DOB(14);

    VitalPathDelay01 (
      OutSignal => DOB14,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB14",
      OutTemp => DOB14_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB14, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(14);
      end process;

    VitalBehavior_DOB15  : process
      variable DOB15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DOB15_zd := DOB(15);

    VitalPathDelay01 (
      OutSignal => DOB15,
      GlitchData => O_GlitchData,
      OutSignalName => "DOB15",
      OutTemp => DOB15_zd,
      Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB15, TRUE),
                1 => (RSTB_ipd'last_event, tpd_RSTB_DOB15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DOB(15);
      end process;



	DPRAM_INST: SC_DPRAM_16K
	   generic map(
		ADDR_WIDTH_A => 9,
		DATA_WIDTH_A => 16,
		ADDR_WIDTH_B => 9,
		DATA_WIDTH_B => 16,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CENA => CENA_ipd,
	        CLKA => CLKA_ipd,
	        WRA  => WRA_ipd,
	        CSA  => CSA,
	        RSTA => RSTA_ipd,
	        DIA  => DIA,
	        ADA  => ADA,
	        DOA  => DOA,

	        CENB => CENB_ipd,
	        CLKB => CLKB_ipd,
	        WRB  => WRB_ipd,
	        CSB  => CSB,
	        RSTB => RSTB_ipd,
	        DIB  => DIB,
	        ADB  => ADB,
	        DOB  => DOB);


end VITAL;

configuration CFG_RAMB8K_X16_X16_VITAL of RAMB8K_X16_X16 is
   for VITAL
   end for;
end CFG_RAMB8K_X16_X16_VITAL;



----- CELL RAMB16KA_WX1_RX1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX1_RX1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD12_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD13_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      WAD13                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RAD11                           :	in    STD_ULOGIC;
      RAD12                           :	in    STD_ULOGIC;
      RAD13                           :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX1_RX1 : entity is FALSE;
end RAMB16KA_WX1_RX1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX1_RX1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 14;
		WDATA_WIDTH    : integer := 1;
		RADDR_WIDTH    : integer := 14;
		RDATA_WIDTH    : integer := 1;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_logic_vector (0 downto 0) ;

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';
      signal WAD13_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';
      signal RAD11_ipd     : std_ulogic := 'X';
      signal RAD12_ipd     : std_ulogic := 'X';
      signal RAD13_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (0 downto 0);
 	signal WAD : std_logic_vector (13 downto 0);
	signal RAD : std_logic_vector (13 downto 0);
	signal RD  : std_logic_vector (0 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD0_ipd;
	WAD <= WAD13_ipd & WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD13_ipd & RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;


  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);


        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd(0), WD0, tipd_WD0);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);
        VitalWireDelay (WAD13_ipd, WAD13, tipd_WAD13);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);
        VitalWireDelay (RAD13_ipd, RAD13, tipd_RAD13);

      end block;

      --------------------
      -- RAM16X1S Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';


        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD13_WCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD13_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD12_WCLK_posedge,
          TimingData              => Tmkr_WAD12_WCLK_posedge,
          TestSignal              => WAD12_ipd,
          TestSignalName          => "WAD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD13_WCLK_posedge,
          TimingData              => Tmkr_WAD13_WCLK_posedge,
          TestSignal              => WAD13_ipd,
          TestSignalName          => "WAD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX1_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
                1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
                2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
                3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
                4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
                5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
                6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
                7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
                8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
                9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
                10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
                11 => (RAD11_ipd'last_event, tpd_RAD11_RD0, TRUE),
                12 => (RAD12_ipd'last_event, tpd_RAD12_RD0, TRUE),
                13 => (RAD13_ipd'last_event, tpd_RAD13_RD0, TRUE),
                14 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD, RD;

      end process VITALBehavior;

	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 14,
		WDATA_WIDTH    => 1,
		RADDR_WIDTH    => 14,
		RDATA_WIDTH    => 1,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX1_RX1_VITAL of RAMB16KA_WX1_RX1 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX1_RX1_VITAL;



----- CELL RAMB16KA_WX1_RX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX1_RX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD12_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD12_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      WAD13                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RAD11                           :	in    STD_ULOGIC;
      RAD12                           :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX1_RX2 : entity is FALSE;
end RAMB16KA_WX1_RX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX1_RX2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 14;
		WDATA_WIDTH    : integer := 1;
		RADDR_WIDTH    : integer := 13;
		RDATA_WIDTH    : integer := 2;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_logic_vector(0 downto 0);

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';
      signal WAD13_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';
      signal RAD11_ipd     : std_ulogic := 'X';
      signal RAD12_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (0 downto 0);
 	signal WAD : std_logic_vector (13 downto 0);
	signal RAD : std_logic_vector (12 downto 0);
	signal RD  : std_logic_vector (1 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD0_ipd;
	WAD <= WAD13_ipd & WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;


  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);


        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd(0), WD0, tipd_WD0);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);
        VitalWireDelay (WAD13_ipd, WAD13, tipd_WAD13);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);

      end block;

      --------------------
      -- RAM16X1S Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';


        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD13_WCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD13_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLk",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD12_WCLK_posedge,
          TimingData              => Tmkr_WAD12_WCLK_posedge,
          TestSignal              => WAD12_ipd,
          TestSignalName          => "WAD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD13_WCLK_posedge,
          TimingData              => Tmkr_WAD13_WCLK_posedge,
          TestSignal              => WAD13_ipd,
          TestSignalName          => "WAD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD, RD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD0, TRUE),
               12 => (RAD12_ipd'last_event, tpd_RAD12_RD0, TRUE),
               13 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD1, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD1, TRUE),
               12 => (RAD12_ipd'last_event, tpd_RAD12_RD1, TRUE),
               13 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;





	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 14,
		WDATA_WIDTH    => 1,
		RADDR_WIDTH    => 13,
		RDATA_WIDTH    => 2,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX1_RX2_VITAL of RAMB16KA_WX1_RX2 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX1_RX2_VITAL;



----- CELL RAMB16KA_WX1_RX4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX1_RX4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD2                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD2                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD3                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD3                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      WAD13                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RAD11                           :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC;
      RD2                             :	out   STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX1_RX4 : entity is FALSE;
end RAMB16KA_WX1_RX4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX1_RX4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 14;
		WDATA_WIDTH    : integer := 1;
		RADDR_WIDTH    : integer := 12;
		RDATA_WIDTH    : integer := 4;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_logic_vector(0 downto 0);

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';
      signal WAD13_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';
      signal RAD11_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (0 downto 0);
 	signal WAD : std_logic_vector (13 downto 0);
	signal RAD : std_logic_vector (11 downto 0);
	signal RD  : std_logic_vector (3 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD0_ipd;
	WAD <= WAD13_ipd & WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);


        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd(0), WD0, tipd_WD0);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);
        VitalWireDelay (WAD13_ipd, WAD13, tipd_WAD13);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);

      end block;

      --------------------
      -- RAM16X1S Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';


        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD13_WCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD13_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLk",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD12_WCLK_posedge,
          TimingData              => Tmkr_WAD12_WCLK_posedge,
          TestSignal              => WAD12_ipd,
          TestSignalName          => "WAD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD13_WCLK_posedge,
          TimingData              => Tmkr_WAD13_WCLK_posedge,
          TestSignal              => WAD13_ipd,
          TestSignalName          => "WAD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD0, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD1, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD1, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD2, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD2, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD2, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD3, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD3, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD3, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;



	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 14,
		WDATA_WIDTH    => 1,
		RADDR_WIDTH    => 12,
		RDATA_WIDTH    => 4,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX1_RX4_VITAL of RAMB16KA_WX1_RX4 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX1_RX4_VITAL;



----- CELL RAMB16KA_WX1_RX8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX1_RX8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD2                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD3                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD4                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD5                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD6                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD7                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      WAD13                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC;
      RD2                             :	out   STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC;
      RD4                             :	out   STD_ULOGIC;
      RD5                             :	out   STD_ULOGIC;
      RD6                             :	out   STD_ULOGIC;
      RD7                             :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX1_RX8 : entity is FALSE;
end RAMB16KA_WX1_RX8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX1_RX8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 14;
		WDATA_WIDTH    : integer := 1;
		RADDR_WIDTH    : integer := 11;
		RDATA_WIDTH    : integer := 8;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_logic_vector(0 downto 0);

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';
      signal WAD13_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (0 downto 0);
 	signal WAD : std_logic_vector (13 downto 0);
	signal RAD : std_logic_vector (10 downto 0);
	signal RD  : std_logic_vector (7 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD0_ipd;
	WAD <= WAD13_ipd & WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);


        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd(0), WD0, tipd_WD0);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);
        VitalWireDelay (WAD13_ipd, WAD13, tipd_WAD13);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);

      end block;

      --------------------
      -- RAM16X1S Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';


        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD13_WCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD13_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLk",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD12_WCLK_posedge,
          TimingData              => Tmkr_WAD12_WCLK_posedge,
          TestSignal              => WAD12_ipd,
          TestSignalName          => "WAD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD13_WCLK_posedge,
          TimingData              => Tmkr_WAD13_WCLK_posedge,
          TestSignal              => WAD13_ipd,
          TestSignalName          => "WAD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;
      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD1, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD2, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD2, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD3, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD3, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD4, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD4, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD4, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD4, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD4, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD4, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD4, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD4, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD4, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD4, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD4, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD5, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD5, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD5, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD5, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD5, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD5, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD5, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD5, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD5, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD5, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD5, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD6, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD6, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD6, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD6, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD6, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD6, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD6, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD6, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD6, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD6, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD6, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD7, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD7, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD7, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD7, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD7, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD7, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD7, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD7, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD7, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD7, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD7, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;



	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 14,
		WDATA_WIDTH    => 1,
		RADDR_WIDTH    => 11,
		RDATA_WIDTH    => 8,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX1_RX8_VITAL of RAMB16KA_WX1_RX8 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX1_RX8_VITAL;



----- CELL RAMB16KA_WX1_RX16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX1_RX16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      WAD13                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC;
      RD2                             :	out   STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC;
      RD4                             :	out   STD_ULOGIC;
      RD5                             :	out   STD_ULOGIC;
      RD6                             :	out   STD_ULOGIC;
      RD7                             :	out   STD_ULOGIC;
      RD8                             :	out   STD_ULOGIC;
      RD9                             :	out   STD_ULOGIC;
      RD10                            :	out   STD_ULOGIC;
      RD11                            :	out   STD_ULOGIC;
      RD12                            :	out   STD_ULOGIC;
      RD13                            :	out   STD_ULOGIC;
      RD14                            :	out   STD_ULOGIC;
      RD15                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX1_RX16 : entity is FALSE;
end RAMB16KA_WX1_RX16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX1_RX16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 14;
		WDATA_WIDTH    : integer := 1;
		RADDR_WIDTH    : integer := 10;
		RDATA_WIDTH    : integer := 16;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_logic_vector(0 downto 0);

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';
      signal WAD13_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';
      signal RAD11_ipd     : std_ulogic := 'X';
      signal RAD12_ipd     : std_ulogic := 'X';
      signal RAD13_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (0 downto 0);
 	signal WAD : std_logic_vector (13 downto 0);
	signal RAD : std_logic_vector (9 downto 0);
	signal RD  : std_logic_vector (15 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD0_ipd;
	WAD <= WAD13_ipd & WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);


        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd(0), WD0, tipd_WD0);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);
        VitalWireDelay (WAD13_ipd, WAD13, tipd_WAD13);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);

      end block;

      --------------------
      -- RAM16X1S Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';


        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD13_WCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD13_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd          : std_ulogic := 'X';
        variable RD11_zd          : std_ulogic := 'X';
        variable RD12_zd          : std_ulogic := 'X';
        variable RD13_zd          : std_ulogic := 'X';
        variable RD14_zd          : std_ulogic := 'X';
        variable RD15_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLk",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD12_WCLK_posedge,
          TimingData              => Tmkr_WAD12_WCLK_posedge,
          TestSignal              => WAD12_ipd,
          TestSignalName          => "WAD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD13_WCLK_posedge,
          TimingData              => Tmkr_WAD13_WCLK_posedge,
          TestSignal              => WAD13_ipd,
          TestSignalName          => "WAD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD2, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD3, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD4, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD4, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD4, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD4, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD4, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD4, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD4, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD4, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD4, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD4, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD5, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD5, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD5, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD5, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD5, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD5, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD5, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD5, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD5, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD5, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD6, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD6, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD6, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD6, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD6, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD6, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD6, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD6, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD6, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD6, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD7, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD7, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD7, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD7, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD7, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD7, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD7, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD7, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD7, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD7, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD8, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD8, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD8, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD8, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD8, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD8, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD8, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD8, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD8, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD8, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD9, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD9, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD9, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD9, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD9, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD9, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD9, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD9, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD9, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD9, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD10, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD10, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD10, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD10, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD10, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD10, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD10, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD10, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD10, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD10, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD11, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD11, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD11, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD11, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD11, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD11, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD11, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD11, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD11, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD11, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD12, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD12, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD12, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD12, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD12, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD12, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD12, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD12, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD12, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD12, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD13, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD13, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD13, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD13, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD13, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD13, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD13, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD13, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD13, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD13, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD14, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD14, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD14, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD14, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD14, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD14, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD14, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD14, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD14, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD14, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD15, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD15, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD15, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD15, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD15, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD15, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD15, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD15, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD15, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD15, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;



	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 14,
		WDATA_WIDTH    => 1,
		RADDR_WIDTH    => 10,
		RDATA_WIDTH    => 16,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX1_RX16_VITAL of RAMB16KA_WX1_RX16 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX1_RX16_VITAL;



----- CELL RAMB16KA_WX1_RX32 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX1_RX32 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      WAD13                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC;
      RD2                             :	out   STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC;
      RD4                             :	out   STD_ULOGIC;
      RD5                             :	out   STD_ULOGIC;
      RD6                             :	out   STD_ULOGIC;
      RD7                             :	out   STD_ULOGIC;
      RD8                             :	out   STD_ULOGIC;
      RD9                             :	out   STD_ULOGIC;
      RD10                            :	out   STD_ULOGIC;
      RD11                            :	out   STD_ULOGIC;
      RD12                            :	out   STD_ULOGIC;
      RD13                            :	out   STD_ULOGIC;
      RD14                            :	out   STD_ULOGIC;
      RD15                            :	out   STD_ULOGIC;
      RD16                             :	out   STD_ULOGIC;
      RD17                             :	out   STD_ULOGIC;
      RD18                             :	out   STD_ULOGIC;
      RD19                             :	out   STD_ULOGIC;
      RD20                             :	out   STD_ULOGIC;
      RD21                             :	out   STD_ULOGIC;
      RD22                             :	out   STD_ULOGIC;
      RD23                             :	out   STD_ULOGIC;
      RD24                             :	out   STD_ULOGIC;
      RD25                             :	out   STD_ULOGIC;
      RD26                            :	out   STD_ULOGIC;
      RD27                            :	out   STD_ULOGIC;
      RD28                            :	out   STD_ULOGIC;
      RD29                            :	out   STD_ULOGIC;
      RD30                            :	out   STD_ULOGIC;
      RD31                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX1_RX32 : entity is FALSE;
end RAMB16KA_WX1_RX32;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX1_RX32 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 14;
		WDATA_WIDTH    : integer := 1;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_logic_vector(0 downto 0);

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';
      signal WAD13_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';
      signal RAD11_ipd     : std_ulogic := 'X';
      signal RAD12_ipd     : std_ulogic := 'X';
      signal RAD13_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (0 downto 0);
 	signal WAD : std_logic_vector (13 downto 0);
	signal RAD : std_logic_vector (8 downto 0);
	signal RD  : std_logic_vector (31 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD0_ipd;
	WAD <= WAD13_ipd & WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);


        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd(0), WD0, tipd_WD0);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);
        VitalWireDelay (WAD13_ipd, WAD13, tipd_WAD13);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);

      end block;

      --------------------
      -- RAM16X1S Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';


        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD13_WCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD13_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd          : std_ulogic := 'X';
        variable RD11_zd          : std_ulogic := 'X';
        variable RD12_zd          : std_ulogic := 'X';
        variable RD13_zd          : std_ulogic := 'X';
        variable RD14_zd          : std_ulogic := 'X';
        variable RD15_zd          : std_ulogic := 'X';
        variable RD16_zd          : std_ulogic := 'X';
        variable RD17_zd          : std_ulogic := 'X';
        variable RD18_zd          : std_ulogic := 'X';
        variable RD19_zd          : std_ulogic := 'X';
        variable RD20_zd          : std_ulogic := 'X';
        variable RD21_zd          : std_ulogic := 'X';
        variable RD22_zd          : std_ulogic := 'X';
        variable RD23_zd          : std_ulogic := 'X';
        variable RD24_zd          : std_ulogic := 'X';
        variable RD25_zd          : std_ulogic := 'X';
        variable RD26_zd          : std_ulogic := 'X';
        variable RD27_zd          : std_ulogic := 'X';
        variable RD28_zd          : std_ulogic := 'X';
        variable RD29_zd          : std_ulogic := 'X';
        variable RD30_zd          : std_ulogic := 'X';
        variable RD31_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLk",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD12_WCLK_posedge,
          TimingData              => Tmkr_WAD12_WCLK_posedge,
          TestSignal              => WAD12_ipd,
          TestSignalName          => "WAD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD13_WCLK_posedge,
          TimingData              => Tmkr_WAD13_WCLK_posedge,
          TestSignal              => WAD13_ipd,
          TestSignalName          => "WAD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD4, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD4, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD4, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD4, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD4, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD4, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD4, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD4, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD4, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD5, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD5, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD5, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD5, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD5, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD5, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD5, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD5, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD5, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD6, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD6, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD6, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD6, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD6, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD6, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD6, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD6, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD6, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD7, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD7, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD7, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD7, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD7, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD7, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD7, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD7, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD7, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD8, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD8, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD8, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD8, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD8, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD8, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD8, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD8, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD8, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD9, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD9, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD9, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD9, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD9, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD9, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD9, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD9, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD9, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD10, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD10, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD10, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD10, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD10, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD10, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD10, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD10, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD10, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD11, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD11, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD11, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD11, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD11, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD11, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD11, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD11, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD11, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD12, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD12, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD12, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD12, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD12, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD12, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD12, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD12, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD12, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD13, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD13, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD13, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD13, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD13, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD13, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD13, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD13, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD13, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD14, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD14, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD14, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD14, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD14, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD14, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD14, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD14, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD14, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD15, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD15, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD15, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD15, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD15, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD15, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD15, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD15, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD15, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;

    VitalBehavior_RD16  : process
      variable RD16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD16_zd := RD(16);

    VitalPathDelay01 (
      OutSignal => RD16,
      GlitchData => O_GlitchData,
      OutSignalName => "RD16",
      OutTemp => RD16_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD16, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD16, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD16, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD16, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD16, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD16, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD16, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD16, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD16, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(16);
      end process;

    VitalBehavior_RD17  : process
      variable RD17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD17_zd := RD(17);

    VitalPathDelay01 (
      OutSignal => RD17,
      GlitchData => O_GlitchData,
      OutSignalName => "RD17",
      OutTemp => RD17_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD17, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD17, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD17, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD17, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD17, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD17, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD17, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD17, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD17, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(17);
      end process;

    VitalBehavior_RD18  : process
      variable RD18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD18_zd := RD(18);

    VitalPathDelay01 (
      OutSignal => RD18,
      GlitchData => O_GlitchData,
      OutSignalName => "RD18",
      OutTemp => RD18_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD18, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD18, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD18, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD18, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD18, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD18, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD18, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD18, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD18, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(18);
      end process;

    VitalBehavior_RD19  : process
      variable RD19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD19_zd := RD(19);

    VitalPathDelay01 (
      OutSignal => RD19,
      GlitchData => O_GlitchData,
      OutSignalName => "RD19",
      OutTemp => RD19_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD19, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD19, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD19, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD19, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD19, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD19, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD19, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD19, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD19, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(19);
      end process;

    VitalBehavior_RD20  : process
      variable RD20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD20_zd := RD(20);

    VitalPathDelay01 (
      OutSignal => RD20,
      GlitchData => O_GlitchData,
      OutSignalName => "RD20",
      OutTemp => RD20_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD20, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD20, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD20, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD20, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD20, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD20, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD20, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD20, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD20, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(20);
      end process;

    VitalBehavior_RD21  : process
      variable RD21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD21_zd := RD(21);

    VitalPathDelay01 (
      OutSignal => RD21,
      GlitchData => O_GlitchData,
      OutSignalName => "RD21",
      OutTemp => RD21_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD21, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD21, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD21, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD21, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD21, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD21, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD21, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD21, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD21, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(21);
      end process;

    VitalBehavior_RD22  : process
      variable RD22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD22_zd := RD(22);

    VitalPathDelay01 (
      OutSignal => RD22,
      GlitchData => O_GlitchData,
      OutSignalName => "RD22",
      OutTemp => RD22_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD22, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD22, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD22, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD22, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD22, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD22, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD22, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD22, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD22, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(22);
      end process;

    VitalBehavior_RD23  : process
      variable RD23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD23_zd := RD(23);

    VitalPathDelay01 (
      OutSignal => RD23,
      GlitchData => O_GlitchData,
      OutSignalName => "RD23",
      OutTemp => RD23_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD23, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD23, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD23, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD23, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD23, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD23, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD23, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD23, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD23, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(23);
      end process;

    VitalBehavior_RD24  : process
      variable RD24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD24_zd := RD(24);

    VitalPathDelay01 (
      OutSignal => RD24,
      GlitchData => O_GlitchData,
      OutSignalName => "RD24",
      OutTemp => RD24_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD24, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD24, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD24, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD24, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD24, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD24, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD24, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD24, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD24, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(24);
      end process;

    VitalBehavior_RD25  : process
      variable RD25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD25_zd := RD(25);

    VitalPathDelay01 (
      OutSignal => RD25,
      GlitchData => O_GlitchData,
      OutSignalName => "RD25",
      OutTemp => RD25_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD25, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD25, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD25, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD25, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD25, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD25, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD25, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD25, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD25, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(25);
      end process;

    VitalBehavior_RD26  : process
      variable RD26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD26_zd := RD(26);

    VitalPathDelay01 (
      OutSignal => RD26,
      GlitchData => O_GlitchData,
      OutSignalName => "RD26",
      OutTemp => RD26_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD26, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD26, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD26, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD26, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD26, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD26, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD26, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD26, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD26, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(26);
      end process;

    VitalBehavior_RD27  : process
      variable RD27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD27_zd := RD(27);

    VitalPathDelay01 (
      OutSignal => RD27,
      GlitchData => O_GlitchData,
      OutSignalName => "RD27",
      OutTemp => RD27_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD27, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD27, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD27, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD27, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD27, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD27, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD27, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD27, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD27, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(27);
      end process;

    VitalBehavior_RD28  : process
      variable RD28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD28_zd := RD(28);

    VitalPathDelay01 (
      OutSignal => RD28,
      GlitchData => O_GlitchData,
      OutSignalName => "RD28",
      OutTemp => RD28_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD28, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD28, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD28, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD28, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD28, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD28, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD28, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD28, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD28, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(28);
      end process;

    VitalBehavior_RD29  : process
      variable RD29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD29_zd := RD(29);

    VitalPathDelay01 (
      OutSignal => RD29,
      GlitchData => O_GlitchData,
      OutSignalName => "RD29",
      OutTemp => RD29_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD29, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD29, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD29, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD29, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD29, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD29, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD29, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD29, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD29, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(29);
      end process;

    VitalBehavior_RD30  : process
      variable RD30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD30_zd := RD(30);

    VitalPathDelay01 (
      OutSignal => RD30,
      GlitchData => O_GlitchData,
      OutSignalName => "RD30",
      OutTemp => RD30_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD30, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD30, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD30, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD30, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD30, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD30, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD30, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD30, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD30, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(30);
      end process;

    VitalBehavior_RD31  : process
      variable RD31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD31_zd := RD(31);

    VitalPathDelay01 (
      OutSignal => RD31,
      GlitchData => O_GlitchData,
      OutSignalName => "RD31",
      OutTemp => RD31_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD31, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD31, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD31, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD31, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD31, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD31, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD31, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD31, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD31, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(31);
      end process;



	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 14,
		WDATA_WIDTH    => 1,
		RADDR_WIDTH    => 9,
		RDATA_WIDTH    => 32,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX1_RX32_VITAL of RAMB16KA_WX1_RX32 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX1_RX32_VITAL;



----- CELL RAMB16KA_WX2_RX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX2_RX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD12_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD12_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RAD11                           :	in    STD_ULOGIC;
      RAD12                           :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX2_RX2 : entity is FALSE;
end RAMB16KA_WX2_RX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX2_RX2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 13;
		WDATA_WIDTH    : integer := 2;
		RADDR_WIDTH    : integer := 13;
		RDATA_WIDTH    : integer := 2;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';
      signal RAD11_ipd     : std_ulogic := 'X';
      signal RAD12_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (1 downto 0);
 	signal WAD : std_logic_vector (12 downto 0);
	signal RAD : std_logic_vector (12 downto 0);
	signal RD  : std_logic_vector (1 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD1_ipd & WD0_ipd;
	WAD <= WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);

      end block;

      --------------------
      -- RAM16X1S Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX2_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD0, TRUE),
               12 => (RAD12_ipd'last_event, tpd_RAD12_RD0, TRUE),
               13 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD1, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD1, TRUE),
               12 => (RAD12_ipd'last_event, tpd_RAD12_RD1, TRUE),
               13 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;



	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 13,
		WDATA_WIDTH    => 2,
		RADDR_WIDTH    => 13,
		RDATA_WIDTH    => 2,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX2_RX2_VITAL of RAMB16KA_WX2_RX2 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX2_RX2_VITAL;



----- CELL RAMB16KA_WX2_RX4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX2_RX4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD2                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD2                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD3                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD3                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RAD11                           :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC;
      RD2                             :	out   STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX2_RX4 : entity is FALSE;
end RAMB16KA_WX2_RX4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX2_RX4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 13;
		WDATA_WIDTH    : integer := 2;
		RADDR_WIDTH    : integer := 12;
		RDATA_WIDTH    : integer := 4;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';
      signal RAD11_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (1 downto 0);
 	signal WAD : std_logic_vector (12 downto 0);
	signal RAD : std_logic_vector (11 downto 0);
	signal RD  : std_logic_vector (3 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD1_ipd & WD0_ipd;
	WAD <= WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);

      end block;

      --------------------
      -- RAM16X1S Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD0, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD1, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD1, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD2, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD2, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD2, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD3, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD3, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD3, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;



	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 13,
		WDATA_WIDTH    => 2,
		RADDR_WIDTH    => 12,
		RDATA_WIDTH    => 4,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX2_RX4_VITAL of RAMB16KA_WX2_RX4 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX2_RX4_VITAL;



----- CELL RAMB16KA_WX2_RX8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX2_RX8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD2                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD3                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD4                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD5                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD6                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD7                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC;
      RD2                             :	out   STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC;
      RD4                             :	out   STD_ULOGIC;
      RD5                             :	out   STD_ULOGIC;
      RD6                             :	out   STD_ULOGIC;
      RD7                             :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX2_RX8 : entity is FALSE;
end RAMB16KA_WX2_RX8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX2_RX8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 13;
		WDATA_WIDTH    : integer := 2;
		RADDR_WIDTH    : integer := 11;
		RDATA_WIDTH    : integer := 8;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (1 downto 0);
 	signal WAD : std_logic_vector (12 downto 0);
	signal RAD : std_logic_vector (10 downto 0);
	signal RD  : std_logic_vector (7 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD1_ipd & WD0_ipd;
	WAD <= WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);

      end block;

      --------------------
      -- RAM16X1S Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD1, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD2, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD2, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD3, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD3, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD4, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD4, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD4, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD4, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD4, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD4, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD4, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD4, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD4, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD4, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD4, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD5, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD5, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD5, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD5, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD5, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD5, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD5, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD5, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD5, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD5, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD5, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD6, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD6, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD6, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD6, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD6, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD6, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD6, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD6, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD6, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD6, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD6, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD7, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD7, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD7, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD7, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD7, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD7, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD7, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD7, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD7, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD7, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD7, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;



	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 13,
		WDATA_WIDTH    => 2,
		RADDR_WIDTH    => 11,
		RDATA_WIDTH    => 8,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX2_RX8_VITAL of RAMB16KA_WX2_RX8 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX2_RX8_VITAL;



----- CELL RAMB16KA_WX2_RX16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX2_RX16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC;
      RD2                             :	out   STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC;
      RD4                             :	out   STD_ULOGIC;
      RD5                             :	out   STD_ULOGIC;
      RD6                             :	out   STD_ULOGIC;
      RD7                             :	out   STD_ULOGIC;
      RD8                             :	out   STD_ULOGIC;
      RD9                             :	out   STD_ULOGIC;
      RD10                            :	out   STD_ULOGIC;
      RD11                            :	out   STD_ULOGIC;
      RD12                            :	out   STD_ULOGIC;
      RD13                            :	out   STD_ULOGIC;
      RD14                            :	out   STD_ULOGIC;
      RD15                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX2_RX16 : entity is FALSE;
end RAMB16KA_WX2_RX16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX2_RX16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 13;
		WDATA_WIDTH    : integer := 2;
		RADDR_WIDTH    : integer := 10;
		RDATA_WIDTH    : integer := 16;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (1 downto 0);
 	signal WAD : std_logic_vector (12 downto 0);
	signal RAD : std_logic_vector (9 downto 0);
	signal RD  : std_logic_vector (15 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD1_ipd & WD0_ipd;
	WAD <= WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);

      end block;

      --------------------
      -- RAM16X1S Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd          : std_ulogic := 'X';
        variable RD11_zd          : std_ulogic := 'X';
        variable RD12_zd          : std_ulogic := 'X';
        variable RD13_zd          : std_ulogic := 'X';
        variable RD14_zd          : std_ulogic := 'X';
        variable RD15_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD2, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD3, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD4, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD4, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD4, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD4, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD4, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD4, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD4, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD4, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD4, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD4, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD5, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD5, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD5, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD5, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD5, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD5, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD5, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD5, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD5, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD5, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD6, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD6, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD6, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD6, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD6, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD6, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD6, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD6, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD6, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD6, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD7, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD7, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD7, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD7, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD7, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD7, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD7, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD7, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD7, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD7, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD8, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD8, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD8, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD8, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD8, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD8, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD8, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD8, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD8, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD8, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD9, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD9, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD9, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD9, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD9, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD9, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD9, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD9, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD9, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD9, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD10, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD10, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD10, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD10, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD10, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD10, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD10, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD10, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD10, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD10, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD11, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD11, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD11, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD11, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD11, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD11, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD11, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD11, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD11, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD11, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD12, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD12, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD12, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD12, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD12, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD12, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD12, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD12, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD12, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD12, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD13, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD13, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD13, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD13, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD13, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD13, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD13, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD13, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD13, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD13, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD14, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD14, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD14, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD14, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD14, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD14, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD14, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD14, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD14, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD14, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD15, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD15, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD15, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD15, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD15, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD15, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD15, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD15, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD15, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD15, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;



	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 13,
		WDATA_WIDTH    => 2,
		RADDR_WIDTH    => 10,
		RDATA_WIDTH    => 16,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX2_RX16_VITAL of RAMB16KA_WX2_RX16 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX2_RX16_VITAL;



----- CELL RAMB16KA_WX2_RX32 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX2_RX32 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      WAD12                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC;
      RD2                             :	out   STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC;
      RD4                             :	out   STD_ULOGIC;
      RD5                             :	out   STD_ULOGIC;
      RD6                             :	out   STD_ULOGIC;
      RD7                             :	out   STD_ULOGIC;
      RD8                             :	out   STD_ULOGIC;
      RD9                             :	out   STD_ULOGIC;
      RD10                            :	out   STD_ULOGIC;
      RD11                            :	out   STD_ULOGIC;
      RD12                            :	out   STD_ULOGIC;
      RD13                            :	out   STD_ULOGIC;
      RD14                            :	out   STD_ULOGIC;
      RD15                            :	out   STD_ULOGIC;
      RD16                             :	out   STD_ULOGIC;
      RD17                             :	out   STD_ULOGIC;
      RD18                             :	out   STD_ULOGIC;
      RD19                             :	out   STD_ULOGIC;
      RD20                             :	out   STD_ULOGIC;
      RD21                             :	out   STD_ULOGIC;
      RD22                             :	out   STD_ULOGIC;
      RD23                             :	out   STD_ULOGIC;
      RD24                             :	out   STD_ULOGIC;
      RD25                             :	out   STD_ULOGIC;
      RD26                            :	out   STD_ULOGIC;
      RD27                            :	out   STD_ULOGIC;
      RD28                            :	out   STD_ULOGIC;
      RD29                            :	out   STD_ULOGIC;
      RD30                            :	out   STD_ULOGIC;
      RD31                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX2_RX32 : entity is FALSE;
end RAMB16KA_WX2_RX32;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX2_RX32 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 13;
		WDATA_WIDTH    : integer := 2;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';
      signal WAD12_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (1 downto 0);
 	signal WAD : std_logic_vector (12 downto 0);
	signal RAD : std_logic_vector (8 downto 0);
	signal RD  : std_logic_vector (31 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD1_ipd & WD0_ipd;
	WAD <= WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);

      end block;

      --------------------
      -- RAM16X1S Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd          : std_ulogic := 'X';
        variable RD11_zd          : std_ulogic := 'X';
        variable RD12_zd          : std_ulogic := 'X';
        variable RD13_zd          : std_ulogic := 'X';
        variable RD14_zd          : std_ulogic := 'X';
        variable RD15_zd          : std_ulogic := 'X';
        variable RD16_zd          : std_ulogic := 'X';
        variable RD17_zd          : std_ulogic := 'X';
        variable RD18_zd          : std_ulogic := 'X';
        variable RD19_zd          : std_ulogic := 'X';
        variable RD20_zd          : std_ulogic := 'X';
        variable RD21_zd          : std_ulogic := 'X';
        variable RD22_zd          : std_ulogic := 'X';
        variable RD23_zd          : std_ulogic := 'X';
        variable RD24_zd          : std_ulogic := 'X';
        variable RD25_zd          : std_ulogic := 'X';
        variable RD26_zd          : std_ulogic := 'X';
        variable RD27_zd          : std_ulogic := 'X';
        variable RD28_zd          : std_ulogic := 'X';
        variable RD29_zd          : std_ulogic := 'X';
        variable RD30_zd          : std_ulogic := 'X';
        variable RD31_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WAD12_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD4, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD4, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD4, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD4, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD4, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD4, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD4, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD4, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD4, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD5, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD5, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD5, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD5, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD5, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD5, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD5, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD5, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD5, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD6, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD6, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD6, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD6, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD6, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD6, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD6, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD6, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD6, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD7, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD7, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD7, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD7, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD7, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD7, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD7, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD7, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD7, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD8, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD8, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD8, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD8, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD8, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD8, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD8, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD8, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD8, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD9, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD9, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD9, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD9, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD9, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD9, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD9, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD9, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD9, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD10, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD10, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD10, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD10, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD10, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD10, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD10, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD10, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD10, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD11, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD11, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD11, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD11, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD11, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD11, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD11, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD11, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD11, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD12, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD12, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD12, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD12, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD12, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD12, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD12, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD12, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD12, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD13, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD13, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD13, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD13, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD13, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD13, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD13, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD13, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD13, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD14, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD14, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD14, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD14, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD14, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD14, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD14, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD14, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD14, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD15, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD15, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD15, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD15, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD15, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD15, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD15, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD15, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD15, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;

    VitalBehavior_RD16  : process
      variable RD16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD16_zd := RD(16);

    VitalPathDelay01 (
      OutSignal => RD16,
      GlitchData => O_GlitchData,
      OutSignalName => "RD16",
      OutTemp => RD16_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD16, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD16, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD16, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD16, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD16, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD16, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD16, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD16, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD16, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(16);
      end process;

    VitalBehavior_RD17  : process
      variable RD17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD17_zd := RD(17);

    VitalPathDelay01 (
      OutSignal => RD17,
      GlitchData => O_GlitchData,
      OutSignalName => "RD17",
      OutTemp => RD17_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD17, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD17, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD17, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD17, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD17, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD17, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD17, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD17, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD17, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(17);
      end process;

    VitalBehavior_RD18  : process
      variable RD18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD18_zd := RD(18);

    VitalPathDelay01 (
      OutSignal => RD18,
      GlitchData => O_GlitchData,
      OutSignalName => "RD18",
      OutTemp => RD18_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD18, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD18, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD18, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD18, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD18, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD18, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD18, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD18, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD18, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(18);
      end process;

    VitalBehavior_RD19  : process
      variable RD19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD19_zd := RD(19);

    VitalPathDelay01 (
      OutSignal => RD19,
      GlitchData => O_GlitchData,
      OutSignalName => "RD19",
      OutTemp => RD19_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD19, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD19, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD19, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD19, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD19, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD19, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD19, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD19, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD19, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(19);
      end process;

    VitalBehavior_RD20  : process
      variable RD20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD20_zd := RD(20);

    VitalPathDelay01 (
      OutSignal => RD20,
      GlitchData => O_GlitchData,
      OutSignalName => "RD20",
      OutTemp => RD20_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD20, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD20, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD20, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD20, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD20, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD20, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD20, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD20, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD20, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(20);
      end process;

    VitalBehavior_RD21  : process
      variable RD21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD21_zd := RD(21);

    VitalPathDelay01 (
      OutSignal => RD21,
      GlitchData => O_GlitchData,
      OutSignalName => "RD21",
      OutTemp => RD21_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD21, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD21, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD21, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD21, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD21, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD21, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD21, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD21, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD21, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(21);
      end process;

    VitalBehavior_RD22  : process
      variable RD22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD22_zd := RD(22);

    VitalPathDelay01 (
      OutSignal => RD22,
      GlitchData => O_GlitchData,
      OutSignalName => "RD22",
      OutTemp => RD22_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD22, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD22, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD22, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD22, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD22, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD22, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD22, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD22, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD22, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(22);
      end process;

    VitalBehavior_RD23  : process
      variable RD23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD23_zd := RD(23);

    VitalPathDelay01 (
      OutSignal => RD23,
      GlitchData => O_GlitchData,
      OutSignalName => "RD23",
      OutTemp => RD23_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD23, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD23, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD23, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD23, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD23, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD23, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD23, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD23, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD23, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(23);
      end process;

    VitalBehavior_RD24  : process
      variable RD24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD24_zd := RD(24);

    VitalPathDelay01 (
      OutSignal => RD24,
      GlitchData => O_GlitchData,
      OutSignalName => "RD24",
      OutTemp => RD24_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD24, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD24, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD24, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD24, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD24, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD24, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD24, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD24, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD24, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(24);
      end process;

    VitalBehavior_RD25  : process
      variable RD25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD25_zd := RD(25);

    VitalPathDelay01 (
      OutSignal => RD25,
      GlitchData => O_GlitchData,
      OutSignalName => "RD25",
      OutTemp => RD25_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD25, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD25, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD25, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD25, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD25, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD25, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD25, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD25, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD25, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(25);
      end process;

    VitalBehavior_RD26  : process
      variable RD26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD26_zd := RD(26);

    VitalPathDelay01 (
      OutSignal => RD26,
      GlitchData => O_GlitchData,
      OutSignalName => "RD26",
      OutTemp => RD26_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD26, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD26, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD26, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD26, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD26, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD26, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD26, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD26, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD26, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(26);
      end process;

    VitalBehavior_RD27  : process
      variable RD27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD27_zd := RD(27);

    VitalPathDelay01 (
      OutSignal => RD27,
      GlitchData => O_GlitchData,
      OutSignalName => "RD27",
      OutTemp => RD27_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD27, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD27, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD27, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD27, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD27, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD27, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD27, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD27, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD27, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(27);
      end process;

    VitalBehavior_RD28  : process
      variable RD28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD28_zd := RD(28);

    VitalPathDelay01 (
      OutSignal => RD28,
      GlitchData => O_GlitchData,
      OutSignalName => "RD28",
      OutTemp => RD28_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD28, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD28, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD28, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD28, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD28, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD28, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD28, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD28, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD28, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(28);
      end process;

    VitalBehavior_RD29  : process
      variable RD29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD29_zd := RD(29);

    VitalPathDelay01 (
      OutSignal => RD29,
      GlitchData => O_GlitchData,
      OutSignalName => "RD29",
      OutTemp => RD29_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD29, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD29, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD29, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD29, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD29, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD29, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD29, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD29, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD29, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(29);
      end process;

    VitalBehavior_RD30  : process
      variable RD30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD30_zd := RD(30);

    VitalPathDelay01 (
      OutSignal => RD30,
      GlitchData => O_GlitchData,
      OutSignalName => "RD30",
      OutTemp => RD30_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD30, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD30, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD30, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD30, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD30, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD30, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD30, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD30, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD30, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(30);
      end process;

    VitalBehavior_RD31  : process
      variable RD31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD31_zd := RD(31);

    VitalPathDelay01 (
      OutSignal => RD31,
      GlitchData => O_GlitchData,
      OutSignalName => "RD31",
      OutTemp => RD31_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD31, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD31, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD31, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD31, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD31, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD31, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD31, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD31, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD31, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(31);
      end process;



	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 13,
		WDATA_WIDTH    => 2,
		RADDR_WIDTH    => 9,
		RDATA_WIDTH    => 32,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX2_RX32_VITAL of RAMB16KA_WX2_RX32 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX2_RX32_VITAL;



----- CELL RAMB16KA_WX4_RX4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX4_RX4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD2                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD2                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD3                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD3                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RAD11                           :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC;
      RD2                             :	out   STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX4_RX4 : entity is FALSE;
end RAMB16KA_WX4_RX4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX4_RX4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 12;
		WDATA_WIDTH    : integer := 4;
		RADDR_WIDTH    : integer := 12;
		RDATA_WIDTH    : integer := 4;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';
      signal RAD11_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (3 downto 0);
 	signal WAD : std_logic_vector (11 downto 0);
	signal RAD : std_logic_vector (11 downto 0);
	signal RD  : std_logic_vector (3 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);

      end block;

      --------------------
      -- RAMB16KA_WX4_RX4 Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX4_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WD0_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD0, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD1, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD1, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD2, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD2, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD2, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD3, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD3, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD3, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;



	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 12,
		WDATA_WIDTH    => 4,
		RADDR_WIDTH    => 12,
		RDATA_WIDTH    => 4,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX4_RX4_VITAL of RAMB16KA_WX4_RX4 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX4_RX4_VITAL;



----- CELL RAMB16KA_WX4_RX8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX4_RX8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD2                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD3                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD4                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD5                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD6                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD7                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC;
      RD2                             :	out   STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC;
      RD4                             :	out   STD_ULOGIC;
      RD5                             :	out   STD_ULOGIC;
      RD6                             :	out   STD_ULOGIC;
      RD7                             :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX4_RX8 : entity is FALSE;
end RAMB16KA_WX4_RX8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX4_RX8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 12;
		WDATA_WIDTH    : integer := 4;
		RADDR_WIDTH    : integer := 11;
		RDATA_WIDTH    : integer := 8;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';
      signal RAD11_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (3 downto 0);
 	signal WAD : std_logic_vector (11 downto 0);
	signal RAD : std_logic_vector (10 downto 0);
	signal RD  : std_logic_vector (7 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);

      end block;

      --------------------
      -- RAMB16KA_WX4_RX8 Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WD0_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD1, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD2, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD2, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD3, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD3, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD4, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD4, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD4, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD4, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD4, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD4, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD4, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD4, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD4, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD4, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD4, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD5, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD5, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD5, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD5, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD5, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD5, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD5, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD5, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD5, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD5, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD5, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD6, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD6, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD6, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD6, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD6, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD6, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD6, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD6, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD6, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD6, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD6, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD7, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD7, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD7, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD7, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD7, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD7, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD7, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD7, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD7, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD7, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD7, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;



	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 12,
		WDATA_WIDTH    => 4,
		RADDR_WIDTH    => 11,
		RDATA_WIDTH    => 8,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX4_RX8_VITAL of RAMB16KA_WX4_RX8 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX4_RX8_VITAL;



----- CELL RAMB16KA_WX4_RX16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX4_RX16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC;
      RD2                             :	out   STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC;
      RD4                             :	out   STD_ULOGIC;
      RD5                             :	out   STD_ULOGIC;
      RD6                             :	out   STD_ULOGIC;
      RD7                             :	out   STD_ULOGIC;
      RD8                             :	out   STD_ULOGIC;
      RD9                             :	out   STD_ULOGIC;
      RD10                            :	out   STD_ULOGIC;
      RD11                            :	out   STD_ULOGIC;
      RD12                            :	out   STD_ULOGIC;
      RD13                            :	out   STD_ULOGIC;
      RD14                            :	out   STD_ULOGIC;
      RD15                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX4_RX16 : entity is FALSE;
end RAMB16KA_WX4_RX16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX4_RX16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 12;
		WDATA_WIDTH    : integer := 4;
		RADDR_WIDTH    : integer := 10;
		RDATA_WIDTH    : integer := 16;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';
      signal RAD11_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (3 downto 0);
 	signal WAD : std_logic_vector (11 downto 0);
	signal RAD : std_logic_vector (9 downto 0);
	signal RD  : std_logic_vector (15 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;


  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);

      end block;

      --------------------
      -- RAMB16KA_WX4_RX16 Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd          : std_ulogic := 'X';
        variable RD11_zd          : std_ulogic := 'X';
        variable RD12_zd          : std_ulogic := 'X';
        variable RD13_zd          : std_ulogic := 'X';
        variable RD14_zd          : std_ulogic := 'X';
        variable RD15_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WD0_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD2, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD3, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD4, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD4, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD4, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD4, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD4, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD4, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD4, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD4, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD4, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD4, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD5, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD5, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD5, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD5, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD5, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD5, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD5, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD5, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD5, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD5, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD6, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD6, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD6, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD6, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD6, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD6, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD6, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD6, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD6, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD6, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD7, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD7, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD7, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD7, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD7, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD7, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD7, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD7, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD7, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD7, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD8, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD8, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD8, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD8, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD8, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD8, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD8, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD8, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD8, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD8, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD9, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD9, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD9, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD9, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD9, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD9, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD9, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD9, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD9, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD9, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD10, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD10, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD10, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD10, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD10, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD10, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD10, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD10, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD10, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD10, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD11, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD11, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD11, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD11, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD11, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD11, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD11, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD11, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD11, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD11, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD12, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD12, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD12, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD12, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD12, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD12, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD12, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD12, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD12, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD12, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD13, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD13, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD13, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD13, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD13, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD13, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD13, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD13, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD13, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD13, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD14, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD14, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD14, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD14, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD14, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD14, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD14, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD14, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD14, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD14, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD15, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD15, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD15, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD15, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD15, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD15, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD15, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD15, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD15, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD15, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;



	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 12,
		WDATA_WIDTH    => 4,
		RADDR_WIDTH    => 10,
		RDATA_WIDTH    => 16,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX4_RX16_VITAL of RAMB16KA_WX4_RX16 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX4_RX16_VITAL;



--- CELL RAMB16KA_WX4_RX32 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX4_RX32 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD23:	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      WAD11                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC;
      RD2                             :	out   STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC;
      RD4                             :	out   STD_ULOGIC;
      RD5                             :	out   STD_ULOGIC;
      RD6                             :	out   STD_ULOGIC;
      RD7                             :	out   STD_ULOGIC;
      RD8                             :	out   STD_ULOGIC;
      RD9                             :	out   STD_ULOGIC;
      RD10                            :	out   STD_ULOGIC;
      RD11                            :	out   STD_ULOGIC;
      RD12                            :	out   STD_ULOGIC;
      RD13                            :	out   STD_ULOGIC;
      RD14                            :	out   STD_ULOGIC;
      RD15                            :	out   STD_ULOGIC;
      RD16                             :	out   STD_ULOGIC;
      RD17                             :	out   STD_ULOGIC;
      RD18                             :	out   STD_ULOGIC;
      RD19                             :	out   STD_ULOGIC;
      RD20                             :	out   STD_ULOGIC;
      RD21                             :	out   STD_ULOGIC;
      RD22                             :	out   STD_ULOGIC;
      RD23                             :	out   STD_ULOGIC;
      RD24                             :	out   STD_ULOGIC;
      RD25                             :	out   STD_ULOGIC;
      RD26                            :	out   STD_ULOGIC;
      RD27                            :	out   STD_ULOGIC;
      RD28                            :	out   STD_ULOGIC;
      RD29                            :	out   STD_ULOGIC;
      RD30                            :	out   STD_ULOGIC;
      RD31                            :	out   STD_ULOGIC);


attribute VITAL_LEVEL0 of RAMB16KA_WX4_RX32 : entity is FALSE;
end RAMB16KA_WX4_RX32;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX4_RX32 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 12;
		WDATA_WIDTH    : integer := 4;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';
      signal WAD11_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';
      signal RAD11_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (3 downto 0);
 	signal WAD : std_logic_vector (11 downto 0);
	signal RAD : std_logic_vector (8 downto 0);
	signal RD  : std_logic_vector (31 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);

begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);

      end block;

      --------------------
      -- RAMB16KA_WX4_RX32 Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd          : std_ulogic := 'X';
        variable RD11_zd          : std_ulogic := 'X';
        variable RD12_zd          : std_ulogic := 'X';
        variable RD13_zd          : std_ulogic := 'X';
        variable RD14_zd          : std_ulogic := 'X';
        variable RD15_zd          : std_ulogic := 'X';
        variable RD16_zd          : std_ulogic := 'X';
        variable RD17_zd          : std_ulogic := 'X';
        variable RD18_zd          : std_ulogic := 'X';
        variable RD19_zd          : std_ulogic := 'X';
        variable RD20_zd          : std_ulogic := 'X';
        variable RD21_zd          : std_ulogic := 'X';
        variable RD22_zd          : std_ulogic := 'X';
        variable RD23_zd          : std_ulogic := 'X';
        variable RD24_zd          : std_ulogic := 'X';
        variable RD25_zd          : std_ulogic := 'X';
        variable RD26_zd          : std_ulogic := 'X';
        variable RD27_zd          : std_ulogic := 'X';
        variable RD28_zd          : std_ulogic := 'X';
        variable RD29_zd          : std_ulogic := 'X';
        variable RD30_zd          : std_ulogic := 'X';
        variable RD31_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WAD11_WCLK_posedge or 
                 Tviol_WD0_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD4, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD4, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD4, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD4, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD4, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD4, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD4, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD4, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD4, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD5, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD5, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD5, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD5, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD5, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD5, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD5, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD5, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD5, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD6, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD6, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD6, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD6, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD6, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD6, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD6, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD6, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD6, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD7, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD7, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD7, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD7, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD7, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD7, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD7, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD7, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD7, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD8, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD8, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD8, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD8, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD8, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD8, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD8, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD8, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD8, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD9, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD9, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD9, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD9, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD9, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD9, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD9, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD9, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD9, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD10, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD10, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD10, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD10, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD10, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD10, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD10, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD10, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD10, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD11, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD11, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD11, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD11, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD11, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD11, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD11, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD11, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD11, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD12, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD12, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD12, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD12, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD12, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD12, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD12, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD12, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD12, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD13, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD13, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD13, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD13, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD13, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD13, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD13, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD13, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD13, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD14, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD14, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD14, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD14, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD14, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD14, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD14, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD14, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD14, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD15, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD15, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD15, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD15, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD15, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD15, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD15, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD15, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD15, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;

    VitalBehavior_RD16  : process
      variable RD16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD16_zd := RD(16);

    VitalPathDelay01 (
      OutSignal => RD16,
      GlitchData => O_GlitchData,
      OutSignalName => "RD16",
      OutTemp => RD16_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD16, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD16, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD16, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD16, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD16, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD16, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD16, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD16, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD16, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(16);
      end process;

    VitalBehavior_RD17  : process
      variable RD17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD17_zd := RD(17);

    VitalPathDelay01 (
      OutSignal => RD17,
      GlitchData => O_GlitchData,
      OutSignalName => "RD17",
      OutTemp => RD17_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD17, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD17, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD17, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD17, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD17, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD17, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD17, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD17, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD17, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(17);
      end process;

    VitalBehavior_RD18  : process
      variable RD18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD18_zd := RD(18);

    VitalPathDelay01 (
      OutSignal => RD18,
      GlitchData => O_GlitchData,
      OutSignalName => "RD18",
      OutTemp => RD18_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD18, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD18, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD18, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD18, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD18, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD18, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD18, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD18, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD18, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(18);
      end process;

    VitalBehavior_RD19  : process
      variable RD19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD19_zd := RD(19);

    VitalPathDelay01 (
      OutSignal => RD19,
      GlitchData => O_GlitchData,
      OutSignalName => "RD19",
      OutTemp => RD19_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD19, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD19, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD19, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD19, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD19, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD19, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD19, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD19, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD19, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(19);
      end process;

    VitalBehavior_RD20  : process
      variable RD20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD20_zd := RD(20);

    VitalPathDelay01 (
      OutSignal => RD20,
      GlitchData => O_GlitchData,
      OutSignalName => "RD20",
      OutTemp => RD20_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD20, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD20, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD20, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD20, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD20, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD20, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD20, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD20, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD20, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(20);
      end process;

    VitalBehavior_RD21  : process
      variable RD21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD21_zd := RD(21);

    VitalPathDelay01 (
      OutSignal => RD21,
      GlitchData => O_GlitchData,
      OutSignalName => "RD21",
      OutTemp => RD21_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD21, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD21, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD21, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD21, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD21, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD21, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD21, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD21, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD21, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(21);
      end process;

    VitalBehavior_RD22  : process
      variable RD22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD22_zd := RD(22);

    VitalPathDelay01 (
      OutSignal => RD22,
      GlitchData => O_GlitchData,
      OutSignalName => "RD22",
      OutTemp => RD22_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD22, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD22, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD22, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD22, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD22, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD22, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD22, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD22, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD22, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(22);
      end process;

    VitalBehavior_RD23  : process
      variable RD23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD23_zd := RD(23);

    VitalPathDelay01 (
      OutSignal => RD23,
      GlitchData => O_GlitchData,
      OutSignalName => "RD23",
      OutTemp => RD23_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD23, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD23, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD23, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD23, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD23, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD23, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD23, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD23, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD23, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(23);
      end process;

    VitalBehavior_RD24  : process
      variable RD24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD24_zd := RD(24);

    VitalPathDelay01 (
      OutSignal => RD24,
      GlitchData => O_GlitchData,
      OutSignalName => "RD24",
      OutTemp => RD24_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD24, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD24, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD24, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD24, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD24, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD24, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD24, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD24, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD24, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(24);
      end process;

    VitalBehavior_RD25  : process
      variable RD25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD25_zd := RD(25);

    VitalPathDelay01 (
      OutSignal => RD25,
      GlitchData => O_GlitchData,
      OutSignalName => "RD25",
      OutTemp => RD25_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD25, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD25, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD25, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD25, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD25, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD25, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD25, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD25, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD25, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(25);
      end process;

    VitalBehavior_RD26  : process
      variable RD26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD26_zd := RD(26);

    VitalPathDelay01 (
      OutSignal => RD26,
      GlitchData => O_GlitchData,
      OutSignalName => "RD26",
      OutTemp => RD26_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD26, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD26, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD26, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD26, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD26, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD26, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD26, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD26, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD26, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(26);
      end process;

    VitalBehavior_RD27  : process
      variable RD27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD27_zd := RD(27);

    VitalPathDelay01 (
      OutSignal => RD27,
      GlitchData => O_GlitchData,
      OutSignalName => "RD27",
      OutTemp => RD27_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD27, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD27, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD27, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD27, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD27, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD27, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD27, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD27, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD27, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(27);
      end process;

    VitalBehavior_RD28  : process
      variable RD28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD28_zd := RD(28);

    VitalPathDelay01 (
      OutSignal => RD28,
      GlitchData => O_GlitchData,
      OutSignalName => "RD28",
      OutTemp => RD28_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD28, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD28, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD28, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD28, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD28, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD28, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD28, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD28, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD28, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(28);
      end process;

    VitalBehavior_RD29  : process
      variable RD29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD29_zd := RD(29);

    VitalPathDelay01 (
      OutSignal => RD29,
      GlitchData => O_GlitchData,
      OutSignalName => "RD29",
      OutTemp => RD29_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD29, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD29, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD29, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD29, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD29, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD29, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD29, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD29, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD29, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(29);
      end process;

    VitalBehavior_RD30  : process
      variable RD30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD30_zd := RD(30);

    VitalPathDelay01 (
      OutSignal => RD30,
      GlitchData => O_GlitchData,
      OutSignalName => "RD30",
      OutTemp => RD30_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD30, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD30, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD30, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD30, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD30, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD30, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD30, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD30, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD30, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(30);
      end process;

    VitalBehavior_RD31  : process
      variable RD31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD31_zd := RD(31);

    VitalPathDelay01 (
      OutSignal => RD31,
      GlitchData => O_GlitchData,
      OutSignalName => "RD31",
      OutTemp => RD31_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD31, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD31, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD31, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD31, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD31, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD31, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD31, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD31, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD31, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(31);
      end process;



	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 12,
		WDATA_WIDTH    => 4,
		RADDR_WIDTH    => 9,
		RDATA_WIDTH    => 32,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX4_RX32_VITAL of RAMB16KA_WX4_RX32 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX4_RX32_VITAL;



----- CELL RAMB16KA_WX8_RX8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX8_RX8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD2                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD3                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD4                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD5                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD6                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD7                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                           :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC;
      RD2                             :	out   STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC;
      RD4                             :	out   STD_ULOGIC;
      RD5                             :	out   STD_ULOGIC;
      RD6                             :	out   STD_ULOGIC;
      RD7                             :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX8_RX8 : entity is FALSE;
end RAMB16KA_WX8_RX8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX8_RX8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 11;
		WDATA_WIDTH    : integer := 8;
		RADDR_WIDTH    : integer := 11;
		RDATA_WIDTH    : integer := 8;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (7 downto 0);
 	signal WAD : std_logic_vector (10 downto 0);
	signal RAD : std_logic_vector (10 downto 0);
	signal RD  : std_logic_vector (7 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 
	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;


  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);

      end block;

      --------------------
      -- RAMB16KA_WX8_RX8 Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX8_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD1, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD2, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD2, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD3, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD3, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD4, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD4, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD4, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD4, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD4, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD4, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD4, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD4, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD4, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD4, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD4, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD5, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD5, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD5, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD5, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD5, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD5, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD5, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD5, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD5, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD5, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD5, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD6, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD6, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD6, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD6, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD6, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD6, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD6, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD6, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD6, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD6, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD6, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD7, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD7, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD7, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD7, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD7, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD7, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD7, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD7, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD7, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD7, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD7, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;



	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 11,
		WDATA_WIDTH    => 8,
		RADDR_WIDTH    => 11,
		RDATA_WIDTH    => 8,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map(
		WCEN => WCEN ,
		WCLK => WCLK ,
		WE   => WE ,
		WCS  => WCS,
		RST  => RST ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX8_RX8_VITAL of RAMB16KA_WX8_RX8 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX8_RX8_VITAL;



----- CELL RAMB16KA_WX8_RX16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX8_RX16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC;
      RD2                             :	out   STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC;
      RD4                             :	out   STD_ULOGIC;
      RD5                             :	out   STD_ULOGIC;
      RD6                             :	out   STD_ULOGIC;
      RD7                             :	out   STD_ULOGIC;
      RD8                             :	out   STD_ULOGIC;
      RD9                             :	out   STD_ULOGIC;
      RD10                            :	out   STD_ULOGIC;
      RD11                            :	out   STD_ULOGIC;
      RD12                            :	out   STD_ULOGIC;
      RD13                            :	out   STD_ULOGIC;
      RD14                            :	out   STD_ULOGIC;
      RD15                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX8_RX16 : entity is FALSE;
end RAMB16KA_WX8_RX16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX8_RX16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 11;
		WDATA_WIDTH    : integer := 8;
		RADDR_WIDTH    : integer := 10;
		RDATA_WIDTH    : integer := 16;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (7 downto 0);
 	signal WAD : std_logic_vector (10 downto 0);
	signal RAD : std_logic_vector (9 downto 0);
	signal RD  : std_logic_vector (15 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);

      end block;

      --------------------
      -- RAMB16KA_WX8_RX16 Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd          : std_ulogic := 'X';
        variable RD11_zd          : std_ulogic := 'X';
        variable RD12_zd          : std_ulogic := 'X';
        variable RD13_zd          : std_ulogic := 'X';
        variable RD14_zd          : std_ulogic := 'X';
        variable RD15_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD2, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD3, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD4, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD4, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD4, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD4, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD4, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD4, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD4, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD4, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD4, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD4, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD5, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD5, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD5, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD5, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD5, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD5, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD5, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD5, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD5, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD5, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD6, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD6, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD6, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD6, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD6, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD6, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD6, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD6, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD6, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD6, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD7, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD7, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD7, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD7, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD7, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD7, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD7, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD7, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD7, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD7, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD8, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD8, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD8, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD8, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD8, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD8, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD8, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD8, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD8, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD8, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD9, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD9, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD9, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD9, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD9, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD9, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD9, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD9, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD9, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD9, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD10, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD10, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD10, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD10, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD10, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD10, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD10, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD10, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD10, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD10, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD11, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD11, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD11, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD11, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD11, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD11, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD11, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD11, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD11, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD11, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD12, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD12, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD12, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD12, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD12, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD12, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD12, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD12, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD12, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD12, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD13, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD13, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD13, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD13, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD13, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD13, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD13, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD13, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD13, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD13, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD14, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD14, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD14, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD14, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD14, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD14, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD14, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD14, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD14, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD14, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD15, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD15, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD15, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD15, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD15, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD15, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD15, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD15, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD15, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD15, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;



	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 11,
		WDATA_WIDTH    => 8,
		RADDR_WIDTH    => 10,
		RDATA_WIDTH    => 16,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX8_RX16_VITAL of RAMB16KA_WX8_RX16 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX8_RX16_VITAL;



----- CELL RAMB16KA_WX8_RX32 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX8_RX32 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                           :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC;
      RD2                             :	out   STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC;
      RD4                             :	out   STD_ULOGIC;
      RD5                             :	out   STD_ULOGIC;
      RD6                             :	out   STD_ULOGIC;
      RD7                             :	out   STD_ULOGIC;
      RD8                             :	out   STD_ULOGIC;
      RD9                             :	out   STD_ULOGIC;
      RD10                            :	out   STD_ULOGIC;
      RD11                            :	out   STD_ULOGIC;
      RD12                            :	out   STD_ULOGIC;
      RD13                            :	out   STD_ULOGIC;
      RD14                            :	out   STD_ULOGIC;
      RD15                            :	out   STD_ULOGIC;
      RD16                             :	out   STD_ULOGIC;
      RD17                             :	out   STD_ULOGIC;
      RD18                             :	out   STD_ULOGIC;
      RD19                             :	out   STD_ULOGIC;
      RD20                             :	out   STD_ULOGIC;
      RD21                             :	out   STD_ULOGIC;
      RD22                             :	out   STD_ULOGIC;
      RD23                             :	out   STD_ULOGIC;
      RD24                             :	out   STD_ULOGIC;
      RD25                             :	out   STD_ULOGIC;
      RD26                            :	out   STD_ULOGIC;
      RD27                            :	out   STD_ULOGIC;
      RD28                            :	out   STD_ULOGIC;
      RD29                            :	out   STD_ULOGIC;
      RD30                            :	out   STD_ULOGIC;
      RD31                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX8_RX32 : entity is FALSE;
end RAMB16KA_WX8_RX32;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX8_RX32 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 11;
		WDATA_WIDTH    : integer := 8;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd     : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd     : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (7 downto 0);
 	signal WAD : std_logic_vector (10 downto 0);
	signal RAD : std_logic_vector (8 downto 0);
	signal RD  : std_logic_vector (31 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);


      end block;

      --------------------
      -- RAMB16KA_WX8_RX32 Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd          : std_ulogic := 'X';
        variable RD11_zd          : std_ulogic := 'X';
        variable RD12_zd          : std_ulogic := 'X';
        variable RD13_zd          : std_ulogic := 'X';
        variable RD14_zd          : std_ulogic := 'X';
        variable RD15_zd          : std_ulogic := 'X';
        variable RD16_zd          : std_ulogic := 'X';
        variable RD17_zd          : std_ulogic := 'X';
        variable RD18_zd          : std_ulogic := 'X';
        variable RD19_zd          : std_ulogic := 'X';
        variable RD20_zd          : std_ulogic := 'X';
        variable RD21_zd          : std_ulogic := 'X';
        variable RD22_zd          : std_ulogic := 'X';
        variable RD23_zd          : std_ulogic := 'X';
        variable RD24_zd          : std_ulogic := 'X';
        variable RD25_zd          : std_ulogic := 'X';
        variable RD26_zd          : std_ulogic := 'X';
        variable RD27_zd          : std_ulogic := 'X';
        variable RD28_zd          : std_ulogic := 'X';
        variable RD29_zd          : std_ulogic := 'X';
        variable RD30_zd          : std_ulogic := 'X';
        variable RD31_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WAD10_WCLK_posedge or Tviol_WD0_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD4, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD4, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD4, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD4, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD4, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD4, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD4, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD4, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD4, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD5, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD5, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD5, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD5, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD5, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD5, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD5, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD5, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD5, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD6, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD6, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD6, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD6, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD6, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD6, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD6, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD6, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD6, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD7, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD7, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD7, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD7, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD7, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD7, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD7, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD7, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD7, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD8, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD8, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD8, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD8, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD8, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD8, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD8, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD8, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD8, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD9, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD9, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD9, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD9, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD9, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD9, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD9, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD9, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD9, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD10, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD10, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD10, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD10, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD10, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD10, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD10, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD10, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD10, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD11, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD11, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD11, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD11, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD11, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD11, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD11, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD11, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD11, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD12, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD12, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD12, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD12, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD12, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD12, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD12, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD12, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD12, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD13, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD13, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD13, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD13, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD13, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD13, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD13, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD13, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD13, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD14, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD14, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD14, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD14, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD14, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD14, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD14, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD14, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD14, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD15, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD15, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD15, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD15, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD15, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD15, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD15, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD15, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD15, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;

    VitalBehavior_RD16  : process
      variable RD16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD16_zd := RD(16);

    VitalPathDelay01 (
      OutSignal => RD16,
      GlitchData => O_GlitchData,
      OutSignalName => "RD16",
      OutTemp => RD16_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD16, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD16, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD16, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD16, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD16, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD16, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD16, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD16, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD16, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(16);
      end process;

    VitalBehavior_RD17  : process
      variable RD17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD17_zd := RD(17);

    VitalPathDelay01 (
      OutSignal => RD17,
      GlitchData => O_GlitchData,
      OutSignalName => "RD17",
      OutTemp => RD17_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD17, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD17, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD17, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD17, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD17, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD17, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD17, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD17, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD17, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(17);
      end process;

    VitalBehavior_RD18  : process
      variable RD18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD18_zd := RD(18);

    VitalPathDelay01 (
      OutSignal => RD18,
      GlitchData => O_GlitchData,
      OutSignalName => "RD18",
      OutTemp => RD18_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD18, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD18, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD18, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD18, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD18, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD18, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD18, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD18, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD18, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(18);
      end process;

    VitalBehavior_RD19  : process
      variable RD19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD19_zd := RD(19);

    VitalPathDelay01 (
      OutSignal => RD19,
      GlitchData => O_GlitchData,
      OutSignalName => "RD19",
      OutTemp => RD19_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD19, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD19, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD19, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD19, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD19, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD19, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD19, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD19, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD19, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(19);
      end process;

    VitalBehavior_RD20  : process
      variable RD20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD20_zd := RD(20);

    VitalPathDelay01 (
      OutSignal => RD20,
      GlitchData => O_GlitchData,
      OutSignalName => "RD20",
      OutTemp => RD20_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD20, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD20, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD20, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD20, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD20, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD20, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD20, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD20, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD20, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(20);
      end process;

    VitalBehavior_RD21  : process
      variable RD21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD21_zd := RD(21);

    VitalPathDelay01 (
      OutSignal => RD21,
      GlitchData => O_GlitchData,
      OutSignalName => "RD21",
      OutTemp => RD21_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD21, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD21, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD21, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD21, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD21, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD21, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD21, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD21, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD21, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(21);
      end process;

    VitalBehavior_RD22  : process
      variable RD22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD22_zd := RD(22);

    VitalPathDelay01 (
      OutSignal => RD22,
      GlitchData => O_GlitchData,
      OutSignalName => "RD22",
      OutTemp => RD22_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD22, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD22, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD22, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD22, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD22, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD22, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD22, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD22, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD22, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(22);
      end process;

    VitalBehavior_RD23  : process
      variable RD23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD23_zd := RD(23);

    VitalPathDelay01 (
      OutSignal => RD23,
      GlitchData => O_GlitchData,
      OutSignalName => "RD23",
      OutTemp => RD23_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD23, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD23, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD23, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD23, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD23, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD23, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD23, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD23, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD23, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(23);
      end process;

    VitalBehavior_RD24  : process
      variable RD24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD24_zd := RD(24);

    VitalPathDelay01 (
      OutSignal => RD24,
      GlitchData => O_GlitchData,
      OutSignalName => "RD24",
      OutTemp => RD24_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD24, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD24, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD24, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD24, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD24, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD24, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD24, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD24, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD24, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(24);
      end process;

    VitalBehavior_RD25  : process
      variable RD25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD25_zd := RD(25);

    VitalPathDelay01 (
      OutSignal => RD25,
      GlitchData => O_GlitchData,
      OutSignalName => "RD25",
      OutTemp => RD25_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD25, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD25, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD25, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD25, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD25, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD25, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD25, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD25, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD25, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(25);
      end process;

    VitalBehavior_RD26  : process
      variable RD26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD26_zd := RD(26);

    VitalPathDelay01 (
      OutSignal => RD26,
      GlitchData => O_GlitchData,
      OutSignalName => "RD26",
      OutTemp => RD26_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD26, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD26, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD26, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD26, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD26, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD26, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD26, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD26, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD26, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(26);
      end process;

    VitalBehavior_RD27  : process
      variable RD27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD27_zd := RD(27);

    VitalPathDelay01 (
      OutSignal => RD27,
      GlitchData => O_GlitchData,
      OutSignalName => "RD27",
      OutTemp => RD27_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD27, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD27, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD27, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD27, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD27, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD27, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD27, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD27, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD27, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(27);
      end process;

    VitalBehavior_RD28  : process
      variable RD28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD28_zd := RD(28);

    VitalPathDelay01 (
      OutSignal => RD28,
      GlitchData => O_GlitchData,
      OutSignalName => "RD28",
      OutTemp => RD28_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD28, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD28, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD28, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD28, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD28, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD28, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD28, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD28, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD28, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(28);
      end process;

    VitalBehavior_RD29  : process
      variable RD29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD29_zd := RD(29);

    VitalPathDelay01 (
      OutSignal => RD29,
      GlitchData => O_GlitchData,
      OutSignalName => "RD29",
      OutTemp => RD29_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD29, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD29, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD29, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD29, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD29, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD29, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD29, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD29, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD29, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(29);
      end process;

    VitalBehavior_RD30  : process
      variable RD30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD30_zd := RD(30);

    VitalPathDelay01 (
      OutSignal => RD30,
      GlitchData => O_GlitchData,
      OutSignalName => "RD30",
      OutTemp => RD30_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD30, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD30, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD30, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD30, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD30, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD30, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD30, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD30, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD30, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(30);
      end process;

    VitalBehavior_RD31  : process
      variable RD31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD31_zd := RD(31);

    VitalPathDelay01 (
      OutSignal => RD31,
      GlitchData => O_GlitchData,
      OutSignalName => "RD31",
      OutTemp => RD31_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD31, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD31, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD31, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD31, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD31, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD31, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD31, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD31, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD31, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(31);
      end process;



	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 11,
		WDATA_WIDTH    => 8,
		RADDR_WIDTH    => 9,
		RDATA_WIDTH    => 32,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX8_RX32_VITAL of RAMB16KA_WX8_RX32 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX8_RX32_VITAL;



----- CELL RAMB16KA_WX16_RX16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX16_RX16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC;
      RD2                             :	out   STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC;
      RD4                             :	out   STD_ULOGIC;
      RD5                             :	out   STD_ULOGIC;
      RD6                             :	out   STD_ULOGIC;
      RD7                             :	out   STD_ULOGIC;
      RD8                             :	out   STD_ULOGIC;
      RD9                             :	out   STD_ULOGIC;
      RD10                            :	out   STD_ULOGIC;
      RD11                            :	out   STD_ULOGIC;
      RD12                            :	out   STD_ULOGIC;
      RD13                            :	out   STD_ULOGIC;
      RD14                            :	out   STD_ULOGIC;
      RD15                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX16_RX16 : entity is FALSE;
end RAMB16KA_WX16_RX16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX16_RX16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 10;
		RDATA_WIDTH    : integer := 16;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';

      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (15 downto 0);
 	signal WAD : std_logic_vector (9 downto 0);
	signal RAD : std_logic_vector (9 downto 0);
	signal RD  : std_logic_vector (15 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;


  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);

      end block;

      --------------------
      -- RAMB16KA_WX16_RX16 Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd          : std_ulogic := 'X';
        variable RD11_zd          : std_ulogic := 'X';
        variable RD12_zd          : std_ulogic := 'X';
        variable RD13_zd          : std_ulogic := 'X';
        variable RD14_zd          : std_ulogic := 'X';
        variable RD15_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WD0_WCLK_posedge or Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or Tviol_WD15_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD2, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD3, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD4, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD4, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD4, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD4, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD4, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD4, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD4, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD4, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD4, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD4, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD5, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD5, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD5, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD5, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD5, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD5, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD5, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD5, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD5, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD5, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD6, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD6, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD6, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD6, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD6, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD6, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD6, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD6, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD6, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD6, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD7, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD7, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD7, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD7, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD7, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD7, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD7, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD7, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD7, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD7, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD8, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD8, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD8, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD8, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD8, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD8, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD8, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD8, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD8, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD8, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD9, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD9, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD9, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD9, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD9, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD9, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD9, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD9, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD9, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD9, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD10, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD10, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD10, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD10, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD10, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD10, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD10, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD10, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD10, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD10, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD11, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD11, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD11, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD11, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD11, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD11, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD11, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD11, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD11, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD11, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD12, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD12, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD12, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD12, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD12, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD12, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD12, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD12, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD12, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD12, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD13, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD13, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD13, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD13, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD13, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD13, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD13, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD13, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD13, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD13, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD14, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD14, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD14, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD14, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD14, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD14, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD14, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD14, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD14, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD14, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD15, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD15, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD15, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD15, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD15, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD15, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD15, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD15, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD15, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD15, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;



	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 10,
		WDATA_WIDTH    => 16,
		RADDR_WIDTH    => 10,
		RDATA_WIDTH    => 16,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX16_RX16_VITAL of RAMB16KA_WX16_RX16 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX16_RX16_VITAL;



----- CELL RAMB16KA_WX16_RX32-----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX16_RX32 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC;
      RD2                             :	out   STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC;
      RD4                             :	out   STD_ULOGIC;
      RD5                             :	out   STD_ULOGIC;
      RD6                             :	out   STD_ULOGIC;
      RD7                             :	out   STD_ULOGIC;
      RD8                             :	out   STD_ULOGIC;
      RD9                             :	out   STD_ULOGIC;
      RD10                            :	out   STD_ULOGIC;
      RD11                            :	out   STD_ULOGIC;
      RD12                            :	out   STD_ULOGIC;
      RD13                            :	out   STD_ULOGIC;
      RD14                            :	out   STD_ULOGIC;
      RD15                            :	out   STD_ULOGIC;
      RD16                             :	out   STD_ULOGIC;
      RD17                             :	out   STD_ULOGIC;
      RD18                             :	out   STD_ULOGIC;
      RD19                             :	out   STD_ULOGIC;
      RD20                             :	out   STD_ULOGIC;
      RD21                             :	out   STD_ULOGIC;
      RD22                             :	out   STD_ULOGIC;
      RD23                             :	out   STD_ULOGIC;
      RD24                             :	out   STD_ULOGIC;
      RD25                             :	out   STD_ULOGIC;
      RD26                            :	out   STD_ULOGIC;
      RD27                            :	out   STD_ULOGIC;
      RD28                            :	out   STD_ULOGIC;
      RD29                            :	out   STD_ULOGIC;
      RD30                            :	out   STD_ULOGIC;
      RD31                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX16_RX32: entity is FALSE;
end RAMB16KA_WX16_RX32;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX16_RX32 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';

      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (15 downto 0);
 	signal WAD : std_logic_vector (9 downto 0);
	signal RAD : std_logic_vector (8 downto 0);
	signal RD  : std_logic_vector (31 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);

      end block;

      --------------------
      -- RAMB16KA_WX16_RX32Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd          : std_ulogic := 'X';
        variable RD11_zd          : std_ulogic := 'X';
        variable RD12_zd          : std_ulogic := 'X';
        variable RD13_zd          : std_ulogic := 'X';
        variable RD14_zd          : std_ulogic := 'X';
        variable RD15_zd          : std_ulogic := 'X';
        variable RD16_zd          : std_ulogic := 'X';
        variable RD17_zd          : std_ulogic := 'X';
        variable RD18_zd          : std_ulogic := 'X';
        variable RD19_zd          : std_ulogic := 'X';
        variable RD20_zd          : std_ulogic := 'X';
        variable RD21_zd          : std_ulogic := 'X';
        variable RD22_zd          : std_ulogic := 'X';
        variable RD23_zd          : std_ulogic := 'X';
        variable RD24_zd          : std_ulogic := 'X';
        variable RD25_zd          : std_ulogic := 'X';
        variable RD26_zd          : std_ulogic := 'X';
        variable RD27_zd          : std_ulogic := 'X';
        variable RD28_zd          : std_ulogic := 'X';
        variable RD29_zd          : std_ulogic := 'X';
        variable RD30_zd          : std_ulogic := 'X';
        variable RD31_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX16_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or Tviol_WAD9_WCLK_posedge or 
                 Tviol_WD0_WCLK_posedge or Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or Tviol_WD15_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD4, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD4, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD4, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD4, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD4, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD4, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD4, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD4, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD4, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD5, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD5, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD5, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD5, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD5, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD5, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD5, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD5, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD5, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD6, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD6, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD6, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD6, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD6, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD6, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD6, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD6, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD6, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD7, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD7, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD7, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD7, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD7, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD7, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD7, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD7, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD7, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD8, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD8, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD8, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD8, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD8, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD8, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD8, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD8, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD8, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD9, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD9, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD9, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD9, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD9, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD9, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD9, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD9, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD9, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD10, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD10, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD10, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD10, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD10, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD10, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD10, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD10, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD10, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD11, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD11, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD11, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD11, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD11, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD11, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD11, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD11, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD11, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD12, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD12, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD12, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD12, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD12, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD12, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD12, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD12, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD12, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD13, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD13, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD13, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD13, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD13, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD13, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD13, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD13, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD13, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD14, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD14, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD14, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD14, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD14, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD14, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD14, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD14, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD14, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD15, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD15, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD15, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD15, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD15, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD15, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD15, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD15, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD15, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;

    VitalBehavior_RD16  : process
      variable RD16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD16_zd := RD(16);

    VitalPathDelay01 (
      OutSignal => RD16,
      GlitchData => O_GlitchData,
      OutSignalName => "RD16",
      OutTemp => RD16_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD16, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD16, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD16, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD16, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD16, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD16, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD16, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD16, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD16, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(16);
      end process;

    VitalBehavior_RD17  : process
      variable RD17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD17_zd := RD(17);

    VitalPathDelay01 (
      OutSignal => RD17,
      GlitchData => O_GlitchData,
      OutSignalName => "RD17",
      OutTemp => RD17_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD17, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD17, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD17, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD17, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD17, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD17, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD17, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD17, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD17, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(17);
      end process;

    VitalBehavior_RD18  : process
      variable RD18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD18_zd := RD(18);

    VitalPathDelay01 (
      OutSignal => RD18,
      GlitchData => O_GlitchData,
      OutSignalName => "RD18",
      OutTemp => RD18_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD18, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD18, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD18, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD18, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD18, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD18, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD18, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD18, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD18, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(18);
      end process;

    VitalBehavior_RD19  : process
      variable RD19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD19_zd := RD(19);

    VitalPathDelay01 (
      OutSignal => RD19,
      GlitchData => O_GlitchData,
      OutSignalName => "RD19",
      OutTemp => RD19_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD19, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD19, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD19, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD19, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD19, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD19, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD19, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD19, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD19, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(19);
      end process;

    VitalBehavior_RD20  : process
      variable RD20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD20_zd := RD(20);

    VitalPathDelay01 (
      OutSignal => RD20,
      GlitchData => O_GlitchData,
      OutSignalName => "RD20",
      OutTemp => RD20_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD20, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD20, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD20, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD20, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD20, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD20, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD20, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD20, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD20, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(20);
      end process;

    VitalBehavior_RD21  : process
      variable RD21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD21_zd := RD(21);

    VitalPathDelay01 (
      OutSignal => RD21,
      GlitchData => O_GlitchData,
      OutSignalName => "RD21",
      OutTemp => RD21_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD21, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD21, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD21, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD21, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD21, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD21, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD21, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD21, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD21, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(21);
      end process;

    VitalBehavior_RD22  : process
      variable RD22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD22_zd := RD(22);

    VitalPathDelay01 (
      OutSignal => RD22,
      GlitchData => O_GlitchData,
      OutSignalName => "RD22",
      OutTemp => RD22_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD22, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD22, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD22, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD22, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD22, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD22, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD22, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD22, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD22, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(22);
      end process;

    VitalBehavior_RD23  : process
      variable RD23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD23_zd := RD(23);

    VitalPathDelay01 (
      OutSignal => RD23,
      GlitchData => O_GlitchData,
      OutSignalName => "RD23",
      OutTemp => RD23_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD23, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD23, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD23, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD23, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD23, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD23, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD23, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD23, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD23, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(23);
      end process;

    VitalBehavior_RD24  : process
      variable RD24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD24_zd := RD(24);

    VitalPathDelay01 (
      OutSignal => RD24,
      GlitchData => O_GlitchData,
      OutSignalName => "RD24",
      OutTemp => RD24_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD24, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD24, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD24, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD24, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD24, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD24, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD24, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD24, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD24, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(24);
      end process;

    VitalBehavior_RD25  : process
      variable RD25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD25_zd := RD(25);

    VitalPathDelay01 (
      OutSignal => RD25,
      GlitchData => O_GlitchData,
      OutSignalName => "RD25",
      OutTemp => RD25_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD25, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD25, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD25, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD25, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD25, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD25, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD25, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD25, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD25, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(25);
      end process;

    VitalBehavior_RD26  : process
      variable RD26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD26_zd := RD(26);

    VitalPathDelay01 (
      OutSignal => RD26,
      GlitchData => O_GlitchData,
      OutSignalName => "RD26",
      OutTemp => RD26_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD26, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD26, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD26, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD26, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD26, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD26, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD26, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD26, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD26, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(26);
      end process;

    VitalBehavior_RD27  : process
      variable RD27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD27_zd := RD(27);

    VitalPathDelay01 (
      OutSignal => RD27,
      GlitchData => O_GlitchData,
      OutSignalName => "RD27",
      OutTemp => RD27_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD27, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD27, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD27, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD27, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD27, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD27, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD27, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD27, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD27, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(27);
      end process;

    VitalBehavior_RD28  : process
      variable RD28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD28_zd := RD(28);

    VitalPathDelay01 (
      OutSignal => RD28,
      GlitchData => O_GlitchData,
      OutSignalName => "RD28",
      OutTemp => RD28_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD28, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD28, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD28, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD28, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD28, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD28, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD28, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD28, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD28, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(28);
      end process;

    VitalBehavior_RD29  : process
      variable RD29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD29_zd := RD(29);

    VitalPathDelay01 (
      OutSignal => RD29,
      GlitchData => O_GlitchData,
      OutSignalName => "RD29",
      OutTemp => RD29_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD29, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD29, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD29, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD29, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD29, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD29, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD29, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD29, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD29, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(29);
      end process;

    VitalBehavior_RD30  : process
      variable RD30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD30_zd := RD(30);

    VitalPathDelay01 (
      OutSignal => RD30,
      GlitchData => O_GlitchData,
      OutSignalName => "RD30",
      OutTemp => RD30_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD30, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD30, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD30, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD30, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD30, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD30, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD30, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD30, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD30, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(30);
      end process;

    VitalBehavior_RD31  : process
      variable RD31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD31_zd := RD(31);

    VitalPathDelay01 (
      OutSignal => RD31,
      GlitchData => O_GlitchData,
      OutSignalName => "RD31",
      OutTemp => RD31_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD31, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD31, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD31, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD31, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD31, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD31, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD31, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD31, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD31, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(31);
      end process;



	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 10,
		WDATA_WIDTH    => 16,
		RADDR_WIDTH    => 9,
		RDATA_WIDTH    => 32,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX16_RX16_VITAL of RAMB16KA_WX16_RX32 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX16_RX16_VITAL;



----- CELL RAMB16KA_WX32_RX32 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_WX32_RX32 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RAD0_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD0_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD16_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD16_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD17_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD17_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD18_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD18_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD19_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD19_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD20_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD20_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD21_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD21_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD22_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD22_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD23_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD23_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD24_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD24_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD25_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD25_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD26_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD26_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD27_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD27_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD28_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD28_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD29_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD29_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD30_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD30_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD31_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD31_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD16                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD17                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD18                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD19                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD20                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD21                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD22                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD23                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD24                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD25                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD26                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD27                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD28                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD29                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD30                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD31                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WD16                            :	in    STD_ULOGIC;
      WD17                            :	in    STD_ULOGIC;
      WD18                            :	in    STD_ULOGIC;
      WD19                            :	in    STD_ULOGIC;
      WD20                            :	in    STD_ULOGIC;
      WD21                            :	in    STD_ULOGIC;
      WD22                            :	in    STD_ULOGIC;
      WD23                            :	in    STD_ULOGIC;
      WD24                            :	in    STD_ULOGIC;
      WD25                            :	in    STD_ULOGIC;
      WD26                            :	in    STD_ULOGIC;
      WD27                            :	in    STD_ULOGIC;
      WD28                            :	in    STD_ULOGIC;
      WD29                            :	in    STD_ULOGIC;
      WD30                            :	in    STD_ULOGIC;
      WD31                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RD0                             :	out   STD_ULOGIC;
      RD1                             :	out   STD_ULOGIC;
      RD2                             :	out   STD_ULOGIC;
      RD3                             :	out   STD_ULOGIC;
      RD4                             :	out   STD_ULOGIC;
      RD5                             :	out   STD_ULOGIC;
      RD6                             :	out   STD_ULOGIC;
      RD7                             :	out   STD_ULOGIC;
      RD8                             :	out   STD_ULOGIC;
      RD9                             :	out   STD_ULOGIC;
      RD10                            :	out   STD_ULOGIC;
      RD11                            :	out   STD_ULOGIC;
      RD12                            :	out   STD_ULOGIC;
      RD13                            :	out   STD_ULOGIC;
      RD14                            :	out   STD_ULOGIC;
      RD15                            :	out   STD_ULOGIC;
      RD16                             :	out   STD_ULOGIC;
      RD17                             :	out   STD_ULOGIC;
      RD18                             :	out   STD_ULOGIC;
      RD19                             :	out   STD_ULOGIC;
      RD20                             :	out   STD_ULOGIC;
      RD21                             :	out   STD_ULOGIC;
      RD22                             :	out   STD_ULOGIC;
      RD23                             :	out   STD_ULOGIC;
      RD24                             :	out   STD_ULOGIC;
      RD25                             :	out   STD_ULOGIC;
      RD26                            :	out   STD_ULOGIC;
      RD27                            :	out   STD_ULOGIC;
      RD28                            :	out   STD_ULOGIC;
      RD29                            :	out   STD_ULOGIC;
      RD30                            :	out   STD_ULOGIC;
      RD31                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_WX32_RX32 : entity is FALSE;
end RAMB16KA_WX32_RX32;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX32_RX32 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 9;
		WDATA_WIDTH    : integer := 32;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';

      signal WD16_ipd      : std_ulogic := 'X';
      signal WD17_ipd      : std_ulogic := 'X';
      signal WD18_ipd      : std_ulogic := 'X';
      signal WD19_ipd      : std_ulogic := 'X';
      signal WD20_ipd      : std_ulogic := 'X';
      signal WD21_ipd      : std_ulogic := 'X';
      signal WD22_ipd      : std_ulogic := 'X';
      signal WD23_ipd      : std_ulogic := 'X';
      signal WD24_ipd      : std_ulogic := 'X';
      signal WD25_ipd      : std_ulogic := 'X';
      signal WD26_ipd      : std_ulogic := 'X';
      signal WD27_ipd      : std_ulogic := 'X';
      signal WD28_ipd      : std_ulogic := 'X';
      signal WD29_ipd      : std_ulogic := 'X';
      signal WD30_ipd      : std_ulogic := 'X';
      signal WD31_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (31 downto 0);
 	signal WAD : std_logic_vector (8 downto 0);
	signal RAD : std_logic_vector (8 downto 0);
	signal RD  : std_logic_vector (31 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD31_ipd & WD30_ipd & WD29_ipd & WD28_ipd & WD27_ipd & WD26_ipd & WD25_ipd & WD24_ipd & WD23_ipd & WD22_ipd & WD21_ipd & WD20_ipd & WD19_ipd & WD18_ipd & WD17_ipd & WD16_ipd & WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);

      end block;

      --------------------
      -- RAMB16KA_WX32_RX32 Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD16_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD17_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD18_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD19_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD20_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD21_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD22_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD23_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD24_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD25_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD26_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD27_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD28_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD29_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD30_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD31_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD16_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD17_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD18_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD19_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD20_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD21_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD22_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD23_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD24_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD25_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD26_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD27_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD28_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD29_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD30_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD31_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd          : std_ulogic := 'X';
        variable RD11_zd          : std_ulogic := 'X';
        variable RD12_zd          : std_ulogic := 'X';
        variable RD13_zd          : std_ulogic := 'X';
        variable RD14_zd          : std_ulogic := 'X';
        variable RD15_zd          : std_ulogic := 'X';
        variable RD16_zd          : std_ulogic := 'X';
        variable RD17_zd          : std_ulogic := 'X';
        variable RD18_zd          : std_ulogic := 'X';
        variable RD19_zd          : std_ulogic := 'X';
        variable RD20_zd          : std_ulogic := 'X';
        variable RD21_zd          : std_ulogic := 'X';
        variable RD22_zd          : std_ulogic := 'X';
        variable RD23_zd          : std_ulogic := 'X';
        variable RD24_zd          : std_ulogic := 'X';
        variable RD25_zd          : std_ulogic := 'X';
        variable RD26_zd          : std_ulogic := 'X';
        variable RD27_zd          : std_ulogic := 'X';
        variable RD28_zd          : std_ulogic := 'X';
        variable RD29_zd          : std_ulogic := 'X';
        variable RD30_zd          : std_ulogic := 'X';
        variable RD31_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD16_WCLK_posedge,
          TimingData              => Tmkr_WD16_WCLK_posedge,
          TestSignal              => WD16_ipd,
          TestSignalName          => "WD16",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD16_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD16_WCLK_noedge_posedge,
          HoldLow                 => thold_WD16_WCLK_noedge_posedge,
          HoldHigh                => thold_WD16_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD17_WCLK_posedge,
          TimingData              => Tmkr_WD17_WCLK_posedge,
          TestSignal              => WD17_ipd,
          TestSignalName          => "WD17",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD17_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD17_WCLK_noedge_posedge,
          HoldLow                 => thold_WD17_WCLK_noedge_posedge,
          HoldHigh                => thold_WD17_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD18_WCLK_posedge,
          TimingData              => Tmkr_WD18_WCLK_posedge,
          TestSignal              => WD18_ipd,
          TestSignalName          => "WD18",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD18_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD18_WCLK_noedge_posedge,
          HoldLow                 => thold_WD18_WCLK_noedge_posedge,
          HoldHigh                => thold_WD18_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD19_WCLK_posedge,
          TimingData              => Tmkr_WD19_WCLK_posedge,
          TestSignal              => WD19_ipd,
          TestSignalName          => "WD19",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD19_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD19_WCLK_noedge_posedge,
          HoldLow                 => thold_WD19_WCLK_noedge_posedge,
          HoldHigh                => thold_WD19_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD20_WCLK_posedge,
          TimingData              => Tmkr_WD20_WCLK_posedge,
          TestSignal              => WD20_ipd,
          TestSignalName          => "WD20",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD20_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD20_WCLK_noedge_posedge,
          HoldLow                 => thold_WD20_WCLK_noedge_posedge,
          HoldHigh                => thold_WD20_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD21_WCLK_posedge,
          TimingData              => Tmkr_WD21_WCLK_posedge,
          TestSignal              => WD21_ipd,
          TestSignalName          => "WD21",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD21_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD21_WCLK_noedge_posedge,
          HoldLow                 => thold_WD21_WCLK_noedge_posedge,
          HoldHigh                => thold_WD21_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD22_WCLK_posedge,
          TimingData              => Tmkr_WD22_WCLK_posedge,
          TestSignal              => WD22_ipd,
          TestSignalName          => "WD22",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD22_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD22_WCLK_noedge_posedge,
          HoldLow                 => thold_WD22_WCLK_noedge_posedge,
          HoldHigh                => thold_WD22_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD23_WCLK_posedge,
          TimingData              => Tmkr_WD23_WCLK_posedge,
          TestSignal              => WD23_ipd,
          TestSignalName          => "WD23",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD23_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD23_WCLK_noedge_posedge,
          HoldLow                 => thold_WD23_WCLK_noedge_posedge,
          HoldHigh                => thold_WD23_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD24_WCLK_posedge,
          TimingData              => Tmkr_WD24_WCLK_posedge,
          TestSignal              => WD24_ipd,
          TestSignalName          => "WD24",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD24_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD24_WCLK_noedge_posedge,
          HoldLow                 => thold_WD24_WCLK_noedge_posedge,
          HoldHigh                => thold_WD24_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD25_WCLK_posedge,
          TimingData              => Tmkr_WD25_WCLK_posedge,
          TestSignal              => WD25_ipd,
          TestSignalName          => "WD25",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD25_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD25_WCLK_noedge_posedge,
          HoldLow                 => thold_WD25_WCLK_noedge_posedge,
          HoldHigh                => thold_WD25_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD26_WCLK_posedge,
          TimingData              => Tmkr_WD26_WCLK_posedge,
          TestSignal              => WD26_ipd,
          TestSignalName          => "WD26",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD26_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD26_WCLK_noedge_posedge,
          HoldLow                 => thold_WD26_WCLK_noedge_posedge,
          HoldHigh                => thold_WD26_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD27_WCLK_posedge,
          TimingData              => Tmkr_WD27_WCLK_posedge,
          TestSignal              => WD27_ipd,
          TestSignalName          => "WD27",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD27_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD27_WCLK_noedge_posedge,
          HoldLow                 => thold_WD27_WCLK_noedge_posedge,
          HoldHigh                => thold_WD27_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD28_WCLK_posedge,
          TimingData              => Tmkr_WD28_WCLK_posedge,
          TestSignal              => WD28_ipd,
          TestSignalName          => "WD28",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD28_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD28_WCLK_noedge_posedge,
          HoldLow                 => thold_WD28_WCLK_noedge_posedge,
          HoldHigh                => thold_WD28_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD29_WCLK_posedge,
          TimingData              => Tmkr_WD29_WCLK_posedge,
          TestSignal              => WD29_ipd,
          TestSignalName          => "WD29",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD29_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD29_WCLK_noedge_posedge,
          HoldLow                 => thold_WD29_WCLK_noedge_posedge,
          HoldHigh                => thold_WD29_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD30_WCLK_posedge,
          TimingData              => Tmkr_WD30_WCLK_posedge,
          TestSignal              => WD30_ipd,
          TestSignalName          => "WD30",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD30_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD30_WCLK_noedge_posedge,
          HoldLow                 => thold_WD30_WCLK_noedge_posedge,
          HoldHigh                => thold_WD30_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD31_WCLK_posedge,
          TimingData              => Tmkr_WD31_WCLK_posedge,
          TestSignal              => WD31_ipd,
          TestSignalName          => "WD31",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD31_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD31_WCLK_noedge_posedge,
          HoldLow                 => thold_WD31_WCLK_noedge_posedge,
          HoldHigh                => thold_WD31_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_WX32_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or Tviol_WAD1_WCLK_posedge or 
                 Tviol_WAD2_WCLK_posedge or Tviol_WAD3_WCLK_posedge or 
                 Tviol_WAD4_WCLK_posedge or Tviol_WAD5_WCLK_posedge or 
                 Tviol_WAD6_WCLK_posedge or Tviol_WAD7_WCLK_posedge or 
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or Tviol_WD15_WCLK_posedge or
                 Tviol_WD16_WCLK_posedge or Tviol_WD17_WCLK_posedge or
                 Tviol_WD18_WCLK_posedge or Tviol_WD19_WCLK_posedge or
                 Tviol_WD20_WCLK_posedge or Tviol_WD21_WCLK_posedge or
                 Tviol_WD22_WCLK_posedge or Tviol_WD23_WCLK_posedge or
                 Tviol_WD24_WCLK_posedge or Tviol_WD25_WCLK_posedge or
                 Tviol_WD26_WCLK_posedge or Tviol_WD27_WCLK_posedge or
                 Tviol_WD28_WCLK_posedge or Tviol_WD29_WCLK_posedge or
                 Tviol_WD30_WCLK_posedge or Tviol_WD31_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on WCEN_ipd, WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;

      end process VITALBehavior;

    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD4, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD4, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD4, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD4, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD4, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD4, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD4, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD4, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD4, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD5, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD5, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD5, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD5, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD5, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD5, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD5, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD5, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD5, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD6, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD6, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD6, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD6, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD6, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD6, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD6, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD6, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD6, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD7, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD7, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD7, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD7, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD7, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD7, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD7, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD7, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD7, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD8, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD8, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD8, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD8, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD8, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD8, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD8, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD8, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD8, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD9, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD9, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD9, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD9, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD9, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD9, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD9, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD9, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD9, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD10, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD10, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD10, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD10, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD10, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD10, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD10, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD10, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD10, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD11, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD11, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD11, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD11, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD11, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD11, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD11, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD11, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD11, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD12, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD12, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD12, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD12, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD12, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD12, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD12, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD12, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD12, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD13, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD13, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD13, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD13, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD13, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD13, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD13, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD13, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD13, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD14, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD14, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD14, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD14, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD14, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD14, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD14, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD14, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD14, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD15, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD15, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD15, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD15, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD15, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD15, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD15, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD15, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD15, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;

    VitalBehavior_RD16  : process
      variable RD16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD16_zd := RD(16);

    VitalPathDelay01 (
      OutSignal => RD16,
      GlitchData => O_GlitchData,
      OutSignalName => "RD16",
      OutTemp => RD16_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD16, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD16, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD16, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD16, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD16, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD16, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD16, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD16, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD16, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(16);
      end process;

    VitalBehavior_RD17  : process
      variable RD17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD17_zd := RD(17);

    VitalPathDelay01 (
      OutSignal => RD17,
      GlitchData => O_GlitchData,
      OutSignalName => "RD17",
      OutTemp => RD17_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD17, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD17, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD17, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD17, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD17, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD17, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD17, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD17, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD17, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(17);
      end process;

    VitalBehavior_RD18  : process
      variable RD18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD18_zd := RD(18);

    VitalPathDelay01 (
      OutSignal => RD18,
      GlitchData => O_GlitchData,
      OutSignalName => "RD18",
      OutTemp => RD18_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD18, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD18, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD18, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD18, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD18, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD18, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD18, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD18, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD18, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(18);
      end process;

    VitalBehavior_RD19  : process
      variable RD19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD19_zd := RD(19);

    VitalPathDelay01 (
      OutSignal => RD19,
      GlitchData => O_GlitchData,
      OutSignalName => "RD19",
      OutTemp => RD19_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD19, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD19, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD19, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD19, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD19, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD19, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD19, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD19, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD19, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(19);
      end process;

    VitalBehavior_RD20  : process
      variable RD20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD20_zd := RD(20);

    VitalPathDelay01 (
      OutSignal => RD20,
      GlitchData => O_GlitchData,
      OutSignalName => "RD20",
      OutTemp => RD20_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD20, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD20, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD20, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD20, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD20, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD20, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD20, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD20, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD20, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(20);
      end process;

    VitalBehavior_RD21  : process
      variable RD21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD21_zd := RD(21);

    VitalPathDelay01 (
      OutSignal => RD21,
      GlitchData => O_GlitchData,
      OutSignalName => "RD21",
      OutTemp => RD21_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD21, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD21, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD21, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD21, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD21, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD21, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD21, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD21, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD21, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(21);
      end process;

    VitalBehavior_RD22  : process
      variable RD22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD22_zd := RD(22);

    VitalPathDelay01 (
      OutSignal => RD22,
      GlitchData => O_GlitchData,
      OutSignalName => "RD22",
      OutTemp => RD22_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD22, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD22, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD22, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD22, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD22, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD22, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD22, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD22, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD22, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(22);
      end process;

    VitalBehavior_RD23  : process
      variable RD23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD23_zd := RD(23);

    VitalPathDelay01 (
      OutSignal => RD23,
      GlitchData => O_GlitchData,
      OutSignalName => "RD23",
      OutTemp => RD23_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD23, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD23, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD23, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD23, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD23, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD23, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD23, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD23, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD23, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(23);
      end process;

    VitalBehavior_RD24  : process
      variable RD24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD24_zd := RD(24);

    VitalPathDelay01 (
      OutSignal => RD24,
      GlitchData => O_GlitchData,
      OutSignalName => "RD24",
      OutTemp => RD24_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD24, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD24, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD24, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD24, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD24, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD24, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD24, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD24, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD24, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(24);
      end process;

    VitalBehavior_RD25  : process
      variable RD25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD25_zd := RD(25);

    VitalPathDelay01 (
      OutSignal => RD25,
      GlitchData => O_GlitchData,
      OutSignalName => "RD25",
      OutTemp => RD25_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD25, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD25, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD25, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD25, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD25, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD25, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD25, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD25, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD25, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(25);
      end process;

    VitalBehavior_RD26  : process
      variable RD26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD26_zd := RD(26);

    VitalPathDelay01 (
      OutSignal => RD26,
      GlitchData => O_GlitchData,
      OutSignalName => "RD26",
      OutTemp => RD26_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD26, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD26, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD26, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD26, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD26, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD26, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD26, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD26, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD26, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(26);
      end process;

    VitalBehavior_RD27  : process
      variable RD27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD27_zd := RD(27);

    VitalPathDelay01 (
      OutSignal => RD27,
      GlitchData => O_GlitchData,
      OutSignalName => "RD27",
      OutTemp => RD27_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD27, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD27, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD27, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD27, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD27, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD27, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD27, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD27, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD27, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(27);
      end process;

    VitalBehavior_RD28  : process
      variable RD28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD28_zd := RD(28);

    VitalPathDelay01 (
      OutSignal => RD28,
      GlitchData => O_GlitchData,
      OutSignalName => "RD28",
      OutTemp => RD28_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD28, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD28, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD28, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD28, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD28, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD28, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD28, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD28, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD28, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(28);
      end process;

    VitalBehavior_RD29  : process
      variable RD29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD29_zd := RD(29);

    VitalPathDelay01 (
      OutSignal => RD29,
      GlitchData => O_GlitchData,
      OutSignalName => "RD29",
      OutTemp => RD29_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD29, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD29, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD29, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD29, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD29, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD29, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD29, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD29, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD29, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(29);
      end process;

    VitalBehavior_RD30  : process
      variable RD30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD30_zd := RD(30);

    VitalPathDelay01 (
      OutSignal => RD30,
      GlitchData => O_GlitchData,
      OutSignalName => "RD30",
      OutTemp => RD30_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD30, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD30, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD30, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD30, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD30, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD30, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD30, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD30, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD30, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(30);
      end process;

    VitalBehavior_RD31  : process
      variable RD31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD31_zd := RD(31);

    VitalPathDelay01 (
      OutSignal => RD31,
      GlitchData => O_GlitchData,
      OutSignalName => "RD31",
      OutTemp => RD31_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD31, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD31, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD31, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD31, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD31, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD31, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD31, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD31, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD31, TRUE),
               9 => (RST_ipd'last_event, tpd_RST_RD31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(31);
      end process;



	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 9,
		WDATA_WIDTH    => 32,
		RADDR_WIDTH    => 9,
		RDATA_WIDTH    => 32,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);

end VITAL;

configuration CFG_RAMB16KA_WX32_RX32_VITAL of RAMB16KA_WX32_RX32 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX32_RX32_VITAL;



----- CELL RAMB16KA_X1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_X1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_AD0_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD10_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD11_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD12_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD13_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO0                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tsetup_WR_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_CEN_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CEN_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD4_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD4_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD5_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD5_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD6_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD6_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD7_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD7_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD8_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD8_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD9_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD9_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD10_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD10_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD11_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD11_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD12_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD12_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD13_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD13_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RST_CLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_CLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLK_posedge                  :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_CEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD8                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD9                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD10                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD11                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD12                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD13                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CEN                            :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      WR                             :	in    STD_ULOGIC;
      CS0                            :	in    STD_ULOGIC;
      CS1                            :	in    STD_ULOGIC;
      RST                            :	in    STD_ULOGIC;
      DI0                            :	in    STD_ULOGIC;
      AD0                            :	in    STD_ULOGIC;
      AD1                            :	in    STD_ULOGIC;
      AD2                            :	in    STD_ULOGIC;
      AD3                            :	in    STD_ULOGIC;
      AD4                            :	in    STD_ULOGIC;
      AD5                            :	in    STD_ULOGIC;
      AD6                            :	in    STD_ULOGIC;
      AD7                            :	in    STD_ULOGIC;
      AD8                            :	in    STD_ULOGIC;
      AD9                            :	in    STD_ULOGIC;
      AD10                           :	in    STD_ULOGIC;
      AD11                           :	in    STD_ULOGIC;
      AD12                           :	in    STD_ULOGIC;
      AD13                           :	in    STD_ULOGIC;
      DO0                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_X1 : entity is FALSE;
end RAMB16KA_X1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_X1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_SPRAMA_16K
	   generic (
		ADDR_WIDTH    : integer := 14;
		DATA_WIDTH    : integer := 1;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CEN : in  STD_LOGIC ;
		CLK : in  STD_LOGIC ;
		WR   : in  STD_LOGIC ;
		CS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		DI   : in  STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0);
		AD  : in  STD_LOGIC_VECTOR (ADDR_WIDTH -1 downto 0);
		DO   : out STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0)
		);
	end component ;

      signal CEN_ipd      : std_ulogic := 'X';
      signal CLK_ipd      : std_ulogic := 'X';
      signal WR_ipd       : std_ulogic := 'X';
      signal CS0_ipd      : std_ulogic := 'X';
      signal CS1_ipd      : std_ulogic := 'X';
      signal RST_ipd      : std_ulogic := 'X';

      signal DI0_ipd      : std_logic_vector(0 downto 0);

      signal AD0_ipd      : std_ulogic := 'X';
      signal AD1_ipd      : std_ulogic := 'X';
      signal AD2_ipd      : std_ulogic := 'X';
      signal AD3_ipd      : std_ulogic := 'X';
      signal AD4_ipd      : std_ulogic := 'X';
      signal AD5_ipd      : std_ulogic := 'X';
      signal AD6_ipd      : std_ulogic := 'X';
      signal AD7_ipd      : std_ulogic := 'X';
      signal AD8_ipd      : std_ulogic := 'X';
      signal AD9_ipd      : std_ulogic := 'X';
      signal AD10_ipd     : std_ulogic := 'X';
      signal AD11_ipd     : std_ulogic := 'X';
      signal AD12_ipd     : std_ulogic := 'X';
      signal AD13_ipd     : std_ulogic := 'X';

	signal CS : std_logic_vector (1 downto 0);
	signal DI  : std_logic_vector (0 downto 0);
 	signal AD : std_logic_vector (13 downto 0);
	signal DO  : std_logic_vector (0 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	CS <= CS1_ipd & CS0_ipd;
	DI <= DI0_ipd;
	AD <= AD13_ipd & AD12_ipd & AD11_ipd & AD10_ipd & AD9_ipd & AD8_ipd & AD7_ipd & AD6_ipd & AD5_ipd & AD4_ipd & AD3_ipd & AD2_ipd & AD1_ipd & AD0_ipd;


  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CEN_ipd, CEN, tipd_CEN);
        VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        VitalWireDelay (WR_ipd, WR, tipd_WR);
        VitalWireDelay (CS0_ipd, CS0, tipd_CS0);
        VitalWireDelay (CS1_ipd, CS1, tipd_CS1);
        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (DI0_ipd(0), DI0, tipd_DI0);

        VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
        VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
        VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
        VitalWireDelay (AD3_ipd, AD3, tipd_AD3);
        VitalWireDelay (AD4_ipd, AD4, tipd_AD4);
        VitalWireDelay (AD5_ipd, AD5, tipd_AD5);
        VitalWireDelay (AD6_ipd, AD6, tipd_AD6);
        VitalWireDelay (AD7_ipd, AD7, tipd_AD7);
        VitalWireDelay (AD8_ipd, AD8, tipd_AD8);
        VitalWireDelay (AD9_ipd, AD9, tipd_AD9);
        VitalWireDelay (AD10_ipd, AD10, tipd_AD10);
        VitalWireDelay (AD11_ipd, AD11, tipd_AD11);
        VitalWireDelay (AD12_ipd, AD12, tipd_AD12);
        VitalWireDelay (AD13_ipd, AD13, tipd_AD13);

      end block;

      --------------------
      -- RAMB16KA_X1 Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CEN_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_WR_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_CS0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_CS1_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_DI0_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_AD0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD3_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD4_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD5_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD6_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD7_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD8_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD9_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD10_CLK_posedge   : std_ulogic  := '0';
        variable Tviol_AD11_CLK_posedge   : std_ulogic  := '0';
        variable Tviol_AD12_CLK_posedge   : std_ulogic  := '0';
        variable Tviol_AD13_CLK_posedge   : std_ulogic  := '0';

        variable Tviol_RST_CLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CEN_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_AD0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD4_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD5_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD6_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD7_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD8_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD9_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD10_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD11_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD12_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD13_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_CLK_posedge_posedge  : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLK       : std_ulogic := '0';
        variable PInfo_CLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CEN_CLK_posedge,
          TimingData              => Tmkr_CEN_CLK_posedge,
          TestSignal              => CEN_ipd,
          TestSignalName          => "CEN",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CEN_CLK_noedge_posedge,
          SetupLow                => tsetup_CEN_CLK_noedge_posedge,
          HoldLow                 => thold_CEN_CLK_noedge_posedge,
          HoldHigh                => thold_CEN_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_CLK_posedge,
          TimingData              => Tmkr_WR_CLK_posedge,
          TestSignal              => WR_ipd,
          TestSignalName          => "WR",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_CLK_noedge_posedge,
          HoldLow                 => thold_WR_CLK_noedge_posedge,
          HoldHigh                => thold_WR_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS0_CLK_posedge,
          TimingData              => Tmkr_CS0_CLK_posedge,
          TestSignal              => CS0_ipd,
          TestSignalName          => "CS0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS0_CLK_noedge_posedge,
          SetupLow                => tsetup_CS0_CLK_noedge_posedge,
          HoldLow                 => thold_CS0_CLK_noedge_posedge,
          HoldHigh                => thold_CS0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS1_CLK_posedge,
          TimingData              => Tmkr_CS1_CLK_posedge,
          TestSignal              => CS1_ipd,
          TestSignalName          => "CS1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS1_CLK_noedge_posedge,
          SetupLow                => tsetup_CS1_CLK_noedge_posedge,
          HoldLow                 => thold_CS1_CLK_noedge_posedge,
          HoldHigh                => thold_CS1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_CLK_posedge,
          TimingData              => Tmkr_AD0_CLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_CLK_noedge_posedge,
          SetupLow                => tsetup_AD0_CLK_noedge_posedge,
          HoldLow                 => thold_AD0_CLK_noedge_posedge,
          HoldHigh                => thold_AD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_CLK_posedge,
          TimingData              => Tmkr_AD1_CLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_CLK_noedge_posedge,
          SetupLow                => tsetup_AD1_CLK_noedge_posedge,
          HoldLow                 => thold_AD1_CLK_noedge_posedge,
          HoldHigh                => thold_AD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_CLK_posedge,
          TimingData              => Tmkr_AD2_CLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_CLK_noedge_posedge,
          SetupLow                => tsetup_AD2_CLK_noedge_posedge,
          HoldLow                 => thold_AD2_CLK_noedge_posedge,
          HoldHigh                => thold_AD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_CLK_posedge,
          TimingData              => Tmkr_AD3_CLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_CLK_noedge_posedge,
          SetupLow                => tsetup_AD3_CLK_noedge_posedge,
          HoldLow                 => thold_AD3_CLK_noedge_posedge,
          HoldHigh                => thold_AD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD4_CLK_posedge,
          TimingData              => Tmkr_AD4_CLK_posedge,
          TestSignal              => AD4_ipd,
          TestSignalName          => "AD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD4_CLK_noedge_posedge,
          SetupLow                => tsetup_AD4_CLK_noedge_posedge,
          HoldLow                 => thold_AD4_CLK_noedge_posedge,
          HoldHigh                => thold_AD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD5_CLK_posedge,
          TimingData              => Tmkr_AD5_CLK_posedge,
          TestSignal              => AD5_ipd,
          TestSignalName          => "AD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD5_CLK_noedge_posedge,
          SetupLow                => tsetup_AD5_CLK_noedge_posedge,
          HoldLow                 => thold_AD5_CLK_noedge_posedge,
          HoldHigh                => thold_AD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD6_CLK_posedge,
          TimingData              => Tmkr_AD6_CLK_posedge,
          TestSignal              => AD6_ipd,
          TestSignalName          => "AD6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD6_CLK_noedge_posedge,
          SetupLow                => tsetup_AD6_CLK_noedge_posedge,
          HoldLow                 => thold_AD6_CLK_noedge_posedge,
          HoldHigh                => thold_AD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD7_CLK_posedge,
          TimingData              => Tmkr_AD7_CLK_posedge,
          TestSignal              => AD7_ipd,
          TestSignalName          => "AD7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD7_CLK_noedge_posedge,
          SetupLow                => tsetup_AD7_CLK_noedge_posedge,
          HoldLow                 => thold_AD7_CLK_noedge_posedge,
          HoldHigh                => thold_AD7_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD8_CLK_posedge,
          TimingData              => Tmkr_AD8_CLK_posedge,
          TestSignal              => AD8_ipd,
          TestSignalName          => "AD8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD8_CLK_noedge_posedge,
          SetupLow                => tsetup_AD8_CLK_noedge_posedge,
          HoldLow                 => thold_AD8_CLK_noedge_posedge,
          HoldHigh                => thold_AD8_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD9_CLK_posedge,
          TimingData              => Tmkr_AD9_CLK_posedge,
          TestSignal              => AD9_ipd,
          TestSignalName          => "AD9",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD9_CLK_noedge_posedge,
          SetupLow                => tsetup_AD9_CLK_noedge_posedge,
          HoldLow                 => thold_AD9_CLK_noedge_posedge,
          HoldHigh                => thold_AD9_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD10_CLK_posedge,
          TimingData              => Tmkr_AD10_CLK_posedge,
          TestSignal              => AD10_ipd,
          TestSignalName          => "AD10",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD10_CLK_noedge_posedge,
          SetupLow                => tsetup_AD10_CLK_noedge_posedge,
          HoldLow                 => thold_AD10_CLK_noedge_posedge,
          HoldHigh                => thold_AD10_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD11_CLK_posedge,
          TimingData              => Tmkr_AD11_CLK_posedge,
          TestSignal              => AD11_ipd,
          TestSignalName          => "AD11",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD11_CLK_noedge_posedge,
          SetupLow                => tsetup_AD11_CLK_noedge_posedge,
          HoldLow                 => thold_AD11_CLK_noedge_posedge,
          HoldHigh                => thold_AD11_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD12_CLK_posedge,
          TimingData              => Tmkr_AD12_CLK_posedge,
          TestSignal              => AD12_ipd,
          TestSignalName          => "AD12",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD12_CLK_noedge_posedge,
          SetupLow                => tsetup_AD12_CLK_noedge_posedge,
          HoldLow                 => thold_AD12_CLK_noedge_posedge,
          HoldHigh                => thold_AD12_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_Ad13_CLK_posedge,
          TimingData              => Tmkr_Ad13_CLK_posedge,
          TestSignal              => Ad13_ipd,
          TestSignalName          => "Ad13",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_Ad13_CLK_noedge_posedge,
          SetupLow                => tsetup_Ad13_CLK_noedge_posedge,
          HoldLow                 => thold_Ad13_CLK_noedge_posedge,
          HoldHigh                => thold_Ad13_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_CLK_posedge_posedge,
          TimingData              => Tmkr_RST_CLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_CLK_posedge_posedge,
          Removal                 => thold_RST_CLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_X1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CEN_CLK_posedge or Tviol_WR_CLK_posedge or 
                 Tviol_CS0_CLK_posedge or Tviol_CS1_CLK_posedge or 
                 Tviol_AD0_CLK_posedge or Tviol_AD1_CLK_posedge or 
                 Tviol_AD2_CLK_posedge or Tviol_AD3_CLK_posedge or 
                 Tviol_AD4_CLK_posedge or Tviol_AD5_CLK_posedge or 
                 Tviol_AD6_CLK_posedge or Tviol_AD7_CLK_posedge or 
                 Tviol_AD8_CLK_posedge or Tviol_AD9_CLK_posedge or 
                 Tviol_AD10_CLK_posedge or Tviol_AD11_CLK_posedge or 
                 Tviol_AD12_CLK_posedge or Tviol_DI0_CLK_posedge or
                 Tviol_AD13_CLK_posedge or Pviol_CLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------
	DO0_zd := DO(0);


    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (AD0_ipd'last_event, tpd_AD0_DO0, TRUE),
                1 => (AD1_ipd'last_event, tpd_AD1_DO0, TRUE),
                2 => (AD2_ipd'last_event, tpd_AD2_DO0, TRUE),
                3 => (AD3_ipd'last_event, tpd_AD3_DO0, TRUE),
                4 => (AD4_ipd'last_event, tpd_AD4_DO0, TRUE),
                5 => (AD5_ipd'last_event, tpd_AD5_DO0, TRUE),
                6 => (AD6_ipd'last_event, tpd_AD6_DO0, TRUE),
                7 => (AD7_ipd'last_event, tpd_AD7_DO0, TRUE),
                8 => (AD8_ipd'last_event, tpd_AD8_DO0, TRUE),
                9 => (AD9_ipd'last_event, tpd_AD9_DO0, TRUE),
                10 => (AD10_ipd'last_event, tpd_AD10_DO0, TRUE),
                11 => (AD11_ipd'last_event, tpd_AD11_DO0, TRUE),
                12 => (AD12_ipd'last_event, tpd_AD12_DO0, TRUE),
                13 => (AD13_ipd'last_event, tpd_AD13_DO0, TRUE),
                14 => (CLK_ipd'last_event, tpd_CLK_DO0, TRUE),
                15 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

	wait on CEN_ipd, CLK_ipd, WR_ipd, CS,  RST_ipd, DI, AD, DO;

      end process VITALBehavior;

	SPRAMA_INST: SC_SPRAMA_16K
	   generic map (
		ADDR_WIDTH    => 14,
		DATA_WIDTH    => 1,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CEN => CEN_ipd,
		CLK => CLK_ipd,
		WR  => WR_ipd,
		CS  => CS,
		RST => RST_ipd,
		DI  => DI,
		AD  => AD,
		DO  => DO
		);

end VITAL;

configuration CFG_RAMB16KA_X1_VITAL of RAMB16KA_X1 is
   for VITAL
   end for;
end CFG_RAMB16KA_X1_VITAL;



----- CELL RAMB16KA_X2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_X2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_AD0_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD10_DO0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD11_DO0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD12_DO0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO0                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD10_DO1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD11_DO1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD12_DO1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO1                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tsetup_WR_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_CEN_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CEN_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD4_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD4_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD5_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD5_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD6_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD6_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD7_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD7_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD8_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD8_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD9_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD9_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD10_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD10_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD11_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD11_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD12_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD12_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RST_CLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_CLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLK_posedge                  :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_CEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD8                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD9                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD10                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD11                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD12                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CEN                            :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      WR                             :	in    STD_ULOGIC;
      CS0                            :	in    STD_ULOGIC;
      CS1                            :	in    STD_ULOGIC;
      RST                            :	in    STD_ULOGIC;
      DI0                            :	in    STD_ULOGIC;
      DI1                            :	in    STD_ULOGIC;
      AD0                            :	in    STD_ULOGIC;
      AD1                            :	in    STD_ULOGIC;
      AD2                            :	in    STD_ULOGIC;
      AD3                            :	in    STD_ULOGIC;
      AD4                            :	in    STD_ULOGIC;
      AD5                            :	in    STD_ULOGIC;
      AD6                            :	in    STD_ULOGIC;
      AD7                            :	in    STD_ULOGIC;
      AD8                            :	in    STD_ULOGIC;
      AD9                            :	in    STD_ULOGIC;
      AD10                           :	in    STD_ULOGIC;
      AD11                           :	in    STD_ULOGIC;
      AD12                           :	in    STD_ULOGIC;
      DO0                            :	out   STD_ULOGIC;
      DO1                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_X2 : entity is FALSE;
end RAMB16KA_X2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_X2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_SPRAMA_16K
	   generic (
		ADDR_WIDTH    : integer := 13;
		DATA_WIDTH    : integer := 2;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CEN : in  STD_LOGIC ;
		CLK : in  STD_LOGIC ;
		WR   : in  STD_LOGIC ;
		CS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		DI   : in  STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0);
		AD  : in  STD_LOGIC_VECTOR (ADDR_WIDTH -1 downto 0);
		DO   : out STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0)
		);
	end component ;

      signal CEN_ipd      : std_ulogic := 'X';
      signal CLK_ipd      : std_ulogic := 'X';
      signal WR_ipd       : std_ulogic := 'X';
      signal CS0_ipd      : std_ulogic := 'X';
      signal CS1_ipd      : std_ulogic := 'X';
      signal RST_ipd      : std_ulogic := 'X';

      signal DI0_ipd      : std_ulogic := 'X';
      signal DI1_ipd      : std_ulogic := 'X';

      signal AD0_ipd      : std_ulogic := 'X';
      signal AD1_ipd      : std_ulogic := 'X';
      signal AD2_ipd      : std_ulogic := 'X';
      signal AD3_ipd      : std_ulogic := 'X';
      signal AD4_ipd      : std_ulogic := 'X';
      signal AD5_ipd      : std_ulogic := 'X';
      signal AD6_ipd      : std_ulogic := 'X';
      signal AD7_ipd      : std_ulogic := 'X';
      signal AD8_ipd      : std_ulogic := 'X';
      signal AD9_ipd      : std_ulogic := 'X';
      signal AD10_ipd     : std_ulogic := 'X';
      signal AD11_ipd     : std_ulogic := 'X';
      signal AD12_ipd     : std_ulogic := 'X';

	signal CS : std_logic_vector (1 downto 0);
	signal DI  : std_logic_vector (1 downto 0);
 	signal AD : std_logic_vector (12 downto 0);
	signal DO  : std_logic_vector (1 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	CS <= CS1_ipd & CS0_ipd;
	DI <= DI1_ipd & DI0_ipd;
	AD <= AD12_ipd & AD11_ipd & AD10_ipd & AD9_ipd & AD8_ipd & AD7_ipd & AD6_ipd & AD5_ipd & AD4_ipd & AD3_ipd & AD2_ipd & AD1_ipd & AD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CEN_ipd, CEN, tipd_CEN);
        VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        VitalWireDelay (WR_ipd, WR, tipd_WR);
        VitalWireDelay (CS0_ipd, CS0, tipd_CS0);
        VitalWireDelay (CS1_ipd, CS1, tipd_CS1);
        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);

        VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
        VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
        VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
        VitalWireDelay (AD3_ipd, AD3, tipd_AD3);
        VitalWireDelay (AD4_ipd, AD4, tipd_AD4);
        VitalWireDelay (AD5_ipd, AD5, tipd_AD5);
        VitalWireDelay (AD6_ipd, AD6, tipd_AD6);
        VitalWireDelay (AD7_ipd, AD7, tipd_AD7);
        VitalWireDelay (AD8_ipd, AD8, tipd_AD8);
        VitalWireDelay (AD9_ipd, AD9, tipd_AD9);
        VitalWireDelay (AD10_ipd, AD10, tipd_AD10);
        VitalWireDelay (AD11_ipd, AD11, tipd_AD11);
        VitalWireDelay (AD12_ipd, AD12, tipd_AD12);

      end block;

      --------------------
      -- RAMB16KA_X2 Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CEN_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_WR_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_CS0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_CS1_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_DI0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI1_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_AD0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD3_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD4_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD5_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD6_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD7_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD8_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD9_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD10_CLK_posedge   : std_ulogic  := '0';
        variable Tviol_AD11_CLK_posedge   : std_ulogic  := '0';
        variable Tviol_AD12_CLK_posedge   : std_ulogic  := '0';

        variable Tviol_RST_CLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CEN_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_AD0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD4_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD5_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD6_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD7_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD8_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD9_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD10_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD11_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD12_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_CLK_posedge_posedge  : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLK       : std_ulogic := '0';
        variable PInfo_CLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CEN_CLK_posedge,
          TimingData              => Tmkr_CEN_CLK_posedge,
          TestSignal              => CEN_ipd,
          TestSignalName          => "CEN",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CEN_CLK_noedge_posedge,
          SetupLow                => tsetup_CEN_CLK_noedge_posedge,
          HoldLow                 => thold_CEN_CLK_noedge_posedge,
          HoldHigh                => thold_CEN_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_CLK_posedge,
          TimingData              => Tmkr_WR_CLK_posedge,
          TestSignal              => WR_ipd,
          TestSignalName          => "WR",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_CLK_noedge_posedge,
          HoldLow                 => thold_WR_CLK_noedge_posedge,
          HoldHigh                => thold_WR_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS0_CLK_posedge,
          TimingData              => Tmkr_CS0_CLK_posedge,
          TestSignal              => CS0_ipd,
          TestSignalName          => "CS0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS0_CLK_noedge_posedge,
          SetupLow                => tsetup_CS0_CLK_noedge_posedge,
          HoldLow                 => thold_CS0_CLK_noedge_posedge,
          HoldHigh                => thold_CS0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS1_CLK_posedge,
          TimingData              => Tmkr_CS1_CLK_posedge,
          TestSignal              => CS1_ipd,
          TestSignalName          => "CS1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS1_CLK_noedge_posedge,
          SetupLow                => tsetup_CS1_CLK_noedge_posedge,
          HoldLow                 => thold_CS1_CLK_noedge_posedge,
          HoldHigh                => thold_CS1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_CLK_posedge,
          TimingData              => Tmkr_DI0_CLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_CLK_noedge_posedge,
          SetupLow                => tsetup_DI0_CLK_noedge_posedge,
          HoldLow                 => thold_DI0_CLK_noedge_posedge,
          HoldHigh                => thold_DI0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_CLK_posedge,
          TimingData              => Tmkr_DI1_CLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_CLK_noedge_posedge,
          SetupLow                => tsetup_DI1_CLK_noedge_posedge,
          HoldLow                 => thold_DI1_CLK_noedge_posedge,
          HoldHigh                => thold_DI1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_CLK_posedge,
          TimingData              => Tmkr_AD0_CLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_CLK_noedge_posedge,
          SetupLow                => tsetup_AD0_CLK_noedge_posedge,
          HoldLow                 => thold_AD0_CLK_noedge_posedge,
          HoldHigh                => thold_AD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_CLK_posedge,
          TimingData              => Tmkr_AD1_CLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_CLK_noedge_posedge,
          SetupLow                => tsetup_AD1_CLK_noedge_posedge,
          HoldLow                 => thold_AD1_CLK_noedge_posedge,
          HoldHigh                => thold_AD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_CLK_posedge,
          TimingData              => Tmkr_AD2_CLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_CLK_noedge_posedge,
          SetupLow                => tsetup_AD2_CLK_noedge_posedge,
          HoldLow                 => thold_AD2_CLK_noedge_posedge,
          HoldHigh                => thold_AD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_CLK_posedge,
          TimingData              => Tmkr_AD3_CLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_CLK_noedge_posedge,
          SetupLow                => tsetup_AD3_CLK_noedge_posedge,
          HoldLow                 => thold_AD3_CLK_noedge_posedge,
          HoldHigh                => thold_AD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD4_CLK_posedge,
          TimingData              => Tmkr_AD4_CLK_posedge,
          TestSignal              => AD4_ipd,
          TestSignalName          => "AD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD4_CLK_noedge_posedge,
          SetupLow                => tsetup_AD4_CLK_noedge_posedge,
          HoldLow                 => thold_AD4_CLK_noedge_posedge,
          HoldHigh                => thold_AD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD5_CLK_posedge,
          TimingData              => Tmkr_AD5_CLK_posedge,
          TestSignal              => AD5_ipd,
          TestSignalName          => "AD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD5_CLK_noedge_posedge,
          SetupLow                => tsetup_AD5_CLK_noedge_posedge,
          HoldLow                 => thold_AD5_CLK_noedge_posedge,
          HoldHigh                => thold_AD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD6_CLK_posedge,
          TimingData              => Tmkr_AD6_CLK_posedge,
          TestSignal              => AD6_ipd,
          TestSignalName          => "AD6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD6_CLK_noedge_posedge,
          SetupLow                => tsetup_AD6_CLK_noedge_posedge,
          HoldLow                 => thold_AD6_CLK_noedge_posedge,
          HoldHigh                => thold_AD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD7_CLK_posedge,
          TimingData              => Tmkr_AD7_CLK_posedge,
          TestSignal              => AD7_ipd,
          TestSignalName          => "AD7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD7_CLK_noedge_posedge,
          SetupLow                => tsetup_AD7_CLK_noedge_posedge,
          HoldLow                 => thold_AD7_CLK_noedge_posedge,
          HoldHigh                => thold_AD7_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD8_CLK_posedge,
          TimingData              => Tmkr_AD8_CLK_posedge,
          TestSignal              => AD8_ipd,
          TestSignalName          => "AD8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD8_CLK_noedge_posedge,
          SetupLow                => tsetup_AD8_CLK_noedge_posedge,
          HoldLow                 => thold_AD8_CLK_noedge_posedge,
          HoldHigh                => thold_AD8_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD9_CLK_posedge,
          TimingData              => Tmkr_AD9_CLK_posedge,
          TestSignal              => AD9_ipd,
          TestSignalName          => "AD9",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD9_CLK_noedge_posedge,
          SetupLow                => tsetup_AD9_CLK_noedge_posedge,
          HoldLow                 => thold_AD9_CLK_noedge_posedge,
          HoldHigh                => thold_AD9_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD10_CLK_posedge,
          TimingData              => Tmkr_AD10_CLK_posedge,
          TestSignal              => AD10_ipd,
          TestSignalName          => "AD10",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD10_CLK_noedge_posedge,
          SetupLow                => tsetup_AD10_CLK_noedge_posedge,
          HoldLow                 => thold_AD10_CLK_noedge_posedge,
          HoldHigh                => thold_AD10_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD11_CLK_posedge,
          TimingData              => Tmkr_AD11_CLK_posedge,
          TestSignal              => AD11_ipd,
          TestSignalName          => "AD11",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD11_CLK_noedge_posedge,
          SetupLow                => tsetup_AD11_CLK_noedge_posedge,
          HoldLow                 => thold_AD11_CLK_noedge_posedge,
          HoldHigh                => thold_AD11_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD12_CLK_posedge,
          TimingData              => Tmkr_AD12_CLK_posedge,
          TestSignal              => AD12_ipd,
          TestSignalName          => "AD12",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD12_CLK_noedge_posedge,
          SetupLow                => tsetup_AD12_CLK_noedge_posedge,
          HoldLow                 => thold_AD12_CLK_noedge_posedge,
          HoldHigh                => thold_AD12_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_CLK_posedge_posedge,
          TimingData              => Tmkr_RST_CLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_CLK_posedge_posedge,
          Removal                 => thold_RST_CLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_X2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CEN_CLK_posedge or Tviol_WR_CLK_posedge or 
                 Tviol_DI0_CLK_posedge or Tviol_DI1_CLK_posedge or 
                 Tviol_CS0_CLK_posedge or Tviol_CS1_CLK_posedge or 
                 Tviol_AD0_CLK_posedge or Tviol_AD1_CLK_posedge or 
                 Tviol_AD2_CLK_posedge or Tviol_AD3_CLK_posedge or 
                 Tviol_AD4_CLK_posedge or Tviol_AD5_CLK_posedge or 
                 Tviol_AD6_CLK_posedge or Tviol_AD7_CLK_posedge or 
                 Tviol_AD8_CLK_posedge or Tviol_AD9_CLK_posedge or 
                 Tviol_AD10_CLK_posedge or Tviol_AD11_CLK_posedge or 
                 Tviol_AD12_CLK_posedge or Tviol_DI0_CLK_posedge or
                 Pviol_CLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------


	wait on CEN_ipd, CLK_ipd, WR_ipd, CS,  RST_ipd, DI, AD, DO;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO0, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO0, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO0, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO0, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO0, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO0, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO0, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO0, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO0, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO0, TRUE),
               10 => (AD10_ipd'last_event, tpd_AD10_DO0, TRUE),
               11 => (AD11_ipd'last_event, tpd_AD11_DO0, TRUE),
               12 => (AD12_ipd'last_event, tpd_AD12_DO0, TRUE),
               13 => (CLK_ipd'last_event, tpd_CLK_DO0, TRUE),
               14 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO1, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO1, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO1, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO1, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO1, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO1, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO1, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO1, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO1, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO1, TRUE),
               10 => (AD10_ipd'last_event, tpd_AD10_DO1, TRUE),
               11 => (AD11_ipd'last_event, tpd_AD11_DO1, TRUE),
               12 => (AD12_ipd'last_event, tpd_AD12_DO1, TRUE),
               13 => (CLK_ipd'last_event, tpd_CLK_DO1, TRUE),
               14 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;



	SPRAMA_INST: SC_SPRAMA_16K
	   generic map (
		ADDR_WIDTH    => 13,
		DATA_WIDTH    => 2,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CEN => CEN_ipd,
		CLK => CLK_ipd,
		WR  => WR_ipd,
		CS  => CS,
		RST => RST_ipd,
		DI  => DI,
		AD  => AD,
		DO  => DO
		);

end VITAL;

configuration CFG_RAMB16KA_X2_VITAL of RAMB16KA_X2 is
   for VITAL
   end for;
end CFG_RAMB16KA_X2_VITAL;



----- CELL RAMB16KA_X4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_X4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_AD0_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD10_DO0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD11_DO0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO0                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD10_DO1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD11_DO1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO1                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD10_DO2                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD11_DO2                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO2                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD10_DO3                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD11_DO3                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO3                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tsetup_WR_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_CEN_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CEN_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD4_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD4_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD5_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD5_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD6_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD6_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD7_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD7_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD8_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD8_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD9_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD9_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD10_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD10_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD11_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD11_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RST_CLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_CLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLK_posedge                  :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_CEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD8                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD9                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD10                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD11                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CEN                            :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      WR                             :	in    STD_ULOGIC;
      CS0                            :	in    STD_ULOGIC;
      CS1                            :	in    STD_ULOGIC;
      RST                            :	in    STD_ULOGIC;
      DI0                            :	in    STD_ULOGIC;
      DI1                            :	in    STD_ULOGIC;
      DI2                            :	in    STD_ULOGIC;
      DI3                            :	in    STD_ULOGIC;
      AD0                            :	in    STD_ULOGIC;
      AD1                            :	in    STD_ULOGIC;
      AD2                            :	in    STD_ULOGIC;
      AD3                            :	in    STD_ULOGIC;
      AD4                            :	in    STD_ULOGIC;
      AD5                            :	in    STD_ULOGIC;
      AD6                            :	in    STD_ULOGIC;
      AD7                            :	in    STD_ULOGIC;
      AD8                            :	in    STD_ULOGIC;
      AD9                            :	in    STD_ULOGIC;
      AD10                           :	in    STD_ULOGIC;
      AD11                           :	in    STD_ULOGIC;
      DO0                            :	out   STD_ULOGIC;
      DO1                            :	out   STD_ULOGIC;
      DO2                            :	out   STD_ULOGIC;
      DO3                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_X4 : entity is FALSE;
end RAMB16KA_X4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_X4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_SPRAMA_16K
	   generic (
		ADDR_WIDTH    : integer := 12;
		DATA_WIDTH    : integer := 4;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CEN : in  STD_LOGIC ;
		CLK : in  STD_LOGIC ;
		WR   : in  STD_LOGIC ;
		CS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		DI   : in  STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0);
		AD  : in  STD_LOGIC_VECTOR (ADDR_WIDTH -1 downto 0);
		DO   : out STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0)
		);
	end component ;

      signal CEN_ipd      : std_ulogic := 'X';
      signal CLK_ipd      : std_ulogic := 'X';
      signal WR_ipd       : std_ulogic := 'X';
      signal CS0_ipd      : std_ulogic := 'X';
      signal CS1_ipd      : std_ulogic := 'X';
      signal RST_ipd      : std_ulogic := 'X';

      signal DI0_ipd      : std_ulogic := 'X';
      signal DI1_ipd      : std_ulogic := 'X';
      signal DI2_ipd      : std_ulogic := 'X';
      signal DI3_ipd      : std_ulogic := 'X';

      signal AD0_ipd      : std_ulogic := 'X';
      signal AD1_ipd      : std_ulogic := 'X';
      signal AD2_ipd      : std_ulogic := 'X';
      signal AD3_ipd      : std_ulogic := 'X';
      signal AD4_ipd      : std_ulogic := 'X';
      signal AD5_ipd      : std_ulogic := 'X';
      signal AD6_ipd      : std_ulogic := 'X';
      signal AD7_ipd      : std_ulogic := 'X';
      signal AD8_ipd      : std_ulogic := 'X';
      signal AD9_ipd      : std_ulogic := 'X';
      signal AD10_ipd     : std_ulogic := 'X';
      signal AD11_ipd     : std_ulogic := 'X';

	signal CS : std_logic_vector (1 downto 0);
	signal DI  : std_logic_vector (3 downto 0);
 	signal AD : std_logic_vector (11 downto 0);
	signal DO  : std_logic_vector (3 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	CS <= CS1_ipd & CS0_ipd;
	DI <= DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd;
	AD <= AD11_ipd & AD10_ipd & AD9_ipd & AD8_ipd & AD7_ipd & AD6_ipd & AD5_ipd & AD4_ipd & AD3_ipd & AD2_ipd & AD1_ipd & AD0_ipd;


  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CEN_ipd, CEN, tipd_CEN);
        VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        VitalWireDelay (WR_ipd, WR, tipd_WR);
        VitalWireDelay (CS0_ipd, CS0, tipd_CS0);
        VitalWireDelay (CS1_ipd, CS1, tipd_CS1);
        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);

        VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
        VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
        VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
        VitalWireDelay (AD3_ipd, AD3, tipd_AD3);
        VitalWireDelay (AD4_ipd, AD4, tipd_AD4);
        VitalWireDelay (AD5_ipd, AD5, tipd_AD5);
        VitalWireDelay (AD6_ipd, AD6, tipd_AD6);
        VitalWireDelay (AD7_ipd, AD7, tipd_AD7);
        VitalWireDelay (AD8_ipd, AD8, tipd_AD8);
        VitalWireDelay (AD9_ipd, AD9, tipd_AD9);
        VitalWireDelay (AD10_ipd, AD10, tipd_AD10);
        VitalWireDelay (AD11_ipd, AD11, tipd_AD11);

      end block;

      --------------------
      -- RAMB16KA_X4 Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CEN_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_WR_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_CS0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_CS1_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_DI0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI3_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_AD0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD3_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD4_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD5_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD6_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD7_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD8_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD9_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD10_CLK_posedge   : std_ulogic  := '0';
        variable Tviol_AD11_CLK_posedge   : std_ulogic  := '0';

        variable Tviol_RST_CLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CEN_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_AD0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD4_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD5_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD6_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD7_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD8_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD9_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD10_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD11_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_CLK_posedge_posedge  : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLK       : std_ulogic := '0';
        variable PInfo_CLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CEN_CLK_posedge,
          TimingData              => Tmkr_CEN_CLK_posedge,
          TestSignal              => CEN_ipd,
          TestSignalName          => "CEN",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CEN_CLK_noedge_posedge,
          SetupLow                => tsetup_CEN_CLK_noedge_posedge,
          HoldLow                 => thold_CEN_CLK_noedge_posedge,
          HoldHigh                => thold_CEN_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_CLK_posedge,
          TimingData              => Tmkr_WR_CLK_posedge,
          TestSignal              => WR_ipd,
          TestSignalName          => "WR",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_CLK_noedge_posedge,
          HoldLow                 => thold_WR_CLK_noedge_posedge,
          HoldHigh                => thold_WR_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS0_CLK_posedge,
          TimingData              => Tmkr_CS0_CLK_posedge,
          TestSignal              => CS0_ipd,
          TestSignalName          => "CS0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS0_CLK_noedge_posedge,
          SetupLow                => tsetup_CS0_CLK_noedge_posedge,
          HoldLow                 => thold_CS0_CLK_noedge_posedge,
          HoldHigh                => thold_CS0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS1_CLK_posedge,
          TimingData              => Tmkr_CS1_CLK_posedge,
          TestSignal              => CS1_ipd,
          TestSignalName          => "CS1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS1_CLK_noedge_posedge,
          SetupLow                => tsetup_CS1_CLK_noedge_posedge,
          HoldLow                 => thold_CS1_CLK_noedge_posedge,
          HoldHigh                => thold_CS1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_CLK_posedge,
          TimingData              => Tmkr_DI0_CLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_CLK_noedge_posedge,
          SetupLow                => tsetup_DI0_CLK_noedge_posedge,
          HoldLow                 => thold_DI0_CLK_noedge_posedge,
          HoldHigh                => thold_DI0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_CLK_posedge,
          TimingData              => Tmkr_DI1_CLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_CLK_noedge_posedge,
          SetupLow                => tsetup_DI1_CLK_noedge_posedge,
          HoldLow                 => thold_DI1_CLK_noedge_posedge,
          HoldHigh                => thold_DI1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_CLK_posedge,
          TimingData              => Tmkr_DI2_CLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_CLK_noedge_posedge,
          SetupLow                => tsetup_DI2_CLK_noedge_posedge,
          HoldLow                 => thold_DI2_CLK_noedge_posedge,
          HoldHigh                => thold_DI2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_CLK_posedge,
          TimingData              => Tmkr_DI3_CLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_CLK_noedge_posedge,
          SetupLow                => tsetup_DI3_CLK_noedge_posedge,
          HoldLow                 => thold_DI3_CLK_noedge_posedge,
          HoldHigh                => thold_DI3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_CLK_posedge,
          TimingData              => Tmkr_AD0_CLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_CLK_noedge_posedge,
          SetupLow                => tsetup_AD0_CLK_noedge_posedge,
          HoldLow                 => thold_AD0_CLK_noedge_posedge,
          HoldHigh                => thold_AD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_CLK_posedge,
          TimingData              => Tmkr_AD1_CLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_CLK_noedge_posedge,
          SetupLow                => tsetup_AD1_CLK_noedge_posedge,
          HoldLow                 => thold_AD1_CLK_noedge_posedge,
          HoldHigh                => thold_AD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_CLK_posedge,
          TimingData              => Tmkr_AD2_CLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_CLK_noedge_posedge,
          SetupLow                => tsetup_AD2_CLK_noedge_posedge,
          HoldLow                 => thold_AD2_CLK_noedge_posedge,
          HoldHigh                => thold_AD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_CLK_posedge,
          TimingData              => Tmkr_AD3_CLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_CLK_noedge_posedge,
          SetupLow                => tsetup_AD3_CLK_noedge_posedge,
          HoldLow                 => thold_AD3_CLK_noedge_posedge,
          HoldHigh                => thold_AD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD4_CLK_posedge,
          TimingData              => Tmkr_AD4_CLK_posedge,
          TestSignal              => AD4_ipd,
          TestSignalName          => "AD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD4_CLK_noedge_posedge,
          SetupLow                => tsetup_AD4_CLK_noedge_posedge,
          HoldLow                 => thold_AD4_CLK_noedge_posedge,
          HoldHigh                => thold_AD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD5_CLK_posedge,
          TimingData              => Tmkr_AD5_CLK_posedge,
          TestSignal              => AD5_ipd,
          TestSignalName          => "AD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD5_CLK_noedge_posedge,
          SetupLow                => tsetup_AD5_CLK_noedge_posedge,
          HoldLow                 => thold_AD5_CLK_noedge_posedge,
          HoldHigh                => thold_AD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD6_CLK_posedge,
          TimingData              => Tmkr_AD6_CLK_posedge,
          TestSignal              => AD6_ipd,
          TestSignalName          => "AD6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD6_CLK_noedge_posedge,
          SetupLow                => tsetup_AD6_CLK_noedge_posedge,
          HoldLow                 => thold_AD6_CLK_noedge_posedge,
          HoldHigh                => thold_AD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD7_CLK_posedge,
          TimingData              => Tmkr_AD7_CLK_posedge,
          TestSignal              => AD7_ipd,
          TestSignalName          => "AD7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD7_CLK_noedge_posedge,
          SetupLow                => tsetup_AD7_CLK_noedge_posedge,
          HoldLow                 => thold_AD7_CLK_noedge_posedge,
          HoldHigh                => thold_AD7_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD8_CLK_posedge,
          TimingData              => Tmkr_AD8_CLK_posedge,
          TestSignal              => AD8_ipd,
          TestSignalName          => "AD8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD8_CLK_noedge_posedge,
          SetupLow                => tsetup_AD8_CLK_noedge_posedge,
          HoldLow                 => thold_AD8_CLK_noedge_posedge,
          HoldHigh                => thold_AD8_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD9_CLK_posedge,
          TimingData              => Tmkr_AD9_CLK_posedge,
          TestSignal              => AD9_ipd,
          TestSignalName          => "AD9",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD9_CLK_noedge_posedge,
          SetupLow                => tsetup_AD9_CLK_noedge_posedge,
          HoldLow                 => thold_AD9_CLK_noedge_posedge,
          HoldHigh                => thold_AD9_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD10_CLK_posedge,
          TimingData              => Tmkr_AD10_CLK_posedge,
          TestSignal              => AD10_ipd,
          TestSignalName          => "AD10",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD10_CLK_noedge_posedge,
          SetupLow                => tsetup_AD10_CLK_noedge_posedge,
          HoldLow                 => thold_AD10_CLK_noedge_posedge,
          HoldHigh                => thold_AD10_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD11_CLK_posedge,
          TimingData              => Tmkr_AD11_CLK_posedge,
          TestSignal              => AD11_ipd,
          TestSignalName          => "AD11",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD11_CLK_noedge_posedge,
          SetupLow                => tsetup_AD11_CLK_noedge_posedge,
          HoldLow                 => thold_AD11_CLK_noedge_posedge,
          HoldHigh                => thold_AD11_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_CLK_posedge_posedge,
          TimingData              => Tmkr_RST_CLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_CLK_posedge_posedge,
          Removal                 => thold_RST_CLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_X4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CEN_CLK_posedge or Tviol_WR_CLK_posedge or 
                 Tviol_DI0_CLK_posedge or Tviol_DI1_CLK_posedge or 
                 Tviol_DI2_CLK_posedge or Tviol_DI3_CLK_posedge or 
                 Tviol_CS0_CLK_posedge or Tviol_CS1_CLK_posedge or 
                 Tviol_AD0_CLK_posedge or Tviol_AD1_CLK_posedge or 
                 Tviol_AD2_CLK_posedge or Tviol_AD3_CLK_posedge or 
                 Tviol_AD4_CLK_posedge or Tviol_AD5_CLK_posedge or 
                 Tviol_AD6_CLK_posedge or Tviol_AD7_CLK_posedge or 
                 Tviol_AD8_CLK_posedge or Tviol_AD9_CLK_posedge or 
                 Tviol_AD10_CLK_posedge or Tviol_AD11_CLK_posedge or 
                 Tviol_DI0_CLK_posedge or
                 Pviol_CLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------
	wait on CEN_ipd, CLK_ipd, WR_ipd, CS,  RST_ipd, DI, AD;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO0, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO0, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO0, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO0, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO0, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO0, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO0, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO0, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO0, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO0, TRUE),
              10 => (AD10_ipd'last_event, tpd_AD10_DO0, TRUE),
              11 => (AD11_ipd'last_event, tpd_AD11_DO0, TRUE),
              12 => (CLK_ipd'last_event, tpd_CLK_DO0, TRUE),
              13 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO1, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO1, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO1, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO1, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO1, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO1, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO1, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO1, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO1, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO1, TRUE),
              10 => (AD10_ipd'last_event, tpd_AD10_DO1, TRUE),
              11 => (AD11_ipd'last_event, tpd_AD11_DO1, TRUE),
              12 => (CLK_ipd'last_event, tpd_CLK_DO1, TRUE),
              13 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO2, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO2, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO2, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO2, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO2, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO2, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO2, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO2, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO2, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO2, TRUE),
              10 => (AD10_ipd'last_event, tpd_AD10_DO2, TRUE),
              11 => (AD11_ipd'last_event, tpd_AD11_DO2, TRUE),
              12 => (CLK_ipd'last_event, tpd_CLK_DO2, TRUE),
              13 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO3, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO3, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO3, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO3, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO3, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO3, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO3, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO3, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO3, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO3, TRUE),
              10 => (AD10_ipd'last_event, tpd_AD10_DO3, TRUE),
              11 => (AD11_ipd'last_event, tpd_AD11_DO3, TRUE),
              12 => (CLK_ipd'last_event, tpd_CLK_DO3, TRUE),
              13 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;



	SPRAMA_INST: SC_SPRAMA_16K
	   generic map (
		ADDR_WIDTH    => 12,
		DATA_WIDTH    => 4,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CEN => CEN_ipd,
		CLK => CLK_ipd,
		WR  => WR_ipd,
		CS  => CS,
		RST => RST_ipd,
		DI  => DI,
		AD  => AD,
		DO  => DO
		);

end VITAL;

configuration CFG_RAMB16KA_X4_VITAL of RAMB16KA_X4 is
   for VITAL
   end for;
end CFG_RAMB16KA_X4_VITAL;



----- CELL RAMB16KA_X8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_X8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_AD0_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD10_DO0                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO0                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD10_DO1                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO1                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD10_DO2                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO2                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD10_DO3                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO3                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD10_DO4                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO4                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD10_DO5                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO5                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD10_DO6                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO6                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD10_DO7                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO7                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tsetup_WR_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_CEN_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CEN_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI4_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI5_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI6_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI7_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD4_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD4_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD5_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD5_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD6_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD6_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD7_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD7_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD8_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD8_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD9_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD9_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD10_CLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD10_CLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      trecovery_RST_CLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_CLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLK_posedge                  :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_CEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD8                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD9                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD10                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CEN                            :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      WR                             :	in    STD_ULOGIC;
      CS0                            :	in    STD_ULOGIC;
      CS1                            :	in    STD_ULOGIC;
      RST                            :	in    STD_ULOGIC;
      DI0                            :	in    STD_ULOGIC;
      DI1                            :	in    STD_ULOGIC;
      DI2                            :	in    STD_ULOGIC;
      DI3                            :	in    STD_ULOGIC;
      DI4                            :	in    STD_ULOGIC;
      DI5                            :	in    STD_ULOGIC;
      DI6                            :	in    STD_ULOGIC;
      DI7                            :	in    STD_ULOGIC;
      AD0                            :	in    STD_ULOGIC;
      AD1                            :	in    STD_ULOGIC;
      AD2                            :	in    STD_ULOGIC;
      AD3                            :	in    STD_ULOGIC;
      AD4                            :	in    STD_ULOGIC;
      AD5                            :	in    STD_ULOGIC;
      AD6                            :	in    STD_ULOGIC;
      AD7                            :	in    STD_ULOGIC;
      AD8                            :	in    STD_ULOGIC;
      AD9                            :	in    STD_ULOGIC;
      AD10                           :	in    STD_ULOGIC;
      DO0                            :	out   STD_ULOGIC;
      DO1                            :	out   STD_ULOGIC;
      DO2                            :	out   STD_ULOGIC;
      DO3                            :	out   STD_ULOGIC;
      DO4                            :	out   STD_ULOGIC;
      DO5                            :	out   STD_ULOGIC;
      DO6                            :	out   STD_ULOGIC;
      DO7                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_X8 : entity is FALSE;
end RAMB16KA_X8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_X8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_SPRAMA_16K
	   generic (
		ADDR_WIDTH    : integer := 11;
		DATA_WIDTH    : integer := 8;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CEN : in  STD_LOGIC ;
		CLK : in  STD_LOGIC ;
		WR   : in  STD_LOGIC ;
		CS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		DI   : in  STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0);
		AD  : in  STD_LOGIC_VECTOR (ADDR_WIDTH -1 downto 0);
		DO   : out STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0)
		);
	end component ;

      signal CEN_ipd      : std_ulogic := 'X';
      signal CLK_ipd      : std_ulogic := 'X';
      signal WR_ipd       : std_ulogic := 'X';
      signal CS0_ipd      : std_ulogic := 'X';
      signal CS1_ipd      : std_ulogic := 'X';
      signal RST_ipd      : std_ulogic := 'X';

      signal DI0_ipd      : std_ulogic := 'X';
      signal DI1_ipd      : std_ulogic := 'X';
      signal DI2_ipd      : std_ulogic := 'X';
      signal DI3_ipd      : std_ulogic := 'X';
      signal DI4_ipd      : std_ulogic := 'X';
      signal DI5_ipd      : std_ulogic := 'X';
      signal DI6_ipd      : std_ulogic := 'X';
      signal DI7_ipd      : std_ulogic := 'X';

      signal AD0_ipd      : std_ulogic := 'X';
      signal AD1_ipd      : std_ulogic := 'X';
      signal AD2_ipd      : std_ulogic := 'X';
      signal AD3_ipd      : std_ulogic := 'X';
      signal AD4_ipd      : std_ulogic := 'X';
      signal AD5_ipd      : std_ulogic := 'X';
      signal AD6_ipd      : std_ulogic := 'X';
      signal AD7_ipd      : std_ulogic := 'X';
      signal AD8_ipd      : std_ulogic := 'X';
      signal AD9_ipd      : std_ulogic := 'X';
      signal AD10_ipd     : std_ulogic := 'X';

	signal CS : std_logic_vector (1 downto 0);
	signal DI  : std_logic_vector (7 downto 0);
 	signal AD : std_logic_vector (10 downto 0);
	signal DO  : std_logic_vector (7 downto 0);
      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	CS <= CS1_ipd & CS0_ipd;
	DI <= DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd;
	AD <= AD10_ipd & AD9_ipd & AD8_ipd & AD7_ipd & AD6_ipd & AD5_ipd & AD4_ipd & AD3_ipd & AD2_ipd & AD1_ipd & AD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CEN_ipd, CEN, tipd_CEN);
        VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        VitalWireDelay (WR_ipd, WR, tipd_WR);
        VitalWireDelay (CS0_ipd, CS0, tipd_CS0);
        VitalWireDelay (CS1_ipd, CS1, tipd_CS1);
        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);

        VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
        VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
        VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
        VitalWireDelay (AD3_ipd, AD3, tipd_AD3);
        VitalWireDelay (AD4_ipd, AD4, tipd_AD4);
        VitalWireDelay (AD5_ipd, AD5, tipd_AD5);
        VitalWireDelay (AD6_ipd, AD6, tipd_AD6);
        VitalWireDelay (AD7_ipd, AD7, tipd_AD7);
        VitalWireDelay (AD8_ipd, AD8, tipd_AD8);
        VitalWireDelay (AD9_ipd, AD9, tipd_AD9);
        VitalWireDelay (AD10_ipd, AD10, tipd_AD10);

      end block;

      --------------------
      -- RAMB16KA_X8 Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CEN_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_WR_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_CS0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_CS1_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_DI0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI3_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI4_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI5_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI6_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI7_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_AD0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD3_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD4_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD5_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD6_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD7_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD8_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD9_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD10_CLK_posedge   : std_ulogic  := '0';

        variable Tviol_RST_CLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CEN_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_AD0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD4_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD5_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD6_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD7_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD8_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD9_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD10_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_CLK_posedge_posedge  : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLK       : std_ulogic := '0';
        variable PInfo_CLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CEN_CLK_posedge,
          TimingData              => Tmkr_CEN_CLK_posedge,
          TestSignal              => CEN_ipd,
          TestSignalName          => "CEN",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CEN_CLK_noedge_posedge,
          SetupLow                => tsetup_CEN_CLK_noedge_posedge,
          HoldLow                 => thold_CEN_CLK_noedge_posedge,
          HoldHigh                => thold_CEN_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_CLK_posedge,
          TimingData              => Tmkr_WR_CLK_posedge,
          TestSignal              => WR_ipd,
          TestSignalName          => "WR",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_CLK_noedge_posedge,
          HoldLow                 => thold_WR_CLK_noedge_posedge,
          HoldHigh                => thold_WR_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS0_CLK_posedge,
          TimingData              => Tmkr_CS0_CLK_posedge,
          TestSignal              => CS0_ipd,
          TestSignalName          => "CS0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS0_CLK_noedge_posedge,
          SetupLow                => tsetup_CS0_CLK_noedge_posedge,
          HoldLow                 => thold_CS0_CLK_noedge_posedge,
          HoldHigh                => thold_CS0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS1_CLK_posedge,
          TimingData              => Tmkr_CS1_CLK_posedge,
          TestSignal              => CS1_ipd,
          TestSignalName          => "CS1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS1_CLK_noedge_posedge,
          SetupLow                => tsetup_CS1_CLK_noedge_posedge,
          HoldLow                 => thold_CS1_CLK_noedge_posedge,
          HoldHigh                => thold_CS1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_CLK_posedge,
          TimingData              => Tmkr_DI0_CLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_CLK_noedge_posedge,
          SetupLow                => tsetup_DI0_CLK_noedge_posedge,
          HoldLow                 => thold_DI0_CLK_noedge_posedge,
          HoldHigh                => thold_DI0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_CLK_posedge,
          TimingData              => Tmkr_DI1_CLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_CLK_noedge_posedge,
          SetupLow                => tsetup_DI1_CLK_noedge_posedge,
          HoldLow                 => thold_DI1_CLK_noedge_posedge,
          HoldHigh                => thold_DI1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_CLK_posedge,
          TimingData              => Tmkr_DI2_CLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_CLK_noedge_posedge,
          SetupLow                => tsetup_DI2_CLK_noedge_posedge,
          HoldLow                 => thold_DI2_CLK_noedge_posedge,
          HoldHigh                => thold_DI2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_CLK_posedge,
          TimingData              => Tmkr_DI3_CLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_CLK_noedge_posedge,
          SetupLow                => tsetup_DI3_CLK_noedge_posedge,
          HoldLow                 => thold_DI3_CLK_noedge_posedge,
          HoldHigh                => thold_DI3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_CLK_posedge,
          TimingData              => Tmkr_DI4_CLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_CLK_noedge_posedge,
          SetupLow                => tsetup_DI4_CLK_noedge_posedge,
          HoldLow                 => thold_DI4_CLK_noedge_posedge,
          HoldHigh                => thold_DI4_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_CLK_posedge,
          TimingData              => Tmkr_DI5_CLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_CLK_noedge_posedge,
          SetupLow                => tsetup_DI5_CLK_noedge_posedge,
          HoldLow                 => thold_DI5_CLK_noedge_posedge,
          HoldHigh                => thold_DI5_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_CLK_posedge,
          TimingData              => Tmkr_DI6_CLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_CLK_noedge_posedge,
          SetupLow                => tsetup_DI6_CLK_noedge_posedge,
          HoldLow                 => thold_DI6_CLK_noedge_posedge,
          HoldHigh                => thold_DI6_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_CLK_posedge,
          TimingData              => Tmkr_DI7_CLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_CLK_noedge_posedge,
          SetupLow                => tsetup_DI7_CLK_noedge_posedge,
          HoldLow                 => thold_DI7_CLK_noedge_posedge,
          HoldHigh                => thold_DI7_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_CLK_posedge,
          TimingData              => Tmkr_AD0_CLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_CLK_noedge_posedge,
          SetupLow                => tsetup_AD0_CLK_noedge_posedge,
          HoldLow                 => thold_AD0_CLK_noedge_posedge,
          HoldHigh                => thold_AD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_CLK_posedge,
          TimingData              => Tmkr_AD1_CLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_CLK_noedge_posedge,
          SetupLow                => tsetup_AD1_CLK_noedge_posedge,
          HoldLow                 => thold_AD1_CLK_noedge_posedge,
          HoldHigh                => thold_AD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_CLK_posedge,
          TimingData              => Tmkr_AD2_CLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_CLK_noedge_posedge,
          SetupLow                => tsetup_AD2_CLK_noedge_posedge,
          HoldLow                 => thold_AD2_CLK_noedge_posedge,
          HoldHigh                => thold_AD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_CLK_posedge,
          TimingData              => Tmkr_AD3_CLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_CLK_noedge_posedge,
          SetupLow                => tsetup_AD3_CLK_noedge_posedge,
          HoldLow                 => thold_AD3_CLK_noedge_posedge,
          HoldHigh                => thold_AD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD4_CLK_posedge,
          TimingData              => Tmkr_AD4_CLK_posedge,
          TestSignal              => AD4_ipd,
          TestSignalName          => "AD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD4_CLK_noedge_posedge,
          SetupLow                => tsetup_AD4_CLK_noedge_posedge,
          HoldLow                 => thold_AD4_CLK_noedge_posedge,
          HoldHigh                => thold_AD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD5_CLK_posedge,
          TimingData              => Tmkr_AD5_CLK_posedge,
          TestSignal              => AD5_ipd,
          TestSignalName          => "AD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD5_CLK_noedge_posedge,
          SetupLow                => tsetup_AD5_CLK_noedge_posedge,
          HoldLow                 => thold_AD5_CLK_noedge_posedge,
          HoldHigh                => thold_AD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD6_CLK_posedge,
          TimingData              => Tmkr_AD6_CLK_posedge,
          TestSignal              => AD6_ipd,
          TestSignalName          => "AD6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD6_CLK_noedge_posedge,
          SetupLow                => tsetup_AD6_CLK_noedge_posedge,
          HoldLow                 => thold_AD6_CLK_noedge_posedge,
          HoldHigh                => thold_AD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD7_CLK_posedge,
          TimingData              => Tmkr_AD7_CLK_posedge,
          TestSignal              => AD7_ipd,
          TestSignalName          => "AD7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD7_CLK_noedge_posedge,
          SetupLow                => tsetup_AD7_CLK_noedge_posedge,
          HoldLow                 => thold_AD7_CLK_noedge_posedge,
          HoldHigh                => thold_AD7_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD8_CLK_posedge,
          TimingData              => Tmkr_AD8_CLK_posedge,
          TestSignal              => AD8_ipd,
          TestSignalName          => "AD8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD8_CLK_noedge_posedge,
          SetupLow                => tsetup_AD8_CLK_noedge_posedge,
          HoldLow                 => thold_AD8_CLK_noedge_posedge,
          HoldHigh                => thold_AD8_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD9_CLK_posedge,
          TimingData              => Tmkr_AD9_CLK_posedge,
          TestSignal              => AD9_ipd,
          TestSignalName          => "AD9",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD9_CLK_noedge_posedge,
          SetupLow                => tsetup_AD9_CLK_noedge_posedge,
          HoldLow                 => thold_AD9_CLK_noedge_posedge,
          HoldHigh                => thold_AD9_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD10_CLK_posedge,
          TimingData              => Tmkr_AD10_CLK_posedge,
          TestSignal              => AD10_ipd,
          TestSignalName          => "AD10",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD10_CLK_noedge_posedge,
          SetupLow                => tsetup_AD10_CLK_noedge_posedge,
          HoldLow                 => thold_AD10_CLK_noedge_posedge,
          HoldHigh                => thold_AD10_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_CLK_posedge_posedge,
          TimingData              => Tmkr_RST_CLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_CLK_posedge_posedge,
          Removal                 => thold_RST_CLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_X8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CEN_CLK_posedge or Tviol_WR_CLK_posedge or 
                 Tviol_DI0_CLK_posedge or Tviol_DI1_CLK_posedge or 
                 Tviol_DI2_CLK_posedge or Tviol_DI3_CLK_posedge or 
                 Tviol_DI4_CLK_posedge or Tviol_DI5_CLK_posedge or 
                 Tviol_DI6_CLK_posedge or Tviol_DI7_CLK_posedge or 
                 Tviol_CS0_CLK_posedge or Tviol_CS1_CLK_posedge or 
                 Tviol_AD0_CLK_posedge or Tviol_AD1_CLK_posedge or 
                 Tviol_AD2_CLK_posedge or Tviol_AD3_CLK_posedge or 
                 Tviol_AD4_CLK_posedge or Tviol_AD5_CLK_posedge or 
                 Tviol_AD6_CLK_posedge or Tviol_AD7_CLK_posedge or 
                 Tviol_AD8_CLK_posedge or Tviol_AD9_CLK_posedge or 
                 Tviol_AD10_CLK_posedge or Tviol_DI0_CLK_posedge or
                 Pviol_CLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on CEN_ipd, CLK_ipd, WR_ipd, CS,  RST_ipd, DI, AD;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO0, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO0, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO0, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO0, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO0, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO0, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO0, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO0, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO0, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO0, TRUE),
              10 => (AD10_ipd'last_event, tpd_AD10_DO0, TRUE),
              11 => (CLK_ipd'last_event, tpd_CLK_DO0, TRUE),
              12 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO1, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO1, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO1, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO1, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO1, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO1, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO1, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO1, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO1, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO1, TRUE),
              10 => (AD10_ipd'last_event, tpd_AD10_DO1, TRUE),
              11 => (CLK_ipd'last_event, tpd_CLK_DO1, TRUE),
              12 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO2, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO2, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO2, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO2, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO2, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO2, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO2, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO2, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO2, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO2, TRUE),
              10 => (AD10_ipd'last_event, tpd_AD10_DO2, TRUE),
              11 => (CLK_ipd'last_event, tpd_CLK_DO2, TRUE),
              12 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO3, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO3, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO3, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO3, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO3, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO3, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO3, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO3, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO3, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO3, TRUE),
              10 => (AD10_ipd'last_event, tpd_AD10_DO3, TRUE),
              11 => (CLK_ipd'last_event, tpd_CLK_DO3, TRUE),
              12 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO4, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO4, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO4, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO4, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO4, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO4, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO4, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO4, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO4, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO4, TRUE),
              10 => (AD10_ipd'last_event, tpd_AD10_DO4, TRUE),
              11 => (CLK_ipd'last_event, tpd_CLK_DO4, TRUE),
              12 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO5, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO5, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO5, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO5, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO5, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO5, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO5, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO5, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO5, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO5, TRUE),
              10 => (AD10_ipd'last_event, tpd_AD10_DO5, TRUE),
              11 => (CLK_ipd'last_event, tpd_CLK_DO5, TRUE),
              12 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO6, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO6, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO6, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO6, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO6, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO6, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO6, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO6, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO6, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO6, TRUE),
              10 => (AD10_ipd'last_event, tpd_AD10_DO6, TRUE),
              11 => (CLK_ipd'last_event, tpd_CLK_DO6, TRUE),
              12 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO7, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO7, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO7, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO7, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO7, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO7, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO7, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO7, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO7, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO7, TRUE),
              10 => (AD10_ipd'last_event, tpd_AD10_DO7, TRUE),
              11 => (CLK_ipd'last_event, tpd_CLK_DO7, TRUE),
              12 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;



	SPRAMA_INST: SC_SPRAMA_16K
	   generic map (
		ADDR_WIDTH    => 11,
		DATA_WIDTH    => 8,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CEN => CEN_ipd,
		CLK => CLK_ipd,
		WR  => WR_ipd,
		CS  => CS,
		RST => RST_ipd,
		DI  => DI,
		AD  => AD,
		DO  => DO
		);

end VITAL;

configuration CFG_RAMB16KA_X8_VITAL of RAMB16KA_X8 is
   for VITAL
   end for;
end CFG_RAMB16KA_X8_VITAL;



----- CELL RAMB16KA_X16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_X16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_AD0_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO0                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO1                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO2                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO3                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO4                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO5                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO6                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO7                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO8                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO9                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO10                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO11                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD0_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO13                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO14                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD9_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO15                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tsetup_WR_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_CEN_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CEN_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI4_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI5_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI6_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI7_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI8_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI8_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI9_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI9_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI10_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI10_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI11_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI11_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI12_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI12_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI13_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI13_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI14_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI14_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI15_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI15_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD4_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD4_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD5_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD5_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD6_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD6_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD7_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD7_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD8_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD8_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD9_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD9_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_CLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_CLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLK_posedge                  :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_CEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI8                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI9                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI10                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI11                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI12                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI13                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI14                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI15                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD8                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD9                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CEN                            :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      WR                             :	in    STD_ULOGIC;
      CS0                            :	in    STD_ULOGIC;
      CS1                            :	in    STD_ULOGIC;
      RST                            :	in    STD_ULOGIC;
      DI0                            :	in    STD_ULOGIC;
      DI1                            :	in    STD_ULOGIC;
      DI2                            :	in    STD_ULOGIC;
      DI3                            :	in    STD_ULOGIC;
      DI4                            :	in    STD_ULOGIC;
      DI5                            :	in    STD_ULOGIC;
      DI6                            :	in    STD_ULOGIC;
      DI7                            :	in    STD_ULOGIC;
      DI8                            :	in    STD_ULOGIC;
      DI9                            :	in    STD_ULOGIC;
      DI10                           :	in    STD_ULOGIC;
      DI11                           :	in    STD_ULOGIC;
      DI12                           :	in    STD_ULOGIC;
      DI13                            :	in    STD_ULOGIC;
      DI14                            :	in    STD_ULOGIC;
      DI15                            :	in    STD_ULOGIC;
      AD0                            :	in    STD_ULOGIC;
      AD1                            :	in    STD_ULOGIC;
      AD2                            :	in    STD_ULOGIC;
      AD3                            :	in    STD_ULOGIC;
      AD4                            :	in    STD_ULOGIC;
      AD5                            :	in    STD_ULOGIC;
      AD6                            :	in    STD_ULOGIC;
      AD7                            :	in    STD_ULOGIC;
      AD8                            :	in    STD_ULOGIC;
      AD9                            :	in    STD_ULOGIC;
      DO0                            :	out   STD_ULOGIC;
      DO1                            :	out   STD_ULOGIC;
      DO2                            :	out   STD_ULOGIC;
      DO3                            :	out   STD_ULOGIC;
      DO4                            :	out   STD_ULOGIC;
      DO5                            :	out   STD_ULOGIC;
      DO6                            :	out   STD_ULOGIC;
      DO7                            :	out   STD_ULOGIC;
      DO8                            :	out   STD_ULOGIC;
      DO9                            :	out   STD_ULOGIC;
      DO10                           :	out   STD_ULOGIC;
      DO11                           :	out   STD_ULOGIC;
      DO12                           :	out   STD_ULOGIC;
      DO13                           :	out   STD_ULOGIC;
      DO14                           :	out   STD_ULOGIC;
      DO15                           :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_X16 : entity is FALSE;
end RAMB16KA_X16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_X16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_SPRAMA_16K
	   generic (
		ADDR_WIDTH    : integer := 10;
		DATA_WIDTH    : integer := 16;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CEN : in  STD_LOGIC ;
		CLK : in  STD_LOGIC ;
		WR   : in  STD_LOGIC ;
		CS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		DI   : in  STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0);
		AD  : in  STD_LOGIC_VECTOR (ADDR_WIDTH -1 downto 0);
		DO   : out STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0)
		);
	end component ;

      signal CEN_ipd      : std_ulogic := 'X';
      signal CLK_ipd      : std_ulogic := 'X';
      signal WR_ipd       : std_ulogic := 'X';
      signal CS0_ipd      : std_ulogic := 'X';
      signal CS1_ipd      : std_ulogic := 'X';
      signal RST_ipd      : std_ulogic := 'X';

      signal DI0_ipd      : std_ulogic := 'X';
      signal DI1_ipd      : std_ulogic := 'X';
      signal DI2_ipd      : std_ulogic := 'X';
      signal DI3_ipd      : std_ulogic := 'X';
      signal DI4_ipd      : std_ulogic := 'X';
      signal DI5_ipd      : std_ulogic := 'X';
      signal DI6_ipd      : std_ulogic := 'X';
      signal DI7_ipd      : std_ulogic := 'X';
      signal DI8_ipd      : std_ulogic := 'X';
      signal DI9_ipd      : std_ulogic := 'X';
      signal DI10_ipd      : std_ulogic := 'X';
      signal DI11_ipd      : std_ulogic := 'X';
      signal DI12_ipd      : std_ulogic := 'X';
      signal DI13_ipd      : std_ulogic := 'X';
      signal DI14_ipd      : std_ulogic := 'X';
      signal DI15_ipd      : std_ulogic := 'X';

      signal AD0_ipd      : std_ulogic := 'X';
      signal AD1_ipd      : std_ulogic := 'X';
      signal AD2_ipd      : std_ulogic := 'X';
      signal AD3_ipd      : std_ulogic := 'X';
      signal AD4_ipd      : std_ulogic := 'X';
      signal AD5_ipd      : std_ulogic := 'X';
      signal AD6_ipd      : std_ulogic := 'X';
      signal AD7_ipd      : std_ulogic := 'X';
      signal AD8_ipd      : std_ulogic := 'X';
      signal AD9_ipd      : std_ulogic := 'X';

	signal CS : std_logic_vector (1 downto 0);
	signal DI  : std_logic_vector (15 downto 0);
 	signal AD : std_logic_vector (9 downto 0);
	signal DO  : std_logic_vector (15 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 
	CS <= CS1_ipd & CS0_ipd;
	DI <= DI15_ipd & DI14_ipd & DI13_ipd & DI12_ipd & DI11_ipd & DI10_ipd & DI9_ipd & DI8_ipd & DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd;
	AD <= AD9_ipd & AD8_ipd & AD7_ipd & AD6_ipd & AD5_ipd & AD4_ipd & AD3_ipd & AD2_ipd & AD1_ipd & AD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CEN_ipd, CEN, tipd_CEN);
        VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        VitalWireDelay (WR_ipd, WR, tipd_WR);
        VitalWireDelay (CS0_ipd, CS0, tipd_CS0);
        VitalWireDelay (CS1_ipd, CS1, tipd_CS1);
        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);
        VitalWireDelay (DI8_ipd, DI8, tipd_DI8);
        VitalWireDelay (DI9_ipd, DI9, tipd_DI9);
        VitalWireDelay (DI10_ipd, DI10, tipd_DI10);
        VitalWireDelay (DI11_ipd, DI11, tipd_DI11);
        VitalWireDelay (DI12_ipd, DI12, tipd_DI12);
        VitalWireDelay (DI13_ipd, DI13, tipd_DI13);
        VitalWireDelay (DI14_ipd, DI14, tipd_DI14);
        VitalWireDelay (DI15_ipd, DI15, tipd_DI15);

        VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
        VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
        VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
        VitalWireDelay (AD3_ipd, AD3, tipd_AD3);
        VitalWireDelay (AD4_ipd, AD4, tipd_AD4);
        VitalWireDelay (AD5_ipd, AD5, tipd_AD5);
        VitalWireDelay (AD6_ipd, AD6, tipd_AD6);
        VitalWireDelay (AD7_ipd, AD7, tipd_AD7);
        VitalWireDelay (AD8_ipd, AD8, tipd_AD8);
        VitalWireDelay (AD9_ipd, AD9, tipd_AD9);

      end block;

      --------------------
      -- RAMB16KA_X16 Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CEN_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_WR_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_CS0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_CS1_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_DI0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI3_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI4_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI5_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI6_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI7_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI8_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI9_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI10_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI11_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI12_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI13_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI14_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI15_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_AD0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD3_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD4_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD5_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD6_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD7_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD8_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD9_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_CLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CEN_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI8_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI9_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI10_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI11_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI12_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI13_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI14_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI15_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_AD0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD4_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD5_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD6_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD7_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD8_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD9_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_CLK_posedge_posedge  : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLK       : std_ulogic := '0';
        variable PInfo_CLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable DO8_zd          : std_ulogic := 'X';
        variable DO9_zd          : std_ulogic := 'X';
        variable DO10_zd          : std_ulogic := 'X';
        variable DO11_zd          : std_ulogic := 'X';
        variable DO12_zd          : std_ulogic := 'X';
        variable DO13_zd          : std_ulogic := 'X';
        variable DO14_zd          : std_ulogic := 'X';
        variable DO15_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CEN_CLK_posedge,
          TimingData              => Tmkr_CEN_CLK_posedge,
          TestSignal              => CEN_ipd,
          TestSignalName          => "CEN",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CEN_CLK_noedge_posedge,
          SetupLow                => tsetup_CEN_CLK_noedge_posedge,
          HoldLow                 => thold_CEN_CLK_noedge_posedge,
          HoldHigh                => thold_CEN_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_CLK_posedge,
          TimingData              => Tmkr_WR_CLK_posedge,
          TestSignal              => WR_ipd,
          TestSignalName          => "WR",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_CLK_noedge_posedge,
          HoldLow                 => thold_WR_CLK_noedge_posedge,
          HoldHigh                => thold_WR_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS0_CLK_posedge,
          TimingData              => Tmkr_CS0_CLK_posedge,
          TestSignal              => CS0_ipd,
          TestSignalName          => "CS0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS0_CLK_noedge_posedge,
          SetupLow                => tsetup_CS0_CLK_noedge_posedge,
          HoldLow                 => thold_CS0_CLK_noedge_posedge,
          HoldHigh                => thold_CS0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS1_CLK_posedge,
          TimingData              => Tmkr_CS1_CLK_posedge,
          TestSignal              => CS1_ipd,
          TestSignalName          => "CS1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS1_CLK_noedge_posedge,
          SetupLow                => tsetup_CS1_CLK_noedge_posedge,
          HoldLow                 => thold_CS1_CLK_noedge_posedge,
          HoldHigh                => thold_CS1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_CLK_posedge,
          TimingData              => Tmkr_DI0_CLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_CLK_noedge_posedge,
          SetupLow                => tsetup_DI0_CLK_noedge_posedge,
          HoldLow                 => thold_DI0_CLK_noedge_posedge,
          HoldHigh                => thold_DI0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_CLK_posedge,
          TimingData              => Tmkr_DI1_CLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_CLK_noedge_posedge,
          SetupLow                => tsetup_DI1_CLK_noedge_posedge,
          HoldLow                 => thold_DI1_CLK_noedge_posedge,
          HoldHigh                => thold_DI1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_CLK_posedge,
          TimingData              => Tmkr_DI2_CLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_CLK_noedge_posedge,
          SetupLow                => tsetup_DI2_CLK_noedge_posedge,
          HoldLow                 => thold_DI2_CLK_noedge_posedge,
          HoldHigh                => thold_DI2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_CLK_posedge,
          TimingData              => Tmkr_DI3_CLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_CLK_noedge_posedge,
          SetupLow                => tsetup_DI3_CLK_noedge_posedge,
          HoldLow                 => thold_DI3_CLK_noedge_posedge,
          HoldHigh                => thold_DI3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_CLK_posedge,
          TimingData              => Tmkr_DI4_CLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_CLK_noedge_posedge,
          SetupLow                => tsetup_DI4_CLK_noedge_posedge,
          HoldLow                 => thold_DI4_CLK_noedge_posedge,
          HoldHigh                => thold_DI4_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_CLK_posedge,
          TimingData              => Tmkr_DI5_CLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_CLK_noedge_posedge,
          SetupLow                => tsetup_DI5_CLK_noedge_posedge,
          HoldLow                 => thold_DI5_CLK_noedge_posedge,
          HoldHigh                => thold_DI5_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_CLK_posedge,
          TimingData              => Tmkr_DI6_CLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_CLK_noedge_posedge,
          SetupLow                => tsetup_DI6_CLK_noedge_posedge,
          HoldLow                 => thold_DI6_CLK_noedge_posedge,
          HoldHigh                => thold_DI6_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_CLK_posedge,
          TimingData              => Tmkr_DI7_CLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_CLK_noedge_posedge,
          SetupLow                => tsetup_DI7_CLK_noedge_posedge,
          HoldLow                 => thold_DI7_CLK_noedge_posedge,
          HoldHigh                => thold_DI7_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI8_CLK_posedge,
          TimingData              => Tmkr_DI8_CLK_posedge,
          TestSignal              => DI8_ipd,
          TestSignalName          => "DI8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI8_CLK_noedge_posedge,
          SetupLow                => tsetup_DI8_CLK_noedge_posedge,
          HoldLow                 => thold_DI8_CLK_noedge_posedge,
          HoldHigh                => thold_DI8_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI9_CLK_posedge,
          TimingData              => Tmkr_DI9_CLK_posedge,
          TestSignal              => DI9_ipd,
          TestSignalName          => "DI9",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI9_CLK_noedge_posedge,
          SetupLow                => tsetup_DI9_CLK_noedge_posedge,
          HoldLow                 => thold_DI9_CLK_noedge_posedge,
          HoldHigh                => thold_DI9_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI10_CLK_posedge,
          TimingData              => Tmkr_DI10_CLK_posedge,
          TestSignal              => DI10_ipd,
          TestSignalName          => "DI10",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI10_CLK_noedge_posedge,
          SetupLow                => tsetup_DI10_CLK_noedge_posedge,
          HoldLow                 => thold_DI10_CLK_noedge_posedge,
          HoldHigh                => thold_DI10_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI11_CLK_posedge,
          TimingData              => Tmkr_DI11_CLK_posedge,
          TestSignal              => DI11_ipd,
          TestSignalName          => "DI11",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI11_CLK_noedge_posedge,
          SetupLow                => tsetup_DI11_CLK_noedge_posedge,
          HoldLow                 => thold_DI11_CLK_noedge_posedge,
          HoldHigh                => thold_DI11_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI12_CLK_posedge,
          TimingData              => Tmkr_DI12_CLK_posedge,
          TestSignal              => DI12_ipd,
          TestSignalName          => "DI12",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI12_CLK_noedge_posedge,
          SetupLow                => tsetup_DI12_CLK_noedge_posedge,
          HoldLow                 => thold_DI12_CLK_noedge_posedge,
          HoldHigh                => thold_DI12_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI13_CLK_posedge,
          TimingData              => Tmkr_DI13_CLK_posedge,
          TestSignal              => DI13_ipd,
          TestSignalName          => "DI13",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI13_CLK_noedge_posedge,
          SetupLow                => tsetup_DI13_CLK_noedge_posedge,
          HoldLow                 => thold_DI13_CLK_noedge_posedge,
          HoldHigh                => thold_DI13_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI14_CLK_posedge,
          TimingData              => Tmkr_DI14_CLK_posedge,
          TestSignal              => DI14_ipd,
          TestSignalName          => "DI14",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI14_CLK_noedge_posedge,
          SetupLow                => tsetup_DI14_CLK_noedge_posedge,
          HoldLow                 => thold_DI14_CLK_noedge_posedge,
          HoldHigh                => thold_DI14_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI15_CLK_posedge,
          TimingData              => Tmkr_DI15_CLK_posedge,
          TestSignal              => DI15_ipd,
          TestSignalName          => "DI15",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI15_CLK_noedge_posedge,
          SetupLow                => tsetup_DI15_CLK_noedge_posedge,
          HoldLow                 => thold_DI15_CLK_noedge_posedge,
          HoldHigh                => thold_DI15_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_CLK_posedge,
          TimingData              => Tmkr_AD0_CLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_CLK_noedge_posedge,
          SetupLow                => tsetup_AD0_CLK_noedge_posedge,
          HoldLow                 => thold_AD0_CLK_noedge_posedge,
          HoldHigh                => thold_AD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_CLK_posedge,
          TimingData              => Tmkr_AD1_CLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_CLK_noedge_posedge,
          SetupLow                => tsetup_AD1_CLK_noedge_posedge,
          HoldLow                 => thold_AD1_CLK_noedge_posedge,
          HoldHigh                => thold_AD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_CLK_posedge,
          TimingData              => Tmkr_AD2_CLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_CLK_noedge_posedge,
          SetupLow                => tsetup_AD2_CLK_noedge_posedge,
          HoldLow                 => thold_AD2_CLK_noedge_posedge,
          HoldHigh                => thold_AD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_CLK_posedge,
          TimingData              => Tmkr_AD3_CLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_CLK_noedge_posedge,
          SetupLow                => tsetup_AD3_CLK_noedge_posedge,
          HoldLow                 => thold_AD3_CLK_noedge_posedge,
          HoldHigh                => thold_AD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD4_CLK_posedge,
          TimingData              => Tmkr_AD4_CLK_posedge,
          TestSignal              => AD4_ipd,
          TestSignalName          => "AD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD4_CLK_noedge_posedge,
          SetupLow                => tsetup_AD4_CLK_noedge_posedge,
          HoldLow                 => thold_AD4_CLK_noedge_posedge,
          HoldHigh                => thold_AD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD5_CLK_posedge,
          TimingData              => Tmkr_AD5_CLK_posedge,
          TestSignal              => AD5_ipd,
          TestSignalName          => "AD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD5_CLK_noedge_posedge,
          SetupLow                => tsetup_AD5_CLK_noedge_posedge,
          HoldLow                 => thold_AD5_CLK_noedge_posedge,
          HoldHigh                => thold_AD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD6_CLK_posedge,
          TimingData              => Tmkr_AD6_CLK_posedge,
          TestSignal              => AD6_ipd,
          TestSignalName          => "AD6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD6_CLK_noedge_posedge,
          SetupLow                => tsetup_AD6_CLK_noedge_posedge,
          HoldLow                 => thold_AD6_CLK_noedge_posedge,
          HoldHigh                => thold_AD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD7_CLK_posedge,
          TimingData              => Tmkr_AD7_CLK_posedge,
          TestSignal              => AD7_ipd,
          TestSignalName          => "AD7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD7_CLK_noedge_posedge,
          SetupLow                => tsetup_AD7_CLK_noedge_posedge,
          HoldLow                 => thold_AD7_CLK_noedge_posedge,
          HoldHigh                => thold_AD7_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD8_CLK_posedge,
          TimingData              => Tmkr_AD8_CLK_posedge,
          TestSignal              => AD8_ipd,
          TestSignalName          => "AD8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD8_CLK_noedge_posedge,
          SetupLow                => tsetup_AD8_CLK_noedge_posedge,
          HoldLow                 => thold_AD8_CLK_noedge_posedge,
          HoldHigh                => thold_AD8_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD9_CLK_posedge,
          TimingData              => Tmkr_AD9_CLK_posedge,
          TestSignal              => AD9_ipd,
          TestSignalName          => "AD9",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD9_CLK_noedge_posedge,
          SetupLow                => tsetup_AD9_CLK_noedge_posedge,
          HoldLow                 => thold_AD9_CLK_noedge_posedge,
          HoldHigh                => thold_AD9_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_CLK_posedge_posedge,
          TimingData              => Tmkr_RST_CLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_CLK_posedge_posedge,
          Removal                 => thold_RST_CLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_X16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CEN_CLK_posedge or Tviol_WR_CLK_posedge or 
                 Tviol_DI0_CLK_posedge or Tviol_DI1_CLK_posedge or 
                 Tviol_DI2_CLK_posedge or Tviol_DI3_CLK_posedge or 
                 Tviol_DI4_CLK_posedge or Tviol_DI5_CLK_posedge or 
                 Tviol_DI6_CLK_posedge or Tviol_DI7_CLK_posedge or 
                 Tviol_DI8_CLK_posedge or Tviol_DI9_CLK_posedge or 
                 Tviol_DI10_CLK_posedge or Tviol_DI11_CLK_posedge or 
                 Tviol_DI12_CLK_posedge or Tviol_DI13_CLK_posedge or 
                 Tviol_DI14_CLK_posedge or Tviol_DI15_CLK_posedge or 
                 Tviol_CS0_CLK_posedge or Tviol_CS1_CLK_posedge or 
                 Tviol_AD0_CLK_posedge or Tviol_AD1_CLK_posedge or 
                 Tviol_AD2_CLK_posedge or Tviol_AD3_CLK_posedge or 
                 Tviol_AD4_CLK_posedge or Tviol_AD5_CLK_posedge or 
                 Tviol_AD6_CLK_posedge or Tviol_AD7_CLK_posedge or 
                 Tviol_AD8_CLK_posedge or Tviol_AD9_CLK_posedge or 
                 Pviol_CLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on CEN_ipd, CLK_ipd, WR_ipd, CS,  RST_ipd, DI, AD;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO0, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO0, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO0, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO0, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO0, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO0, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO0, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO0, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO0, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO0, TRUE),
               10 => (CLK_ipd'last_event, tpd_CLK_DO0, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO1, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO1, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO1, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO1, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO1, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO1, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO1, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO1, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO1, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO1, TRUE),
               10 => (CLK_ipd'last_event, tpd_CLK_DO1, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO2, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO2, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO2, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO2, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO2, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO2, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO2, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO2, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO2, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO2, TRUE),
               10 => (CLK_ipd'last_event, tpd_CLK_DO2, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO3, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO3, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO3, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO3, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO3, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO3, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO3, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO3, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO3, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO3, TRUE),
               10 => (CLK_ipd'last_event, tpd_CLK_DO3, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO4, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO4, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO4, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO4, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO4, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO4, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO4, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO4, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO4, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO4, TRUE),
               10 => (CLK_ipd'last_event, tpd_CLK_DO4, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO5, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO5, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO5, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO5, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO5, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO5, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO5, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO5, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO5, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO5, TRUE),
               10 => (CLK_ipd'last_event, tpd_CLK_DO5, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO6, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO6, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO6, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO6, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO6, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO6, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO6, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO6, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO6, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO6, TRUE),
               10 => (CLK_ipd'last_event, tpd_CLK_DO6, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO7, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO7, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO7, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO7, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO7, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO7, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO7, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO7, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO7, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO7, TRUE),
               10 => (CLK_ipd'last_event, tpd_CLK_DO7, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_DO8  : process
      variable DO8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO8_zd := DO(8);

    VitalPathDelay01 (
      OutSignal => DO8,
      GlitchData => O_GlitchData,
      OutSignalName => "DO8",
      OutTemp => DO8_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO8, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO8, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO8, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO8, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO8, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO8, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO8, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO8, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO8, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO8, TRUE),
               10 => (CLK_ipd'last_event, tpd_CLK_DO8, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_DO8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(8);
      end process;

    VitalBehavior_DO9  : process
      variable DO9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO9_zd := DO(9);

    VitalPathDelay01 (
      OutSignal => DO9,
      GlitchData => O_GlitchData,
      OutSignalName => "DO9",
      OutTemp => DO9_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO9, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO9, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO9, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO9, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO9, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO9, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO9, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO9, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO9, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO9, TRUE),
               10 => (CLK_ipd'last_event, tpd_CLK_DO9, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_DO9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(9);
      end process;

    VitalBehavior_DO10  : process
      variable DO10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO10_zd := DO(10);

    VitalPathDelay01 (
      OutSignal => DO10,
      GlitchData => O_GlitchData,
      OutSignalName => "DO10",
      OutTemp => DO10_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO10, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO10, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO10, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO10, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO10, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO10, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO10, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO10, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO10, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO10, TRUE),
               10 => (CLK_ipd'last_event, tpd_CLK_DO10, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_DO10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(10);
      end process;

    VitalBehavior_DO11  : process
      variable DO11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO11_zd := DO(11);

    VitalPathDelay01 (
      OutSignal => DO11,
      GlitchData => O_GlitchData,
      OutSignalName => "DO11",
      OutTemp => DO11_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO11, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO11, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO11, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO11, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO11, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO11, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO11, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO11, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO11, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO11, TRUE),
               10 => (CLK_ipd'last_event, tpd_CLK_DO11, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_DO11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(11);
      end process;

    VitalBehavior_DO12  : process
      variable DO12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO12_zd := DO(12);

    VitalPathDelay01 (
      OutSignal => DO12,
      GlitchData => O_GlitchData,
      OutSignalName => "DO12",
      OutTemp => DO12_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO12, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO12, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO12, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO12, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO12, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO12, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO12, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO12, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO12, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO12, TRUE),
               10 => (CLK_ipd'last_event, tpd_CLK_DO12, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_DO12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(12);
      end process;

    VitalBehavior_DO13  : process
      variable DO13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO13_zd := DO(13);

    VitalPathDelay01 (
      OutSignal => DO13,
      GlitchData => O_GlitchData,
      OutSignalName => "DO13",
      OutTemp => DO13_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO13, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO13, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO13, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO13, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO13, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO13, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO13, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO13, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO13, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO13, TRUE),
               10 => (CLK_ipd'last_event, tpd_CLK_DO13, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_DO13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(13);
      end process;

    VitalBehavior_DO14  : process
      variable DO14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO14_zd := DO(14);

    VitalPathDelay01 (
      OutSignal => DO14,
      GlitchData => O_GlitchData,
      OutSignalName => "DO14",
      OutTemp => DO14_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO14, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO14, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO14, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO14, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO14, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO14, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO14, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO14, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO14, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO14, TRUE),
               10 => (CLK_ipd'last_event, tpd_CLK_DO14, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_DO14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(14);
      end process;

    VitalBehavior_DO15  : process
      variable DO15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO15_zd := DO(15);

    VitalPathDelay01 (
      OutSignal => DO15,
      GlitchData => O_GlitchData,
      OutSignalName => "DO15",
      OutTemp => DO15_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO15, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO15, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO15, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO15, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO15, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO15, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO15, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO15, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO15, TRUE),
               9 => (AD9_ipd'last_event, tpd_AD9_DO15, TRUE),
               10 => (CLK_ipd'last_event, tpd_CLK_DO15, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_DO15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(15);
      end process;



	SPRAMA_INST: SC_SPRAMA_16K
	   generic map (
		ADDR_WIDTH    => 10,
		DATA_WIDTH    => 16,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CEN => CEN_ipd,
		CLK => CLK_ipd,
		WR  => WR_ipd,
		CS  => CS,
		RST => RST_ipd,
		DI  => DI,
		AD  => AD,
		DO  => DO
		);

end VITAL;

configuration CFG_RAMB16KA_X16_VITAL of RAMB16KA_X16 is
   for VITAL
   end for;
end CFG_RAMB16KA_X16_VITAL;



----- CELL RAMB16KA_X32 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity RAMB16KA_X32 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_AD0_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO0                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO1                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO2                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO3                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO4                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO5                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO6                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO7                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO8                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO9                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO10                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO11                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO12                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO13                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO14                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO15                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO16                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO17                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO18                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO19                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO20                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO21                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO22                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO23                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO24                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO25                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO26                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO27                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO28                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO29                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO30                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tpd_AD0_DO31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_DO31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_DO31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_DO31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_DO31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_DO31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD6_DO31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD7_DO31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD8_DO31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_DO31                      :	VitalDelayType01 := (0.2 ns, 0.2 ns);
      tsetup_WR_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_CEN_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CEN_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CS1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_CS1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI4_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI5_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI6_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI7_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI8_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI8_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI9_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI9_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI10_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI10_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI11_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI11_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI12_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI12_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI13_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI13_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI14_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI14_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI15_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI15_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI16_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI16_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI17_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI17_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI18_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI18_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI19_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI19_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI20_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI20_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI21_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI21_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI22_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI22_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI23_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI23_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI24_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI24_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI25_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI25_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI26_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI26_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI27_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI27_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI28_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI28_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI29_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI29_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI30_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI30_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_DI31_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_DI31_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD0_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD0_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD1_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD1_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD2_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD2_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD3_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD3_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD4_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD4_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD5_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD5_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD6_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD6_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD7_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD7_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_AD8_CLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_AD8_CLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_CLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_CLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLK_posedge                  :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_CEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI8                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI9                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI10                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI11                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI12                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI13                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI14                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI15                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI16                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI17                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI18                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI19                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI20                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI21                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI22                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI23                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI24                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI25                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI26                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI27                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI28                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI29                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI30                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI31                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD8                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CEN                            :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      WR                             :	in    STD_ULOGIC;
      CS0                            :	in    STD_ULOGIC;
      CS1                            :	in    STD_ULOGIC;
      RST                            :	in    STD_ULOGIC;
      DI0                            :	in    STD_ULOGIC;
      DI1                            :	in    STD_ULOGIC;
      DI2                            :	in    STD_ULOGIC;
      DI3                            :	in    STD_ULOGIC;
      DI4                            :	in    STD_ULOGIC;
      DI5                            :	in    STD_ULOGIC;
      DI6                            :	in    STD_ULOGIC;
      DI7                            :	in    STD_ULOGIC;
      DI8                            :	in    STD_ULOGIC;
      DI9                            :	in    STD_ULOGIC;
      DI10                           :	in    STD_ULOGIC;
      DI11                           :	in    STD_ULOGIC;
      DI12                           :	in    STD_ULOGIC;
      DI13                            :	in    STD_ULOGIC;
      DI14                            :	in    STD_ULOGIC;
      DI15                            :	in    STD_ULOGIC;
      DI16                            :	in    STD_ULOGIC;
      DI17                            :	in    STD_ULOGIC;
      DI18                            :	in    STD_ULOGIC;
      DI19                            :	in    STD_ULOGIC;
      DI20                            :	in    STD_ULOGIC;
      DI21                            :	in    STD_ULOGIC;
      DI22                            :	in    STD_ULOGIC;
      DI23                            :	in    STD_ULOGIC;
      DI24                            :	in    STD_ULOGIC;
      DI25                            :	in    STD_ULOGIC;
      DI26                           :	in    STD_ULOGIC;
      DI27                           :	in    STD_ULOGIC;
      DI28                           :	in    STD_ULOGIC;
      DI29                            :	in    STD_ULOGIC;
      DI30                            :	in    STD_ULOGIC;
      DI31                            :	in    STD_ULOGIC;
      AD0                            :	in    STD_ULOGIC;
      AD1                            :	in    STD_ULOGIC;
      AD2                            :	in    STD_ULOGIC;
      AD3                            :	in    STD_ULOGIC;
      AD4                            :	in    STD_ULOGIC;
      AD5                            :	in    STD_ULOGIC;
      AD6                            :	in    STD_ULOGIC;
      AD7                            :	in    STD_ULOGIC;
      AD8                            :	in    STD_ULOGIC;
      DO0                            :	out   STD_ULOGIC;
      DO1                            :	out   STD_ULOGIC;
      DO2                            :	out   STD_ULOGIC;
      DO3                            :	out   STD_ULOGIC;
      DO4                            :	out   STD_ULOGIC;
      DO5                            :	out   STD_ULOGIC;
      DO6                            :	out   STD_ULOGIC;
      DO7                            :	out   STD_ULOGIC;
      DO8                            :	out   STD_ULOGIC;
      DO9                            :	out   STD_ULOGIC;
      DO10                           :	out   STD_ULOGIC;
      DO11                           :	out   STD_ULOGIC;
      DO12                           :	out   STD_ULOGIC;
      DO13                           :	out   STD_ULOGIC;
      DO14                           :	out   STD_ULOGIC;
      DO15                           :	out   STD_ULOGIC;
      DO16                            :	out   STD_ULOGIC;
      DO17                            :	out   STD_ULOGIC;
      DO18                           :	out   STD_ULOGIC;
      DO19                            :	out   STD_ULOGIC;
      DO20                            :	out   STD_ULOGIC;
      DO21                            :	out   STD_ULOGIC;
      DO22                            :	out   STD_ULOGIC;
      DO23                            :	out   STD_ULOGIC;
      DO24                            :	out   STD_ULOGIC;
      DO25                            :	out   STD_ULOGIC;
      DO26                           :	out   STD_ULOGIC;
      DO27                           :	out   STD_ULOGIC;
      DO28                           :	out   STD_ULOGIC;
      DO29                           :	out   STD_ULOGIC;
      DO30                           :	out   STD_ULOGIC;
      DO31                           :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMB16KA_X32 : entity is FALSE;
end RAMB16KA_X32;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_X32 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_SPRAMA_16K
	   generic (
		ADDR_WIDTH    : integer := 9;
		DATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		CEN : in  STD_LOGIC ;
		CLK : in  STD_LOGIC ;
		WR   : in  STD_LOGIC ;
		CS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		DI   : in  STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0);
		AD  : in  STD_LOGIC_VECTOR (ADDR_WIDTH -1 downto 0);
		DO   : out STD_LOGIC_VECTOR (DATA_WIDTH -1 downto 0)
		);
	end component ;

      signal CEN_ipd      : std_ulogic := 'X';
      signal CLK_ipd      : std_ulogic := 'X';
      signal WR_ipd       : std_ulogic := 'X';
      signal CS0_ipd      : std_ulogic := 'X';
      signal CS1_ipd      : std_ulogic := 'X';
      signal RST_ipd      : std_ulogic := 'X';

      signal DI0_ipd      : std_ulogic := 'X';
      signal DI1_ipd      : std_ulogic := 'X';
      signal DI2_ipd      : std_ulogic := 'X';
      signal DI3_ipd      : std_ulogic := 'X';
      signal DI4_ipd      : std_ulogic := 'X';
      signal DI5_ipd      : std_ulogic := 'X';
      signal DI6_ipd      : std_ulogic := 'X';
      signal DI7_ipd      : std_ulogic := 'X';
      signal DI8_ipd      : std_ulogic := 'X';
      signal DI9_ipd      : std_ulogic := 'X';
      signal DI10_ipd      : std_ulogic := 'X';
      signal DI11_ipd      : std_ulogic := 'X';
      signal DI12_ipd      : std_ulogic := 'X';
      signal DI13_ipd      : std_ulogic := 'X';
      signal DI14_ipd      : std_ulogic := 'X';
      signal DI15_ipd      : std_ulogic := 'X';
      signal DI16_ipd      : std_ulogic := 'X';
      signal DI17_ipd      : std_ulogic := 'X';
      signal DI18_ipd      : std_ulogic := 'X';
      signal DI19_ipd      : std_ulogic := 'X';
      signal DI20_ipd      : std_ulogic := 'X';
      signal DI21_ipd      : std_ulogic := 'X';
      signal DI22_ipd      : std_ulogic := 'X';
      signal DI23_ipd      : std_ulogic := 'X';
      signal DI24_ipd      : std_ulogic := 'X';
      signal DI25_ipd      : std_ulogic := 'X';
      signal DI26_ipd      : std_ulogic := 'X';
      signal DI27_ipd      : std_ulogic := 'X';
      signal DI28_ipd      : std_ulogic := 'X';
      signal DI29_ipd      : std_ulogic := 'X';
      signal DI30_ipd      : std_ulogic := 'X';
      signal DI31_ipd      : std_ulogic := 'X';

      signal AD0_ipd      : std_ulogic := 'X';
      signal AD1_ipd      : std_ulogic := 'X';
      signal AD2_ipd      : std_ulogic := 'X';
      signal AD3_ipd      : std_ulogic := 'X';
      signal AD4_ipd      : std_ulogic := 'X';
      signal AD5_ipd      : std_ulogic := 'X';
      signal AD6_ipd      : std_ulogic := 'X';
      signal AD7_ipd      : std_ulogic := 'X';
      signal AD8_ipd      : std_ulogic := 'X';

	signal CS : std_logic_vector (1 downto 0);
	signal DI  : std_logic_vector (31 downto 0);
 	signal AD : std_logic_vector (8 downto 0);
	signal DO  : std_logic_vector (31 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	CS <= CS1_ipd & CS0_ipd;
	DI <= DI31_ipd & DI30_ipd & DI29_ipd & DI28_ipd & DI27_ipd & DI26_ipd & DI25_ipd & DI24_ipd & DI23_ipd & DI22_ipd & DI21_ipd & DI20_ipd & DI19_ipd & DI18_ipd & DI17_ipd & DI16_ipd & DI15_ipd & DI14_ipd & DI13_ipd & DI12_ipd & DI11_ipd & DI10_ipd & DI9_ipd & DI8_ipd & DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd;
	AD <= AD8_ipd & AD7_ipd & AD6_ipd & AD5_ipd & AD4_ipd & AD3_ipd & AD2_ipd & AD1_ipd & AD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CEN_ipd, CEN, tipd_CEN);
        VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        VitalWireDelay (WR_ipd, WR, tipd_WR);
        VitalWireDelay (CS0_ipd, CS0, tipd_CS0);
        VitalWireDelay (CS1_ipd, CS1, tipd_CS1);
        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);
        VitalWireDelay (DI8_ipd, DI8, tipd_DI8);
        VitalWireDelay (DI9_ipd, DI9, tipd_DI9);
        VitalWireDelay (DI10_ipd, DI10, tipd_DI10);
        VitalWireDelay (DI11_ipd, DI11, tipd_DI11);
        VitalWireDelay (DI12_ipd, DI12, tipd_DI12);
        VitalWireDelay (DI13_ipd, DI13, tipd_DI13);
        VitalWireDelay (DI14_ipd, DI14, tipd_DI14);
        VitalWireDelay (DI15_ipd, DI15, tipd_DI15);
        VitalWireDelay (DI16_ipd, DI16, tipd_DI16);
        VitalWireDelay (DI17_ipd, DI17, tipd_DI1);
        VitalWireDelay (DI18_ipd, DI18, tipd_DI2);
        VitalWireDelay (DI19_ipd, DI19, tipd_DI3);
        VitalWireDelay (DI20_ipd, DI20, tipd_DI4);
        VitalWireDelay (DI21_ipd, DI21, tipd_DI5);
        VitalWireDelay (DI22_ipd, DI22, tipd_DI6);
        VitalWireDelay (DI23_ipd, DI23, tipd_DI7);
        VitalWireDelay (DI24_ipd, DI24, tipd_DI8);
        VitalWireDelay (DI25_ipd, DI25, tipd_DI9);
        VitalWireDelay (DI26_ipd, DI26, tipd_DI10);
        VitalWireDelay (DI27_ipd, DI27, tipd_DI11);
        VitalWireDelay (DI28_ipd, DI28, tipd_DI12);
        VitalWireDelay (DI29_ipd, DI29, tipd_DI13);
        VitalWireDelay (DI30_ipd, DI30, tipd_DI14);
        VitalWireDelay (DI31_ipd, DI31, tipd_DI15);

        VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
        VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
        VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
        VitalWireDelay (AD3_ipd, AD3, tipd_AD3);
        VitalWireDelay (AD4_ipd, AD4, tipd_AD4);
        VitalWireDelay (AD5_ipd, AD5, tipd_AD5);
        VitalWireDelay (AD6_ipd, AD6, tipd_AD6);
        VitalWireDelay (AD7_ipd, AD7, tipd_AD7);
        VitalWireDelay (AD8_ipd, AD8, tipd_AD8);

      end block;

      --------------------
      -- RAMB16KA_X32 Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CEN_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_WR_CLK_posedge     : std_ulogic  := '0';
        variable Tviol_CS0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_CS1_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_DI0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI3_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI4_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI5_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI6_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI7_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI8_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI9_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI10_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI11_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI12_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI13_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI14_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI15_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI16_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI17_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI18_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI19_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI20_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI21_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI22_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI23_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI24_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI25_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI26_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI27_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI28_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI29_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI30_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_DI31_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_AD0_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD1_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD2_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD3_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD4_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD5_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD6_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD7_CLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD8_CLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_CLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_CEN_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI8_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI9_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI10_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI11_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI12_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI13_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI14_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI15_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI16_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI17_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI18_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI19_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI20_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI21_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI22_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI23_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI24_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI25_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI26_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI27_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI28_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI29_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI30_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI31_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_AD0_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD1_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD2_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD3_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD4_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD5_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD6_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD7_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD8_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_CLK_posedge_posedge  : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLK       : std_ulogic := '0';
        variable PInfo_CLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable DO8_zd          : std_ulogic := 'X';
        variable DO9_zd          : std_ulogic := 'X';
        variable DO10_zd          : std_ulogic := 'X';
        variable DO11_zd          : std_ulogic := 'X';
        variable DO12_zd          : std_ulogic := 'X';
        variable DO13_zd          : std_ulogic := 'X';
        variable DO14_zd          : std_ulogic := 'X';
        variable DO15_zd          : std_ulogic := 'X';
        variable DO16_zd          : std_ulogic := 'X';
        variable DO17_zd          : std_ulogic := 'X';
        variable DO18_zd          : std_ulogic := 'X';
        variable DO19_zd          : std_ulogic := 'X';
        variable DO20_zd          : std_ulogic := 'X';
        variable DO21_zd          : std_ulogic := 'X';
        variable DO22_zd          : std_ulogic := 'X';
        variable DO23_zd          : std_ulogic := 'X';
        variable DO24_zd          : std_ulogic := 'X';
        variable DO25_zd          : std_ulogic := 'X';
        variable DO26_zd          : std_ulogic := 'X';
        variable DO27_zd          : std_ulogic := 'X';
        variable DO28_zd          : std_ulogic := 'X';
        variable DO29_zd          : std_ulogic := 'X';
        variable DO30_zd          : std_ulogic := 'X';
        variable DO31_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CEN_CLK_posedge,
          TimingData              => Tmkr_CEN_CLK_posedge,
          TestSignal              => CEN_ipd,
          TestSignalName          => "CEN",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CEN_CLK_noedge_posedge,
          SetupLow                => tsetup_CEN_CLK_noedge_posedge,
          HoldLow                 => thold_CEN_CLK_noedge_posedge,
          HoldHigh                => thold_CEN_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_CLK_posedge,
          TimingData              => Tmkr_WR_CLK_posedge,
          TestSignal              => WR_ipd,
          TestSignalName          => "WR",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_CLK_noedge_posedge,
          HoldLow                 => thold_WR_CLK_noedge_posedge,
          HoldHigh                => thold_WR_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS0_CLK_posedge,
          TimingData              => Tmkr_CS0_CLK_posedge,
          TestSignal              => CS0_ipd,
          TestSignalName          => "CS0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS0_CLK_noedge_posedge,
          SetupLow                => tsetup_CS0_CLK_noedge_posedge,
          HoldLow                 => thold_CS0_CLK_noedge_posedge,
          HoldHigh                => thold_CS0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS1_CLK_posedge,
          TimingData              => Tmkr_CS1_CLK_posedge,
          TestSignal              => CS1_ipd,
          TestSignalName          => "CS1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS1_CLK_noedge_posedge,
          SetupLow                => tsetup_CS1_CLK_noedge_posedge,
          HoldLow                 => thold_CS1_CLK_noedge_posedge,
          HoldHigh                => thold_CS1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_CLK_posedge,
          TimingData              => Tmkr_DI0_CLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_CLK_noedge_posedge,
          SetupLow                => tsetup_DI0_CLK_noedge_posedge,
          HoldLow                 => thold_DI0_CLK_noedge_posedge,
          HoldHigh                => thold_DI0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_CLK_posedge,
          TimingData              => Tmkr_DI1_CLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_CLK_noedge_posedge,
          SetupLow                => tsetup_DI1_CLK_noedge_posedge,
          HoldLow                 => thold_DI1_CLK_noedge_posedge,
          HoldHigh                => thold_DI1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_CLK_posedge,
          TimingData              => Tmkr_DI2_CLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_CLK_noedge_posedge,
          SetupLow                => tsetup_DI2_CLK_noedge_posedge,
          HoldLow                 => thold_DI2_CLK_noedge_posedge,
          HoldHigh                => thold_DI2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_CLK_posedge,
          TimingData              => Tmkr_DI3_CLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_CLK_noedge_posedge,
          SetupLow                => tsetup_DI3_CLK_noedge_posedge,
          HoldLow                 => thold_DI3_CLK_noedge_posedge,
          HoldHigh                => thold_DI3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_CLK_posedge,
          TimingData              => Tmkr_DI4_CLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_CLK_noedge_posedge,
          SetupLow                => tsetup_DI4_CLK_noedge_posedge,
          HoldLow                 => thold_DI4_CLK_noedge_posedge,
          HoldHigh                => thold_DI4_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_CLK_posedge,
          TimingData              => Tmkr_DI5_CLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_CLK_noedge_posedge,
          SetupLow                => tsetup_DI5_CLK_noedge_posedge,
          HoldLow                 => thold_DI5_CLK_noedge_posedge,
          HoldHigh                => thold_DI5_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_CLK_posedge,
          TimingData              => Tmkr_DI6_CLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_CLK_noedge_posedge,
          SetupLow                => tsetup_DI6_CLK_noedge_posedge,
          HoldLow                 => thold_DI6_CLK_noedge_posedge,
          HoldHigh                => thold_DI6_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_CLK_posedge,
          TimingData              => Tmkr_DI7_CLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_CLK_noedge_posedge,
          SetupLow                => tsetup_DI7_CLK_noedge_posedge,
          HoldLow                 => thold_DI7_CLK_noedge_posedge,
          HoldHigh                => thold_DI7_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI8_CLK_posedge,
          TimingData              => Tmkr_DI8_CLK_posedge,
          TestSignal              => DI8_ipd,
          TestSignalName          => "DI8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI8_CLK_noedge_posedge,
          SetupLow                => tsetup_DI8_CLK_noedge_posedge,
          HoldLow                 => thold_DI8_CLK_noedge_posedge,
          HoldHigh                => thold_DI8_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI9_CLK_posedge,
          TimingData              => Tmkr_DI9_CLK_posedge,
          TestSignal              => DI9_ipd,
          TestSignalName          => "DI9",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI9_CLK_noedge_posedge,
          SetupLow                => tsetup_DI9_CLK_noedge_posedge,
          HoldLow                 => thold_DI9_CLK_noedge_posedge,
          HoldHigh                => thold_DI9_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI10_CLK_posedge,
          TimingData              => Tmkr_DI10_CLK_posedge,
          TestSignal              => DI10_ipd,
          TestSignalName          => "DI10",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI10_CLK_noedge_posedge,
          SetupLow                => tsetup_DI10_CLK_noedge_posedge,
          HoldLow                 => thold_DI10_CLK_noedge_posedge,
          HoldHigh                => thold_DI10_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI11_CLK_posedge,
          TimingData              => Tmkr_DI11_CLK_posedge,
          TestSignal              => DI11_ipd,
          TestSignalName          => "DI11",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI11_CLK_noedge_posedge,
          SetupLow                => tsetup_DI11_CLK_noedge_posedge,
          HoldLow                 => thold_DI11_CLK_noedge_posedge,
          HoldHigh                => thold_DI11_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI12_CLK_posedge,
          TimingData              => Tmkr_DI12_CLK_posedge,
          TestSignal              => DI12_ipd,
          TestSignalName          => "DI12",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI12_CLK_noedge_posedge,
          SetupLow                => tsetup_DI12_CLK_noedge_posedge,
          HoldLow                 => thold_DI12_CLK_noedge_posedge,
          HoldHigh                => thold_DI12_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI13_CLK_posedge,
          TimingData              => Tmkr_DI13_CLK_posedge,
          TestSignal              => DI13_ipd,
          TestSignalName          => "DI13",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI13_CLK_noedge_posedge,
          SetupLow                => tsetup_DI13_CLK_noedge_posedge,
          HoldLow                 => thold_DI13_CLK_noedge_posedge,
          HoldHigh                => thold_DI13_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI14_CLK_posedge,
          TimingData              => Tmkr_DI14_CLK_posedge,
          TestSignal              => DI14_ipd,
          TestSignalName          => "DI14",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI14_CLK_noedge_posedge,
          SetupLow                => tsetup_DI14_CLK_noedge_posedge,
          HoldLow                 => thold_DI14_CLK_noedge_posedge,
          HoldHigh                => thold_DI14_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI15_CLK_posedge,
          TimingData              => Tmkr_DI15_CLK_posedge,
          TestSignal              => DI15_ipd,
          TestSignalName          => "DI15",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI15_CLK_noedge_posedge,
          SetupLow                => tsetup_DI15_CLK_noedge_posedge,
          HoldLow                 => thold_DI15_CLK_noedge_posedge,
          HoldHigh                => thold_DI15_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI16_CLK_posedge,
          TimingData              => Tmkr_DI16_CLK_posedge,
          TestSignal              => DI16_ipd,
          TestSignalName          => "DI16",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI16_CLK_noedge_posedge,
          SetupLow                => tsetup_DI16_CLK_noedge_posedge,
          HoldLow                 => thold_DI16_CLK_noedge_posedge,
          HoldHigh                => thold_DI16_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI17_CLK_posedge,
          TimingData              => Tmkr_DI17_CLK_posedge,
          TestSignal              => DI17_ipd,
          TestSignalName          => "DI17",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI17_CLK_noedge_posedge,
          SetupLow                => tsetup_DI17_CLK_noedge_posedge,
          HoldLow                 => thold_DI17_CLK_noedge_posedge,
          HoldHigh                => thold_DI17_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI18_CLK_posedge,
          TimingData              => Tmkr_DI18_CLK_posedge,
          TestSignal              => DI18_ipd,
          TestSignalName          => "DI18",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI18_CLK_noedge_posedge,
          SetupLow                => tsetup_DI18_CLK_noedge_posedge,
          HoldLow                 => thold_DI18_CLK_noedge_posedge,
          HoldHigh                => thold_DI18_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI19_CLK_posedge,
          TimingData              => Tmkr_DI19_CLK_posedge,
          TestSignal              => DI19_ipd,
          TestSignalName          => "DI19",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI19_CLK_noedge_posedge,
          SetupLow                => tsetup_DI19_CLK_noedge_posedge,
          HoldLow                 => thold_DI19_CLK_noedge_posedge,
          HoldHigh                => thold_DI19_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI20_CLK_posedge,
          TimingData              => Tmkr_DI20_CLK_posedge,
          TestSignal              => DI20_ipd,
          TestSignalName          => "DI20",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI20_CLK_noedge_posedge,
          SetupLow                => tsetup_DI20_CLK_noedge_posedge,
          HoldLow                 => thold_DI20_CLK_noedge_posedge,
          HoldHigh                => thold_DI20_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI21_CLK_posedge,
          TimingData              => Tmkr_DI21_CLK_posedge,
          TestSignal              => DI21_ipd,
          TestSignalName          => "DI21",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI21_CLK_noedge_posedge,
          SetupLow                => tsetup_DI21_CLK_noedge_posedge,
          HoldLow                 => thold_DI21_CLK_noedge_posedge,
          HoldHigh                => thold_DI21_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI22_CLK_posedge,
          TimingData              => Tmkr_DI22_CLK_posedge,
          TestSignal              => DI22_ipd,
          TestSignalName          => "DI22",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI22_CLK_noedge_posedge,
          SetupLow                => tsetup_DI22_CLK_noedge_posedge,
          HoldLow                 => thold_DI22_CLK_noedge_posedge,
          HoldHigh                => thold_DI22_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI23_CLK_posedge,
          TimingData              => Tmkr_DI23_CLK_posedge,
          TestSignal              => DI23_ipd,
          TestSignalName          => "DI23",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI23_CLK_noedge_posedge,
          SetupLow                => tsetup_DI23_CLK_noedge_posedge,
          HoldLow                 => thold_DI23_CLK_noedge_posedge,
          HoldHigh                => thold_DI23_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI24_CLK_posedge,
          TimingData              => Tmkr_DI24_CLK_posedge,
          TestSignal              => DI24_ipd,
          TestSignalName          => "DI24",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI24_CLK_noedge_posedge,
          SetupLow                => tsetup_DI24_CLK_noedge_posedge,
          HoldLow                 => thold_DI24_CLK_noedge_posedge,
          HoldHigh                => thold_DI24_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI25_CLK_posedge,
          TimingData              => Tmkr_DI25_CLK_posedge,
          TestSignal              => DI25_ipd,
          TestSignalName          => "DI25",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI25_CLK_noedge_posedge,
          SetupLow                => tsetup_DI25_CLK_noedge_posedge,
          HoldLow                 => thold_DI25_CLK_noedge_posedge,
          HoldHigh                => thold_DI25_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI26_CLK_posedge,
          TimingData              => Tmkr_DI26_CLK_posedge,
          TestSignal              => DI26_ipd,
          TestSignalName          => "DI26",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI26_CLK_noedge_posedge,
          SetupLow                => tsetup_DI26_CLK_noedge_posedge,
          HoldLow                 => thold_DI26_CLK_noedge_posedge,
          HoldHigh                => thold_DI26_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI27_CLK_posedge,
          TimingData              => Tmkr_DI27_CLK_posedge,
          TestSignal              => DI27_ipd,
          TestSignalName          => "DI27",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI27_CLK_noedge_posedge,
          SetupLow                => tsetup_DI27_CLK_noedge_posedge,
          HoldLow                 => thold_DI27_CLK_noedge_posedge,
          HoldHigh                => thold_DI27_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI28_CLK_posedge,
          TimingData              => Tmkr_DI28_CLK_posedge,
          TestSignal              => DI28_ipd,
          TestSignalName          => "DI28",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI28_CLK_noedge_posedge,
          SetupLow                => tsetup_DI28_CLK_noedge_posedge,
          HoldLow                 => thold_DI28_CLK_noedge_posedge,
          HoldHigh                => thold_DI28_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI29_CLK_posedge,
          TimingData              => Tmkr_DI29_CLK_posedge,
          TestSignal              => DI29_ipd,
          TestSignalName          => "DI29",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI29_CLK_noedge_posedge,
          SetupLow                => tsetup_DI29_CLK_noedge_posedge,
          HoldLow                 => thold_DI29_CLK_noedge_posedge,
          HoldHigh                => thold_DI29_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI30_CLK_posedge,
          TimingData              => Tmkr_DI30_CLK_posedge,
          TestSignal              => DI30_ipd,
          TestSignalName          => "DI30",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI30_CLK_noedge_posedge,
          SetupLow                => tsetup_DI30_CLK_noedge_posedge,
          HoldLow                 => thold_DI30_CLK_noedge_posedge,
          HoldHigh                => thold_DI30_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI31_CLK_posedge,
          TimingData              => Tmkr_DI31_CLK_posedge,
          TestSignal              => DI31_ipd,
          TestSignalName          => "DI31",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI31_CLK_noedge_posedge,
          SetupLow                => tsetup_DI31_CLK_noedge_posedge,
          HoldLow                 => thold_DI31_CLK_noedge_posedge,
          HoldHigh                => thold_DI31_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_CLK_posedge,
          TimingData              => Tmkr_AD0_CLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_CLK_noedge_posedge,
          SetupLow                => tsetup_AD0_CLK_noedge_posedge,
          HoldLow                 => thold_AD0_CLK_noedge_posedge,
          HoldHigh                => thold_AD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_CLK_posedge,
          TimingData              => Tmkr_AD1_CLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_CLK_noedge_posedge,
          SetupLow                => tsetup_AD1_CLK_noedge_posedge,
          HoldLow                 => thold_AD1_CLK_noedge_posedge,
          HoldHigh                => thold_AD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_CLK_posedge,
          TimingData              => Tmkr_AD2_CLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_CLK_noedge_posedge,
          SetupLow                => tsetup_AD2_CLK_noedge_posedge,
          HoldLow                 => thold_AD2_CLK_noedge_posedge,
          HoldHigh                => thold_AD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_CLK_posedge,
          TimingData              => Tmkr_AD3_CLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_CLK_noedge_posedge,
          SetupLow                => tsetup_AD3_CLK_noedge_posedge,
          HoldLow                 => thold_AD3_CLK_noedge_posedge,
          HoldHigh                => thold_AD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD4_CLK_posedge,
          TimingData              => Tmkr_AD4_CLK_posedge,
          TestSignal              => AD4_ipd,
          TestSignalName          => "AD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD4_CLK_noedge_posedge,
          SetupLow                => tsetup_AD4_CLK_noedge_posedge,
          HoldLow                 => thold_AD4_CLK_noedge_posedge,
          HoldHigh                => thold_AD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD5_CLK_posedge,
          TimingData              => Tmkr_AD5_CLK_posedge,
          TestSignal              => AD5_ipd,
          TestSignalName          => "AD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD5_CLK_noedge_posedge,
          SetupLow                => tsetup_AD5_CLK_noedge_posedge,
          HoldLow                 => thold_AD5_CLK_noedge_posedge,
          HoldHigh                => thold_AD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD6_CLK_posedge,
          TimingData              => Tmkr_AD6_CLK_posedge,
          TestSignal              => AD6_ipd,
          TestSignalName          => "AD6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD6_CLK_noedge_posedge,
          SetupLow                => tsetup_AD6_CLK_noedge_posedge,
          HoldLow                 => thold_AD6_CLK_noedge_posedge,
          HoldHigh                => thold_AD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD7_CLK_posedge,
          TimingData              => Tmkr_AD7_CLK_posedge,
          TestSignal              => AD7_ipd,
          TestSignalName          => "AD7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD7_CLK_noedge_posedge,
          SetupLow                => tsetup_AD7_CLK_noedge_posedge,
          HoldLow                 => thold_AD7_CLK_noedge_posedge,
          HoldHigh                => thold_AD7_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD8_CLK_posedge,
          TimingData              => Tmkr_AD8_CLK_posedge,
          TestSignal              => AD8_ipd,
          TestSignalName          => "AD8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD8_CLK_noedge_posedge,
          SetupLow                => tsetup_AD8_CLK_noedge_posedge,
          HoldLow                 => thold_AD8_CLK_noedge_posedge,
          HoldHigh                => thold_AD8_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_CLK_posedge_posedge,
          TimingData              => Tmkr_RST_CLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_CLK_posedge_posedge,
          Removal                 => thold_RST_CLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB16KA_X32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CEN_CLK_posedge or Tviol_WR_CLK_posedge or 
                 Tviol_DI0_CLK_posedge or Tviol_DI1_CLK_posedge or 
                 Tviol_DI2_CLK_posedge or Tviol_DI3_CLK_posedge or 
                 Tviol_DI4_CLK_posedge or Tviol_DI5_CLK_posedge or 
                 Tviol_DI6_CLK_posedge or Tviol_DI7_CLK_posedge or 
                 Tviol_DI8_CLK_posedge or Tviol_DI9_CLK_posedge or 
                 Tviol_DI10_CLK_posedge or Tviol_DI11_CLK_posedge or 
                 Tviol_DI12_CLK_posedge or Tviol_DI13_CLK_posedge or 
                 Tviol_DI14_CLK_posedge or Tviol_DI15_CLK_posedge or 
                 Tviol_DI16_CLK_posedge or Tviol_DI17_CLK_posedge or 
                 Tviol_DI18_CLK_posedge or Tviol_DI19_CLK_posedge or 
                 Tviol_DI20_CLK_posedge or Tviol_DI21_CLK_posedge or 
                 Tviol_DI22_CLK_posedge or Tviol_DI23_CLK_posedge or 
                 Tviol_DI24_CLK_posedge or Tviol_DI25_CLK_posedge or 
                 Tviol_DI26_CLK_posedge or Tviol_DI27_CLK_posedge or 
                 Tviol_DI28_CLK_posedge or Tviol_DI29_CLK_posedge or 
                 Tviol_DI30_CLK_posedge or Tviol_DI31_CLK_posedge or 
                 Tviol_CS0_CLK_posedge or Tviol_CS1_CLK_posedge or 
                 Tviol_AD0_CLK_posedge or Tviol_AD1_CLK_posedge or 
                 Tviol_AD2_CLK_posedge or Tviol_AD3_CLK_posedge or 
                 Tviol_AD4_CLK_posedge or Tviol_AD5_CLK_posedge or 
                 Tviol_AD6_CLK_posedge or Tviol_AD7_CLK_posedge or 
                 Tviol_AD8_CLK_posedge or Pviol_CLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

	wait on CEN_ipd, CLK_ipd, WR_ipd, CS,  RST_ipd, DI, AD;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO0, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO0, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO0, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO0, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO0, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO0, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO0, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO0, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO0, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO0, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO1, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO1, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO1, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO1, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO1, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO1, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO1, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO1, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO1, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO1, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO2, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO2, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO2, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO2, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO2, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO2, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO2, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO2, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO2, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO2, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO3, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO3, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO3, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO3, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO3, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO3, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO3, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO3, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO3, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO3, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO4, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO4, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO4, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO4, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO4, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO4, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO4, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO4, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO4, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO4, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO5, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO5, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO5, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO5, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO5, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO5, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO5, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO5, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO5, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO5, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO6, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO6, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO6, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO6, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO6, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO6, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO6, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO6, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO6, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO6, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO7, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO7, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO7, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO7, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO7, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO7, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO7, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO7, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO7, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO7, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_DO8  : process
      variable DO8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO8_zd := DO(8);

    VitalPathDelay01 (
      OutSignal => DO8,
      GlitchData => O_GlitchData,
      OutSignalName => "DO8",
      OutTemp => DO8_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO8, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO8, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO8, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO8, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO8, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO8, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO8, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO8, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO8, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO8, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_DO8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(8);
      end process;

    VitalBehavior_DO9  : process
      variable DO9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO9_zd := DO(9);

    VitalPathDelay01 (
      OutSignal => DO9,
      GlitchData => O_GlitchData,
      OutSignalName => "DO9",
      OutTemp => DO9_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO9, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO9, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO9, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO9, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO9, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO9, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO9, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO9, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO9, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO9, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_DO9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(9);
      end process;

    VitalBehavior_DO10  : process
      variable DO10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO10_zd := DO(10);

    VitalPathDelay01 (
      OutSignal => DO10,
      GlitchData => O_GlitchData,
      OutSignalName => "DO10",
      OutTemp => DO10_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO10, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO10, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO10, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO10, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO10, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO10, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO10, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO10, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO10, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO10, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_DO10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(10);
      end process;

    VitalBehavior_DO11  : process
      variable DO11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO11_zd := DO(11);

    VitalPathDelay01 (
      OutSignal => DO11,
      GlitchData => O_GlitchData,
      OutSignalName => "DO11",
      OutTemp => DO11_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO11, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO11, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO11, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO11, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO11, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO11, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO11, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO11, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO11, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO11, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_DO11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(11);
      end process;

    VitalBehavior_DO12  : process
      variable DO12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO12_zd := DO(12);

    VitalPathDelay01 (
      OutSignal => DO12,
      GlitchData => O_GlitchData,
      OutSignalName => "DO12",
      OutTemp => DO12_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO12, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO12, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO12, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO12, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO12, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO12, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO12, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO12, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO12, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO12, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_DO12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(12);
      end process;

    VitalBehavior_DO13  : process
      variable DO13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO13_zd := DO(13);

    VitalPathDelay01 (
      OutSignal => DO13,
      GlitchData => O_GlitchData,
      OutSignalName => "DO13",
      OutTemp => DO13_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO13, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO13, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO13, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO13, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO13, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO13, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO13, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO13, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO13, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO13, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_DO13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(13);
      end process;

    VitalBehavior_DO14  : process
      variable DO14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO14_zd := DO(14);

    VitalPathDelay01 (
      OutSignal => DO14,
      GlitchData => O_GlitchData,
      OutSignalName => "DO14",
      OutTemp => DO14_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO14, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO14, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO14, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO14, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO14, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO14, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO14, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO14, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO14, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO14, TRUE),
              10 => (RST_ipd'last_event, tpd_RST_DO14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(14);
      end process;

    VitalBehavior_DO15  : process
      variable DO15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO15_zd := DO(15);

    VitalPathDelay01 (
      OutSignal => DO15,
      GlitchData => O_GlitchData,
      OutSignalName => "DO15",
      OutTemp => DO15_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO15, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO15, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO15, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO15, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO15, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO15, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO15, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO15, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO15, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO15, TRUE),
              10 => (RST_ipd'last_event, tpd_RST_DO15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(15);
      end process;

    VitalBehavior_DO16  : process
      variable DO16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO16_zd := DO(16);

    VitalPathDelay01 (
      OutSignal => DO16,
      GlitchData => O_GlitchData,
      OutSignalName => "DO16",
      OutTemp => DO16_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO16, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO16, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO16, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO16, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO16, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO16, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO16, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO16, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO16, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO16, TRUE),
              10 => (RST_ipd'last_event, tpd_RST_DO16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(16);
      end process;

    VitalBehavior_DO17  : process
      variable DO17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO17_zd := DO(17);

    VitalPathDelay01 (
      OutSignal => DO17,
      GlitchData => O_GlitchData,
      OutSignalName => "DO17",
      OutTemp => DO17_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO17, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO17, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO17, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO17, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO17, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO17, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO17, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO17, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO17, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO17, TRUE),
              10 => (RST_ipd'last_event, tpd_RST_DO17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(17);
      end process;

    VitalBehavior_DO18  : process
      variable DO18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO18_zd := DO(18);

    VitalPathDelay01 (
      OutSignal => DO18,
      GlitchData => O_GlitchData,
      OutSignalName => "DO18",
      OutTemp => DO18_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO18, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO18, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO18, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO18, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO18, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO18, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO18, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO18, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO18, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO18, TRUE),
              10 => (RST_ipd'last_event, tpd_RST_DO18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(18);
      end process;

    VitalBehavior_DO19  : process
      variable DO19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO19_zd := DO(19);

    VitalPathDelay01 (
      OutSignal => DO19,
      GlitchData => O_GlitchData,
      OutSignalName => "DO19",
      OutTemp => DO19_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO19, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO19, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO19, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO19, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO19, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO19, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO19, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO19, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO19, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO19, TRUE),
              10 => (RST_ipd'last_event, tpd_RST_DO19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(19);
      end process;

    VitalBehavior_DO20  : process
      variable DO20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO20_zd := DO(20);

    VitalPathDelay01 (
      OutSignal => DO20,
      GlitchData => O_GlitchData,
      OutSignalName => "DO20",
      OutTemp => DO20_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO20, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO20, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO20, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO20, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO20, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO20, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO20, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO20, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO20, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO20, TRUE),
              10 => (RST_ipd'last_event, tpd_RST_DO20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(20);
      end process;

    VitalBehavior_DO21  : process
      variable DO21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO21_zd := DO(21);

    VitalPathDelay01 (
      OutSignal => DO21,
      GlitchData => O_GlitchData,
      OutSignalName => "DO21",
      OutTemp => DO21_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO21, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO21, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO21, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO21, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO21, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO21, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO21, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO21, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO21, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO21, TRUE),
              10 => (RST_ipd'last_event, tpd_RST_DO21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(21);
      end process;

    VitalBehavior_DO22  : process
      variable DO22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO22_zd := DO(22);

    VitalPathDelay01 (
      OutSignal => DO22,
      GlitchData => O_GlitchData,
      OutSignalName => "DO22",
      OutTemp => DO22_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO22, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO22, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO22, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO22, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO22, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO22, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO22, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO22, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO22, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO22, TRUE),
              10 => (RST_ipd'last_event, tpd_RST_DO22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(22);
      end process;

    VitalBehavior_DO23  : process
      variable DO23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO23_zd := DO(23);

    VitalPathDelay01 (
      OutSignal => DO23,
      GlitchData => O_GlitchData,
      OutSignalName => "DO23",
      OutTemp => DO23_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO23, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO23, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO23, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO23, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO23, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO23, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO23, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO23, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO23, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO23, TRUE),
              10 => (RST_ipd'last_event, tpd_RST_DO23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(23);
      end process;

    VitalBehavior_DO24  : process
      variable DO24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO24_zd := DO(24);

    VitalPathDelay01 (
      OutSignal => DO24,
      GlitchData => O_GlitchData,
      OutSignalName => "DO24",
      OutTemp => DO24_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO24, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO24, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO24, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO24, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO24, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO24, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO24, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO24, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO24, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO24, TRUE),
              10 => (RST_ipd'last_event, tpd_RST_DO24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(24);
      end process;

    VitalBehavior_DO25  : process
      variable DO25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO25_zd := DO(25);

    VitalPathDelay01 (
      OutSignal => DO25,
      GlitchData => O_GlitchData,
      OutSignalName => "DO25",
      OutTemp => DO25_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO25, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO25, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO25, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO25, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO25, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO25, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO25, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO25, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO25, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO25, TRUE),
              10 => (RST_ipd'last_event, tpd_RST_DO25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(25);
      end process;

    VitalBehavior_DO26  : process
      variable DO26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO26_zd := DO(26);

    VitalPathDelay01 (
      OutSignal => DO26,
      GlitchData => O_GlitchData,
      OutSignalName => "DO26",
      OutTemp => DO26_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO26, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO26, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO26, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO26, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO26, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO26, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO26, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO26, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO26, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO26, TRUE),
              10 => (RST_ipd'last_event, tpd_RST_DO26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(26);
      end process;

    VitalBehavior_DO27  : process
      variable DO27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO27_zd := DO(27);

    VitalPathDelay01 (
      OutSignal => DO27,
      GlitchData => O_GlitchData,
      OutSignalName => "DO27",
      OutTemp => DO27_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO27, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO27, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO27, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO27, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO27, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO27, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO27, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO27, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO27, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO27, TRUE),
              10 => (RST_ipd'last_event, tpd_RST_DO27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(27);
      end process;

    VitalBehavior_DO28  : process
      variable DO28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO28_zd := DO(28);

    VitalPathDelay01 (
      OutSignal => DO28,
      GlitchData => O_GlitchData,
      OutSignalName => "DO28",
      OutTemp => DO28_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO28, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO28, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO28, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO28, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO28, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO28, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO28, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO28, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO28, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO28, TRUE),
              10 => (RST_ipd'last_event, tpd_RST_DO28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(28);
      end process;

    VitalBehavior_DO29  : process
      variable DO29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO29_zd := DO(29);

    VitalPathDelay01 (
      OutSignal => DO29,
      GlitchData => O_GlitchData,
      OutSignalName => "DO29",
      OutTemp => DO29_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO29, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO29, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO29, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO29, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO29, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO29, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO29, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO29, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO29, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO29, TRUE),
              10 => (RST_ipd'last_event, tpd_RST_DO29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(29);
      end process;

    VitalBehavior_DO30  : process
      variable DO30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO30_zd := DO(30);

    VitalPathDelay01 (
      OutSignal => DO30,
      GlitchData => O_GlitchData,
      OutSignalName => "DO30",
      OutTemp => DO30_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO30, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO30, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO30, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO30, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO30, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO30, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO30, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO30, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO30, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO30, TRUE),
              10 => (RST_ipd'last_event, tpd_RST_DO30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(30);
      end process;

    VitalBehavior_DO31  : process
      variable DO31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO31_zd := DO(31);

    VitalPathDelay01 (
      OutSignal => DO31,
      GlitchData => O_GlitchData,
      OutSignalName => "DO31",
      OutTemp => DO31_zd,
      Paths => (
               0 => (AD0_ipd'last_event, tpd_AD0_DO31, TRUE),
               1 => (AD1_ipd'last_event, tpd_AD1_DO31, TRUE),
               2 => (AD2_ipd'last_event, tpd_AD2_DO31, TRUE),
               3 => (AD3_ipd'last_event, tpd_AD3_DO31, TRUE),
               4 => (AD4_ipd'last_event, tpd_AD4_DO31, TRUE),
               5 => (AD5_ipd'last_event, tpd_AD5_DO31, TRUE),
               6 => (AD6_ipd'last_event, tpd_AD6_DO31, TRUE),
               7 => (AD7_ipd'last_event, tpd_AD7_DO31, TRUE),
               8 => (AD8_ipd'last_event, tpd_AD8_DO31, TRUE),
               9 => (CLK_ipd'last_event, tpd_CLK_DO31, TRUE),
              10 => (RST_ipd'last_event, tpd_RST_DO31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(31);
      end process;



	SPRAMA_INST: SC_SPRAMA_16K
	   generic map (
		ADDR_WIDTH    => 9,
		DATA_WIDTH    => 32,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
		MEM_INIT_FILE => RAM_INIT_FILE)
	   port map (
		CEN => CEN_ipd,
		CLK => CLK_ipd,
		WR  => WR_ipd,
		CS  => CS,
		RST => RST_ipd,
		DI  => DI,
		AD  => AD,
		DO  => DO
		);

end VITAL;

configuration CFG_RAMB16KA_X32_VITAL of RAMB16KA_X32 is
   for VITAL
   end for;
end CFG_RAMB16KA_X32_VITAL;



----- CELL RAMBFIFO16KX1A -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity RAMBFIFO16KX1A is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
--      RAM_INIT_FILE      : string  := "dummy";
      FIFO_FULL_FLAG     : integer  := 16384;
      FIFO_AMFULL_FLAG   : integer :=  1;
      FIFO_AMEMPTY_FLAG  : integer := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO0                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             :	in    STD_ULOGIC;
      DO0                             :	out   STD_ULOGIC;
      FULL                            :	out   STD_ULOGIC;
      EMPTY                           :	out   STD_ULOGIC;
      AMFULL                          :	out   STD_ULOGIC;
      AMEMPTY                         :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KX1A : entity is FALSE;
end RAMBFIFO16KX1A;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMBFIFO16KX1A is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';

      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_logic_vector(0 downto 0);

      signal DI : std_logic_vector(0 downto 0);
      signal DO : std_logic_vector(0 downto 0);
      signal FULL_sig  : std_logic;
      signal EMPTY_sig : std_logic;
      signal AMFULL_sig  : std_logic;
      signal AMEMPTY_sig : std_logic;

begin 

      DI <= DI0_ipd ; 

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd(0), DI0, tipd_DI0);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KX1A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KX1A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd(0),
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KX1A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KX1A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KX1A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KX1A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KX1A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KX1A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KX1A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;


      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_16K 
  generic map (
        WADDR_WIDTH    => 14,
        WDATA_WIDTH    => 1,
        RADDR_WIDTH    => 14,
        RDATA_WIDTH    => 1,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open
         )
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO); 

end VITAL;

configuration CFG_RAMBFIFO16KX1A_VITAL of RAMBFIFO16KX1A is
   for VITAL
   end for;
end CFG_RAMBFIFO16KX1A_VITAL;



----- CELL RAMBFIFO8KX2A -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity RAMBFIFO8KX2A is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
--      RAM_INIT_FILE   : string  := "dummy";
      FIFO_FULL_FLAG     : integer  := 8192;
      FIFO_AMFULL_FLAG   : integer :=  1;
      FIFO_AMEMPTY_FLAG  : integer := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO0                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             :	in    STD_ULOGIC;
      DI1                             :	in    STD_ULOGIC;
      DO0                             :	out   STD_ULOGIC;
      DO1                             :	out   STD_ULOGIC;
      FULL                            :	out   STD_ULOGIC;
      EMPTY                           :	out   STD_ULOGIC;
      AMFULL                          :	out   STD_ULOGIC;
      AMEMPTY                         :	out   STD_ULOGIC);


attribute VITAL_LEVEL0 of RAMBFIFO8KX2A : entity is FALSE;
end RAMBFIFO8KX2A;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMBFIFO8KX2A is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';

      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';

      signal DI : std_logic_vector(1 downto 0);
      signal DO : std_logic_vector(1 downto 0);
      signal FULL_sig  : std_logic;
      signal EMPTY_sig : std_logic;
      signal AMFULL_sig  : std_logic;
      signal AMEMPTY_sig : std_logic;

begin 

      DI <= DI1_ipd & DI0_ipd ; 
 

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO8KX2A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO8KX2A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO8KX2A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO8KX2A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO8KX2A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO8KX2A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO8KX2A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO8KX2A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO8KX2A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO8KX2A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or Tviol_DI1_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;


      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;



  FIFO_INST: SC_FIFO_16K 
  generic map (
        WADDR_WIDTH    => 13,
        WDATA_WIDTH    => 2,
        RADDR_WIDTH    => 13,
        RDATA_WIDTH    => 2,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open
         )
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      );

end VITAL;

configuration CFG_RAMBFIFO8KX2A_VITAL of RAMBFIFO8KX2A is
   for VITAL
   end for;
end CFG_RAMBFIFO8KX2A_VITAL;



----- CELL RAMBFIFO4KX4A -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity RAMBFIFO4KX4A is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
--      RAM_INIT_FILE   : string  := "dummy";
      FIFO_FULL_FLAG     : integer  := 4096;
      FIFO_AMFULL_FLAG   : integer :=  1;
      FIFO_AMEMPTY_FLAG  : integer := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             :	in    STD_ULOGIC;
      DI1                             :	in    STD_ULOGIC;
      DI2                             :	in    STD_ULOGIC;
      DI3                             :	in    STD_ULOGIC;
      DO0                             :	out   STD_ULOGIC;
      DO1                             :	out   STD_ULOGIC;
      DO2                             :	out   STD_ULOGIC;
      DO3                             :	out   STD_ULOGIC;
      FULL                            :	out   STD_ULOGIC;
      EMPTY                           :	out   STD_ULOGIC;
      AMFULL                          :	out   STD_ULOGIC;
      AMEMPTY                         :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO4KX4A : entity is FALSE;
end RAMBFIFO4KX4A;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMBFIFO4KX4A is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';

      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';

      signal DI : std_logic_vector(3 downto 0);
      signal DO : std_logic_vector(3 downto 0);
      signal FULL_sig  : std_logic;
      signal EMPTY_sig : std_logic;
      signal AMFULL_sig  : std_logic;
      signal AMEMPTY_sig : std_logic;

begin 

      DI <= DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ; 
 

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI0);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI1);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO4KX4A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO4KX4A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO4KX4A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO4KX4A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO4KX4A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO4KX4A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO4KX4A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO4KX4A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO4KX4A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO4KX4A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO4KX4A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO4KX4A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or Tviol_DI3_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;


      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_16K 
  generic map (
        WADDR_WIDTH    => 12,
        WDATA_WIDTH    => 4,
        RADDR_WIDTH    => 12,
        RDATA_WIDTH    => 4,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open
         )
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO4KX4A_VITAL of RAMBFIFO4KX4A is
   for VITAL
   end for;
end CFG_RAMBFIFO4KX4A_VITAL;



----- CELL RAMBFIFO2KX8A -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity RAMBFIFO2KX8A is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
--      RAM_INIT_FILE   : string  := "dummy";
      FIFO_FULL_FLAG     : integer  := 2048;
      FIFO_AMFULL_FLAG   : integer :=  1;
      FIFO_AMEMPTY_FLAG  : integer := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI4_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI5_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI6_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI7_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             :	in    STD_ULOGIC;
      DI1                             :	in    STD_ULOGIC;
      DI2                             :	in    STD_ULOGIC;
      DI3                             :	in    STD_ULOGIC;
      DI4                             :	in    STD_ULOGIC;
      DI5                             :	in    STD_ULOGIC;
      DI6                             :	in    STD_ULOGIC;
      DI7                             :	in    STD_ULOGIC;
      DO0                             :	out   STD_ULOGIC;
      DO1                             :	out   STD_ULOGIC;
      DO2                             :	out   STD_ULOGIC;
      DO3                             :	out   STD_ULOGIC;
      DO4                             :	out   STD_ULOGIC;
      DO5                             :	out   STD_ULOGIC;
      DO6                             :	out   STD_ULOGIC;
      DO7                             :	out   STD_ULOGIC;
      FULL                            :	out   STD_ULOGIC;
      EMPTY                           :	out   STD_ULOGIC;
      AMFULL                          :	out   STD_ULOGIC;
      AMEMPTY                         :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO2KX8A : entity is FALSE;
end RAMBFIFO2KX8A;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMBFIFO2KX8A is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';

      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI4_ipd       : std_ulogic := 'X';
      signal DI5_ipd       : std_ulogic := 'X';
      signal DI6_ipd       : std_ulogic := 'X';
      signal DI7_ipd       : std_ulogic := 'X';

      signal DI : std_logic_vector(7 downto 0);
      signal DO : std_logic_vector(7 downto 0);
      signal FULL_sig  : std_logic;
      signal EMPTY_sig : std_logic;
      signal AMFULL_sig  : std_logic;
      signal AMEMPTY_sig : std_logic;

begin 

      DI <= DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & 
            DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ; 
  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI4_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI5_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI6_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI7_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO2KX8A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO2KX8A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO2KX8A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO2KX8A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO2KX8A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO2KX8A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_WCLK_posedge,
          TimingData              => Tmkr_DI4_WCLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI4_WCLK_noedge_posedge,
          HoldLow                 => thold_DI4_WCLK_noedge_posedge,
          HoldHigh                => thold_DI4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO2KX8A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_WCLK_posedge,
          TimingData              => Tmkr_DI5_WCLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI5_WCLK_noedge_posedge,
          HoldLow                 => thold_DI5_WCLK_noedge_posedge,
          HoldHigh                => thold_DI5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO2KX8A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_WCLK_posedge,
          TimingData              => Tmkr_DI6_WCLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI6_WCLK_noedge_posedge,
          HoldLow                 => thold_DI6_WCLK_noedge_posedge,
          HoldHigh                => thold_DI6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO2KX8A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_WCLK_posedge,
          TimingData              => Tmkr_DI7_WCLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI7_WCLK_noedge_posedge,
          HoldLow                 => thold_DI7_WCLK_noedge_posedge,
          HoldHigh                => thold_DI7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO2KX8A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO2KX8A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO2KX8A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO2KX8A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO2KX8A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO2KX8A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO2KX8A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or Tviol_DI3_WCLK_posedge or 
                 Tviol_DI4_WCLK_posedge or Tviol_DI5_WCLK_posedge or 
                 Tviol_DI6_WCLK_posedge or Tviol_DI7_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;


      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_16K 
  generic map (
        WADDR_WIDTH    => 11,
        WDATA_WIDTH    => 8,
        RADDR_WIDTH    => 11,
        RDATA_WIDTH    => 8,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open
         )
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO2KX8A_VITAL of RAMBFIFO2KX8A is
   for VITAL
   end for;
end CFG_RAMBFIFO2KX8A_VITAL;



----- CELL RAMBFIFO1KX16A -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity RAMBFIFO1KX16A is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
--      RAM_INIT_FILE   : string  := "dummy";
      FIFO_FULL_FLAG     : integer  := 1024;
      FIFO_AMFULL_FLAG   : integer :=  1;
      FIFO_AMEMPTY_FLAG  : integer := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO8                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO9                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO15                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI4_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI5_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI6_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI7_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI8_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI8_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI9_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI9_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI10_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI10_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI11_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI11_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI12_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI12_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI13_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI13_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI14_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI14_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI15_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI15_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI8                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI9                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI10                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI11                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI12                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI13                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI14                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI15                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             :	in    STD_ULOGIC;
      DI1                             :	in    STD_ULOGIC;
      DI2                             :	in    STD_ULOGIC;
      DI3                             :	in    STD_ULOGIC;
      DI4                             :	in    STD_ULOGIC;
      DI5                             :	in    STD_ULOGIC;
      DI6                             :	in    STD_ULOGIC;
      DI7                             :	in    STD_ULOGIC;
      DI8                             :	in    STD_ULOGIC;
      DI9                             :	in    STD_ULOGIC;
      DI10                            :	in    STD_ULOGIC;
      DI11                            :	in    STD_ULOGIC;
      DI12                            :	in    STD_ULOGIC;
      DI13                            :	in    STD_ULOGIC;
      DI14                            :	in    STD_ULOGIC;
      DI15                            :	in    STD_ULOGIC;
      DO0                             :	out   STD_ULOGIC;
      DO1                             :	out   STD_ULOGIC;
      DO2                             :	out   STD_ULOGIC;
      DO3                             :	out   STD_ULOGIC;
      DO4                             :	out   STD_ULOGIC;
      DO5                             :	out   STD_ULOGIC;
      DO6                             :	out   STD_ULOGIC;
      DO7                             :	out   STD_ULOGIC;
      DO8                             :	out   STD_ULOGIC;
      DO9                             :	out   STD_ULOGIC;
      DO10                            :	out   STD_ULOGIC;
      DO11                            :	out   STD_ULOGIC;
      DO12                            :	out   STD_ULOGIC;
      DO13                            :	out   STD_ULOGIC;
      DO14                            :	out   STD_ULOGIC;
      DO15                            :	out   STD_ULOGIC;
      FULL                            :	out   STD_ULOGIC;
      EMPTY                           :	out   STD_ULOGIC;
      AMFULL                          :	out   STD_ULOGIC;
      AMEMPTY                         :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO1KX16A : entity is FALSE;
end RAMBFIFO1KX16A;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMBFIFO1KX16A is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';

      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI4_ipd       : std_ulogic := 'X';
      signal DI5_ipd       : std_ulogic := 'X';
      signal DI6_ipd       : std_ulogic := 'X';
      signal DI7_ipd       : std_ulogic := 'X';
      signal DI8_ipd       : std_ulogic := 'X';
      signal DI9_ipd       : std_ulogic := 'X';
      signal DI10_ipd       : std_ulogic := 'X';
      signal DI11_ipd       : std_ulogic := 'X';
      signal DI12_ipd       : std_ulogic := 'X';
      signal DI13_ipd       : std_ulogic := 'X';
      signal DI14_ipd       : std_ulogic := 'X';
      signal DI15_ipd       : std_ulogic := 'X';

      signal DI : std_logic_vector(15 downto 0);
      signal DO : std_logic_vector(15 downto 0);
      signal FULL_sig  : std_logic;
      signal EMPTY_sig : std_logic;
      signal AMFULL_sig  : std_logic;
      signal AMEMPTY_sig : std_logic;

begin 

      DI <= DI15_ipd & DI14_ipd & DI13_ipd & DI12_ipd & 
            DI11_ipd & DI10_ipd & DI9_ipd & DI8_ipd & 
            DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & 
            DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ; 

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);
        VitalWireDelay (DI8_ipd, DI8, tipd_DI8);
        VitalWireDelay (DI9_ipd, DI9, tipd_DI9);
        VitalWireDelay (DI10_ipd, DI10, tipd_DI10);
        VitalWireDelay (DI11_ipd, DI11, tipd_DI11);
        VitalWireDelay (DI12_ipd, DI12, tipd_DI12);
        VitalWireDelay (DI13_ipd, DI13, tipd_DI13);
        VitalWireDelay (DI14_ipd, DI14, tipd_DI14);
        VitalWireDelay (DI15_ipd, DI15, tipd_DI15);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI4_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI5_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI6_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI7_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI8_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI9_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI10_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI11_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI12_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI13_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI14_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI15_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI8_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI9_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI10_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI11_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI12_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI13_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI14_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI15_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable DO8_zd          : std_ulogic := 'X';
        variable DO9_zd          : std_ulogic := 'X';
        variable DO10_zd          : std_ulogic := 'X';
        variable DO11_zd          : std_ulogic := 'X';
        variable DO12_zd          : std_ulogic := 'X';
        variable DO13_zd          : std_ulogic := 'X';
        variable DO14_zd          : std_ulogic := 'X';
        variable DO15_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_WCLK_posedge,
          TimingData              => Tmkr_DI4_WCLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI4_WCLK_noedge_posedge,
          HoldLow                 => thold_DI4_WCLK_noedge_posedge,
          HoldHigh                => thold_DI4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_WCLK_posedge,
          TimingData              => Tmkr_DI5_WCLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI5_WCLK_noedge_posedge,
          HoldLow                 => thold_DI5_WCLK_noedge_posedge,
          HoldHigh                => thold_DI5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_WCLK_posedge,
          TimingData              => Tmkr_DI6_WCLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI6_WCLK_noedge_posedge,
          HoldLow                 => thold_DI6_WCLK_noedge_posedge,
          HoldHigh                => thold_DI6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_WCLK_posedge,
          TimingData              => Tmkr_DI7_WCLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI7_WCLK_noedge_posedge,
          HoldLow                 => thold_DI7_WCLK_noedge_posedge,
          HoldHigh                => thold_DI7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI8_WCLK_posedge,
          TimingData              => Tmkr_DI8_WCLK_posedge,
          TestSignal              => DI8_ipd,
          TestSignalName          => "DI8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI8_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI8_WCLK_noedge_posedge,
          HoldLow                 => thold_DI8_WCLK_noedge_posedge,
          HoldHigh                => thold_DI8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI9_WCLK_posedge,
          TimingData              => Tmkr_DI9_WCLK_posedge,
          TestSignal              => DI9_ipd,
          TestSignalName          => "DI9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI9_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI9_WCLK_noedge_posedge,
          HoldLow                 => thold_DI9_WCLK_noedge_posedge,
          HoldHigh                => thold_DI9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI10_WCLK_posedge,
          TimingData              => Tmkr_DI10_WCLK_posedge,
          TestSignal              => DI10_ipd,
          TestSignalName          => "DI10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI10_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI10_WCLK_noedge_posedge,
          HoldLow                 => thold_DI10_WCLK_noedge_posedge,
          HoldHigh                => thold_DI10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI11_WCLK_posedge,
          TimingData              => Tmkr_DI11_WCLK_posedge,
          TestSignal              => DI11_ipd,
          TestSignalName          => "DI11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI11_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI11_WCLK_noedge_posedge,
          HoldLow                 => thold_DI11_WCLK_noedge_posedge,
          HoldHigh                => thold_DI11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI12_WCLK_posedge,
          TimingData              => Tmkr_DI12_WCLK_posedge,
          TestSignal              => DI12_ipd,
          TestSignalName          => "DI12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI12_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI12_WCLK_noedge_posedge,
          HoldLow                 => thold_DI12_WCLK_noedge_posedge,
          HoldHigh                => thold_DI12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI13_WCLK_posedge,
          TimingData              => Tmkr_DI13_WCLK_posedge,
          TestSignal              => DI13_ipd,
          TestSignalName          => "DI13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI13_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI13_WCLK_noedge_posedge,
          HoldLow                 => thold_DI13_WCLK_noedge_posedge,
          HoldHigh                => thold_DI13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI14_WCLK_posedge,
          TimingData              => Tmkr_DI14_WCLK_posedge,
          TestSignal              => DI14_ipd,
          TestSignalName          => "DI14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI14_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI14_WCLK_noedge_posedge,
          HoldLow                 => thold_DI14_WCLK_noedge_posedge,
          HoldHigh                => thold_DI14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI15_WCLK_posedge,
          TimingData              => Tmkr_DI15_WCLK_posedge,
          TestSignal              => DI15_ipd,
          TestSignalName          => "DI15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI15_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI15_WCLK_noedge_posedge,
          HoldLow                 => thold_DI15_WCLK_noedge_posedge,
          HoldHigh                => thold_DI15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO1KX16A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or Tviol_DI3_WCLK_posedge or 
                 Tviol_DI4_WCLK_posedge or Tviol_DI5_WCLK_posedge or 
                 Tviol_DI6_WCLK_posedge or Tviol_DI7_WCLK_posedge or 
                 Tviol_DI8_WCLK_posedge or Tviol_DI9_WCLK_posedge or 
                 Tviol_DI10_WCLK_posedge or Tviol_DI11_WCLK_posedge or 
                 Tviol_DI12_WCLK_posedge or Tviol_DI13_WCLK_posedge or 
                 Tviol_DI14_WCLK_posedge or Tviol_DI15_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_DO8  : process
      variable DO8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO8_zd := DO(8);

    VitalPathDelay01 (
      OutSignal => DO8,
      GlitchData => O_GlitchData,
      OutSignalName => "DO8",
      OutTemp => DO8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(8);
      end process;

    VitalBehavior_DO9  : process
      variable DO9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO9_zd := DO(9);

    VitalPathDelay01 (
      OutSignal => DO9,
      GlitchData => O_GlitchData,
      OutSignalName => "DO9",
      OutTemp => DO9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(9);
      end process;

    VitalBehavior_DO10  : process
      variable DO10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO10_zd := DO(10);

    VitalPathDelay01 (
      OutSignal => DO10,
      GlitchData => O_GlitchData,
      OutSignalName => "DO10",
      OutTemp => DO10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(10);
      end process;

    VitalBehavior_DO11  : process
      variable DO11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO11_zd := DO(11);

    VitalPathDelay01 (
      OutSignal => DO11,
      GlitchData => O_GlitchData,
      OutSignalName => "DO11",
      OutTemp => DO11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(11);
      end process;

    VitalBehavior_DO12  : process
      variable DO12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO12_zd := DO(12);

    VitalPathDelay01 (
      OutSignal => DO12,
      GlitchData => O_GlitchData,
      OutSignalName => "DO12",
      OutTemp => DO12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(12);
      end process;

    VitalBehavior_DO13  : process
      variable DO13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO13_zd := DO(13);

    VitalPathDelay01 (
      OutSignal => DO13,
      GlitchData => O_GlitchData,
      OutSignalName => "DO13",
      OutTemp => DO13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(13);
      end process;

    VitalBehavior_DO14  : process
      variable DO14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO14_zd := DO(14);

    VitalPathDelay01 (
      OutSignal => DO14,
      GlitchData => O_GlitchData,
      OutSignalName => "DO14",
      OutTemp => DO14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(14);
      end process;

    VitalBehavior_DO15  : process
      variable DO15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO15_zd := DO(15);

    VitalPathDelay01 (
      OutSignal => DO15,
      GlitchData => O_GlitchData,
      OutSignalName => "DO15",
      OutTemp => DO15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(15);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_16K 
  generic map (
        WADDR_WIDTH    => 10,
        WDATA_WIDTH    => 16,
        RADDR_WIDTH    => 10,
        RDATA_WIDTH    => 16,
        MEM_INIT_FLAG  => 0, 
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG, 
        MEM_INIT_FILE  => open
         )
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 
end VITAL;

configuration CFG_RAMBFIFO1KX16A_VITAL of RAMBFIFO1KX16A is
   for VITAL
   end for;
end CFG_RAMBFIFO1KX16A_VITAL;



----- CELL RAMBFIFO512X28A -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity RAMBFIFO512X28A is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
--      RAM_INIT_FILE   : string  := "dummy";
      FIFO_FULL_FLAG     : integer  := 512;
      FIFO_AMFULL_FLAG   : integer :=  1;
      FIFO_AMEMPTY_FLAG  : integer := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO16                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO17                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO18                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO19                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO20                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO21                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO22                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO23                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO24                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO25                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO8                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO9                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO15                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO16                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO17                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO18                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO19                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO20                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO21                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO22                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO23                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO24                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO25                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO26                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO27                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI4_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI5_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI6_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI7_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI8_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI8_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI9_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI9_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI10_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI10_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI11_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI11_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI12_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI12_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI13_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI13_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI14_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI14_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI15_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI15_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI16_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI16_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI17_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI17_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI18_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI18_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI19_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI19_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI20_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI20_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI21_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI21_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI22_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI22_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI23_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI23_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI24_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI24_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI25_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI25_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI26_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI26_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI27_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI27_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI8                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI9                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI10                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI11                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI12                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI13                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI14                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI15                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI16                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI17                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI18                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI19                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI20                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI21                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI22                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI23                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI24                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI25                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI26                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI27                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             :	in    STD_ULOGIC;
      DI1                             :	in    STD_ULOGIC;
      DI2                             :	in    STD_ULOGIC;
      DI3                             :	in    STD_ULOGIC;
      DI4                             :	in    STD_ULOGIC;
      DI5                             :	in    STD_ULOGIC;
      DI6                             :	in    STD_ULOGIC;
      DI7                             :	in    STD_ULOGIC;
      DI8                             :	in    STD_ULOGIC;
      DI9                             :	in    STD_ULOGIC;
      DI10                            :	in    STD_ULOGIC;
      DI11                            :	in    STD_ULOGIC;
      DI12                            :	in    STD_ULOGIC;
      DI13                            :	in    STD_ULOGIC;
      DI14                            :	in    STD_ULOGIC;
      DI15                            :	in    STD_ULOGIC;
      DI16                            :	in    STD_ULOGIC;
      DI17                            :	in    STD_ULOGIC;
      DI18                            :	in    STD_ULOGIC;
      DI19                            :	in    STD_ULOGIC;
      DI20                            :	in    STD_ULOGIC;
      DI21                            :	in    STD_ULOGIC;
      DI22                            :	in    STD_ULOGIC;
      DI23                            :	in    STD_ULOGIC;
      DI24                            :	in    STD_ULOGIC;
      DI25                            :	in    STD_ULOGIC;
      DI26                            :	in    STD_ULOGIC;
      DI27                            :	in    STD_ULOGIC;
      DO0                             :	out   STD_ULOGIC;
      DO1                             :	out   STD_ULOGIC;
      DO2                             :	out   STD_ULOGIC;
      DO3                             :	out   STD_ULOGIC;
      DO4                             :	out   STD_ULOGIC;
      DO5                             :	out   STD_ULOGIC;
      DO6                             :	out   STD_ULOGIC;
      DO7                             :	out   STD_ULOGIC;
      DO8                             :	out   STD_ULOGIC;
      DO9                             :	out   STD_ULOGIC;
      DO10                            :	out   STD_ULOGIC;
      DO11                            :	out   STD_ULOGIC;
      DO12                            :	out   STD_ULOGIC;
      DO13                            :	out   STD_ULOGIC;
      DO14                            :	out   STD_ULOGIC;
      DO15                            :	out   STD_ULOGIC;
      DO16                            :	out   STD_ULOGIC;
      DO17                            :	out   STD_ULOGIC;
      DO18                            :	out   STD_ULOGIC;
      DO19                            :	out   STD_ULOGIC;
      DO20                            :	out   STD_ULOGIC;
      DO21                            :	out   STD_ULOGIC;
      DO22                            :	out   STD_ULOGIC;
      DO23                            :	out   STD_ULOGIC;
      DO24                            :	out   STD_ULOGIC;
      DO25                            :	out   STD_ULOGIC;
      DO26                            :	out   STD_ULOGIC;
      DO27                            :	out   STD_ULOGIC;
      FULL                            :	out   STD_ULOGIC;
      EMPTY                           :	out   STD_ULOGIC;
      AMFULL                          :	out   STD_ULOGIC;
      AMEMPTY                         :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO512X28A : entity is FALSE;
end RAMBFIFO512X28A;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMBFIFO512X28A is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';

      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI4_ipd       : std_ulogic := 'X';
      signal DI5_ipd       : std_ulogic := 'X';
      signal DI6_ipd       : std_ulogic := 'X';
      signal DI7_ipd       : std_ulogic := 'X';
      signal DI8_ipd       : std_ulogic := 'X';
      signal DI9_ipd       : std_ulogic := 'X';
      signal DI10_ipd       : std_ulogic := 'X';
      signal DI11_ipd       : std_ulogic := 'X';
      signal DI12_ipd       : std_ulogic := 'X';
      signal DI13_ipd       : std_ulogic := 'X';
      signal DI14_ipd       : std_ulogic := 'X';
      signal DI15_ipd       : std_ulogic := 'X';
      signal DI16_ipd       : std_ulogic := 'X';
      signal DI17_ipd       : std_ulogic := 'X';
      signal DI18_ipd       : std_ulogic := 'X';
      signal DI19_ipd       : std_ulogic := 'X';
      signal DI20_ipd       : std_ulogic := 'X';
      signal DI21_ipd       : std_ulogic := 'X';
      signal DI22_ipd       : std_ulogic := 'X';
      signal DI23_ipd       : std_ulogic := 'X';
      signal DI24_ipd       : std_ulogic := 'X';
      signal DI25_ipd       : std_ulogic := 'X';
      signal DI26_ipd       : std_ulogic := 'X';
      signal DI27_ipd       : std_ulogic := 'X';

      signal DI : std_logic_vector(27 downto 0);
      signal DO : std_logic_vector(27 downto 0);
      signal FULL_sig  : std_logic;
      signal EMPTY_sig : std_logic;
      signal AMFULL_sig  : std_logic;
      signal AMEMPTY_sig : std_logic;

begin 

      DI <= DI27_ipd & DI26_ipd & DI25_ipd & DI24_ipd & 
            DI23_ipd & DI22_ipd & DI21_ipd & DI20_ipd & 
            DI19_ipd & DI18_ipd & DI17_ipd & DI16_ipd & 
            DI15_ipd & DI14_ipd & DI13_ipd & DI12_ipd & 
            DI11_ipd & DI10_ipd & DI9_ipd & DI8_ipd & 
            DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & 
            DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ; 

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);
        VitalWireDelay (DI8_ipd, DI8, tipd_DI8);
        VitalWireDelay (DI9_ipd, DI9, tipd_DI9);
        VitalWireDelay (DI10_ipd, DI10, tipd_DI10);
        VitalWireDelay (DI11_ipd, DI11, tipd_DI11);
        VitalWireDelay (DI12_ipd, DI12, tipd_DI12);
        VitalWireDelay (DI13_ipd, DI13, tipd_DI13);
        VitalWireDelay (DI14_ipd, DI14, tipd_DI14);
        VitalWireDelay (DI15_ipd, DI15, tipd_DI15);
        VitalWireDelay (DI16_ipd, DI16, tipd_DI16);
        VitalWireDelay (DI17_ipd, DI17, tipd_DI17);
        VitalWireDelay (DI18_ipd, DI18, tipd_DI18);
        VitalWireDelay (DI19_ipd, DI19, tipd_DI19);
        VitalWireDelay (DI20_ipd, DI20, tipd_DI20);
        VitalWireDelay (DI21_ipd, DI21, tipd_DI21);
        VitalWireDelay (DI22_ipd, DI22, tipd_DI22);
        VitalWireDelay (DI23_ipd, DI23, tipd_DI23);
        VitalWireDelay (DI24_ipd, DI24, tipd_DI24);
        VitalWireDelay (DI25_ipd, DI25, tipd_DI25);
        VitalWireDelay (DI26_ipd, DI26, tipd_DI26);
        VitalWireDelay (DI27_ipd, DI27, tipd_DI27);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI4_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI5_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI6_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI7_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI8_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI9_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI10_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI11_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI12_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI13_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI14_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI15_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI16_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI17_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI18_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI19_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI20_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI21_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI22_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI23_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI24_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI25_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI26_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI27_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI8_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI9_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI10_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI11_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI12_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI13_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI14_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI15_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI16_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI17_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI18_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI19_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI20_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI21_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI22_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI23_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI24_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI25_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI26_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI27_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable DO8_zd          : std_ulogic := 'X';
        variable DO9_zd          : std_ulogic := 'X';
        variable DO10_zd          : std_ulogic := 'X';
        variable DO11_zd          : std_ulogic := 'X';
        variable DO12_zd          : std_ulogic := 'X';
        variable DO13_zd          : std_ulogic := 'X';
        variable DO14_zd          : std_ulogic := 'X';
        variable DO15_zd          : std_ulogic := 'X';
        variable DO16_zd          : std_ulogic := 'X';
        variable DO17_zd          : std_ulogic := 'X';
        variable DO18_zd          : std_ulogic := 'X';
        variable DO19_zd          : std_ulogic := 'X';
        variable DO20_zd          : std_ulogic := 'X';
        variable DO21_zd          : std_ulogic := 'X';
        variable DO22_zd          : std_ulogic := 'X';
        variable DO23_zd          : std_ulogic := 'X';
        variable DO24_zd          : std_ulogic := 'X';
        variable DO25_zd          : std_ulogic := 'X';
        variable DO26_zd          : std_ulogic := 'X';
        variable DO27_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_WCLK_posedge,
          TimingData              => Tmkr_DI4_WCLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI4_WCLK_noedge_posedge,
          HoldLow                 => thold_DI4_WCLK_noedge_posedge,
          HoldHigh                => thold_DI4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_WCLK_posedge,
          TimingData              => Tmkr_DI5_WCLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI5_WCLK_noedge_posedge,
          HoldLow                 => thold_DI5_WCLK_noedge_posedge,
          HoldHigh                => thold_DI5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_WCLK_posedge,
          TimingData              => Tmkr_DI6_WCLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI6_WCLK_noedge_posedge,
          HoldLow                 => thold_DI6_WCLK_noedge_posedge,
          HoldHigh                => thold_DI6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_WCLK_posedge,
          TimingData              => Tmkr_DI7_WCLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI7_WCLK_noedge_posedge,
          HoldLow                 => thold_DI7_WCLK_noedge_posedge,
          HoldHigh                => thold_DI7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI8_WCLK_posedge,
          TimingData              => Tmkr_DI8_WCLK_posedge,
          TestSignal              => DI8_ipd,
          TestSignalName          => "DI8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI8_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI8_WCLK_noedge_posedge,
          HoldLow                 => thold_DI8_WCLK_noedge_posedge,
          HoldHigh                => thold_DI8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI9_WCLK_posedge,
          TimingData              => Tmkr_DI9_WCLK_posedge,
          TestSignal              => DI9_ipd,
          TestSignalName          => "DI9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI9_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI9_WCLK_noedge_posedge,
          HoldLow                 => thold_DI9_WCLK_noedge_posedge,
          HoldHigh                => thold_DI9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI10_WCLK_posedge,
          TimingData              => Tmkr_DI10_WCLK_posedge,
          TestSignal              => DI10_ipd,
          TestSignalName          => "DI10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI10_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI10_WCLK_noedge_posedge,
          HoldLow                 => thold_DI10_WCLK_noedge_posedge,
          HoldHigh                => thold_DI10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI11_WCLK_posedge,
          TimingData              => Tmkr_DI11_WCLK_posedge,
          TestSignal              => DI11_ipd,
          TestSignalName          => "DI11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI11_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI11_WCLK_noedge_posedge,
          HoldLow                 => thold_DI11_WCLK_noedge_posedge,
          HoldHigh                => thold_DI11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI12_WCLK_posedge,
          TimingData              => Tmkr_DI12_WCLK_posedge,
          TestSignal              => DI12_ipd,
          TestSignalName          => "DI12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI12_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI12_WCLK_noedge_posedge,
          HoldLow                 => thold_DI12_WCLK_noedge_posedge,
          HoldHigh                => thold_DI12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI13_WCLK_posedge,
          TimingData              => Tmkr_DI13_WCLK_posedge,
          TestSignal              => DI13_ipd,
          TestSignalName          => "DI13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI13_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI13_WCLK_noedge_posedge,
          HoldLow                 => thold_DI13_WCLK_noedge_posedge,
          HoldHigh                => thold_DI13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI14_WCLK_posedge,
          TimingData              => Tmkr_DI14_WCLK_posedge,
          TestSignal              => DI14_ipd,
          TestSignalName          => "DI14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI14_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI14_WCLK_noedge_posedge,
          HoldLow                 => thold_DI14_WCLK_noedge_posedge,
          HoldHigh                => thold_DI14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI15_WCLK_posedge,
          TimingData              => Tmkr_DI15_WCLK_posedge,
          TestSignal              => DI15_ipd,
          TestSignalName          => "DI15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI15_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI15_WCLK_noedge_posedge,
          HoldLow                 => thold_DI15_WCLK_noedge_posedge,
          HoldHigh                => thold_DI15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI16_WCLK_posedge,
          TimingData              => Tmkr_DI16_WCLK_posedge,
          TestSignal              => DI16_ipd,
          TestSignalName          => "DI16",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI16_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI16_WCLK_noedge_posedge,
          HoldLow                 => thold_DI16_WCLK_noedge_posedge,
          HoldHigh                => thold_DI16_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI17_WCLK_posedge,
          TimingData              => Tmkr_DI17_WCLK_posedge,
          TestSignal              => DI17_ipd,
          TestSignalName          => "DI17",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI17_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI17_WCLK_noedge_posedge,
          HoldLow                 => thold_DI17_WCLK_noedge_posedge,
          HoldHigh                => thold_DI17_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI18_WCLK_posedge,
          TimingData              => Tmkr_DI18_WCLK_posedge,
          TestSignal              => DI18_ipd,
          TestSignalName          => "DI18",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI18_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI18_WCLK_noedge_posedge,
          HoldLow                 => thold_DI18_WCLK_noedge_posedge,
          HoldHigh                => thold_DI18_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI19_WCLK_posedge,
          TimingData              => Tmkr_DI19_WCLK_posedge,
          TestSignal              => DI19_ipd,
          TestSignalName          => "DI19",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI19_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI19_WCLK_noedge_posedge,
          HoldLow                 => thold_DI19_WCLK_noedge_posedge,
          HoldHigh                => thold_DI19_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI20_WCLK_posedge,
          TimingData              => Tmkr_DI20_WCLK_posedge,
          TestSignal              => DI20_ipd,
          TestSignalName          => "DI20",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI20_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI20_WCLK_noedge_posedge,
          HoldLow                 => thold_DI20_WCLK_noedge_posedge,
          HoldHigh                => thold_DI20_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI21_WCLK_posedge,
          TimingData              => Tmkr_DI21_WCLK_posedge,
          TestSignal              => DI21_ipd,
          TestSignalName          => "DI21",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI21_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI21_WCLK_noedge_posedge,
          HoldLow                 => thold_DI21_WCLK_noedge_posedge,
          HoldHigh                => thold_DI21_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI22_WCLK_posedge,
          TimingData              => Tmkr_DI22_WCLK_posedge,
          TestSignal              => DI22_ipd,
          TestSignalName          => "DI22",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI22_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI22_WCLK_noedge_posedge,
          HoldLow                 => thold_DI22_WCLK_noedge_posedge,
          HoldHigh                => thold_DI22_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI23_WCLK_posedge,
          TimingData              => Tmkr_DI23_WCLK_posedge,
          TestSignal              => DI23_ipd,
          TestSignalName          => "DI23",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI23_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI23_WCLK_noedge_posedge,
          HoldLow                 => thold_DI23_WCLK_noedge_posedge,
          HoldHigh                => thold_DI23_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI24_WCLK_posedge,
          TimingData              => Tmkr_DI24_WCLK_posedge,
          TestSignal              => DI24_ipd,
          TestSignalName          => "DI24",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI24_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI24_WCLK_noedge_posedge,
          HoldLow                 => thold_DI24_WCLK_noedge_posedge,
          HoldHigh                => thold_DI24_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI25_WCLK_posedge,
          TimingData              => Tmkr_DI25_WCLK_posedge,
          TestSignal              => DI25_ipd,
          TestSignalName          => "DI25",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI25_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI25_WCLK_noedge_posedge,
          HoldLow                 => thold_DI25_WCLK_noedge_posedge,
          HoldHigh                => thold_DI25_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI26_WCLK_posedge,
          TimingData              => Tmkr_DI26_WCLK_posedge,
          TestSignal              => DI26_ipd,
          TestSignalName          => "DI26",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI26_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI26_WCLK_noedge_posedge,
          HoldLow                 => thold_DI26_WCLK_noedge_posedge,
          HoldHigh                => thold_DI26_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI27_WCLK_posedge,
          TimingData              => Tmkr_DI27_WCLK_posedge,
          TestSignal              => DI27_ipd,
          TestSignalName          => "DI27",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI27_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI27_WCLK_noedge_posedge,
          HoldLow                 => thold_DI27_WCLK_noedge_posedge,
          HoldHigh                => thold_DI27_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X28A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or Tviol_DI3_WCLK_posedge or 
                 Tviol_DI4_WCLK_posedge or Tviol_DI5_WCLK_posedge or 
                 Tviol_DI6_WCLK_posedge or Tviol_DI7_WCLK_posedge or 
                 Tviol_DI8_WCLK_posedge or Tviol_DI9_WCLK_posedge or 
                 Tviol_DI10_WCLK_posedge or Tviol_DI11_WCLK_posedge or 
                 Tviol_DI12_WCLK_posedge or Tviol_DI13_WCLK_posedge or 
                 Tviol_DI14_WCLK_posedge or Tviol_DI15_WCLK_posedge or 
                 Tviol_DI16_WCLK_posedge or Tviol_DI17_WCLK_posedge or 
                 Tviol_DI18_WCLK_posedge or Tviol_DI19_WCLK_posedge or
                 Tviol_DI20_WCLK_posedge or Tviol_DI21_WCLK_posedge or 
                 Tviol_DI22_WCLK_posedge or Tviol_DI23_WCLK_posedge or 
                 Tviol_DI24_WCLK_posedge or Tviol_DI25_WCLK_posedge or 
                 Tviol_DI26_WCLK_posedge or Tviol_DI27_WCLK_posedge or  
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_DO8  : process
      variable DO8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO8_zd := DO(8);

    VitalPathDelay01 (
      OutSignal => DO8,
      GlitchData => O_GlitchData,
      OutSignalName => "DO8",
      OutTemp => DO8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(8);
      end process;

    VitalBehavior_DO9  : process
      variable DO9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO9_zd := DO(9);

    VitalPathDelay01 (
      OutSignal => DO9,
      GlitchData => O_GlitchData,
      OutSignalName => "DO9",
      OutTemp => DO9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(9);
      end process;

    VitalBehavior_DO10  : process
      variable DO10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO10_zd := DO(10);

    VitalPathDelay01 (
      OutSignal => DO10,
      GlitchData => O_GlitchData,
      OutSignalName => "DO10",
      OutTemp => DO10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(10);
      end process;

    VitalBehavior_DO11  : process
      variable DO11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO11_zd := DO(11);

    VitalPathDelay01 (
      OutSignal => DO11,
      GlitchData => O_GlitchData,
      OutSignalName => "DO11",
      OutTemp => DO11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(11);
      end process;

    VitalBehavior_DO12  : process
      variable DO12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO12_zd := DO(12);

    VitalPathDelay01 (
      OutSignal => DO12,
      GlitchData => O_GlitchData,
      OutSignalName => "DO12",
      OutTemp => DO12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(12);
      end process;

    VitalBehavior_DO13  : process
      variable DO13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO13_zd := DO(13);

    VitalPathDelay01 (
      OutSignal => DO13,
      GlitchData => O_GlitchData,
      OutSignalName => "DO13",
      OutTemp => DO13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(13);
      end process;

    VitalBehavior_DO14  : process
      variable DO14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO14_zd := DO(14);

    VitalPathDelay01 (
      OutSignal => DO14,
      GlitchData => O_GlitchData,
      OutSignalName => "DO14",
      OutTemp => DO14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(14);
      end process;

    VitalBehavior_DO15  : process
      variable DO15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO15_zd := DO(15);

    VitalPathDelay01 (
      OutSignal => DO15,
      GlitchData => O_GlitchData,
      OutSignalName => "DO15",
      OutTemp => DO15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(15);
      end process;

    VitalBehavior_DO16  : process
      variable DO16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO16_zd := DO(16);

    VitalPathDelay01 (
      OutSignal => DO16,
      GlitchData => O_GlitchData,
      OutSignalName => "DO16",
      OutTemp => DO16_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO16, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(16);
      end process;

    VitalBehavior_DO17  : process
      variable DO17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO17_zd := DO(17);

    VitalPathDelay01 (
      OutSignal => DO17,
      GlitchData => O_GlitchData,
      OutSignalName => "DO17",
      OutTemp => DO17_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO17, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(17);
      end process;

    VitalBehavior_DO18  : process
      variable DO18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO18_zd := DO(18);

    VitalPathDelay01 (
      OutSignal => DO18,
      GlitchData => O_GlitchData,
      OutSignalName => "DO18",
      OutTemp => DO18_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO18, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(18);
      end process;

    VitalBehavior_DO19  : process
      variable DO19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO19_zd := DO(19);

    VitalPathDelay01 (
      OutSignal => DO19,
      GlitchData => O_GlitchData,
      OutSignalName => "DO19",
      OutTemp => DO19_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO19, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(19);
      end process;

    VitalBehavior_DO20  : process
      variable DO20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO20_zd := DO(20);

    VitalPathDelay01 (
      OutSignal => DO20,
      GlitchData => O_GlitchData,
      OutSignalName => "DO20",
      OutTemp => DO20_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO20, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(20);
      end process;

    VitalBehavior_DO21  : process
      variable DO21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO21_zd := DO(21);

    VitalPathDelay01 (
      OutSignal => DO21,
      GlitchData => O_GlitchData,
      OutSignalName => "DO21",
      OutTemp => DO21_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO21, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(21);
      end process;

    VitalBehavior_DO22  : process
      variable DO22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO22_zd := DO(22);

    VitalPathDelay01 (
      OutSignal => DO22,
      GlitchData => O_GlitchData,
      OutSignalName => "DO22",
      OutTemp => DO22_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO22, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(22);
      end process;

    VitalBehavior_DO23  : process
      variable DO23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO23_zd := DO(23);

    VitalPathDelay01 (
      OutSignal => DO23,
      GlitchData => O_GlitchData,
      OutSignalName => "DO23",
      OutTemp => DO23_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO23, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(23);
      end process;

    VitalBehavior_DO24  : process
      variable DO24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO24_zd := DO(24);

    VitalPathDelay01 (
      OutSignal => DO24,
      GlitchData => O_GlitchData,
      OutSignalName => "DO24",
      OutTemp => DO24_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO24, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(24);
      end process;

    VitalBehavior_DO25  : process
      variable DO25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO25_zd := DO(25);

    VitalPathDelay01 (
      OutSignal => DO25,
      GlitchData => O_GlitchData,
      OutSignalName => "DO25",
      OutTemp => DO25_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO25, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(25);
      end process;

    VitalBehavior_DO26  : process
      variable DO26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO26_zd := DO(26);

    VitalPathDelay01 (
      OutSignal => DO26,
      GlitchData => O_GlitchData,
      OutSignalName => "DO26",
      OutTemp => DO26_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO26, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(26);
      end process;

    VitalBehavior_DO27  : process
      variable DO27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO27_zd := DO(27);

    VitalPathDelay01 (
      OutSignal => DO27,
      GlitchData => O_GlitchData,
      OutSignalName => "DO27",
      OutTemp => DO27_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO27, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(27);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_16K 
  generic map (
        WADDR_WIDTH    => 9,
        WDATA_WIDTH    => 28,
        RADDR_WIDTH    => 9,
        RDATA_WIDTH    => 28,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open
         )
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO512X28A_VITAL of RAMBFIFO512X28A is
   for VITAL
   end for;
end CFG_RAMBFIFO512X28A_VITAL;



----- CELL RAMBFIFO512X32A -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity RAMBFIFO512X32A is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
--      RAM_INIT_FILE   : string  := "dummy";
      FIFO_FULL_FLAG     : integer  := 512;
      FIFO_AMFULL_FLAG   : integer :=  1;
      FIFO_AMEMPTY_FLAG  : integer := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO16                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO17                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO18                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO19                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO20                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO21                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO22                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO23                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO24                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO25                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO8                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO9                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO15                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO16                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO17                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO18                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO19                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO20                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO21                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO22                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO23                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO24                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO25                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO26                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO27                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO28                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO29                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO30                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO31                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI4_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI5_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI6_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI7_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI8_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI8_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI9_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI9_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI10_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI10_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI11_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI11_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI12_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI12_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI13_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI13_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI14_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI14_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI15_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI15_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI16_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI16_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI17_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI17_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI18_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI18_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI19_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI19_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI20_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI20_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI21_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI21_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI22_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI22_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI23_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI23_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI24_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI24_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI25_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI25_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI26_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI26_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI27_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI27_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI28_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI28_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI29_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI29_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI30_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI30_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI31_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI31_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI8                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI9                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI10                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI11                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI12                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI13                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI14                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI15                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI16                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI17                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI18                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI19                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI20                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI21                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI22                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI23                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI24                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI25                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI26                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI27                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI28                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI29                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI30                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI31                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             :	in    STD_ULOGIC;
      DI1                             :	in    STD_ULOGIC;
      DI2                             :	in    STD_ULOGIC;
      DI3                             :	in    STD_ULOGIC;
      DI4                             :	in    STD_ULOGIC;
      DI5                             :	in    STD_ULOGIC;
      DI6                             :	in    STD_ULOGIC;
      DI7                             :	in    STD_ULOGIC;
      DI8                             :	in    STD_ULOGIC;
      DI9                             :	in    STD_ULOGIC;
      DI10                            :	in    STD_ULOGIC;
      DI11                            :	in    STD_ULOGIC;
      DI12                            :	in    STD_ULOGIC;
      DI13                            :	in    STD_ULOGIC;
      DI14                            :	in    STD_ULOGIC;
      DI15                            :	in    STD_ULOGIC;
      DI16                            :	in    STD_ULOGIC;
      DI17                            :	in    STD_ULOGIC;
      DI18                            :	in    STD_ULOGIC;
      DI19                            :	in    STD_ULOGIC;
      DI20                            :	in    STD_ULOGIC;
      DI21                            :	in    STD_ULOGIC;
      DI22                            :	in    STD_ULOGIC;
      DI23                            :	in    STD_ULOGIC;
      DI24                            :	in    STD_ULOGIC;
      DI25                            :	in    STD_ULOGIC;
      DI26                            :	in    STD_ULOGIC;
      DI27                            :	in    STD_ULOGIC;
      DI28                            :	in    STD_ULOGIC;
      DI29                            :	in    STD_ULOGIC;
      DI30                            :	in    STD_ULOGIC;
      DI31                            :	in    STD_ULOGIC;
      DO0                             :	out   STD_ULOGIC;
      DO1                             :	out   STD_ULOGIC;
      DO2                             :	out   STD_ULOGIC;
      DO3                             :	out   STD_ULOGIC;
      DO4                             :	out   STD_ULOGIC;
      DO5                             :	out   STD_ULOGIC;
      DO6                             :	out   STD_ULOGIC;
      DO7                             :	out   STD_ULOGIC;
      DO8                             :	out   STD_ULOGIC;
      DO9                             :	out   STD_ULOGIC;
      DO10                            :	out   STD_ULOGIC;
      DO11                            :	out   STD_ULOGIC;
      DO12                            :	out   STD_ULOGIC;
      DO13                            :	out   STD_ULOGIC;
      DO14                            :	out   STD_ULOGIC;
      DO15                            :	out   STD_ULOGIC;
      DO16                            :	out   STD_ULOGIC;
      DO17                            :	out   STD_ULOGIC;
      DO18                            :	out   STD_ULOGIC;
      DO19                            :	out   STD_ULOGIC;
      DO20                            :	out   STD_ULOGIC;
      DO21                            :	out   STD_ULOGIC;
      DO22                            :	out   STD_ULOGIC;
      DO23                            :	out   STD_ULOGIC;
      DO24                            :	out   STD_ULOGIC;
      DO25                            :	out   STD_ULOGIC;
      DO26                            :	out   STD_ULOGIC;
      DO27                            :	out   STD_ULOGIC;
      DO28                            :	out   STD_ULOGIC;
      DO29                            :	out   STD_ULOGIC;
      DO30                            :	out   STD_ULOGIC;
      DO31                            :	out   STD_ULOGIC;
      FULL                            :	out   STD_ULOGIC;
      EMPTY                           :	out   STD_ULOGIC;
      AMFULL                          :	out   STD_ULOGIC;
      AMEMPTY                         :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO512X32A : entity is FALSE;
end RAMBFIFO512X32A;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMBFIFO512X32A is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';

      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI4_ipd       : std_ulogic := 'X';
      signal DI5_ipd       : std_ulogic := 'X';
      signal DI6_ipd       : std_ulogic := 'X';
      signal DI7_ipd       : std_ulogic := 'X';
      signal DI8_ipd       : std_ulogic := 'X';
      signal DI9_ipd       : std_ulogic := 'X';
      signal DI10_ipd       : std_ulogic := 'X';
      signal DI11_ipd       : std_ulogic := 'X';
      signal DI12_ipd       : std_ulogic := 'X';
      signal DI13_ipd       : std_ulogic := 'X';
      signal DI14_ipd       : std_ulogic := 'X';
      signal DI15_ipd       : std_ulogic := 'X';
      signal DI16_ipd       : std_ulogic := 'X';
      signal DI17_ipd       : std_ulogic := 'X';
      signal DI18_ipd       : std_ulogic := 'X';
      signal DI19_ipd       : std_ulogic := 'X';
      signal DI20_ipd       : std_ulogic := 'X';
      signal DI21_ipd       : std_ulogic := 'X';
      signal DI22_ipd       : std_ulogic := 'X';
      signal DI23_ipd       : std_ulogic := 'X';
      signal DI24_ipd       : std_ulogic := 'X';
      signal DI25_ipd       : std_ulogic := 'X';
      signal DI26_ipd       : std_ulogic := 'X';
      signal DI27_ipd       : std_ulogic := 'X';
      signal DI28_ipd       : std_ulogic := 'X';
      signal DI29_ipd       : std_ulogic := 'X';
      signal DI30_ipd       : std_ulogic := 'X';
      signal DI31_ipd       : std_ulogic := 'X';

      signal DI : std_logic_vector(31 downto 0);
      signal DO : std_logic_vector(31 downto 0);
      signal FULL_sig  : std_logic;
      signal EMPTY_sig : std_logic;
      signal AMFULL_sig  : std_logic;
      signal AMEMPTY_sig : std_logic;

begin 

      DI <= DI31_ipd & DI30_ipd & DI29_ipd & DI28_ipd & 
            DI27_ipd & DI26_ipd & DI25_ipd & DI24_ipd & 
            DI23_ipd & DI22_ipd & DI21_ipd & DI20_ipd & 
            DI19_ipd & DI18_ipd & DI17_ipd & DI16_ipd & 
            DI15_ipd & DI14_ipd & DI13_ipd & DI12_ipd & 
            DI11_ipd & DI10_ipd & DI9_ipd & DI8_ipd & 
            DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & 
            DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ; 

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);
        VitalWireDelay (DI8_ipd, DI8, tipd_DI8);
        VitalWireDelay (DI9_ipd, DI9, tipd_DI9);
        VitalWireDelay (DI10_ipd, DI10, tipd_DI10);
        VitalWireDelay (DI11_ipd, DI11, tipd_DI11);
        VitalWireDelay (DI12_ipd, DI12, tipd_DI12);
        VitalWireDelay (DI13_ipd, DI13, tipd_DI13);
        VitalWireDelay (DI14_ipd, DI14, tipd_DI14);
        VitalWireDelay (DI15_ipd, DI15, tipd_DI15);
        VitalWireDelay (DI16_ipd, DI16, tipd_DI16);
        VitalWireDelay (DI17_ipd, DI17, tipd_DI17);
        VitalWireDelay (DI18_ipd, DI18, tipd_DI18);
        VitalWireDelay (DI19_ipd, DI19, tipd_DI19);
        VitalWireDelay (DI20_ipd, DI20, tipd_DI20);
        VitalWireDelay (DI21_ipd, DI21, tipd_DI21);
        VitalWireDelay (DI22_ipd, DI22, tipd_DI22);
        VitalWireDelay (DI23_ipd, DI23, tipd_DI23);
        VitalWireDelay (DI24_ipd, DI24, tipd_DI24);
        VitalWireDelay (DI25_ipd, DI25, tipd_DI25);
        VitalWireDelay (DI26_ipd, DI26, tipd_DI26);
        VitalWireDelay (DI27_ipd, DI27, tipd_DI27);
        VitalWireDelay (DI28_ipd, DI28, tipd_DI28);
        VitalWireDelay (DI29_ipd, DI29, tipd_DI29);
        VitalWireDelay (DI30_ipd, DI30, tipd_DI30);
        VitalWireDelay (DI31_ipd, DI31, tipd_DI31);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI4_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI5_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI6_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI7_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI8_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI9_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI10_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI11_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI12_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI13_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI14_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI15_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI16_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI17_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI18_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI19_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI20_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI21_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI22_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI23_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI24_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI25_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI26_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI27_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI28_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI29_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI30_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI31_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI8_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI9_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI10_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI11_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI12_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI13_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI14_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI15_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI16_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI17_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI18_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI19_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI20_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI21_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI22_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI23_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI24_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI25_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI26_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI27_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI28_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI29_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI30_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI31_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable DO8_zd          : std_ulogic := 'X';
        variable DO9_zd          : std_ulogic := 'X';
        variable DO10_zd          : std_ulogic := 'X';
        variable DO11_zd          : std_ulogic := 'X';
        variable DO12_zd          : std_ulogic := 'X';
        variable DO13_zd          : std_ulogic := 'X';
        variable DO14_zd          : std_ulogic := 'X';
        variable DO15_zd          : std_ulogic := 'X';
        variable DO16_zd          : std_ulogic := 'X';
        variable DO17_zd          : std_ulogic := 'X';
        variable DO18_zd          : std_ulogic := 'X';
        variable DO19_zd          : std_ulogic := 'X';
        variable DO20_zd          : std_ulogic := 'X';
        variable DO21_zd          : std_ulogic := 'X';
        variable DO22_zd          : std_ulogic := 'X';
        variable DO23_zd          : std_ulogic := 'X';
        variable DO24_zd          : std_ulogic := 'X';
        variable DO25_zd          : std_ulogic := 'X';
        variable DO26_zd          : std_ulogic := 'X';
        variable DO27_zd          : std_ulogic := 'X';
        variable DO28_zd          : std_ulogic := 'X';
        variable DO29_zd          : std_ulogic := 'X';
        variable DO30_zd          : std_ulogic := 'X';
        variable DO31_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_WCLK_posedge,
          TimingData              => Tmkr_DI4_WCLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI4_WCLK_noedge_posedge,
          HoldLow                 => thold_DI4_WCLK_noedge_posedge,
          HoldHigh                => thold_DI4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_WCLK_posedge,
          TimingData              => Tmkr_DI5_WCLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI5_WCLK_noedge_posedge,
          HoldLow                 => thold_DI5_WCLK_noedge_posedge,
          HoldHigh                => thold_DI5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_WCLK_posedge,
          TimingData              => Tmkr_DI6_WCLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI6_WCLK_noedge_posedge,
          HoldLow                 => thold_DI6_WCLK_noedge_posedge,
          HoldHigh                => thold_DI6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_WCLK_posedge,
          TimingData              => Tmkr_DI7_WCLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI7_WCLK_noedge_posedge,
          HoldLow                 => thold_DI7_WCLK_noedge_posedge,
          HoldHigh                => thold_DI7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI8_WCLK_posedge,
          TimingData              => Tmkr_DI8_WCLK_posedge,
          TestSignal              => DI8_ipd,
          TestSignalName          => "DI8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI8_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI8_WCLK_noedge_posedge,
          HoldLow                 => thold_DI8_WCLK_noedge_posedge,
          HoldHigh                => thold_DI8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI9_WCLK_posedge,
          TimingData              => Tmkr_DI9_WCLK_posedge,
          TestSignal              => DI9_ipd,
          TestSignalName          => "DI9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI9_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI9_WCLK_noedge_posedge,
          HoldLow                 => thold_DI9_WCLK_noedge_posedge,
          HoldHigh                => thold_DI9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI10_WCLK_posedge,
          TimingData              => Tmkr_DI10_WCLK_posedge,
          TestSignal              => DI10_ipd,
          TestSignalName          => "DI10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI10_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI10_WCLK_noedge_posedge,
          HoldLow                 => thold_DI10_WCLK_noedge_posedge,
          HoldHigh                => thold_DI10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI11_WCLK_posedge,
          TimingData              => Tmkr_DI11_WCLK_posedge,
          TestSignal              => DI11_ipd,
          TestSignalName          => "DI11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI11_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI11_WCLK_noedge_posedge,
          HoldLow                 => thold_DI11_WCLK_noedge_posedge,
          HoldHigh                => thold_DI11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI12_WCLK_posedge,
          TimingData              => Tmkr_DI12_WCLK_posedge,
          TestSignal              => DI12_ipd,
          TestSignalName          => "DI12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI12_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI12_WCLK_noedge_posedge,
          HoldLow                 => thold_DI12_WCLK_noedge_posedge,
          HoldHigh                => thold_DI12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI13_WCLK_posedge,
          TimingData              => Tmkr_DI13_WCLK_posedge,
          TestSignal              => DI13_ipd,
          TestSignalName          => "DI13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI13_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI13_WCLK_noedge_posedge,
          HoldLow                 => thold_DI13_WCLK_noedge_posedge,
          HoldHigh                => thold_DI13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI14_WCLK_posedge,
          TimingData              => Tmkr_DI14_WCLK_posedge,
          TestSignal              => DI14_ipd,
          TestSignalName          => "DI14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI14_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI14_WCLK_noedge_posedge,
          HoldLow                 => thold_DI14_WCLK_noedge_posedge,
          HoldHigh                => thold_DI14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI15_WCLK_posedge,
          TimingData              => Tmkr_DI15_WCLK_posedge,
          TestSignal              => DI15_ipd,
          TestSignalName          => "DI15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI15_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI15_WCLK_noedge_posedge,
          HoldLow                 => thold_DI15_WCLK_noedge_posedge,
          HoldHigh                => thold_DI15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI16_WCLK_posedge,
          TimingData              => Tmkr_DI16_WCLK_posedge,
          TestSignal              => DI16_ipd,
          TestSignalName          => "DI16",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI16_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI16_WCLK_noedge_posedge,
          HoldLow                 => thold_DI16_WCLK_noedge_posedge,
          HoldHigh                => thold_DI16_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI17_WCLK_posedge,
          TimingData              => Tmkr_DI17_WCLK_posedge,
          TestSignal              => DI17_ipd,
          TestSignalName          => "DI17",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI17_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI17_WCLK_noedge_posedge,
          HoldLow                 => thold_DI17_WCLK_noedge_posedge,
          HoldHigh                => thold_DI17_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI18_WCLK_posedge,
          TimingData              => Tmkr_DI18_WCLK_posedge,
          TestSignal              => DI18_ipd,
          TestSignalName          => "DI18",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI18_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI18_WCLK_noedge_posedge,
          HoldLow                 => thold_DI18_WCLK_noedge_posedge,
          HoldHigh                => thold_DI18_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI19_WCLK_posedge,
          TimingData              => Tmkr_DI19_WCLK_posedge,
          TestSignal              => DI19_ipd,
          TestSignalName          => "DI19",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI19_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI19_WCLK_noedge_posedge,
          HoldLow                 => thold_DI19_WCLK_noedge_posedge,
          HoldHigh                => thold_DI19_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI20_WCLK_posedge,
          TimingData              => Tmkr_DI20_WCLK_posedge,
          TestSignal              => DI20_ipd,
          TestSignalName          => "DI20",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI20_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI20_WCLK_noedge_posedge,
          HoldLow                 => thold_DI20_WCLK_noedge_posedge,
          HoldHigh                => thold_DI20_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI21_WCLK_posedge,
          TimingData              => Tmkr_DI21_WCLK_posedge,
          TestSignal              => DI21_ipd,
          TestSignalName          => "DI21",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI21_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI21_WCLK_noedge_posedge,
          HoldLow                 => thold_DI21_WCLK_noedge_posedge,
          HoldHigh                => thold_DI21_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI22_WCLK_posedge,
          TimingData              => Tmkr_DI22_WCLK_posedge,
          TestSignal              => DI22_ipd,
          TestSignalName          => "DI22",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI22_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI22_WCLK_noedge_posedge,
          HoldLow                 => thold_DI22_WCLK_noedge_posedge,
          HoldHigh                => thold_DI22_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI23_WCLK_posedge,
          TimingData              => Tmkr_DI23_WCLK_posedge,
          TestSignal              => DI23_ipd,
          TestSignalName          => "DI23",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI23_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI23_WCLK_noedge_posedge,
          HoldLow                 => thold_DI23_WCLK_noedge_posedge,
          HoldHigh                => thold_DI23_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI24_WCLK_posedge,
          TimingData              => Tmkr_DI24_WCLK_posedge,
          TestSignal              => DI24_ipd,
          TestSignalName          => "DI24",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI24_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI24_WCLK_noedge_posedge,
          HoldLow                 => thold_DI24_WCLK_noedge_posedge,
          HoldHigh                => thold_DI24_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI25_WCLK_posedge,
          TimingData              => Tmkr_DI25_WCLK_posedge,
          TestSignal              => DI25_ipd,
          TestSignalName          => "DI25",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI25_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI25_WCLK_noedge_posedge,
          HoldLow                 => thold_DI25_WCLK_noedge_posedge,
          HoldHigh                => thold_DI25_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI26_WCLK_posedge,
          TimingData              => Tmkr_DI26_WCLK_posedge,
          TestSignal              => DI26_ipd,
          TestSignalName          => "DI26",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI26_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI26_WCLK_noedge_posedge,
          HoldLow                 => thold_DI26_WCLK_noedge_posedge,
          HoldHigh                => thold_DI26_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI27_WCLK_posedge,
          TimingData              => Tmkr_DI27_WCLK_posedge,
          TestSignal              => DI27_ipd,
          TestSignalName          => "DI27",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI27_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI27_WCLK_noedge_posedge,
          HoldLow                 => thold_DI27_WCLK_noedge_posedge,
          HoldHigh                => thold_DI27_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI28_WCLK_posedge,
          TimingData              => Tmkr_DI28_WCLK_posedge,
          TestSignal              => DI28_ipd,
          TestSignalName          => "DI28",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI28_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI28_WCLK_noedge_posedge,
          HoldLow                 => thold_DI28_WCLK_noedge_posedge,
          HoldHigh                => thold_DI28_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI29_WCLK_posedge,
          TimingData              => Tmkr_DI29_WCLK_posedge,
          TestSignal              => DI29_ipd,
          TestSignalName          => "DI29",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI29_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI29_WCLK_noedge_posedge,
          HoldLow                 => thold_DI29_WCLK_noedge_posedge,
          HoldHigh                => thold_DI29_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI30_WCLK_posedge,
          TimingData              => Tmkr_DI30_WCLK_posedge,
          TestSignal              => DI30_ipd,
          TestSignalName          => "DI30",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI30_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI30_WCLK_noedge_posedge,
          HoldLow                 => thold_DI30_WCLK_noedge_posedge,
          HoldHigh                => thold_DI30_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI31_WCLK_posedge,
          TimingData              => Tmkr_DI31_WCLK_posedge,
          TestSignal              => DI31_ipd,
          TestSignalName          => "DI31",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI31_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI31_WCLK_noedge_posedge,
          HoldLow                 => thold_DI31_WCLK_noedge_posedge,
          HoldHigh                => thold_DI31_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or Tviol_DI3_WCLK_posedge or 
                 Tviol_DI4_WCLK_posedge or Tviol_DI5_WCLK_posedge or 
                 Tviol_DI6_WCLK_posedge or Tviol_DI7_WCLK_posedge or 
                 Tviol_DI8_WCLK_posedge or Tviol_DI9_WCLK_posedge or 
                 Tviol_DI10_WCLK_posedge or Tviol_DI11_WCLK_posedge or 
                 Tviol_DI12_WCLK_posedge or Tviol_DI13_WCLK_posedge or 
                 Tviol_DI14_WCLK_posedge or Tviol_DI15_WCLK_posedge or 
                 Tviol_DI16_WCLK_posedge or Tviol_DI17_WCLK_posedge or 
                 Tviol_DI18_WCLK_posedge or Tviol_DI19_WCLK_posedge or
                 Tviol_DI20_WCLK_posedge or Tviol_DI21_WCLK_posedge or 
                 Tviol_DI22_WCLK_posedge or Tviol_DI23_WCLK_posedge or 
                 Tviol_DI24_WCLK_posedge or Tviol_DI25_WCLK_posedge or 
                 Tviol_DI26_WCLK_posedge or Tviol_DI27_WCLK_posedge or 
                 Tviol_DI28_WCLK_posedge or Tviol_DI29_WCLK_posedge or 
                 Tviol_DI30_WCLK_posedge or Tviol_DI31_WCLK_posedge or  
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_DO8  : process
      variable DO8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO8_zd := DO(8);

    VitalPathDelay01 (
      OutSignal => DO8,
      GlitchData => O_GlitchData,
      OutSignalName => "DO8",
      OutTemp => DO8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(8);
      end process;

    VitalBehavior_DO9  : process
      variable DO9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO9_zd := DO(9);

    VitalPathDelay01 (
      OutSignal => DO9,
      GlitchData => O_GlitchData,
      OutSignalName => "DO9",
      OutTemp => DO9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(9);
      end process;

    VitalBehavior_DO10  : process
      variable DO10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO10_zd := DO(10);

    VitalPathDelay01 (
      OutSignal => DO10,
      GlitchData => O_GlitchData,
      OutSignalName => "DO10",
      OutTemp => DO10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(10);
      end process;

    VitalBehavior_DO11  : process
      variable DO11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO11_zd := DO(11);

    VitalPathDelay01 (
      OutSignal => DO11,
      GlitchData => O_GlitchData,
      OutSignalName => "DO11",
      OutTemp => DO11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(11);
      end process;

    VitalBehavior_DO12  : process
      variable DO12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO12_zd := DO(12);

    VitalPathDelay01 (
      OutSignal => DO12,
      GlitchData => O_GlitchData,
      OutSignalName => "DO12",
      OutTemp => DO12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(12);
      end process;

    VitalBehavior_DO13  : process
      variable DO13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO13_zd := DO(13);

    VitalPathDelay01 (
      OutSignal => DO13,
      GlitchData => O_GlitchData,
      OutSignalName => "DO13",
      OutTemp => DO13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(13);
      end process;

    VitalBehavior_DO14  : process
      variable DO14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO14_zd := DO(14);

    VitalPathDelay01 (
      OutSignal => DO14,
      GlitchData => O_GlitchData,
      OutSignalName => "DO14",
      OutTemp => DO14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(14);
      end process;

    VitalBehavior_DO15  : process
      variable DO15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO15_zd := DO(15);

    VitalPathDelay01 (
      OutSignal => DO15,
      GlitchData => O_GlitchData,
      OutSignalName => "DO15",
      OutTemp => DO15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(15);
      end process;

    VitalBehavior_DO16  : process
      variable DO16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO16_zd := DO(16);

    VitalPathDelay01 (
      OutSignal => DO16,
      GlitchData => O_GlitchData,
      OutSignalName => "DO16",
      OutTemp => DO16_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO16, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(16);
      end process;

    VitalBehavior_DO17  : process
      variable DO17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO17_zd := DO(17);

    VitalPathDelay01 (
      OutSignal => DO17,
      GlitchData => O_GlitchData,
      OutSignalName => "DO17",
      OutTemp => DO17_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO17, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(17);
      end process;

    VitalBehavior_DO18  : process
      variable DO18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO18_zd := DO(18);

    VitalPathDelay01 (
      OutSignal => DO18,
      GlitchData => O_GlitchData,
      OutSignalName => "DO18",
      OutTemp => DO18_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO18, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(18);
      end process;

    VitalBehavior_DO19  : process
      variable DO19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO19_zd := DO(19);

    VitalPathDelay01 (
      OutSignal => DO19,
      GlitchData => O_GlitchData,
      OutSignalName => "DO19",
      OutTemp => DO19_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO19, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(19);
      end process;

    VitalBehavior_DO20  : process
      variable DO20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO20_zd := DO(20);

    VitalPathDelay01 (
      OutSignal => DO20,
      GlitchData => O_GlitchData,
      OutSignalName => "DO20",
      OutTemp => DO20_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO20, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(20);
      end process;

    VitalBehavior_DO21  : process
      variable DO21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO21_zd := DO(21);

    VitalPathDelay01 (
      OutSignal => DO21,
      GlitchData => O_GlitchData,
      OutSignalName => "DO21",
      OutTemp => DO21_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO21, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(21);
      end process;

    VitalBehavior_DO22  : process
      variable DO22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO22_zd := DO(22);

    VitalPathDelay01 (
      OutSignal => DO22,
      GlitchData => O_GlitchData,
      OutSignalName => "DO22",
      OutTemp => DO22_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO22, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(22);
      end process;

    VitalBehavior_DO23  : process
      variable DO23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO23_zd := DO(23);

    VitalPathDelay01 (
      OutSignal => DO23,
      GlitchData => O_GlitchData,
      OutSignalName => "DO23",
      OutTemp => DO23_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO23, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(23);
      end process;

    VitalBehavior_DO24  : process
      variable DO24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO24_zd := DO(24);

    VitalPathDelay01 (
      OutSignal => DO24,
      GlitchData => O_GlitchData,
      OutSignalName => "DO24",
      OutTemp => DO24_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO24, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(24);
      end process;

    VitalBehavior_DO25  : process
      variable DO25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO25_zd := DO(25);

    VitalPathDelay01 (
      OutSignal => DO25,
      GlitchData => O_GlitchData,
      OutSignalName => "DO25",
      OutTemp => DO25_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO25, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(25);
      end process;

    VitalBehavior_DO26  : process
      variable DO26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO26_zd := DO(26);

    VitalPathDelay01 (
      OutSignal => DO26,
      GlitchData => O_GlitchData,
      OutSignalName => "DO26",
      OutTemp => DO26_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO26, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(26);
      end process;

    VitalBehavior_DO27  : process
      variable DO27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO27_zd := DO(27);

    VitalPathDelay01 (
      OutSignal => DO27,
      GlitchData => O_GlitchData,
      OutSignalName => "DO27",
      OutTemp => DO27_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO27, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(27);
      end process;

    VitalBehavior_DO28  : process
      variable DO28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO28_zd := DO(28);

    VitalPathDelay01 (
      OutSignal => DO28,
      GlitchData => O_GlitchData,
      OutSignalName => "DO28",
      OutTemp => DO28_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO28, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(28);
      end process;

    VitalBehavior_DO29  : process
      variable DO29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO29_zd := DO(29);

    VitalPathDelay01 (
      OutSignal => DO29,
      GlitchData => O_GlitchData,
      OutSignalName => "DO29",
      OutTemp => DO29_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO29, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(29);
      end process;

    VitalBehavior_DO30  : process
      variable DO30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO30_zd := DO(30);

    VitalPathDelay01 (
      OutSignal => DO30,
      GlitchData => O_GlitchData,
      OutSignalName => "DO30",
      OutTemp => DO30_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO30, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(30);
      end process;

    VitalBehavior_DO31  : process
      variable DO31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO31_zd := DO(31);

    VitalPathDelay01 (
      OutSignal => DO31,
      GlitchData => O_GlitchData,
      OutSignalName => "DO31",
      OutTemp => DO31_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO31, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(31);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_16K 
  generic map (
        WADDR_WIDTH    => 9,
        WDATA_WIDTH    => 32,
        RADDR_WIDTH    => 9,
        RDATA_WIDTH    => 32,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open
         )
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO512X32A_VITAL of RAMBFIFO512X32A is
   for VITAL
   end for;
end CFG_RAMBFIFO512X32A_VITAL;


----- CELL RAMBFIFO16KA_WX1_RX32_FLAG -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity RAMBFIFO16KA_WX1_RX32_FLAG is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
--      RAM_INIT_FILE   : string  := "dummy";
      FIFO_FULL_FLAG     : integer  := 512;
      FIFO_AMFULL_FLAG   : integer :=  1;
      FIFO_AMEMPTY_FLAG  : integer :=  1;

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      FULL                            :	out   STD_ULOGIC;
      EMPTY                           :	out   STD_ULOGIC;
      AMFULL                          :	out   STD_ULOGIC;
      AMEMPTY                         :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX1_RX32_FLAG : entity is FALSE;
end RAMBFIFO16KA_WX1_RX32_FLAG;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMBFIFO16KA_WX1_RX32_FLAG is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';

      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';
      signal FULL_sig  : std_logic;
      signal EMPTY_sig : std_logic;
      signal AMFULL_sig  : std_logic;
      signal AMEMPTY_sig : std_logic;
      signal DI : std_logic_vector(31 downto 0);
      signal DO : std_logic_vector(31 downto 0);

begin 

      DI <= "00000000000000000000000000000000";
      FULLIN_ipd <= '1';
      EMPTYIN_ipd <= '1';

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);


      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or Tviol_RE_RCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, RST_ipd, RPRST_ipd;

      end process VITALBehavior;


    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;



  FIFO_INST: SC_FIFO_16K 
  generic map (
        WADDR_WIDTH    => 9,
        WDATA_WIDTH    => 32,
        RADDR_WIDTH    => 9,
        RDATA_WIDTH    => 32,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open
         )
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX1_RX32_FLAG_VITAL of RAMBFIFO16KA_WX1_RX32_FLAG is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX1_RX32_FLAG_VITAL;
----- CELL RAMBFIFO16KA_WX2_RX32_FLAG -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity RAMBFIFO16KA_WX2_RX32_FLAG is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
--      RAM_INIT_FILE   : string  := "dummy";
      FIFO_FULL_FLAG     : integer  := 512;
      FIFO_AMFULL_FLAG   : integer :=  1;
      FIFO_AMEMPTY_FLAG  : integer :=  1;

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      FULL                            :	out   STD_ULOGIC;
      EMPTY                           :	out   STD_ULOGIC;
      AMFULL                          :	out   STD_ULOGIC;
      AMEMPTY                         :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX2_RX32_FLAG : entity is FALSE;
end RAMBFIFO16KA_WX2_RX32_FLAG;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMBFIFO16KA_WX2_RX32_FLAG is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';

      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';
      signal FULL_sig  : std_logic;
      signal EMPTY_sig : std_logic;
      signal AMFULL_sig  : std_logic;
      signal AMEMPTY_sig : std_logic;
      signal DI : std_logic_vector(31 downto 0);
      signal DO : std_logic_vector(31 downto 0);

begin 

      DI <= "00000000000000000000000000000000";
      FULLIN_ipd <= '1';
      EMPTYIN_ipd <= '1';

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);


      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or Tviol_RE_RCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, RST_ipd, RPRST_ipd;

      end process VITALBehavior;


    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;



  FIFO_INST: SC_FIFO_16K 
  generic map (
        WADDR_WIDTH    => 9,
        WDATA_WIDTH    => 32,
        RADDR_WIDTH    => 9,
        RDATA_WIDTH    => 32,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open
         )
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX2_RX32_FLAG_VITAL of RAMBFIFO16KA_WX2_RX32_FLAG is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX2_RX32_FLAG_VITAL;
----- CELL RAMBFIFO16KA_WX4_RX32_FLAG -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity RAMBFIFO16KA_WX4_RX32_FLAG is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
--      RAM_INIT_FILE   : string  := "dummy";
      FIFO_FULL_FLAG     : integer  := 512;
      FIFO_AMFULL_FLAG   : integer :=  1;
      FIFO_AMEMPTY_FLAG  : integer :=  1;

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      FULL                            :	out   STD_ULOGIC;
      EMPTY                           :	out   STD_ULOGIC;
      AMFULL                          :	out   STD_ULOGIC;
      AMEMPTY                         :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX4_RX32_FLAG : entity is FALSE;
end RAMBFIFO16KA_WX4_RX32_FLAG;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMBFIFO16KA_WX4_RX32_FLAG is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';

      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';
      signal FULL_sig  : std_logic;
      signal EMPTY_sig : std_logic;
      signal AMFULL_sig  : std_logic;
      signal AMEMPTY_sig : std_logic;
      signal DI : std_logic_vector(31 downto 0);
      signal DO : std_logic_vector(31 downto 0);

begin 

      DI <= "00000000000000000000000000000000";
      FULLIN_ipd <= '1';
      EMPTYIN_ipd <= '1';

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);


      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or Tviol_RE_RCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, RST_ipd, RPRST_ipd;

      end process VITALBehavior;


    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;



  FIFO_INST: SC_FIFO_16K 
  generic map (
        WADDR_WIDTH    => 9,
        WDATA_WIDTH    => 32,
        RADDR_WIDTH    => 9,
        RDATA_WIDTH    => 32,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open
         )
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX4_RX32_FLAG_VITAL of RAMBFIFO16KA_WX4_RX32_FLAG is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX4_RX32_FLAG_VITAL;
----- CELL RAMBFIFO16KA_WX8_RX32_FLAG -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity RAMBFIFO16KA_WX8_RX32_FLAG is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
--      RAM_INIT_FILE   : string  := "dummy";
      FIFO_FULL_FLAG     : integer  := 512;
      FIFO_AMFULL_FLAG   : integer :=  1;
      FIFO_AMEMPTY_FLAG  : integer :=  1;

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      FULL                            :	out   STD_ULOGIC;
      EMPTY                           :	out   STD_ULOGIC;
      AMFULL                          :	out   STD_ULOGIC;
      AMEMPTY                         :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX8_RX32_FLAG : entity is FALSE;
end RAMBFIFO16KA_WX8_RX32_FLAG;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMBFIFO16KA_WX8_RX32_FLAG is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';

      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';
      signal FULL_sig  : std_logic;
      signal EMPTY_sig : std_logic;
      signal AMFULL_sig  : std_logic;
      signal AMEMPTY_sig : std_logic;
      signal DI : std_logic_vector(31 downto 0);
      signal DO : std_logic_vector(31 downto 0);

begin 

      DI <= "00000000000000000000000000000000";
      FULLIN_ipd <= '1';
      EMPTYIN_ipd <= '1';

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);


      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or Tviol_RE_RCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, RST_ipd, RPRST_ipd;

      end process VITALBehavior;


    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;



  FIFO_INST: SC_FIFO_16K 
  generic map (
        WADDR_WIDTH    => 9,
        WDATA_WIDTH    => 32,
        RADDR_WIDTH    => 9,
        RDATA_WIDTH    => 32,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open
         )
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX8_RX32_FLAG_VITAL of RAMBFIFO16KA_WX8_RX32_FLAG is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX8_RX32_FLAG_VITAL;
----- CELL RAMBFIFO16KA_WX16_RX32_FLAG -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity RAMBFIFO16KA_WX16_RX32_FLAG is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
--      RAM_INIT_FILE   : string  := "dummy";
      FIFO_FULL_FLAG     : integer  := 512;
      FIFO_AMFULL_FLAG   : integer :=  1;
      FIFO_AMEMPTY_FLAG  : integer :=  1;

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      FULL                            :	out   STD_ULOGIC;
      EMPTY                           :	out   STD_ULOGIC;
      AMFULL                          :	out   STD_ULOGIC;
      AMEMPTY                         :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX16_RX32_FLAG : entity is FALSE;
end RAMBFIFO16KA_WX16_RX32_FLAG;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMBFIFO16KA_WX16_RX32_FLAG is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';

      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';
      signal FULL_sig  : std_logic;
      signal EMPTY_sig : std_logic;
      signal AMFULL_sig  : std_logic;
      signal AMEMPTY_sig : std_logic;
      signal DI : std_logic_vector(31 downto 0);
      signal DO : std_logic_vector(31 downto 0);

begin 

      DI <= "00000000000000000000000000000000";
      FULLIN_ipd <= '1';
      EMPTYIN_ipd <= '1';

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);


      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or Tviol_RE_RCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, RST_ipd, RPRST_ipd;

      end process VITALBehavior;


    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;



  FIFO_INST: SC_FIFO_16K 
  generic map (
        WADDR_WIDTH    => 9,
        WDATA_WIDTH    => 32,
        RADDR_WIDTH    => 9,
        RDATA_WIDTH    => 32,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open
         )
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX16_RX32_FLAG_VITAL of RAMBFIFO16KA_WX16_RX32_FLAG is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX16_RX32_FLAG_VITAL;

----- CELL RAMBFIFO512X32A_FLAG -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity RAMBFIFO512X32A_FLAG is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
--      RAM_INIT_FILE   : string  := "dummy";
      FIFO_FULL_FLAG     : integer  := 512;
      FIFO_AMFULL_FLAG   : integer :=  1;
      FIFO_AMEMPTY_FLAG  : integer :=  1;

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      FULL                            :	out   STD_ULOGIC;
      EMPTY                           :	out   STD_ULOGIC;
      AMFULL                          :	out   STD_ULOGIC;
      AMEMPTY                         :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO512X32A_FLAG : entity is FALSE;
end RAMBFIFO512X32A_FLAG;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMBFIFO512X32A_FLAG is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';

      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';
      signal FULL_sig  : std_logic;
      signal EMPTY_sig : std_logic;
      signal AMFULL_sig  : std_logic;
      signal AMEMPTY_sig : std_logic;
      signal DI : std_logic_vector(31 downto 0);
      signal DO : std_logic_vector(31 downto 0);

begin 

      DI <= "00000000000000000000000000000000";
      FULLIN_ipd <= '1';
      EMPTYIN_ipd <= '1';

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);


      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO512X32A_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO512X32A_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO512X32A_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO512X32A_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO512X32A_FLAG",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or Tviol_RE_RCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, RST_ipd, RPRST_ipd;

      end process VITALBehavior;


    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;



  FIFO_INST: SC_FIFO_16K 
  generic map (
        WADDR_WIDTH    => 9,
        WDATA_WIDTH    => 32,
        RADDR_WIDTH    => 9,
        RDATA_WIDTH    => 32,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open
         )
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO512X32A_FLAG_VITAL of RAMBFIFO512X32A_FLAG is
   for VITAL
   end for;
end CFG_RAMBFIFO512X32A_FLAG_VITAL;



----- CELL CAM128X48 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity CAM128X48 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_CLK_CO0                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CO1                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CO2                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CO3                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CO4                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CO5                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CO6                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_CLK_MATCH                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_MUL_MATCH                  :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_CO0                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CO1                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CO2                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CO3                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CO4                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CO5                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CO6                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_MATCH                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_MUL_MATCH                  :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WE_CLK_noedge_posedge       :	VitalDelayType   := 0.1 ns;
      thold_WE_CLK_noedge_posedge        :	VitalDelayType   := 0.0 ns;

      tsetup_CE_CLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_CE_CLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_EN_MASK_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_EN_MASK_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WR_MASK_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_MASK_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WR_DC_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_DC_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CS0_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_CS0_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CS1_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_CS1_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD0_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD1_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD1_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD2_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD2_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD3_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD3_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD4_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD4_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD5_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD5_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD6_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD6_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD0_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD1_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD1_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD2_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD2_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD3_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD3_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD4_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD4_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD5_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD5_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD6_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD6_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD7_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD7_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD8_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD8_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD9_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD9_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD10_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD10_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD11_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD11_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD12_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD12_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD13_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD13_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD14_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD14_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD15_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD15_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD16_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD16_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD17_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD17_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD18_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD18_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD19_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD19_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD20_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD20_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD21_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD21_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD22_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD22_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD23_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD23_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD24_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD24_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD25_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD25_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD26_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD26_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD27_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD27_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD28_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD28_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD29_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD29_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD30_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD30_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD31_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD31_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD32_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD32_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD33_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD33_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD34_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD34_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD35_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD35_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD36_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD36_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD37_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD37_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD38_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD38_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD39_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD39_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD40_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD40_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD41_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD41_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD42_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD42_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD43_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD43_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD44_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD44_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD45_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD45_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD46_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD46_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD47_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD47_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_CLK_posedge_posedge :	VitalDelayType   := 0.1 ns;
      thold_RST_CLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLK_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      tipd_CE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CLK                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_EN_MASK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR_MASK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR_DC                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CS0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD16                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD17                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD18                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD19                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD20                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD21                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD22                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD23                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD24                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD25                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD26                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD27                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD28                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD29                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD30                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD31                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD32                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD33                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD34                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD35                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD36                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD37                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD38                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD39                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD40                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD41                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD42                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD43                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD44                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD45                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD46                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD47                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                              :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      CLK                             :	in    STD_ULOGIC;
      EN_MASK                         :	in    STD_ULOGIC;
      WR_MASK                         :	in    STD_ULOGIC;
      WR_DC                           :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      CS0                             :	in    STD_ULOGIC;
      CS1                             :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WD0                             :	in    STD_ULOGIC;
      WD1                             :	in    STD_ULOGIC;
      WD2                             :	in    STD_ULOGIC;
      WD3                             :	in    STD_ULOGIC;
      WD4                             :	in    STD_ULOGIC;
      WD5                             :	in    STD_ULOGIC;
      WD6                             :	in    STD_ULOGIC;
      WD7                             :	in    STD_ULOGIC;
      WD8                             :	in    STD_ULOGIC;
      WD9                             :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WD16                            :	in    STD_ULOGIC;
      WD17                            :	in    STD_ULOGIC;
      WD18                            :	in    STD_ULOGIC;
      WD19                            :	in    STD_ULOGIC;
      WD20                            :	in    STD_ULOGIC;
      WD21                            :	in    STD_ULOGIC;
      WD22                            :	in    STD_ULOGIC;
      WD23                            :	in    STD_ULOGIC;
      WD24                            :	in    STD_ULOGIC;
      WD25                            :	in    STD_ULOGIC;
      WD26                            :	in    STD_ULOGIC;
      WD27                            :	in    STD_ULOGIC;
      WD28                            :	in    STD_ULOGIC;
      WD29                            :	in    STD_ULOGIC;
      WD30                            :	in    STD_ULOGIC;
      WD31                            :	in    STD_ULOGIC;
      WD32                            :	in    STD_ULOGIC;
      WD33                            :	in    STD_ULOGIC;
      WD34                            :	in    STD_ULOGIC;
      WD35                            :	in    STD_ULOGIC;
      WD36                            :	in    STD_ULOGIC;
      WD37                            :	in    STD_ULOGIC;
      WD38                            :	in    STD_ULOGIC;
      WD39                            :	in    STD_ULOGIC;
      WD40                            :	in    STD_ULOGIC;
      WD41                            :	in    STD_ULOGIC;
      WD42                            :	in    STD_ULOGIC;
      WD43                            :	in    STD_ULOGIC;
      WD44                            :	in    STD_ULOGIC;
      WD45                            :	in    STD_ULOGIC;
      WD46                            :	in    STD_ULOGIC;
      WD47                            :	in    STD_ULOGIC;
      CO0                             :	out   STD_ULOGIC;
      CO1                             :	out   STD_ULOGIC;
      CO2                             :	out   STD_ULOGIC;
      CO3                             :	out   STD_ULOGIC;
      CO4                             :	out   STD_ULOGIC;
      CO5                             :	out   STD_ULOGIC;
      CO6                             :	out   STD_ULOGIC;
      MATCH                           :	out   STD_ULOGIC;
      MUL_MATCH                       :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of CAM128X48 : entity is FALSE;
end CAM128X48;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CAM128X48 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_CAM_16K

	generic (
		ADDR_WIDTH    : integer :=  7;
		DATA_WIDTH    : integer := 48;
                MEM_INIT_FLAG : integer :=  0;  
	        MEM_INIT_FILE : string  := ""
		);
	port (
		CE        :  in  STD_LOGIC ;
		WE        :  in  STD_LOGIC ;
		CLK       :  in  STD_LOGIC ;
		EN_MASK   :  in  STD_LOGIC ;
		WR_MASK   :  in  STD_LOGIC ;
		WR_DC     :  in  STD_LOGIC ;
		RST       :  in  STD_LOGIC ;
		CS        :  in  STD_LOGIC_VECTOR ( 1 downto 0) ;
		WAD       :  in  STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0);
		WD        :  in  STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0);
		CO        :  out STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0);
		MATCH     :  out STD_LOGIC;
		MUL_MATCH :  out STD_LOGIC
		);

	end component ;


      signal CE_ipd        : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal CLK_ipd       : std_ulogic := 'X';
      signal EN_MASK_ipd   : std_ulogic := 'X';
      signal WR_MASK_ipd   : std_ulogic := 'X';
      signal WR_DC_ipd     : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal CS0_ipd       : std_ulogic := 'X';
      signal CS1_ipd       : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';

      signal WD0_ipd       : std_ulogic := 'X';
      signal WD1_ipd       : std_ulogic := 'X';
      signal WD2_ipd       : std_ulogic := 'X';
      signal WD3_ipd       : std_ulogic := 'X';
      signal WD4_ipd       : std_ulogic := 'X';
      signal WD5_ipd       : std_ulogic := 'X';
      signal WD6_ipd       : std_ulogic := 'X';
      signal WD7_ipd       : std_ulogic := 'X';
      signal WD8_ipd       : std_ulogic := 'X';
      signal WD9_ipd       : std_ulogic := 'X';
      signal WD10_ipd       : std_ulogic := 'X';
      signal WD11_ipd       : std_ulogic := 'X';
      signal WD12_ipd       : std_ulogic := 'X';
      signal WD13_ipd       : std_ulogic := 'X';
      signal WD14_ipd       : std_ulogic := 'X';
      signal WD15_ipd       : std_ulogic := 'X';
      signal WD16_ipd       : std_ulogic := 'X';
      signal WD17_ipd       : std_ulogic := 'X';
      signal WD18_ipd       : std_ulogic := 'X';
      signal WD19_ipd       : std_ulogic := 'X';
      signal WD20_ipd       : std_ulogic := 'X';
      signal WD21_ipd       : std_ulogic := 'X';
      signal WD22_ipd       : std_ulogic := 'X';
      signal WD23_ipd       : std_ulogic := 'X';
      signal WD24_ipd       : std_ulogic := 'X';
      signal WD25_ipd       : std_ulogic := 'X';
      signal WD26_ipd       : std_ulogic := 'X';
      signal WD27_ipd       : std_ulogic := 'X';
      signal WD28_ipd       : std_ulogic := 'X';
      signal WD29_ipd       : std_ulogic := 'X';
      signal WD30_ipd       : std_ulogic := 'X';
      signal WD31_ipd       : std_ulogic := 'X';
      signal WD32_ipd       : std_ulogic := 'X';
      signal WD33_ipd       : std_ulogic := 'X';
      signal WD34_ipd       : std_ulogic := 'X';
      signal WD35_ipd       : std_ulogic := 'X';
      signal WD36_ipd       : std_ulogic := 'X';
      signal WD37_ipd       : std_ulogic := 'X';
      signal WD38_ipd       : std_ulogic := 'X';
      signal WD39_ipd       : std_ulogic := 'X';
      signal WD40_ipd       : std_ulogic := 'X';
      signal WD41_ipd       : std_ulogic := 'X';
      signal WD42_ipd       : std_ulogic := 'X';
      signal WD43_ipd       : std_ulogic := 'X';
      signal WD44_ipd       : std_ulogic := 'X';
      signal WD45_ipd       : std_ulogic := 'X';
      signal WD46_ipd       : std_ulogic := 'X';
      signal WD47_ipd       : std_ulogic := 'X';
      signal MATCH_ipd      : std_ulogic := 'X'; --QQ05
      signal MUL_MATCH_ipd  : std_ulogic := 'X'; --QQ05
      signal CS             : std_logic_vector (1 downto 0);
      signal WAD             : std_logic_vector (6 downto 0);
      signal WD             : std_logic_vector (47 downto 0);
      signal CO             : std_logic_vector (6 downto 0);
      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);

begin 
 
      CS  <= CS1_ipd & CS0_ipd;
      WAD <= WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
      WD  <= WD47_ipd & WD46_ipd & WD45_ipd & WD44_ipd & WD43_ipd & WD42_ipd & WD41_ipd & WD40_ipd & WD39_ipd & WD38_ipd & WD37_ipd & WD36_ipd & WD35_ipd & WD34_ipd & WD33_ipd & WD32_ipd & WD31_ipd & WD30_ipd & WD29_ipd & WD28_ipd & WD27_ipd & WD26_ipd & WD25_ipd & WD24_ipd & WD23_ipd & WD22_ipd & WD21_ipd & WD20_ipd & WD19_ipd & WD18_ipd & WD17_ipd & WD16_ipd & WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CE_ipd, CE, tipd_CE);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (CLK_ipd, CLK, tipd_CLK);

        VitalWireDelay (EN_MASK_ipd, EN_MASK, tipd_EN_MASK);
        VitalWireDelay (WR_MASK_ipd, WR_MASK, tipd_WR_MASK);

        VitalWireDelay (WR_DC_ipd, WR_DC, tipd_WR_DC);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (CS0_ipd, CS0, tipd_CS0);
        VitalWireDelay (CS1_ipd, CS1, tipd_CS1);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);
        VitalWireDelay (WD16_ipd, WD16, tipd_WD16);
        VitalWireDelay (WD17_ipd, WD17, tipd_WD17);
        VitalWireDelay (WD18_ipd, WD18, tipd_WD18);
        VitalWireDelay (WD19_ipd, WD19, tipd_WD19);
        VitalWireDelay (WD20_ipd, WD20, tipd_WD20);
        VitalWireDelay (WD21_ipd, WD21, tipd_WD21);
        VitalWireDelay (WD22_ipd, WD22, tipd_WD22);
        VitalWireDelay (WD23_ipd, WD23, tipd_WD23);
        VitalWireDelay (WD24_ipd, WD24, tipd_WD24);
        VitalWireDelay (WD25_ipd, WD25, tipd_WD25);
        VitalWireDelay (WD26_ipd, WD26, tipd_WD26);
        VitalWireDelay (WD27_ipd, WD27, tipd_WD27);
        VitalWireDelay (WD28_ipd, WD28, tipd_WD28);
        VitalWireDelay (WD29_ipd, WD29, tipd_WD29);
        VitalWireDelay (WD30_ipd, WD30, tipd_WD30);
        VitalWireDelay (WD31_ipd, WD31, tipd_WD31);
        VitalWireDelay (WD32_ipd, WD32, tipd_WD32);
        VitalWireDelay (WD33_ipd, WD33, tipd_WD33);
        VitalWireDelay (WD34_ipd, WD34, tipd_WD34);
        VitalWireDelay (WD35_ipd, WD35, tipd_WD35);
        VitalWireDelay (WD36_ipd, WD36, tipd_WD36);
        VitalWireDelay (WD37_ipd, WD37, tipd_WD37);
        VitalWireDelay (WD38_ipd, WD38, tipd_WD38);
        VitalWireDelay (WD39_ipd, WD39, tipd_WD39);
        VitalWireDelay (WD40_ipd, WD40, tipd_WD40);
        VitalWireDelay (WD41_ipd, WD41, tipd_WD41);
        VitalWireDelay (WD42_ipd, WD42, tipd_WD42);
        VitalWireDelay (WD43_ipd, WD43, tipd_WD43);
        VitalWireDelay (WD44_ipd, WD44, tipd_WD44);
        VitalWireDelay (WD45_ipd, WD45, tipd_WD45);
        VitalWireDelay (WD46_ipd, WD46, tipd_WD46);
        VitalWireDelay (WD47_ipd, WD47, tipd_WD47);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CE_CLK_posedge      : std_ulogic  := '0';
        variable Tviol_WE_CLK_posedge      : std_ulogic  := '0';
        variable Tviol_EN_MASK_CLK_posedge      : std_ulogic  := '0';
        variable Tviol_WR_MASK_CLK_posedge      : std_ulogic  := '0';
        variable Tviol_WR_DC_CLK_posedge        : std_ulogic  := '0';
        variable Tviol_CS0_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_CS1_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WAD0_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD1_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD2_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD3_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD4_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD5_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD6_CLK_posedge         : std_ulogic  := '0';

        variable Tviol_WD0_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD1_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD2_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD3_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD4_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD5_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD6_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD7_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD8_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD9_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD10_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD11_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD12_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD13_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD14_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD15_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD16_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD17_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD18_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD19_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD20_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD21_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD22_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD23_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD24_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD25_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD26_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD27_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD28_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD29_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD30_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD31_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD32_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD33_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD34_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD35_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD36_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD37_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD38_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD39_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD40_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD41_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD42_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD43_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD44_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD45_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD46_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD47_CLK_posedge          : std_ulogic  := '0';

        variable Tviol_RST_CLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_CE_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WE_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EN_MASK_CLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_MASK_CLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_DC_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS0_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS1_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD0_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD16_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD17_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD18_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD19_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD20_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD21_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD22_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD23_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD24_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD25_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD26_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD27_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD28_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD29_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD30_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD31_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD32_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD33_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD34_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD35_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD36_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD37_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD38_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD39_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD40_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD41_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD42_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD43_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD44_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD45_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD46_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD47_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_CLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLK        : std_ulogic := '0';
        variable PInfo_CLK        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable CO0_zd          : std_ulogic := 'X';
        variable CO1_zd          : std_ulogic := 'X';
        variable CO2_zd          : std_ulogic := 'X';
        variable CO3_zd          : std_ulogic := 'X';
        variable CO4_zd          : std_ulogic := 'X';
        variable CO5_zd          : std_ulogic := 'X';
        variable CO6_zd          : std_ulogic := 'X';
        variable MATCH_zd        : std_ulogic := 'X'; --QQ05
        variable MUL_MATCH_zd    : std_ulogic := 'X'; --QQ05
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_posedge,
          TimingData              => Tmkr_CE_CLK_posedge,
          TestSignal              => CE_ipd,
          TestSignalName          => "CE",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE_CLK_noedge_posedge,
          SetupLow                => tsetup_CE_CLK_noedge_posedge,
          HoldLow                 => thold_CE_CLK_noedge_posedge,
          HoldHigh                => thold_CE_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_CLK_posedge,
          TimingData              => Tmkr_WE_CLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_CLK_noedge_posedge,
          SetupLow                => tsetup_WE_CLK_noedge_posedge,
          HoldLow                 => thold_WE_CLK_noedge_posedge,
          HoldHigh                => thold_WE_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_MASK_CLK_posedge,
          TimingData              => Tmkr_WR_MASK_CLK_posedge,
          TestSignal              => WR_MASK_ipd,
          TestSignalName          => "WR_MASK",
          TestDelay               => 0 ns,
          RefSignal               => CLk_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_MASK_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_MASK_CLK_noedge_posedge,
          HoldLow                 => thold_WR_MASK_CLK_noedge_posedge,
          HoldHigh                => thold_WR_MASK_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_DC_CLK_posedge,
          TimingData              => Tmkr_WR_DC_CLK_posedge,
          TestSignal              => WR_DC_ipd,
          TestSignalName          => "WR_RC",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_DC_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_DC_CLK_noedge_posedge,
          HoldLow                 => thold_WR_DC_CLK_noedge_posedge,
          HoldHigh                => thold_WR_DC_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS0_CLK_posedge,
          TimingData              => Tmkr_CS0_CLK_posedge,
          TestSignal              => CS0_ipd,
          TestSignalName          => "CS0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS0_CLK_noedge_posedge,
          SetupLow                => tsetup_CS0_CLK_noedge_posedge,
          HoldLow                 => thold_CS0_CLK_noedge_posedge,
          HoldHigh                => thold_CS0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS1_CLK_posedge,
          TimingData              => Tmkr_CS1_CLK_posedge,
          TestSignal              => CS1_ipd,
          TestSignalName          => "CS1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS1_CLK_noedge_posedge,
          SetupLow                => tsetup_CS1_CLK_noedge_posedge,
          HoldLow                 => thold_CS1_CLK_noedge_posedge,
          HoldHigh                => thold_CS1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EN_MASK_CLK_posedge,
          TimingData              => Tmkr_EN_MASK_CLK_posedge,
          TestSignal              => EN_MASK_ipd,
          TestSignalName          => "EN_MASK",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EN_MASK_CLK_noedge_posedge,
          SetupLow                => tsetup_EN_MASK_CLK_noedge_posedge,
          HoldLow                 => thold_EN_MASK_CLK_noedge_posedge,
          HoldHigh                => thold_EN_MASK_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_CLK_posedge,
          TimingData              => Tmkr_WAD0_CLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_CLK_noedge_posedge,
          HoldLow                 => thold_WAD0_CLK_noedge_posedge,
          HoldHigh                => thold_WAD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_CLK_posedge,
          TimingData              => Tmkr_WAD1_CLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_CLK_noedge_posedge,
          HoldLow                 => thold_WAD1_CLK_noedge_posedge,
          HoldHigh                => thold_WAD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_CLK_posedge,
          TimingData              => Tmkr_WAD2_CLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_CLK_noedge_posedge,
          HoldLow                 => thold_WAD2_CLK_noedge_posedge,
          HoldHigh                => thold_WAD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_CLK_posedge,
          TimingData              => Tmkr_WAD3_CLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_CLK_noedge_posedge,
          HoldLow                 => thold_WAD3_CLK_noedge_posedge,
          HoldHigh                => thold_WAD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_CLK_posedge,
          TimingData              => Tmkr_WAD4_CLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_CLK_noedge_posedge,
          HoldLow                 => thold_WAD4_CLK_noedge_posedge,
          HoldHigh                => thold_WAD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_CLK_posedge,
          TimingData              => Tmkr_WAD5_CLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_CLK_noedge_posedge,
          HoldLow                 => thold_WAD5_CLK_noedge_posedge,
          HoldHigh                => thold_WAD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_CLK_posedge,
          TimingData              => Tmkr_WAD6_CLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_CLK_noedge_posedge,
          HoldLow                 => thold_WAD6_CLK_noedge_posedge,
          HoldHigh                => thold_WAD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_CLK_posedge,
          TimingData              => Tmkr_WD0_CLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_CLK_noedge_posedge,
          SetupLow                => tsetup_WD0_CLK_noedge_posedge,
          HoldLow                 => thold_WD0_CLK_noedge_posedge,
          HoldHigh                => thold_WD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_CLK_posedge,
          TimingData              => Tmkr_WD1_CLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_CLK_noedge_posedge,
          SetupLow                => tsetup_WD1_CLK_noedge_posedge,
          HoldLow                 => thold_WD1_CLK_noedge_posedge,
          HoldHigh                => thold_WD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_CLK_posedge,
          TimingData              => Tmkr_WD2_CLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_CLK_noedge_posedge,
          SetupLow                => tsetup_WD2_CLK_noedge_posedge,
          HoldLow                 => thold_WD2_CLK_noedge_posedge,
          HoldHigh                => thold_WD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_CLK_posedge,
          TimingData              => Tmkr_WD3_CLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_CLK_noedge_posedge,
          SetupLow                => tsetup_WD3_CLK_noedge_posedge,
          HoldLow                 => thold_WD3_CLK_noedge_posedge,
          HoldHigh                => thold_WD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_CLK_posedge,
          TimingData              => Tmkr_WD4_CLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_CLK_noedge_posedge,
          SetupLow                => tsetup_WD4_CLK_noedge_posedge,
          HoldLow                 => thold_WD4_CLK_noedge_posedge,
          HoldHigh                => thold_WD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_CLK_posedge,
          TimingData              => Tmkr_WD5_CLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_CLK_noedge_posedge,
          SetupLow                => tsetup_WD5_CLK_noedge_posedge,
          HoldLow                 => thold_WD5_CLK_noedge_posedge,
          HoldHigh                => thold_WD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_CLK_posedge,
          TimingData              => Tmkr_WD6_CLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_CLK_noedge_posedge,
          SetupLow                => tsetup_WD6_CLK_noedge_posedge,
          HoldLow                 => thold_WD6_CLK_noedge_posedge,
          HoldHigh                => thold_WD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_CLK_posedge,
          TimingData              => Tmkr_WD7_CLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_CLK_noedge_posedge,
          SetupLow                => tsetup_WD7_CLK_noedge_posedge,
          HoldLow                 => thold_WD7_CLK_noedge_posedge,
          HoldHigh                => thold_WD7_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_CLK_posedge,
          TimingData              => Tmkr_WD8_CLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_CLK_noedge_posedge,
          SetupLow                => tsetup_WD8_CLK_noedge_posedge,
          HoldLow                 => thold_WD8_CLK_noedge_posedge,
          HoldHigh                => thold_WD8_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_CLK_posedge,
          TimingData              => Tmkr_WD9_CLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_CLK_noedge_posedge,
          SetupLow                => tsetup_WD9_CLK_noedge_posedge,
          HoldLow                 => thold_WD9_CLK_noedge_posedge,
          HoldHigh                => thold_WD9_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_CLK_posedge,
          TimingData              => Tmkr_WD10_CLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_CLK_noedge_posedge,
          SetupLow                => tsetup_WD10_CLK_noedge_posedge,
          HoldLow                 => thold_WD10_CLK_noedge_posedge,
          HoldHigh                => thold_WD10_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_CLK_posedge,
          TimingData              => Tmkr_WD11_CLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_CLK_noedge_posedge,
          SetupLow                => tsetup_WD11_CLK_noedge_posedge,
          HoldLow                 => thold_WD11_CLK_noedge_posedge,
          HoldHigh                => thold_WD11_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_CLK_posedge,
          TimingData              => Tmkr_WD12_CLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_CLK_noedge_posedge,
          SetupLow                => tsetup_WD12_CLK_noedge_posedge,
          HoldLow                 => thold_WD12_CLK_noedge_posedge,
          HoldHigh                => thold_WD12_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_CLK_posedge,
          TimingData              => Tmkr_WD13_CLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_CLK_noedge_posedge,
          SetupLow                => tsetup_WD13_CLK_noedge_posedge,
          HoldLow                 => thold_WD13_CLK_noedge_posedge,
          HoldHigh                => thold_WD13_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_CLK_posedge,
          TimingData              => Tmkr_WD14_CLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_CLK_noedge_posedge,
          SetupLow                => tsetup_WD14_CLK_noedge_posedge,
          HoldLow                 => thold_WD14_CLK_noedge_posedge,
          HoldHigh                => thold_WD14_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_CLK_posedge,
          TimingData              => Tmkr_WD15_CLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_CLK_noedge_posedge,
          SetupLow                => tsetup_WD15_CLK_noedge_posedge,
          HoldLow                 => thold_WD15_CLK_noedge_posedge,
          HoldHigh                => thold_WD15_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD16_CLK_posedge,
          TimingData              => Tmkr_WD16_CLK_posedge,
          TestSignal              => WD16_ipd,
          TestSignalName          => "WD16",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD16_CLK_noedge_posedge,
          SetupLow                => tsetup_WD16_CLK_noedge_posedge,
          HoldLow                 => thold_WD16_CLK_noedge_posedge,
          HoldHigh                => thold_WD16_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD17_CLK_posedge,
          TimingData              => Tmkr_WD17_CLK_posedge,
          TestSignal              => WD17_ipd,
          TestSignalName          => "WD17",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD17_CLK_noedge_posedge,
          SetupLow                => tsetup_WD17_CLK_noedge_posedge,
          HoldLow                 => thold_WD17_CLK_noedge_posedge,
          HoldHigh                => thold_WD17_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD18_CLK_posedge,
          TimingData              => Tmkr_WD18_CLK_posedge,
          TestSignal              => WD18_ipd,
          TestSignalName          => "WD18",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD18_CLK_noedge_posedge,
          SetupLow                => tsetup_WD18_CLK_noedge_posedge,
          HoldLow                 => thold_WD18_CLK_noedge_posedge,
          HoldHigh                => thold_WD18_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD19_CLK_posedge,
          TimingData              => Tmkr_WD19_CLK_posedge,
          TestSignal              => WD19_ipd,
          TestSignalName          => "WD19",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD19_CLK_noedge_posedge,
          SetupLow                => tsetup_WD19_CLK_noedge_posedge,
          HoldLow                 => thold_WD19_CLK_noedge_posedge,
          HoldHigh                => thold_WD19_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD20_CLK_posedge,
          TimingData              => Tmkr_WD20_CLK_posedge,
          TestSignal              => WD20_ipd,
          TestSignalName          => "WD20",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD20_CLK_noedge_posedge,
          SetupLow                => tsetup_WD20_CLK_noedge_posedge,
          HoldLow                 => thold_WD20_CLK_noedge_posedge,
          HoldHigh                => thold_WD20_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD21_CLK_posedge,
          TimingData              => Tmkr_WD21_CLK_posedge,
          TestSignal              => WD21_ipd,
          TestSignalName          => "WD21",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD21_CLK_noedge_posedge,
          SetupLow                => tsetup_WD21_CLK_noedge_posedge,
          HoldLow                 => thold_WD21_CLK_noedge_posedge,
          HoldHigh                => thold_WD21_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD22_CLK_posedge,
          TimingData              => Tmkr_WD22_CLK_posedge,
          TestSignal              => WD22_ipd,
          TestSignalName          => "WD22",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD22_CLK_noedge_posedge,
          SetupLow                => tsetup_WD22_CLK_noedge_posedge,
          HoldLow                 => thold_WD22_CLK_noedge_posedge,
          HoldHigh                => thold_WD22_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD23_CLK_posedge,
          TimingData              => Tmkr_WD23_CLK_posedge,
          TestSignal              => WD23_ipd,
          TestSignalName          => "WD23",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD23_CLK_noedge_posedge,
          SetupLow                => tsetup_WD23_CLK_noedge_posedge,
          HoldLow                 => thold_WD23_CLK_noedge_posedge,
          HoldHigh                => thold_WD23_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD24_CLK_posedge,
          TimingData              => Tmkr_WD24_CLK_posedge,
          TestSignal              => WD24_ipd,
          TestSignalName          => "WD24",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD24_CLK_noedge_posedge,
          SetupLow                => tsetup_WD24_CLK_noedge_posedge,
          HoldLow                 => thold_WD24_CLK_noedge_posedge,
          HoldHigh                => thold_WD24_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD25_CLK_posedge,
          TimingData              => Tmkr_WD25_CLK_posedge,
          TestSignal              => WD25_ipd,
          TestSignalName          => "WD25",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD25_CLK_noedge_posedge,
          SetupLow                => tsetup_WD25_CLK_noedge_posedge,
          HoldLow                 => thold_WD25_CLK_noedge_posedge,
          HoldHigh                => thold_WD25_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD26_CLK_posedge,
          TimingData              => Tmkr_WD26_CLK_posedge,
          TestSignal              => WD26_ipd,
          TestSignalName          => "WD26",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD26_CLK_noedge_posedge,
          SetupLow                => tsetup_WD26_CLK_noedge_posedge,
          HoldLow                 => thold_WD26_CLK_noedge_posedge,
          HoldHigh                => thold_WD26_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD27_CLK_posedge,
          TimingData              => Tmkr_WD27_CLK_posedge,
          TestSignal              => WD27_ipd,
          TestSignalName          => "WD27",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD27_CLK_noedge_posedge,
          SetupLow                => tsetup_WD27_CLK_noedge_posedge,
          HoldLow                 => thold_WD27_CLK_noedge_posedge,
          HoldHigh                => thold_WD27_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD28_CLK_posedge,
          TimingData              => Tmkr_WD28_CLK_posedge,
          TestSignal              => WD28_ipd,
          TestSignalName          => "WD28",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD28_CLK_noedge_posedge,
          SetupLow                => tsetup_WD28_CLK_noedge_posedge,
          HoldLow                 => thold_WD28_CLK_noedge_posedge,
          HoldHigh                => thold_WD28_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD29_CLK_posedge,
          TimingData              => Tmkr_WD29_CLK_posedge,
          TestSignal              => WD29_ipd,
          TestSignalName          => "WD29",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD29_CLK_noedge_posedge,
          SetupLow                => tsetup_WD29_CLK_noedge_posedge,
          HoldLow                 => thold_WD29_CLK_noedge_posedge,
          HoldHigh                => thold_WD29_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD30_CLK_posedge,
          TimingData              => Tmkr_WD30_CLK_posedge,
          TestSignal              => WD30_ipd,
          TestSignalName          => "WD30",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD30_CLK_noedge_posedge,
          SetupLow                => tsetup_WD30_CLK_noedge_posedge,
          HoldLow                 => thold_WD30_CLK_noedge_posedge,
          HoldHigh                => thold_WD30_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD31_CLK_posedge,
          TimingData              => Tmkr_WD31_CLK_posedge,
          TestSignal              => WD31_ipd,
          TestSignalName          => "WD31",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD31_CLK_noedge_posedge,
          SetupLow                => tsetup_WD31_CLK_noedge_posedge,
          HoldLow                 => thold_WD31_CLK_noedge_posedge,
          HoldHigh                => thold_WD31_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD32_CLK_posedge,
          TimingData              => Tmkr_WD32_CLK_posedge,
          TestSignal              => WD32_ipd,
          TestSignalName          => "WD32",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD32_CLK_noedge_posedge,
          SetupLow                => tsetup_WD32_CLK_noedge_posedge,
          HoldLow                 => thold_WD32_CLK_noedge_posedge,
          HoldHigh                => thold_WD32_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD33_CLK_posedge,
          TimingData              => Tmkr_WD33_CLK_posedge,
          TestSignal              => WD33_ipd,
          TestSignalName          => "WD33",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD33_CLK_noedge_posedge,
          SetupLow                => tsetup_WD33_CLK_noedge_posedge,
          HoldLow                 => thold_WD33_CLK_noedge_posedge,
          HoldHigh                => thold_WD33_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD34_CLK_posedge,
          TimingData              => Tmkr_WD34_CLK_posedge,
          TestSignal              => WD34_ipd,
          TestSignalName          => "WD34",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD34_CLK_noedge_posedge,
          SetupLow                => tsetup_WD34_CLK_noedge_posedge,
          HoldLow                 => thold_WD34_CLK_noedge_posedge,
          HoldHigh                => thold_WD34_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD35_CLK_posedge,
          TimingData              => Tmkr_WD35_CLK_posedge,
          TestSignal              => WD35_ipd,
          TestSignalName          => "WD35",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD35_CLK_noedge_posedge,
          SetupLow                => tsetup_WD35_CLK_noedge_posedge,
          HoldLow                 => thold_WD35_CLK_noedge_posedge,
          HoldHigh                => thold_WD35_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD36_CLK_posedge,
          TimingData              => Tmkr_WD36_CLK_posedge,
          TestSignal              => WD36_ipd,
          TestSignalName          => "WD36",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD36_CLK_noedge_posedge,
          SetupLow                => tsetup_WD36_CLK_noedge_posedge,
          HoldLow                 => thold_WD36_CLK_noedge_posedge,
          HoldHigh                => thold_WD36_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD37_CLK_posedge,
          TimingData              => Tmkr_WD37_CLK_posedge,
          TestSignal              => WD37_ipd,
          TestSignalName          => "WD37",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD37_CLK_noedge_posedge,
          SetupLow                => tsetup_WD37_CLK_noedge_posedge,
          HoldLow                 => thold_WD37_CLK_noedge_posedge,
          HoldHigh                => thold_WD37_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD38_CLK_posedge,
          TimingData              => Tmkr_WD38_CLK_posedge,
          TestSignal              => WD38_ipd,
          TestSignalName          => "WD38",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD38_CLK_noedge_posedge,
          SetupLow                => tsetup_WD38_CLK_noedge_posedge,
          HoldLow                 => thold_WD38_CLK_noedge_posedge,
          HoldHigh                => thold_WD38_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD39_CLK_posedge,
          TimingData              => Tmkr_WD39_CLK_posedge,
          TestSignal              => WD39_ipd,
          TestSignalName          => "WD39",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD39_CLK_noedge_posedge,
          SetupLow                => tsetup_WD39_CLK_noedge_posedge,
          HoldLow                 => thold_WD39_CLK_noedge_posedge,
          HoldHigh                => thold_WD39_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD40_CLK_posedge,
          TimingData              => Tmkr_WD40_CLK_posedge,
          TestSignal              => WD40_ipd,
          TestSignalName          => "WD40",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD40_CLK_noedge_posedge,
          SetupLow                => tsetup_WD40_CLK_noedge_posedge,
          HoldLow                 => thold_WD40_CLK_noedge_posedge,
          HoldHigh                => thold_WD40_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD41_CLK_posedge,
          TimingData              => Tmkr_WD41_CLK_posedge,
          TestSignal              => WD41_ipd,
          TestSignalName          => "WD41",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD41_CLK_noedge_posedge,
          SetupLow                => tsetup_WD41_CLK_noedge_posedge,
          HoldLow                 => thold_WD41_CLK_noedge_posedge,
          HoldHigh                => thold_WD41_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD42_CLK_posedge,
          TimingData              => Tmkr_WD42_CLK_posedge,
          TestSignal              => WD42_ipd,
          TestSignalName          => "WD42",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD42_CLK_noedge_posedge,
          SetupLow                => tsetup_WD42_CLK_noedge_posedge,
          HoldLow                 => thold_WD42_CLK_noedge_posedge,
          HoldHigh                => thold_WD42_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD43_CLK_posedge,
          TimingData              => Tmkr_WD43_CLK_posedge,
          TestSignal              => WD43_ipd,
          TestSignalName          => "WD43",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD43_CLK_noedge_posedge,
          SetupLow                => tsetup_WD43_CLK_noedge_posedge,
          HoldLow                 => thold_WD43_CLK_noedge_posedge,
          HoldHigh                => thold_WD43_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD44_CLK_posedge,
          TimingData              => Tmkr_WD44_CLK_posedge,
          TestSignal              => WD44_ipd,
          TestSignalName          => "WD44",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD44_CLK_noedge_posedge,
          SetupLow                => tsetup_WD44_CLK_noedge_posedge,
          HoldLow                 => thold_WD44_CLK_noedge_posedge,
          HoldHigh                => thold_WD44_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD45_CLK_posedge,
          TimingData              => Tmkr_WD45_CLK_posedge,
          TestSignal              => WD45_ipd,
          TestSignalName          => "WD45",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD45_CLK_noedge_posedge,
          SetupLow                => tsetup_WD45_CLK_noedge_posedge,
          HoldLow                 => thold_WD45_CLK_noedge_posedge,
          HoldHigh                => thold_WD45_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD46_CLK_posedge,
          TimingData              => Tmkr_WD46_CLK_posedge,
          TestSignal              => WD46_ipd,
          TestSignalName          => "WD46",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD46_CLK_noedge_posedge,
          SetupLow                => tsetup_WD46_CLK_noedge_posedge,
          HoldLow                 => thold_WD46_CLK_noedge_posedge,
          HoldHigh                => thold_WD46_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD47_CLK_posedge,
          TimingData              => Tmkr_WD47_CLK_posedge,
          TestSignal              => WD47_ipd,
          TestSignalName          => "WD47",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD47_CLK_noedge_posedge,
          SetupLow                => tsetup_WD47_CLK_noedge_posedge,
          HoldLow                 => thold_WD47_CLK_noedge_posedge,
          HoldHigh                => thold_WD47_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_CLK_posedge_posedge,
          TimingData              => Tmkr_RST_CLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_CLK_posedge_posedge,
          Removal                 => thold_RST_CLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CE_CLK_posedge or Tviol_WE_CLK_posedge or 
                 Tviol_EN_MASK_CLK_posedge or Tviol_EN_MASK_CLK_posedge or 
                 Tviol_WR_DC_CLK_posedge or Tviol_CS0_CLK_posedge or Tviol_CS1_CLK_posedge or 
                 Tviol_WAD0_CLK_posedge or Tviol_WAD1_CLK_posedge or 
                 Tviol_WAD2_CLK_posedge or Tviol_WAD3_CLK_posedge or 
                 Tviol_WAD4_CLK_posedge or Tviol_WAD4_CLK_posedge or 
                 Tviol_WAD6_CLK_posedge or 
                 Tviol_WD0_CLK_posedge or Tviol_WD1_CLK_posedge or 
                 Tviol_WD2_CLK_posedge or Tviol_WD3_CLK_posedge or 
                 Tviol_WD4_CLK_posedge or Tviol_WD5_CLK_posedge or 
                 Tviol_WD6_CLK_posedge or Tviol_WD7_CLK_posedge or 
                 Tviol_WD8_CLK_posedge or Tviol_WD9_CLK_posedge or 
                 Tviol_WD10_CLK_posedge or Tviol_WD11_CLK_posedge or 
                 Tviol_WD12_CLK_posedge or Tviol_WD13_CLK_posedge or 
                 Tviol_WD14_CLK_posedge or Tviol_WD15_CLK_posedge or 
                 Tviol_WD16_CLK_posedge or Tviol_WD17_CLK_posedge or 
                 Tviol_WD18_CLK_posedge or Tviol_WD19_CLK_posedge or 
                 Tviol_WD20_CLK_posedge or Tviol_WD21_CLK_posedge or 
                 Tviol_WD22_CLK_posedge or Tviol_WD23_CLK_posedge or 
                 Tviol_WD24_CLK_posedge or Tviol_WD25_CLK_posedge or 
                 Tviol_WD26_CLK_posedge or Tviol_WD27_CLK_posedge or 
                 Tviol_WD28_CLK_posedge or Tviol_WD29_CLK_posedge or 
                 Tviol_WD30_CLK_posedge or Tviol_WD31_CLK_posedge or 
                 Tviol_WD32_CLK_posedge or Tviol_WD33_CLK_posedge or 
                 Tviol_WD34_CLK_posedge or Tviol_WD35_CLK_posedge or 
                 Tviol_WD36_CLK_posedge or Tviol_WD37_CLK_posedge or 
                 Tviol_WD38_CLK_posedge or Tviol_WD39_CLK_posedge or 
                 Tviol_WD40_CLK_posedge or Tviol_WD41_CLK_posedge or 
                 Tviol_WD42_CLK_posedge or Tviol_WD43_CLK_posedge or 
                 Tviol_WD44_CLK_posedge or Tviol_WD45_CLK_posedge or 
                 Tviol_WD46_CLK_posedge or Tviol_WD47_CLK_posedge or 
                 Pviol_CLK or Pviol_RST or 
                 Tviol_RST_CLK_posedge_posedge; 

      wait on CE_ipd, WE_ipd, CLK_ipd, EN_MASK_ipd, WR_MASK_ipd, WR_DC_ipd, CS, WAD, WD;
      end process VITALBehavior;

      VITALBehavior_C0 : process
        variable CO0_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;
      begin
    -------------------------
    --  Functionality Section
    -------------------------
    CO0_zd := CO(0);

    VitalPathDelay01 (
      OutSignal => CO0,
      GlitchData => O_GlitchData,
      OutSignalName => "CO0",
      OutTemp => CO0_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_CO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_CO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on CO(0);
      end process VITALBehavior_C0;

      VITALBehavior_C1 : process
        variable CO1_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;
      begin
    -------------------------
    --  Functionality Section
    -------------------------
    CO1_zd := CO(1);

    VitalPathDelay01 (
      OutSignal => CO1,
      GlitchData => O_GlitchData,
      OutSignalName => "CO1",
      OutTemp => CO1_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_CO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_CO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on CO(1);
      end process VITALBehavior_C1;

      VITALBehavior_C2 : process
        variable CO2_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;
      begin
    -------------------------
    --  Functionality Section
    -------------------------
    CO2_zd := CO(2);

    VitalPathDelay01 (
      OutSignal => CO2,
      GlitchData => O_GlitchData,
      OutSignalName => "CO2",
      OutTemp => CO2_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_CO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_CO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on CO(2);
      end process VITALBehavior_C2;

      VITALBehavior_C3 : process
        variable CO3_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;
      begin
    -------------------------
    --  Functionality Section
    -------------------------
    CO3_zd := CO(3);

    VitalPathDelay01 (
      OutSignal => CO3,
      GlitchData => O_GlitchData,
      OutSignalName => "CO3",
      OutTemp => CO3_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_CO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_CO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on CO(3);
      end process VITALBehavior_C3;

      VITALBehavior_C4 : process
        variable CO4_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;
      begin
    -------------------------
    --  Functionality Section
    -------------------------
    CO4_zd := CO(4);

    VitalPathDelay01 (
      OutSignal => CO4,
      GlitchData => O_GlitchData,
      OutSignalName => "CO4",
      OutTemp => CO4_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_CO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_CO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on CO(4);
      end process VITALBehavior_C4;

      VITALBehavior_C5 : process
        variable CO5_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;
      begin
    -------------------------
    --  Functionality Section
    -------------------------
    CO5_zd := CO(5);

    VitalPathDelay01 (
      OutSignal => CO5,
      GlitchData => O_GlitchData,
      OutSignalName => "CO5",
      OutTemp => CO5_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_CO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_CO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on CO(5);
      end process VITALBehavior_C5;

      VITALBehavior_C6 : process
        variable CO6_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;
      begin
    -------------------------
    --  Functionality Section
    -------------------------
    CO6_zd := CO(6);

    VitalPathDelay01 (
      OutSignal => CO6,
      GlitchData => O_GlitchData,
      OutSignalName => "CO6",
      OutTemp => CO6_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_CO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_CO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on CO(6);
      end process VITALBehavior_C6;

--QQ05
    VITALBehavior_MATCH : process
        variable MATCH_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;
      begin
    -------------------------
    --  Functionality Section
    -------------------------
    MATCH_zd := MATCH_ipd;

    VitalPathDelay01 (
      OutSignal => MATCH,
      GlitchData => O_GlitchData,
      OutSignalName => "MATCH",
      OutTemp => MATCH_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_MATCH, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_MATCH, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on MATCH_ipd;
      end process VITALBehavior_MATCH;

    VITALBehavior_MUL_MATCH : process
        variable MUL_MATCH_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;
      begin
    -------------------------
    --  Functionality Section
    -------------------------
    MUL_MATCH_zd := MUL_MATCH_ipd;

    VitalPathDelay01 (
      OutSignal => MUL_MATCH,
      GlitchData => O_GlitchData,
      OutSignalName => "MUL_MATCH",
      OutTemp => MUL_MATCH_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_MUL_MATCH, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_MUL_MATCH, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on MUL_MATCH_ipd;
      end process VITALBehavior_MUL_MATCH;
--QQ05
	CAM_INST: SC_CAM_16K

	generic MAP (
		ADDR_WIDTH    =>  7,
		DATA_WIDTH    => 48,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
                MEM_INIT_FILE => RAM_INIT_FILE
		)
	port MAP (
		CE        => CE_ipd ,
		WE        => WE_ipd ,
		CLK       => CLK_ipd ,
		EN_MASK   => EN_MASK_ipd ,
		WR_MASK   => WR_MASK_ipd ,
		WR_DC     => WR_DC_ipd ,
		RST       => RST_ipd ,
		CS        => CS ,
		WAD       => WAD ,
		WD        => WD ,
		CO        => CO ,
		MATCH     => MATCH_ipd,     --QQ50
		MUL_MATCH => MUL_MATCH_ipd  --QQ50
		);

end VITAL;

configuration CFG_CAM128X48_VITAL of CAM128X48 is
   for VITAL
   end for;
end CFG_CAM128X48_VITAL;



----- CELL CAM128X48CL -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity CAM128X48CL is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_CLK_CMO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO32                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO33                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO34                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO35                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO36                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO37                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO38                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO39                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO40                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO41                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO42                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO43                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO44                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO45                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO46                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO47                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO48                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO49                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO50                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO51                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO52                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO53                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO54                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO55                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO56                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO57                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO58                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO59                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO60                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO61                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO62                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO63                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO64                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO65                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO66                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO67                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO68                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO69                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO70                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO71                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO72                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO73                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO74                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO75                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO76                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO77                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO78                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO79                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO80                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO81                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO82                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO83                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO84                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO85                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO86                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO87                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO88                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO89                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO90                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO91                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO92                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO93                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO94                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO95                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO96                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO97                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO98                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO99                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO100                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO101                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO102                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO103                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO104                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO105                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO106                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO107                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO108                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO109                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO110                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO111                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO112                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO113                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO114                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO115                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO116                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO117                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO118                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO119                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO120                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO121                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO122                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO123                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO124                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO125                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO126                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO127                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_CMO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO32                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO33                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO34                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO35                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO36                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO37                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO38                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO39                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO40                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO41                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO42                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO43                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO44                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO45                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO46                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO47                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO48                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO49                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO50                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO51                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO52                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO53                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO54                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO55                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO56                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO57                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO58                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO59                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO60                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO61                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO62                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO63                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO64                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO65                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO66                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO67                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO68                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO69                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO70                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO71                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO72                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO73                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO74                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO75                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO76                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO77                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO78                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO79                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO80                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO81                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO82                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO83                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO84                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO85                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO86                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO87                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO88                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO89                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO90                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO91                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO92                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO93                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO94                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO95                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO96                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO97                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO98                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO99                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO100                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO101                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO102                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO103                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO104                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO105                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO106                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO107                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO108                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO109                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO110                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO111                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO112                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO113                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO114                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO115                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO116                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO117                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO118                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO119                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO120                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO121                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO122                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO123                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO124                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO125                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO126                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO127                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WE_CLK_noedge_posedge       :	VitalDelayType   := 0.1 ns;
      thold_WE_CLK_noedge_posedge        :	VitalDelayType   := 0.0 ns;

      tsetup_CE_CLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_CE_CLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_EN_MASK_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_EN_MASK_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WR_MASK_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_MASK_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WR_DC_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_DC_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CS0_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_CS0_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CS1_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_CS1_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD0_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD1_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD1_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD2_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD2_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD3_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD3_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD4_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD4_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD5_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD5_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD6_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD6_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD0_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD1_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD1_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD2_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD2_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD3_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD3_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD4_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD4_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD5_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD5_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD6_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD6_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD7_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD7_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD8_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD8_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD9_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD9_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD10_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD10_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD11_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD11_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD12_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD12_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD13_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD13_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD14_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD14_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD15_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD15_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD16_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD16_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD17_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD17_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD18_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD18_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD19_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD19_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD20_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD20_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD21_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD21_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD22_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD22_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD23_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD23_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD24_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD24_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD25_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD25_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD26_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD26_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD27_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD27_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD28_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD28_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD29_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD29_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD30_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD30_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD31_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD31_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD32_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD32_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD33_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD33_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD34_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD34_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD35_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD35_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD36_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD36_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD37_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD37_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD38_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD38_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD39_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD39_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD40_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD40_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD41_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD41_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD42_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD42_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD43_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD43_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD44_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD44_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD45_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD45_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD46_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD46_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD47_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD47_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_CLK_posedge_posedge :	VitalDelayType   := 0.1 ns;
      thold_RST_CLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLK_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      tipd_CE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CLK                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_EN_MASK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR_MASK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR_DC                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CS0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD16                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD17                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD18                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD19                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD20                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD21                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD22                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD23                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD24                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD25                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD26                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD27                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD28                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD29                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD30                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD31                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD32                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD33                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD34                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD35                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD36                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD37                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD38                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD39                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD40                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD41                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD42                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD43                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD44                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD45                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD46                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD47                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                              :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      CLK                             :	in    STD_ULOGIC;
      EN_MASK                         :	in    STD_ULOGIC;
      WR_MASK                         :	in    STD_ULOGIC;
      WR_DC                           :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      CS0                             :	in    STD_ULOGIC;
      CS1                             :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WD0                             :	in    STD_ULOGIC;
      WD1                             :	in    STD_ULOGIC;
      WD2                             :	in    STD_ULOGIC;
      WD3                             :	in    STD_ULOGIC;
      WD4                             :	in    STD_ULOGIC;
      WD5                             :	in    STD_ULOGIC;
      WD6                             :	in    STD_ULOGIC;
      WD7                             :	in    STD_ULOGIC;
      WD8                             :	in    STD_ULOGIC;
      WD9                             :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WD16                            :	in    STD_ULOGIC;
      WD17                            :	in    STD_ULOGIC;
      WD18                            :	in    STD_ULOGIC;
      WD19                            :	in    STD_ULOGIC;
      WD20                            :	in    STD_ULOGIC;
      WD21                            :	in    STD_ULOGIC;
      WD22                            :	in    STD_ULOGIC;
      WD23                            :	in    STD_ULOGIC;
      WD24                            :	in    STD_ULOGIC;
      WD25                            :	in    STD_ULOGIC;
      WD26                            :	in    STD_ULOGIC;
      WD27                            :	in    STD_ULOGIC;
      WD28                            :	in    STD_ULOGIC;
      WD29                            :	in    STD_ULOGIC;
      WD30                            :	in    STD_ULOGIC;
      WD31                            :	in    STD_ULOGIC;
      WD32                            :	in    STD_ULOGIC;
      WD33                            :	in    STD_ULOGIC;
      WD34                            :	in    STD_ULOGIC;
      WD35                            :	in    STD_ULOGIC;
      WD36                            :	in    STD_ULOGIC;
      WD37                            :	in    STD_ULOGIC;
      WD38                            :	in    STD_ULOGIC;
      WD39                            :	in    STD_ULOGIC;
      WD40                            :	in    STD_ULOGIC;
      WD41                            :	in    STD_ULOGIC;
      WD42                            :	in    STD_ULOGIC;
      WD43                            :	in    STD_ULOGIC;
      WD44                            :	in    STD_ULOGIC;
      WD45                            :	in    STD_ULOGIC;
      WD46                            :	in    STD_ULOGIC;
      WD47                            :	in    STD_ULOGIC;
      CMO0                            :	out   STD_ULOGIC;
      CMO1                            :	out   STD_ULOGIC;
      CMO2                            :	out   STD_ULOGIC;
      CMO3                            :	out   STD_ULOGIC;
      CMO4                            :	out   STD_ULOGIC;
      CMO5                            :	out   STD_ULOGIC;
      CMO6                            :	out   STD_ULOGIC;
      CMO7                            :	out   STD_ULOGIC;
      CMO8                            :	out   STD_ULOGIC;
      CMO9                            :	out   STD_ULOGIC;
      CMO10                            :	out   STD_ULOGIC;
      CMO11                            :	out   STD_ULOGIC;
      CMO12                            :	out   STD_ULOGIC;
      CMO13                            :	out   STD_ULOGIC;
      CMO14                            :	out   STD_ULOGIC;
      CMO15                            :	out   STD_ULOGIC;
      CMO16                            :	out   STD_ULOGIC;
      CMO17                            :	out   STD_ULOGIC;
      CMO18                            :	out   STD_ULOGIC;
      CMO19                            :	out   STD_ULOGIC;
      CMO20                            :	out   STD_ULOGIC;
      CMO21                            :	out   STD_ULOGIC;
      CMO22                            :	out   STD_ULOGIC;
      CMO23                            :	out   STD_ULOGIC;
      CMO24                            :	out   STD_ULOGIC;
      CMO25                            :	out   STD_ULOGIC;
      CMO26                            :	out   STD_ULOGIC;
      CMO27                            :	out   STD_ULOGIC;
      CMO28                            :	out   STD_ULOGIC;
      CMO29                            :	out   STD_ULOGIC;
      CMO30                            :	out   STD_ULOGIC;
      CMO31                            :	out   STD_ULOGIC;
      CMO32                            :	out   STD_ULOGIC;
      CMO33                            :	out   STD_ULOGIC;
      CMO34                            :	out   STD_ULOGIC;
      CMO35                            :	out   STD_ULOGIC;
      CMO36                            :	out   STD_ULOGIC;
      CMO37                            :	out   STD_ULOGIC;
      CMO38                            :	out   STD_ULOGIC;
      CMO39                            :	out   STD_ULOGIC;
      CMO40                            :	out   STD_ULOGIC;
      CMO41                            :	out   STD_ULOGIC;
      CMO42                            :	out   STD_ULOGIC;
      CMO43                            :	out   STD_ULOGIC;
      CMO44                            :	out   STD_ULOGIC;
      CMO45                            :	out   STD_ULOGIC;
      CMO46                            :	out   STD_ULOGIC;
      CMO47                            :	out   STD_ULOGIC;
      CMO48                            :	out   STD_ULOGIC;
      CMO49                            :	out   STD_ULOGIC;
      CMO50                            :	out   STD_ULOGIC;
      CMO51                            :	out   STD_ULOGIC;
      CMO52                            :	out   STD_ULOGIC;
      CMO53                            :	out   STD_ULOGIC;
      CMO54                            :	out   STD_ULOGIC;
      CMO55                            :	out   STD_ULOGIC;
      CMO56                            :	out   STD_ULOGIC;
      CMO57                            :	out   STD_ULOGIC;
      CMO58                            :	out   STD_ULOGIC;
      CMO59                            :	out   STD_ULOGIC;
      CMO60                            :	out   STD_ULOGIC;
      CMO61                            :	out   STD_ULOGIC;
      CMO62                            :	out   STD_ULOGIC;
      CMO63                            :	out   STD_ULOGIC;
      CMO64                            :	out   STD_ULOGIC;
      CMO65                            :	out   STD_ULOGIC;
      CMO66                            :	out   STD_ULOGIC;
      CMO67                            :	out   STD_ULOGIC;
      CMO68                            :	out   STD_ULOGIC;
      CMO69                            :	out   STD_ULOGIC;
      CMO70                            :	out   STD_ULOGIC;
      CMO71                            :	out   STD_ULOGIC;
      CMO72                            :	out   STD_ULOGIC;
      CMO73                            :	out   STD_ULOGIC;
      CMO74                            :	out   STD_ULOGIC;
      CMO75                            :	out   STD_ULOGIC;
      CMO76                            :	out   STD_ULOGIC;
      CMO77                            :	out   STD_ULOGIC;
      CMO78                            :	out   STD_ULOGIC;
      CMO79                            :	out   STD_ULOGIC;
      CMO80                            :	out   STD_ULOGIC;
      CMO81                            :	out   STD_ULOGIC;
      CMO82                            :	out   STD_ULOGIC;
      CMO83                            :	out   STD_ULOGIC;
      CMO84                            :	out   STD_ULOGIC;
      CMO85                            :	out   STD_ULOGIC;
      CMO86                            :	out   STD_ULOGIC;
      CMO87                            :	out   STD_ULOGIC;
      CMO88                            :	out   STD_ULOGIC;
      CMO89                            :	out   STD_ULOGIC;
      CMO90                            :	out   STD_ULOGIC;
      CMO91                            :	out   STD_ULOGIC;
      CMO92                            :	out   STD_ULOGIC;
      CMO93                            :	out   STD_ULOGIC;
      CMO94                            :	out   STD_ULOGIC;
      CMO95                            :	out   STD_ULOGIC;
      CMO96                            :	out   STD_ULOGIC;
      CMO97                            :	out   STD_ULOGIC;
      CMO98                            :	out   STD_ULOGIC;
      CMO99                            :	out   STD_ULOGIC;
      CMO100                            :	out   STD_ULOGIC;
      CMO101                            :	out   STD_ULOGIC;
      CMO102                            :	out   STD_ULOGIC;
      CMO103                            :	out   STD_ULOGIC;
      CMO104                            :	out   STD_ULOGIC;
      CMO105                            :	out   STD_ULOGIC;
      CMO106                            :	out   STD_ULOGIC;
      CMO107                            :	out   STD_ULOGIC;
      CMO108                            :	out   STD_ULOGIC;
      CMO109                            :	out   STD_ULOGIC;
      CMO110                            :	out   STD_ULOGIC;
      CMO111                            :	out   STD_ULOGIC;
      CMO112                            :	out   STD_ULOGIC;
      CMO113                            :	out   STD_ULOGIC;
      CMO114                            :	out   STD_ULOGIC;
      CMO115                            :	out   STD_ULOGIC;
      CMO116                            :	out   STD_ULOGIC;
      CMO117                            :	out   STD_ULOGIC;
      CMO118                            :	out   STD_ULOGIC;
      CMO119                            :	out   STD_ULOGIC;
      CMO120                            :	out   STD_ULOGIC;
      CMO121                            :	out   STD_ULOGIC;
      CMO122                            :	out   STD_ULOGIC;
      CMO123                            :	out   STD_ULOGIC;
      CMO124                            :	out   STD_ULOGIC;
      CMO125                            :	out   STD_ULOGIC;
      CMO126                            :	out   STD_ULOGIC;
      CMO127                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of CAM128X48CL : entity is FALSE;
end CAM128X48CL;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CAM128X48CL is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_CAMCL_16K

	generic (
		ADDR_WIDTH    : integer :=  7;
		DATA_WIDTH    : integer := 48;
                MEM_INIT_FLAG : integer :=  0;  
	        MEM_INIT_FILE : string  := ""
		);
	port (
		CE        :  in  STD_LOGIC ;
		WE        :  in  STD_LOGIC ;
		CLK       :  in  STD_LOGIC ;
		EN_MASK   :  in  STD_LOGIC ;
		WR_MASK   :  in  STD_LOGIC ;
		WR_DC     :  in  STD_LOGIC ;
		RST       :  in  STD_LOGIC ;
		CS        :  in  STD_LOGIC_VECTOR ( 1 downto 0) ;
		WAD       :  in  STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0);
		WD        :  in  STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0);
                CMO       : out  STD_LOGIC_VECTOR ( 2**ADDR_WIDTH -1 downto 0)
		);
	end component;

      signal CE_ipd        : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal CLK_ipd       : std_ulogic := 'X';
      signal EN_MASK_ipd   : std_ulogic := 'X';
      signal WR_MASK_ipd   : std_ulogic := 'X';
      signal WR_DC_ipd     : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal CS0_ipd       : std_ulogic := 'X';
      signal CS1_ipd       : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';

      signal WD0_ipd       : std_ulogic := 'X';
      signal WD1_ipd       : std_ulogic := 'X';
      signal WD2_ipd       : std_ulogic := 'X';
      signal WD3_ipd       : std_ulogic := 'X';
      signal WD4_ipd       : std_ulogic := 'X';
      signal WD5_ipd       : std_ulogic := 'X';
      signal WD6_ipd       : std_ulogic := 'X';
      signal WD7_ipd       : std_ulogic := 'X';
      signal WD8_ipd       : std_ulogic := 'X';
      signal WD9_ipd       : std_ulogic := 'X';
      signal WD10_ipd       : std_ulogic := 'X';
      signal WD11_ipd       : std_ulogic := 'X';
      signal WD12_ipd       : std_ulogic := 'X';
      signal WD13_ipd       : std_ulogic := 'X';
      signal WD14_ipd       : std_ulogic := 'X';
      signal WD15_ipd       : std_ulogic := 'X';
      signal WD16_ipd       : std_ulogic := 'X';
      signal WD17_ipd       : std_ulogic := 'X';
      signal WD18_ipd       : std_ulogic := 'X';
      signal WD19_ipd       : std_ulogic := 'X';
      signal WD20_ipd       : std_ulogic := 'X';
      signal WD21_ipd       : std_ulogic := 'X';
      signal WD22_ipd       : std_ulogic := 'X';
      signal WD23_ipd       : std_ulogic := 'X';
      signal WD24_ipd       : std_ulogic := 'X';
      signal WD25_ipd       : std_ulogic := 'X';
      signal WD26_ipd       : std_ulogic := 'X';
      signal WD27_ipd       : std_ulogic := 'X';
      signal WD28_ipd       : std_ulogic := 'X';
      signal WD29_ipd       : std_ulogic := 'X';
      signal WD30_ipd       : std_ulogic := 'X';
      signal WD31_ipd       : std_ulogic := 'X';
      signal WD32_ipd       : std_ulogic := 'X';
      signal WD33_ipd       : std_ulogic := 'X';
      signal WD34_ipd       : std_ulogic := 'X';
      signal WD35_ipd       : std_ulogic := 'X';
      signal WD36_ipd       : std_ulogic := 'X';
      signal WD37_ipd       : std_ulogic := 'X';
      signal WD38_ipd       : std_ulogic := 'X';
      signal WD39_ipd       : std_ulogic := 'X';
      signal WD40_ipd       : std_ulogic := 'X';
      signal WD41_ipd       : std_ulogic := 'X';
      signal WD42_ipd       : std_ulogic := 'X';
      signal WD43_ipd       : std_ulogic := 'X';
      signal WD44_ipd       : std_ulogic := 'X';
      signal WD45_ipd       : std_ulogic := 'X';
      signal WD46_ipd       : std_ulogic := 'X';
      signal WD47_ipd       : std_ulogic := 'X';

      signal CS             : std_logic_vector (1 downto 0);
      signal WAD             : std_logic_vector (6 downto 0);
      signal WD             : std_logic_vector (47 downto 0);
      signal CMO             : std_logic_vector (127 downto 0);
      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);

begin 

      CS  <= CS1_ipd & CS0_ipd;
      WAD <= WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
      WD  <= WD47_ipd & WD46_ipd & WD45_ipd & WD44_ipd & WD43_ipd & WD42_ipd & WD41_ipd & WD40_ipd & WD39_ipd & WD38_ipd & WD37_ipd & WD36_ipd & WD35_ipd & WD34_ipd & WD33_ipd & WD32_ipd & WD31_ipd & WD30_ipd & WD29_ipd & WD28_ipd & WD27_ipd & WD26_ipd & WD25_ipd & WD24_ipd & WD23_ipd & WD22_ipd & WD21_ipd & WD20_ipd & WD19_ipd & WD18_ipd & WD17_ipd & WD16_ipd & WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
     
	CMO0 <= CMO(0);
	CMO1 <= CMO(1);
	CMO2 <= CMO(2);
	CMO3 <= CMO(3);
	CMO4 <= CMO(4);
	CMO5 <= CMO(5);
	CMO6 <= CMO(6);
	CMO7 <= CMO(7);
	CMO8 <= CMO(8);
	CMO9 <= CMO(9);
	CMO10 <= CMO(10);
	CMO11 <= CMO(11);
	CMO12 <= CMO(12);
	CMO13 <= CMO(13);
	CMO14 <= CMO(14);
	CMO15 <= CMO(15);
	CMO16 <= CMO(16);
	CMO17 <= CMO(17);
	CMO18 <= CMO(18);
	CMO19 <= CMO(19);
	CMO20 <= CMO(20);
	CMO21 <= CMO(21);
	CMO22 <= CMO(22);
	CMO23 <= CMO(23);
	CMO24 <= CMO(24);
	CMO25 <= CMO(25);
	CMO26 <= CMO(26);
	CMO27 <= CMO(27);
	CMO28 <= CMO(28);
	CMO29 <= CMO(29);
	CMO30 <= CMO(30);
	CMO31 <= CMO(31);
	CMO32 <= CMO(32);
	CMO33 <= CMO(33);
	CMO34 <= CMO(34);
	CMO35 <= CMO(35);
	CMO36 <= CMO(36);
	CMO37 <= CMO(37);
	CMO38 <= CMO(38);
	CMO39 <= CMO(39);
	CMO40 <= CMO(40);
	CMO41 <= CMO(41);
	CMO42 <= CMO(42);
	CMO43 <= CMO(43);
	CMO44 <= CMO(44);
	CMO45 <= CMO(45);
	CMO46 <= CMO(46);
	CMO47 <= CMO(47);
	CMO48 <= CMO(48);
	CMO49 <= CMO(49);
	CMO50 <= CMO(50);
	CMO51 <= CMO(51);
	CMO52 <= CMO(52);
	CMO53 <= CMO(53);
	CMO54 <= CMO(54);
	CMO55 <= CMO(55);
	CMO56 <= CMO(56);
	CMO57 <= CMO(57);
	CMO58 <= CMO(58);
	CMO59 <= CMO(59);
	CMO60 <= CMO(60);
	CMO61 <= CMO(61);
	CMO62 <= CMO(62);
	CMO63 <= CMO(63);
	CMO64 <= CMO(64);
	CMO65 <= CMO(65);
	CMO66 <= CMO(66);
	CMO67 <= CMO(67);
	CMO68 <= CMO(68);
	CMO69 <= CMO(69);
	CMO70 <= CMO(70);
	CMO71 <= CMO(71);
	CMO72 <= CMO(72);
	CMO73 <= CMO(73);
	CMO74 <= CMO(74);
	CMO75 <= CMO(75);
	CMO76 <= CMO(76);
	CMO77 <= CMO(77);
	CMO78 <= CMO(78);
	CMO79 <= CMO(79);
	CMO80 <= CMO(80);
	CMO81 <= CMO(81);
	CMO82 <= CMO(82);
	CMO83 <= CMO(83);
	CMO84 <= CMO(84);
	CMO85 <= CMO(85);
	CMO86 <= CMO(86);
	CMO87 <= CMO(87);
	CMO88 <= CMO(88);
	CMO89 <= CMO(89);
	CMO90 <= CMO(90);
	CMO91 <= CMO(91);
	CMO92 <= CMO(92);
	CMO93 <= CMO(93);
	CMO94 <= CMO(94);
	CMO95 <= CMO(95);
	CMO96 <= CMO(96);
	CMO97 <= CMO(97);
	CMO98 <= CMO(98);
	CMO99 <= CMO(99);
	CMO100 <= CMO(100);
	CMO101 <= CMO(101);
	CMO102 <= CMO(102);
	CMO103 <= CMO(103);
	CMO104 <= CMO(104);
	CMO105 <= CMO(105);
	CMO106 <= CMO(106);
	CMO107 <= CMO(107);
	CMO108 <= CMO(108);
	CMO109 <= CMO(109);
	CMO110 <= CMO(110);
	CMO111 <= CMO(111);
	CMO112 <= CMO(112);
	CMO113 <= CMO(113);
	CMO114 <= CMO(114);
	CMO115 <= CMO(115);
	CMO116 <= CMO(116);
	CMO117 <= CMO(117);
	CMO118 <= CMO(118);
	CMO119 <= CMO(119);
	CMO120 <= CMO(120);
	CMO121 <= CMO(121);
	CMO122 <= CMO(122);
	CMO123 <= CMO(123);
	CMO124 <= CMO(124);
	CMO125 <= CMO(125);
	CMO126 <= CMO(126);
	CMO127 <= CMO(127);


  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CE_ipd, CE, tipd_CE);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (CLK_ipd, CLK, tipd_CLK);

        VitalWireDelay (EN_MASK_ipd, EN_MASK, tipd_EN_MASK);
        VitalWireDelay (WR_MASK_ipd, WR_MASK, tipd_WR_MASK);

        VitalWireDelay (WR_DC_ipd, WR_DC, tipd_WR_DC);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (CS0_ipd, CS0, tipd_CS0);
        VitalWireDelay (CS1_ipd, CS1, tipd_CS1);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);
        VitalWireDelay (WD16_ipd, WD16, tipd_WD16);
        VitalWireDelay (WD17_ipd, WD17, tipd_WD17);
        VitalWireDelay (WD18_ipd, WD18, tipd_WD18);
        VitalWireDelay (WD19_ipd, WD19, tipd_WD19);
        VitalWireDelay (WD20_ipd, WD20, tipd_WD20);
        VitalWireDelay (WD21_ipd, WD21, tipd_WD21);
        VitalWireDelay (WD22_ipd, WD22, tipd_WD22);
        VitalWireDelay (WD23_ipd, WD23, tipd_WD23);
        VitalWireDelay (WD24_ipd, WD24, tipd_WD24);
        VitalWireDelay (WD25_ipd, WD25, tipd_WD25);
        VitalWireDelay (WD26_ipd, WD26, tipd_WD26);
        VitalWireDelay (WD27_ipd, WD27, tipd_WD27);
        VitalWireDelay (WD28_ipd, WD28, tipd_WD28);
        VitalWireDelay (WD29_ipd, WD29, tipd_WD29);
        VitalWireDelay (WD30_ipd, WD30, tipd_WD30);
        VitalWireDelay (WD31_ipd, WD31, tipd_WD31);
        VitalWireDelay (WD32_ipd, WD32, tipd_WD32);
        VitalWireDelay (WD33_ipd, WD33, tipd_WD33);
        VitalWireDelay (WD34_ipd, WD34, tipd_WD34);
        VitalWireDelay (WD35_ipd, WD35, tipd_WD35);
        VitalWireDelay (WD36_ipd, WD36, tipd_WD36);
        VitalWireDelay (WD37_ipd, WD37, tipd_WD37);
        VitalWireDelay (WD38_ipd, WD38, tipd_WD38);
        VitalWireDelay (WD39_ipd, WD39, tipd_WD39);
        VitalWireDelay (WD40_ipd, WD40, tipd_WD40);
        VitalWireDelay (WD41_ipd, WD41, tipd_WD41);
        VitalWireDelay (WD42_ipd, WD42, tipd_WD42);
        VitalWireDelay (WD43_ipd, WD43, tipd_WD43);
        VitalWireDelay (WD44_ipd, WD44, tipd_WD44);
        VitalWireDelay (WD45_ipd, WD45, tipd_WD45);
        VitalWireDelay (WD46_ipd, WD46, tipd_WD46);
        VitalWireDelay (WD47_ipd, WD47, tipd_WD47);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CE_CLK_posedge      : std_ulogic  := '0';
        variable Tviol_WE_CLK_posedge      : std_ulogic  := '0';
        variable Tviol_EN_MASK_CLK_posedge      : std_ulogic  := '0';
        variable Tviol_WR_MASK_CLK_posedge      : std_ulogic  := '0';
        variable Tviol_WR_DC_CLK_posedge        : std_ulogic  := '0';
        variable Tviol_CS0_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_CS1_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WAD0_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD1_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD2_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD3_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD4_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD5_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD6_CLK_posedge         : std_ulogic  := '0';

        variable Tviol_WD0_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD1_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD2_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD3_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD4_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD5_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD6_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD7_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD8_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD9_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD10_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD11_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD12_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD13_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD14_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD15_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD16_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD17_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD18_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD19_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD20_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD21_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD22_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD23_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD24_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD25_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD26_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD27_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD28_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD29_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD30_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD31_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD32_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD33_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD34_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD35_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD36_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD37_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD38_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD39_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD40_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD41_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD42_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD43_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD44_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD45_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD46_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD47_CLK_posedge          : std_ulogic  := '0';

        variable Tviol_RST_CLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_CE_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WE_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EN_MASK_CLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_MASK_CLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_DC_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS0_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS1_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD0_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD16_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD17_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD18_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD19_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD20_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD21_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD22_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD23_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD24_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD25_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD26_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD27_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD28_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD29_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD30_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD31_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD32_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD33_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD34_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD35_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD36_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD37_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD38_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD39_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD40_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD41_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD42_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD43_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD44_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD45_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD46_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD47_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_CLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLK        : std_ulogic := '0';
        variable PInfo_CLK        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable CO0_zd          : std_ulogic := 'X';
        variable CO1_zd          : std_ulogic := 'X';
        variable CO2_zd          : std_ulogic := 'X';
        variable CO3_zd          : std_ulogic := 'X';
        variable CO4_zd          : std_ulogic := 'X';
        variable CO5_zd          : std_ulogic := 'X';
        variable CO6_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_posedge,
          TimingData              => Tmkr_CE_CLK_posedge,
          TestSignal              => CE_ipd,
          TestSignalName          => "CE",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE_CLK_noedge_posedge,
          SetupLow                => tsetup_CE_CLK_noedge_posedge,
          HoldLow                 => thold_CE_CLK_noedge_posedge,
          HoldHigh                => thold_CE_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_CLK_posedge,
          TimingData              => Tmkr_WE_CLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_CLK_noedge_posedge,
          SetupLow                => tsetup_WE_CLK_noedge_posedge,
          HoldLow                 => thold_WE_CLK_noedge_posedge,
          HoldHigh                => thold_WE_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_MASK_CLK_posedge,
          TimingData              => Tmkr_WR_MASK_CLK_posedge,
          TestSignal              => WR_MASK_ipd,
          TestSignalName          => "WR_MASK",
          TestDelay               => 0 ns,
          RefSignal               => CLk_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_MASK_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_MASK_CLK_noedge_posedge,
          HoldLow                 => thold_WR_MASK_CLK_noedge_posedge,
          HoldHigh                => thold_WR_MASK_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_DC_CLK_posedge,
          TimingData              => Tmkr_WR_DC_CLK_posedge,
          TestSignal              => WR_DC_ipd,
          TestSignalName          => "WR_RC",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_DC_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_DC_CLK_noedge_posedge,
          HoldLow                 => thold_WR_DC_CLK_noedge_posedge,
          HoldHigh                => thold_WR_DC_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS0_CLK_posedge,
          TimingData              => Tmkr_CS0_CLK_posedge,
          TestSignal              => CS0_ipd,
          TestSignalName          => "CS0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS0_CLK_noedge_posedge,
          SetupLow                => tsetup_CS0_CLK_noedge_posedge,
          HoldLow                 => thold_CS0_CLK_noedge_posedge,
          HoldHigh                => thold_CS0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS1_CLK_posedge,
          TimingData              => Tmkr_CS1_CLK_posedge,
          TestSignal              => CS1_ipd,
          TestSignalName          => "CS1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS1_CLK_noedge_posedge,
          SetupLow                => tsetup_CS1_CLK_noedge_posedge,
          HoldLow                 => thold_CS1_CLK_noedge_posedge,
          HoldHigh                => thold_CS1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EN_MASK_CLK_posedge,
          TimingData              => Tmkr_EN_MASK_CLK_posedge,
          TestSignal              => EN_MASK_ipd,
          TestSignalName          => "EN_MASK",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EN_MASK_CLK_noedge_posedge,
          SetupLow                => tsetup_EN_MASK_CLK_noedge_posedge,
          HoldLow                 => thold_EN_MASK_CLK_noedge_posedge,
          HoldHigh                => thold_EN_MASK_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_CLK_posedge,
          TimingData              => Tmkr_WAD0_CLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_CLK_noedge_posedge,
          HoldLow                 => thold_WAD0_CLK_noedge_posedge,
          HoldHigh                => thold_WAD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_CLK_posedge,
          TimingData              => Tmkr_WAD1_CLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_CLK_noedge_posedge,
          HoldLow                 => thold_WAD1_CLK_noedge_posedge,
          HoldHigh                => thold_WAD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_CLK_posedge,
          TimingData              => Tmkr_WAD2_CLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_CLK_noedge_posedge,
          HoldLow                 => thold_WAD2_CLK_noedge_posedge,
          HoldHigh                => thold_WAD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_CLK_posedge,
          TimingData              => Tmkr_WAD3_CLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_CLK_noedge_posedge,
          HoldLow                 => thold_WAD3_CLK_noedge_posedge,
          HoldHigh                => thold_WAD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_CLK_posedge,
          TimingData              => Tmkr_WAD4_CLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_CLK_noedge_posedge,
          HoldLow                 => thold_WAD4_CLK_noedge_posedge,
          HoldHigh                => thold_WAD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_CLK_posedge,
          TimingData              => Tmkr_WAD5_CLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_CLK_noedge_posedge,
          HoldLow                 => thold_WAD5_CLK_noedge_posedge,
          HoldHigh                => thold_WAD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_CLK_posedge,
          TimingData              => Tmkr_WAD6_CLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_CLK_noedge_posedge,
          HoldLow                 => thold_WAD6_CLK_noedge_posedge,
          HoldHigh                => thold_WAD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_CLK_posedge,
          TimingData              => Tmkr_WD0_CLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_CLK_noedge_posedge,
          SetupLow                => tsetup_WD0_CLK_noedge_posedge,
          HoldLow                 => thold_WD0_CLK_noedge_posedge,
          HoldHigh                => thold_WD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_CLK_posedge,
          TimingData              => Tmkr_WD1_CLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_CLK_noedge_posedge,
          SetupLow                => tsetup_WD1_CLK_noedge_posedge,
          HoldLow                 => thold_WD1_CLK_noedge_posedge,
          HoldHigh                => thold_WD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_CLK_posedge,
          TimingData              => Tmkr_WD2_CLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_CLK_noedge_posedge,
          SetupLow                => tsetup_WD2_CLK_noedge_posedge,
          HoldLow                 => thold_WD2_CLK_noedge_posedge,
          HoldHigh                => thold_WD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_CLK_posedge,
          TimingData              => Tmkr_WD3_CLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_CLK_noedge_posedge,
          SetupLow                => tsetup_WD3_CLK_noedge_posedge,
          HoldLow                 => thold_WD3_CLK_noedge_posedge,
          HoldHigh                => thold_WD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_CLK_posedge,
          TimingData              => Tmkr_WD4_CLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_CLK_noedge_posedge,
          SetupLow                => tsetup_WD4_CLK_noedge_posedge,
          HoldLow                 => thold_WD4_CLK_noedge_posedge,
          HoldHigh                => thold_WD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_CLK_posedge,
          TimingData              => Tmkr_WD5_CLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_CLK_noedge_posedge,
          SetupLow                => tsetup_WD5_CLK_noedge_posedge,
          HoldLow                 => thold_WD5_CLK_noedge_posedge,
          HoldHigh                => thold_WD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_CLK_posedge,
          TimingData              => Tmkr_WD6_CLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_CLK_noedge_posedge,
          SetupLow                => tsetup_WD6_CLK_noedge_posedge,
          HoldLow                 => thold_WD6_CLK_noedge_posedge,
          HoldHigh                => thold_WD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_CLK_posedge,
          TimingData              => Tmkr_WD7_CLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_CLK_noedge_posedge,
          SetupLow                => tsetup_WD7_CLK_noedge_posedge,
          HoldLow                 => thold_WD7_CLK_noedge_posedge,
          HoldHigh                => thold_WD7_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_CLK_posedge,
          TimingData              => Tmkr_WD8_CLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_CLK_noedge_posedge,
          SetupLow                => tsetup_WD8_CLK_noedge_posedge,
          HoldLow                 => thold_WD8_CLK_noedge_posedge,
          HoldHigh                => thold_WD8_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_CLK_posedge,
          TimingData              => Tmkr_WD9_CLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_CLK_noedge_posedge,
          SetupLow                => tsetup_WD9_CLK_noedge_posedge,
          HoldLow                 => thold_WD9_CLK_noedge_posedge,
          HoldHigh                => thold_WD9_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_CLK_posedge,
          TimingData              => Tmkr_WD10_CLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_CLK_noedge_posedge,
          SetupLow                => tsetup_WD10_CLK_noedge_posedge,
          HoldLow                 => thold_WD10_CLK_noedge_posedge,
          HoldHigh                => thold_WD10_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_CLK_posedge,
          TimingData              => Tmkr_WD11_CLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_CLK_noedge_posedge,
          SetupLow                => tsetup_WD11_CLK_noedge_posedge,
          HoldLow                 => thold_WD11_CLK_noedge_posedge,
          HoldHigh                => thold_WD11_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_CLK_posedge,
          TimingData              => Tmkr_WD12_CLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_CLK_noedge_posedge,
          SetupLow                => tsetup_WD12_CLK_noedge_posedge,
          HoldLow                 => thold_WD12_CLK_noedge_posedge,
          HoldHigh                => thold_WD12_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_CLK_posedge,
          TimingData              => Tmkr_WD13_CLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_CLK_noedge_posedge,
          SetupLow                => tsetup_WD13_CLK_noedge_posedge,
          HoldLow                 => thold_WD13_CLK_noedge_posedge,
          HoldHigh                => thold_WD13_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_CLK_posedge,
          TimingData              => Tmkr_WD14_CLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_CLK_noedge_posedge,
          SetupLow                => tsetup_WD14_CLK_noedge_posedge,
          HoldLow                 => thold_WD14_CLK_noedge_posedge,
          HoldHigh                => thold_WD14_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_CLK_posedge,
          TimingData              => Tmkr_WD15_CLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_CLK_noedge_posedge,
          SetupLow                => tsetup_WD15_CLK_noedge_posedge,
          HoldLow                 => thold_WD15_CLK_noedge_posedge,
          HoldHigh                => thold_WD15_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD16_CLK_posedge,
          TimingData              => Tmkr_WD16_CLK_posedge,
          TestSignal              => WD16_ipd,
          TestSignalName          => "WD16",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD16_CLK_noedge_posedge,
          SetupLow                => tsetup_WD16_CLK_noedge_posedge,
          HoldLow                 => thold_WD16_CLK_noedge_posedge,
          HoldHigh                => thold_WD16_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD17_CLK_posedge,
          TimingData              => Tmkr_WD17_CLK_posedge,
          TestSignal              => WD17_ipd,
          TestSignalName          => "WD17",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD17_CLK_noedge_posedge,
          SetupLow                => tsetup_WD17_CLK_noedge_posedge,
          HoldLow                 => thold_WD17_CLK_noedge_posedge,
          HoldHigh                => thold_WD17_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD18_CLK_posedge,
          TimingData              => Tmkr_WD18_CLK_posedge,
          TestSignal              => WD18_ipd,
          TestSignalName          => "WD18",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD18_CLK_noedge_posedge,
          SetupLow                => tsetup_WD18_CLK_noedge_posedge,
          HoldLow                 => thold_WD18_CLK_noedge_posedge,
          HoldHigh                => thold_WD18_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD19_CLK_posedge,
          TimingData              => Tmkr_WD19_CLK_posedge,
          TestSignal              => WD19_ipd,
          TestSignalName          => "WD19",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD19_CLK_noedge_posedge,
          SetupLow                => tsetup_WD19_CLK_noedge_posedge,
          HoldLow                 => thold_WD19_CLK_noedge_posedge,
          HoldHigh                => thold_WD19_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD20_CLK_posedge,
          TimingData              => Tmkr_WD20_CLK_posedge,
          TestSignal              => WD20_ipd,
          TestSignalName          => "WD20",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD20_CLK_noedge_posedge,
          SetupLow                => tsetup_WD20_CLK_noedge_posedge,
          HoldLow                 => thold_WD20_CLK_noedge_posedge,
          HoldHigh                => thold_WD20_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD21_CLK_posedge,
          TimingData              => Tmkr_WD21_CLK_posedge,
          TestSignal              => WD21_ipd,
          TestSignalName          => "WD21",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD21_CLK_noedge_posedge,
          SetupLow                => tsetup_WD21_CLK_noedge_posedge,
          HoldLow                 => thold_WD21_CLK_noedge_posedge,
          HoldHigh                => thold_WD21_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD22_CLK_posedge,
          TimingData              => Tmkr_WD22_CLK_posedge,
          TestSignal              => WD22_ipd,
          TestSignalName          => "WD22",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD22_CLK_noedge_posedge,
          SetupLow                => tsetup_WD22_CLK_noedge_posedge,
          HoldLow                 => thold_WD22_CLK_noedge_posedge,
          HoldHigh                => thold_WD22_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD23_CLK_posedge,
          TimingData              => Tmkr_WD23_CLK_posedge,
          TestSignal              => WD23_ipd,
          TestSignalName          => "WD23",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD23_CLK_noedge_posedge,
          SetupLow                => tsetup_WD23_CLK_noedge_posedge,
          HoldLow                 => thold_WD23_CLK_noedge_posedge,
          HoldHigh                => thold_WD23_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD24_CLK_posedge,
          TimingData              => Tmkr_WD24_CLK_posedge,
          TestSignal              => WD24_ipd,
          TestSignalName          => "WD24",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD24_CLK_noedge_posedge,
          SetupLow                => tsetup_WD24_CLK_noedge_posedge,
          HoldLow                 => thold_WD24_CLK_noedge_posedge,
          HoldHigh                => thold_WD24_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD25_CLK_posedge,
          TimingData              => Tmkr_WD25_CLK_posedge,
          TestSignal              => WD25_ipd,
          TestSignalName          => "WD25",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD25_CLK_noedge_posedge,
          SetupLow                => tsetup_WD25_CLK_noedge_posedge,
          HoldLow                 => thold_WD25_CLK_noedge_posedge,
          HoldHigh                => thold_WD25_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD26_CLK_posedge,
          TimingData              => Tmkr_WD26_CLK_posedge,
          TestSignal              => WD26_ipd,
          TestSignalName          => "WD26",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD26_CLK_noedge_posedge,
          SetupLow                => tsetup_WD26_CLK_noedge_posedge,
          HoldLow                 => thold_WD26_CLK_noedge_posedge,
          HoldHigh                => thold_WD26_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD27_CLK_posedge,
          TimingData              => Tmkr_WD27_CLK_posedge,
          TestSignal              => WD27_ipd,
          TestSignalName          => "WD27",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD27_CLK_noedge_posedge,
          SetupLow                => tsetup_WD27_CLK_noedge_posedge,
          HoldLow                 => thold_WD27_CLK_noedge_posedge,
          HoldHigh                => thold_WD27_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD28_CLK_posedge,
          TimingData              => Tmkr_WD28_CLK_posedge,
          TestSignal              => WD28_ipd,
          TestSignalName          => "WD28",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD28_CLK_noedge_posedge,
          SetupLow                => tsetup_WD28_CLK_noedge_posedge,
          HoldLow                 => thold_WD28_CLK_noedge_posedge,
          HoldHigh                => thold_WD28_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD29_CLK_posedge,
          TimingData              => Tmkr_WD29_CLK_posedge,
          TestSignal              => WD29_ipd,
          TestSignalName          => "WD29",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD29_CLK_noedge_posedge,
          SetupLow                => tsetup_WD29_CLK_noedge_posedge,
          HoldLow                 => thold_WD29_CLK_noedge_posedge,
          HoldHigh                => thold_WD29_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD30_CLK_posedge,
          TimingData              => Tmkr_WD30_CLK_posedge,
          TestSignal              => WD30_ipd,
          TestSignalName          => "WD30",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD30_CLK_noedge_posedge,
          SetupLow                => tsetup_WD30_CLK_noedge_posedge,
          HoldLow                 => thold_WD30_CLK_noedge_posedge,
          HoldHigh                => thold_WD30_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD31_CLK_posedge,
          TimingData              => Tmkr_WD31_CLK_posedge,
          TestSignal              => WD31_ipd,
          TestSignalName          => "WD31",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD31_CLK_noedge_posedge,
          SetupLow                => tsetup_WD31_CLK_noedge_posedge,
          HoldLow                 => thold_WD31_CLK_noedge_posedge,
          HoldHigh                => thold_WD31_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD32_CLK_posedge,
          TimingData              => Tmkr_WD32_CLK_posedge,
          TestSignal              => WD32_ipd,
          TestSignalName          => "WD32",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD32_CLK_noedge_posedge,
          SetupLow                => tsetup_WD32_CLK_noedge_posedge,
          HoldLow                 => thold_WD32_CLK_noedge_posedge,
          HoldHigh                => thold_WD32_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD33_CLK_posedge,
          TimingData              => Tmkr_WD33_CLK_posedge,
          TestSignal              => WD33_ipd,
          TestSignalName          => "WD33",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD33_CLK_noedge_posedge,
          SetupLow                => tsetup_WD33_CLK_noedge_posedge,
          HoldLow                 => thold_WD33_CLK_noedge_posedge,
          HoldHigh                => thold_WD33_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD34_CLK_posedge,
          TimingData              => Tmkr_WD34_CLK_posedge,
          TestSignal              => WD34_ipd,
          TestSignalName          => "WD34",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD34_CLK_noedge_posedge,
          SetupLow                => tsetup_WD34_CLK_noedge_posedge,
          HoldLow                 => thold_WD34_CLK_noedge_posedge,
          HoldHigh                => thold_WD34_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD35_CLK_posedge,
          TimingData              => Tmkr_WD35_CLK_posedge,
          TestSignal              => WD35_ipd,
          TestSignalName          => "WD35",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD35_CLK_noedge_posedge,
          SetupLow                => tsetup_WD35_CLK_noedge_posedge,
          HoldLow                 => thold_WD35_CLK_noedge_posedge,
          HoldHigh                => thold_WD35_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD36_CLK_posedge,
          TimingData              => Tmkr_WD36_CLK_posedge,
          TestSignal              => WD36_ipd,
          TestSignalName          => "WD36",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD36_CLK_noedge_posedge,
          SetupLow                => tsetup_WD36_CLK_noedge_posedge,
          HoldLow                 => thold_WD36_CLK_noedge_posedge,
          HoldHigh                => thold_WD36_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD37_CLK_posedge,
          TimingData              => Tmkr_WD37_CLK_posedge,
          TestSignal              => WD37_ipd,
          TestSignalName          => "WD37",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD37_CLK_noedge_posedge,
          SetupLow                => tsetup_WD37_CLK_noedge_posedge,
          HoldLow                 => thold_WD37_CLK_noedge_posedge,
          HoldHigh                => thold_WD37_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD38_CLK_posedge,
          TimingData              => Tmkr_WD38_CLK_posedge,
          TestSignal              => WD38_ipd,
          TestSignalName          => "WD38",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD38_CLK_noedge_posedge,
          SetupLow                => tsetup_WD38_CLK_noedge_posedge,
          HoldLow                 => thold_WD38_CLK_noedge_posedge,
          HoldHigh                => thold_WD38_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD39_CLK_posedge,
          TimingData              => Tmkr_WD39_CLK_posedge,
          TestSignal              => WD39_ipd,
          TestSignalName          => "WD39",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD39_CLK_noedge_posedge,
          SetupLow                => tsetup_WD39_CLK_noedge_posedge,
          HoldLow                 => thold_WD39_CLK_noedge_posedge,
          HoldHigh                => thold_WD39_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD40_CLK_posedge,
          TimingData              => Tmkr_WD40_CLK_posedge,
          TestSignal              => WD40_ipd,
          TestSignalName          => "WD40",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD40_CLK_noedge_posedge,
          SetupLow                => tsetup_WD40_CLK_noedge_posedge,
          HoldLow                 => thold_WD40_CLK_noedge_posedge,
          HoldHigh                => thold_WD40_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD41_CLK_posedge,
          TimingData              => Tmkr_WD41_CLK_posedge,
          TestSignal              => WD41_ipd,
          TestSignalName          => "WD41",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD41_CLK_noedge_posedge,
          SetupLow                => tsetup_WD41_CLK_noedge_posedge,
          HoldLow                 => thold_WD41_CLK_noedge_posedge,
          HoldHigh                => thold_WD41_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD42_CLK_posedge,
          TimingData              => Tmkr_WD42_CLK_posedge,
          TestSignal              => WD42_ipd,
          TestSignalName          => "WD42",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD42_CLK_noedge_posedge,
          SetupLow                => tsetup_WD42_CLK_noedge_posedge,
          HoldLow                 => thold_WD42_CLK_noedge_posedge,
          HoldHigh                => thold_WD42_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD43_CLK_posedge,
          TimingData              => Tmkr_WD43_CLK_posedge,
          TestSignal              => WD43_ipd,
          TestSignalName          => "WD43",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD43_CLK_noedge_posedge,
          SetupLow                => tsetup_WD43_CLK_noedge_posedge,
          HoldLow                 => thold_WD43_CLK_noedge_posedge,
          HoldHigh                => thold_WD43_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD44_CLK_posedge,
          TimingData              => Tmkr_WD44_CLK_posedge,
          TestSignal              => WD44_ipd,
          TestSignalName          => "WD44",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD44_CLK_noedge_posedge,
          SetupLow                => tsetup_WD44_CLK_noedge_posedge,
          HoldLow                 => thold_WD44_CLK_noedge_posedge,
          HoldHigh                => thold_WD44_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD45_CLK_posedge,
          TimingData              => Tmkr_WD45_CLK_posedge,
          TestSignal              => WD45_ipd,
          TestSignalName          => "WD45",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD45_CLK_noedge_posedge,
          SetupLow                => tsetup_WD45_CLK_noedge_posedge,
          HoldLow                 => thold_WD45_CLK_noedge_posedge,
          HoldHigh                => thold_WD45_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD46_CLK_posedge,
          TimingData              => Tmkr_WD46_CLK_posedge,
          TestSignal              => WD46_ipd,
          TestSignalName          => "WD46",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD46_CLK_noedge_posedge,
          SetupLow                => tsetup_WD46_CLK_noedge_posedge,
          HoldLow                 => thold_WD46_CLK_noedge_posedge,
          HoldHigh                => thold_WD46_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD47_CLK_posedge,
          TimingData              => Tmkr_WD47_CLK_posedge,
          TestSignal              => WD47_ipd,
          TestSignalName          => "WD47",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD47_CLK_noedge_posedge,
          SetupLow                => tsetup_WD47_CLK_noedge_posedge,
          HoldLow                 => thold_WD47_CLK_noedge_posedge,
          HoldHigh                => thold_WD47_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/CAM128X48CL",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/CAM128X48CL",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_CLK_posedge_posedge,
          TimingData              => Tmkr_RST_CLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_CLK_posedge_posedge,
          Removal                 => thold_RST_CLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48CL",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CE_CLK_posedge or Tviol_WE_CLK_posedge or 
                 Tviol_EN_MASK_CLK_posedge or Tviol_EN_MASK_CLK_posedge or 
                 Tviol_WR_DC_CLK_posedge or Tviol_CS0_CLK_posedge or Tviol_CS1_CLK_posedge or 
                 Tviol_WAD0_CLK_posedge or Tviol_WAD1_CLK_posedge or 
                 Tviol_WAD2_CLK_posedge or Tviol_WAD3_CLK_posedge or 
                 Tviol_WAD4_CLK_posedge or Tviol_WAD4_CLK_posedge or 
                 Tviol_WAD6_CLK_posedge or 
                 Tviol_WD0_CLK_posedge or Tviol_WD1_CLK_posedge or 
                 Tviol_WD2_CLK_posedge or Tviol_WD3_CLK_posedge or 
                 Tviol_WD4_CLK_posedge or Tviol_WD5_CLK_posedge or 
                 Tviol_WD6_CLK_posedge or Tviol_WD7_CLK_posedge or 
                 Tviol_WD8_CLK_posedge or Tviol_WD9_CLK_posedge or 
                 Tviol_WD10_CLK_posedge or Tviol_WD11_CLK_posedge or 
                 Tviol_WD12_CLK_posedge or Tviol_WD13_CLK_posedge or 
                 Tviol_WD14_CLK_posedge or Tviol_WD15_CLK_posedge or 
                 Tviol_WD16_CLK_posedge or Tviol_WD17_CLK_posedge or 
                 Tviol_WD18_CLK_posedge or Tviol_WD19_CLK_posedge or 
                 Tviol_WD20_CLK_posedge or Tviol_WD21_CLK_posedge or 
                 Tviol_WD22_CLK_posedge or Tviol_WD23_CLK_posedge or 
                 Tviol_WD24_CLK_posedge or Tviol_WD25_CLK_posedge or 
                 Tviol_WD26_CLK_posedge or Tviol_WD27_CLK_posedge or 
                 Tviol_WD28_CLK_posedge or Tviol_WD29_CLK_posedge or 
                 Tviol_WD30_CLK_posedge or Tviol_WD31_CLK_posedge or 
                 Tviol_WD32_CLK_posedge or Tviol_WD33_CLK_posedge or 
                 Tviol_WD34_CLK_posedge or Tviol_WD35_CLK_posedge or 
                 Tviol_WD36_CLK_posedge or Tviol_WD37_CLK_posedge or 
                 Tviol_WD38_CLK_posedge or Tviol_WD39_CLK_posedge or 
                 Tviol_WD40_CLK_posedge or Tviol_WD41_CLK_posedge or 
                 Tviol_WD42_CLK_posedge or Tviol_WD43_CLK_posedge or 
                 Tviol_WD44_CLK_posedge or Tviol_WD45_CLK_posedge or 
                 Tviol_WD46_CLK_posedge or Tviol_WD47_CLK_posedge or 
                 Pviol_CLK or Pviol_RST or 
                 Tviol_RST_CLK_posedge_posedge; 

    -------------------------
    --  Functionality Section
    -------------------------


wait on CE_ipd, WE_ipd, CLK_ipd, EN_MASK_ipd, WR_MASK_ipd, WR_DC_ipd, CS, WAD, WD, CMO;

      end process VITALBehavior;

	CAMCL_inst : SC_CAMCL_16K

	generic map (
		ADDR_WIDTH    =>  7,
		DATA_WIDTH    => 48,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
                MEM_INIT_FILE => RAM_INIT_FILE
		)
	port map (
		CE        => CE_ipd ,
		WE        => WE_ipd ,
		CLK       => CLK_ipd ,
		EN_MASK   => EN_MASK_ipd ,
		WR_MASK   => WR_MASK_ipd ,
		WR_DC     => WR_DC_ipd ,
		RST       => RST_ipd ,
		CS        => CS ,
		WAD       => WAD ,
		WD        => WD ,
                CMO       => CMO
		);

end VITAL;

configuration CFG_CAM128X48CL_VITAL of CAM128X48CL is
   for VITAL
   end for;
end CFG_CAM128X48CL_VITAL;



----- CELL CAM128X48CM -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity CAM128X48CM is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_CLK_CMO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO32                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO33                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO34                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO35                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO36                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO37                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO38                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO39                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO40                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO41                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO42                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO43                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO44                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO45                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO46                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO47                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO48                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO49                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO50                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO51                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO52                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO53                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO54                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO55                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO56                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO57                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO58                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO59                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO60                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO61                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO62                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO63                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO64                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO65                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO66                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO67                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO68                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO69                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO70                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO71                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO72                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO73                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO74                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO75                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO76                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO77                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO78                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO79                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO80                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO81                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO82                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO83                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO84                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO85                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO86                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO87                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO88                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO89                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO90                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO91                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO92                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO93                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO94                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO95                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO96                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO97                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO98                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO99                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO100                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO101                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO102                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO103                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO104                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO105                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO106                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO107                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO108                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO109                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO110                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO111                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO112                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO113                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO114                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO115                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO116                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO117                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO118                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO119                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO120                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO121                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO122                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO123                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO124                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO125                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO126                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CMO127                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_CMO0                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO1                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO2                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO3                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO4                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO5                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO6                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO7                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO8                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO9                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO10                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO11                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO12                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO13                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO14                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO15                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO16                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO17                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO18                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO19                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO20                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO21                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO22                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO23                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO24                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO25                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO26                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO27                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO28                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO29                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO30                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO31                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO32                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO33                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO34                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO35                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO36                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO37                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO38                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO39                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO40                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO41                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO42                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO43                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO44                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO45                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO46                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO47                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO48                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO49                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO50                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO51                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO52                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO53                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO54                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO55                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO56                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO57                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO58                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO59                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO60                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO61                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO62                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO63                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO64                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO65                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO66                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO67                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO68                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO69                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO70                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO71                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO72                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO73                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO74                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO75                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO76                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO77                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO78                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO79                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO80                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO81                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO82                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO83                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO84                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO85                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO86                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO87                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO88                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO89                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO90                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO91                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO92                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO93                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO94                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO95                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO96                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO97                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO98                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO99                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO100                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO101                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO102                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO103                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO104                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO105                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO106                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO107                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO108                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO109                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO110                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO111                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO112                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO113                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO114                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO115                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO116                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO117                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO118                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO119                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO120                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO121                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO122                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO123                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO124                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO125                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO126                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CMO127                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WE_CLK_noedge_posedge       :	VitalDelayType   := 0.1 ns;
      thold_WE_CLK_noedge_posedge        :	VitalDelayType   := 0.0 ns;

      tsetup_CE_CLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_CE_CLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_EN_MASK_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_EN_MASK_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WR_MASK_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_MASK_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WR_DC_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_DC_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CS0_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_CS0_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CS1_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_CS1_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD0_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD1_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD1_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD2_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD2_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD3_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD3_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD4_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD4_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD5_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD5_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD6_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD6_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD0_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD1_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD1_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD2_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD2_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD3_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD3_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD4_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD4_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD5_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD5_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD6_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD6_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD7_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD7_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD8_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD8_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD9_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD9_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD10_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD10_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD11_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD11_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD12_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD12_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD13_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD13_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD14_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD14_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD15_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD15_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD16_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD16_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD17_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD17_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD18_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD18_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD19_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD19_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD20_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD20_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD21_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD21_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD22_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD22_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD23_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD23_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD24_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD24_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD25_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD25_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD26_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD26_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD27_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD27_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD28_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD28_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD29_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD29_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD30_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD30_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD31_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD31_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD32_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD32_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD33_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD33_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD34_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD34_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD35_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD35_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD36_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD36_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD37_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD37_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD38_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD38_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD39_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD39_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD40_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD40_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD41_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD41_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD42_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD42_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD43_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD43_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD44_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD44_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD45_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD45_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD46_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD46_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD47_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD47_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_CLK_posedge_posedge :	VitalDelayType   := 0.1 ns;
      thold_RST_CLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLK_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      tipd_CE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CLK                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_EN_MASK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR_MASK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR_DC                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CS0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD16                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD17                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD18                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD19                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD20                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD21                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD22                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD23                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD24                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD25                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD26                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD27                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD28                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD29                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD30                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD31                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD32                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD33                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD34                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD35                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD36                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD37                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD38                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD39                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD40                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD41                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD42                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD43                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD44                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD45                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD46                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD47                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI8                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI9                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI16                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI17                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI18                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI19                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI20                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI21                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI22                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI23                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI24                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI25                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI26                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI27                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI28                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI29                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI30                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI31                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI32                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI33                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI34                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI35                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI36                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI37                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI38                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI39                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI40                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI41                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI42                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI43                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI44                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI45                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI46                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI47                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI48                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI49                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI50                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI51                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI52                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI53                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI54                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI55                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI56                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI57                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI58                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI59                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI60                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI61                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI62                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI63                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI64                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI65                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI66                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI67                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI68                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI69                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI70                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI71                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI72                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI73                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI74                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI75                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI76                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI77                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI78                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI79                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI80                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI81                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI82                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI83                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI84                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI85                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI86                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI87                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI88                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI89                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI90                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI91                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI92                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI93                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI94                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI95                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI96                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI97                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI98                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI99                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI100                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI101                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI102                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI103                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI104                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI105                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI106                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI107                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI108                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI109                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI110                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI111                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI112                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI113                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI114                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI115                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI116                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI117                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI118                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI119                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI120                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI121                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI122                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI123                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI124                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI125                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI126                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI127                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                              :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      CLK                             :	in    STD_ULOGIC;
      EN_MASK                         :	in    STD_ULOGIC;
      WR_MASK                         :	in    STD_ULOGIC;
      WR_DC                           :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      CS0                             :	in    STD_ULOGIC;
      CS1                             :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WD0                             :	in    STD_ULOGIC;
      WD1                             :	in    STD_ULOGIC;
      WD2                             :	in    STD_ULOGIC;
      WD3                             :	in    STD_ULOGIC;
      WD4                             :	in    STD_ULOGIC;
      WD5                             :	in    STD_ULOGIC;
      WD6                             :	in    STD_ULOGIC;
      WD7                             :	in    STD_ULOGIC;
      WD8                             :	in    STD_ULOGIC;
      WD9                             :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WD16                            :	in    STD_ULOGIC;
      WD17                            :	in    STD_ULOGIC;
      WD18                            :	in    STD_ULOGIC;
      WD19                            :	in    STD_ULOGIC;
      WD20                            :	in    STD_ULOGIC;
      WD21                            :	in    STD_ULOGIC;
      WD22                            :	in    STD_ULOGIC;
      WD23                            :	in    STD_ULOGIC;
      WD24                            :	in    STD_ULOGIC;
      WD25                            :	in    STD_ULOGIC;
      WD26                            :	in    STD_ULOGIC;
      WD27                            :	in    STD_ULOGIC;
      WD28                            :	in    STD_ULOGIC;
      WD29                            :	in    STD_ULOGIC;
      WD30                            :	in    STD_ULOGIC;
      WD31                            :	in    STD_ULOGIC;
      WD32                            :	in    STD_ULOGIC;
      WD33                            :	in    STD_ULOGIC;
      WD34                            :	in    STD_ULOGIC;
      WD35                            :	in    STD_ULOGIC;
      WD36                            :	in    STD_ULOGIC;
      WD37                            :	in    STD_ULOGIC;
      WD38                            :	in    STD_ULOGIC;
      WD39                            :	in    STD_ULOGIC;
      WD40                            :	in    STD_ULOGIC;
      WD41                            :	in    STD_ULOGIC;
      WD42                            :	in    STD_ULOGIC;
      WD43                            :	in    STD_ULOGIC;
      WD44                            :	in    STD_ULOGIC;
      WD45                            :	in    STD_ULOGIC;
      WD46                            :	in    STD_ULOGIC;
      WD47                            :	in    STD_ULOGIC;
      CMI0                            :	in   STD_ULOGIC;
      CMI1                            :	in   STD_ULOGIC;
      CMI2                            :	in   STD_ULOGIC;
      CMI3                            :	in   STD_ULOGIC;
      CMI4                            :	in   STD_ULOGIC;
      CMI5                            :	in   STD_ULOGIC;
      CMI6                            :	in   STD_ULOGIC;
      CMI7                            :	in   STD_ULOGIC;
      CMI8                            :	in   STD_ULOGIC;
      CMI9                            :	in   STD_ULOGIC;
      CMI10                            :	in   STD_ULOGIC;
      CMI11                            :	in   STD_ULOGIC;
      CMI12                            :	in   STD_ULOGIC;
      CMI13                            :	in   STD_ULOGIC;
      CMI14                            :	in   STD_ULOGIC;
      CMI15                            :	in   STD_ULOGIC;
      CMI16                            :	in   STD_ULOGIC;
      CMI17                            :	in   STD_ULOGIC;
      CMI18                            :	in   STD_ULOGIC;
      CMI19                            :	in   STD_ULOGIC;
      CMI20                            :	in   STD_ULOGIC;
      CMI21                            :	in   STD_ULOGIC;
      CMI22                            :	in   STD_ULOGIC;
      CMI23                            :	in   STD_ULOGIC;
      CMI24                            :	in   STD_ULOGIC;
      CMI25                            :	in   STD_ULOGIC;
      CMI26                            :	in   STD_ULOGIC;
      CMI27                            :	in   STD_ULOGIC;
      CMI28                            :	in   STD_ULOGIC;
      CMI29                            :	in   STD_ULOGIC;
      CMI30                            :	in   STD_ULOGIC;
      CMI31                            :	in   STD_ULOGIC;
      CMI32                            :	in   STD_ULOGIC;
      CMI33                            :	in   STD_ULOGIC;
      CMI34                            :	in   STD_ULOGIC;
      CMI35                            :	in   STD_ULOGIC;
      CMI36                            :	in   STD_ULOGIC;
      CMI37                            :	in   STD_ULOGIC;
      CMI38                            :	in   STD_ULOGIC;
      CMI39                            :	in   STD_ULOGIC;
      CMI40                            :	in   STD_ULOGIC;
      CMI41                            :	in   STD_ULOGIC;
      CMI42                            :	in   STD_ULOGIC;
      CMI43                            :	in   STD_ULOGIC;
      CMI44                            :	in   STD_ULOGIC;
      CMI45                            :	in   STD_ULOGIC;
      CMI46                            :	in   STD_ULOGIC;
      CMI47                            :	in   STD_ULOGIC;
      CMI48                            :	in   STD_ULOGIC;
      CMI49                            :	in   STD_ULOGIC;
      CMI50                            :	in   STD_ULOGIC;
      CMI51                            :	in   STD_ULOGIC;
      CMI52                            :	in   STD_ULOGIC;
      CMI53                            :	in   STD_ULOGIC;
      CMI54                            :	in   STD_ULOGIC;
      CMI55                            :	in   STD_ULOGIC;
      CMI56                            :	in   STD_ULOGIC;
      CMI57                            :	in   STD_ULOGIC;
      CMI58                            :	in   STD_ULOGIC;
      CMI59                            :	in   STD_ULOGIC;
      CMI60                            :	in   STD_ULOGIC;
      CMI61                            :	in   STD_ULOGIC;
      CMI62                            :	in   STD_ULOGIC;
      CMI63                            :	in   STD_ULOGIC;
      CMI64                            :	in   STD_ULOGIC;
      CMI65                            :	in   STD_ULOGIC;
      CMI66                            :	in   STD_ULOGIC;
      CMI67                            :	in   STD_ULOGIC;
      CMI68                            :	in   STD_ULOGIC;
      CMI69                            :	in   STD_ULOGIC;
      CMI70                            :	in   STD_ULOGIC;
      CMI71                            :	in   STD_ULOGIC;
      CMI72                            :	in   STD_ULOGIC;
      CMI73                            :	in   STD_ULOGIC;
      CMI74                            :	in   STD_ULOGIC;
      CMI75                            :	in   STD_ULOGIC;
      CMI76                            :	in   STD_ULOGIC;
      CMI77                            :	in   STD_ULOGIC;
      CMI78                            :	in   STD_ULOGIC;
      CMI79                            :	in   STD_ULOGIC;
      CMI80                            :	in   STD_ULOGIC;
      CMI81                            :	in   STD_ULOGIC;
      CMI82                            :	in   STD_ULOGIC;
      CMI83                            :	in   STD_ULOGIC;
      CMI84                            :	in   STD_ULOGIC;
      CMI85                            :	in   STD_ULOGIC;
      CMI86                            :	in   STD_ULOGIC;
      CMI87                            :	in   STD_ULOGIC;
      CMI88                            :	in   STD_ULOGIC;
      CMI89                            :	in   STD_ULOGIC;
      CMI90                            :	in   STD_ULOGIC;
      CMI91                            :	in   STD_ULOGIC;
      CMI92                            :	in   STD_ULOGIC;
      CMI93                            :	in   STD_ULOGIC;
      CMI94                            :	in   STD_ULOGIC;
      CMI95                            :	in   STD_ULOGIC;
      CMI96                            :	in   STD_ULOGIC;
      CMI97                            :	in   STD_ULOGIC;
      CMI98                            :	in   STD_ULOGIC;
      CMI99                            :	in   STD_ULOGIC;
      CMI100                            :	in   STD_ULOGIC;
      CMI101                            :	in   STD_ULOGIC;
      CMI102                            :	in   STD_ULOGIC;
      CMI103                            :	in   STD_ULOGIC;
      CMI104                            :	in   STD_ULOGIC;
      CMI105                            :	in   STD_ULOGIC;
      CMI106                            :	in   STD_ULOGIC;
      CMI107                            :	in   STD_ULOGIC;
      CMI108                            :	in   STD_ULOGIC;
      CMI109                            :	in   STD_ULOGIC;
      CMI110                            :	in   STD_ULOGIC;
      CMI111                            :	in   STD_ULOGIC;
      CMI112                            :	in   STD_ULOGIC;
      CMI113                            :	in   STD_ULOGIC;
      CMI114                            :	in   STD_ULOGIC;
      CMI115                            :	in   STD_ULOGIC;
      CMI116                            :	in   STD_ULOGIC;
      CMI117                            :	in   STD_ULOGIC;
      CMI118                            :	in   STD_ULOGIC;
      CMI119                            :	in   STD_ULOGIC;
      CMI120                            :	in   STD_ULOGIC;
      CMI121                            :	in   STD_ULOGIC;
      CMI122                            :	in   STD_ULOGIC;
      CMI123                            :	in   STD_ULOGIC;
      CMI124                            :	in   STD_ULOGIC;
      CMI125                            :	in   STD_ULOGIC;
      CMI126                            :	in   STD_ULOGIC;
      CMI127                            :	in   STD_ULOGIC;
      CMO0                            :	out   STD_ULOGIC;
      CMO1                            :	out   STD_ULOGIC;
      CMO2                            :	out   STD_ULOGIC;
      CMO3                            :	out   STD_ULOGIC;
      CMO4                            :	out   STD_ULOGIC;
      CMO5                            :	out   STD_ULOGIC;
      CMO6                            :	out   STD_ULOGIC;
      CMO7                            :	out   STD_ULOGIC;
      CMO8                            :	out   STD_ULOGIC;
      CMO9                            :	out   STD_ULOGIC;
      CMO10                            :	out   STD_ULOGIC;
      CMO11                            :	out   STD_ULOGIC;
      CMO12                            :	out   STD_ULOGIC;
      CMO13                            :	out   STD_ULOGIC;
      CMO14                            :	out   STD_ULOGIC;
      CMO15                            :	out   STD_ULOGIC;
      CMO16                            :	out   STD_ULOGIC;
      CMO17                            :	out   STD_ULOGIC;
      CMO18                            :	out   STD_ULOGIC;
      CMO19                            :	out   STD_ULOGIC;
      CMO20                            :	out   STD_ULOGIC;
      CMO21                            :	out   STD_ULOGIC;
      CMO22                            :	out   STD_ULOGIC;
      CMO23                            :	out   STD_ULOGIC;
      CMO24                            :	out   STD_ULOGIC;
      CMO25                            :	out   STD_ULOGIC;
      CMO26                            :	out   STD_ULOGIC;
      CMO27                            :	out   STD_ULOGIC;
      CMO28                            :	out   STD_ULOGIC;
      CMO29                            :	out   STD_ULOGIC;
      CMO30                            :	out   STD_ULOGIC;
      CMO31                            :	out   STD_ULOGIC;
      CMO32                            :	out   STD_ULOGIC;
      CMO33                            :	out   STD_ULOGIC;
      CMO34                            :	out   STD_ULOGIC;
      CMO35                            :	out   STD_ULOGIC;
      CMO36                            :	out   STD_ULOGIC;
      CMO37                            :	out   STD_ULOGIC;
      CMO38                            :	out   STD_ULOGIC;
      CMO39                            :	out   STD_ULOGIC;
      CMO40                            :	out   STD_ULOGIC;
      CMO41                            :	out   STD_ULOGIC;
      CMO42                            :	out   STD_ULOGIC;
      CMO43                            :	out   STD_ULOGIC;
      CMO44                            :	out   STD_ULOGIC;
      CMO45                            :	out   STD_ULOGIC;
      CMO46                            :	out   STD_ULOGIC;
      CMO47                            :	out   STD_ULOGIC;
      CMO48                            :	out   STD_ULOGIC;
      CMO49                            :	out   STD_ULOGIC;
      CMO50                            :	out   STD_ULOGIC;
      CMO51                            :	out   STD_ULOGIC;
      CMO52                            :	out   STD_ULOGIC;
      CMO53                            :	out   STD_ULOGIC;
      CMO54                            :	out   STD_ULOGIC;
      CMO55                            :	out   STD_ULOGIC;
      CMO56                            :	out   STD_ULOGIC;
      CMO57                            :	out   STD_ULOGIC;
      CMO58                            :	out   STD_ULOGIC;
      CMO59                            :	out   STD_ULOGIC;
      CMO60                            :	out   STD_ULOGIC;
      CMO61                            :	out   STD_ULOGIC;
      CMO62                            :	out   STD_ULOGIC;
      CMO63                            :	out   STD_ULOGIC;
      CMO64                            :	out   STD_ULOGIC;
      CMO65                            :	out   STD_ULOGIC;
      CMO66                            :	out   STD_ULOGIC;
      CMO67                            :	out   STD_ULOGIC;
      CMO68                            :	out   STD_ULOGIC;
      CMO69                            :	out   STD_ULOGIC;
      CMO70                            :	out   STD_ULOGIC;
      CMO71                            :	out   STD_ULOGIC;
      CMO72                            :	out   STD_ULOGIC;
      CMO73                            :	out   STD_ULOGIC;
      CMO74                            :	out   STD_ULOGIC;
      CMO75                            :	out   STD_ULOGIC;
      CMO76                            :	out   STD_ULOGIC;
      CMO77                            :	out   STD_ULOGIC;
      CMO78                            :	out   STD_ULOGIC;
      CMO79                            :	out   STD_ULOGIC;
      CMO80                            :	out   STD_ULOGIC;
      CMO81                            :	out   STD_ULOGIC;
      CMO82                            :	out   STD_ULOGIC;
      CMO83                            :	out   STD_ULOGIC;
      CMO84                            :	out   STD_ULOGIC;
      CMO85                            :	out   STD_ULOGIC;
      CMO86                            :	out   STD_ULOGIC;
      CMO87                            :	out   STD_ULOGIC;
      CMO88                            :	out   STD_ULOGIC;
      CMO89                            :	out   STD_ULOGIC;
      CMO90                            :	out   STD_ULOGIC;
      CMO91                            :	out   STD_ULOGIC;
      CMO92                            :	out   STD_ULOGIC;
      CMO93                            :	out   STD_ULOGIC;
      CMO94                            :	out   STD_ULOGIC;
      CMO95                            :	out   STD_ULOGIC;
      CMO96                            :	out   STD_ULOGIC;
      CMO97                            :	out   STD_ULOGIC;
      CMO98                            :	out   STD_ULOGIC;
      CMO99                            :	out   STD_ULOGIC;
      CMO100                            :	out   STD_ULOGIC;
      CMO101                            :	out   STD_ULOGIC;
      CMO102                            :	out   STD_ULOGIC;
      CMO103                            :	out   STD_ULOGIC;
      CMO104                            :	out   STD_ULOGIC;
      CMO105                            :	out   STD_ULOGIC;
      CMO106                            :	out   STD_ULOGIC;
      CMO107                            :	out   STD_ULOGIC;
      CMO108                            :	out   STD_ULOGIC;
      CMO109                            :	out   STD_ULOGIC;
      CMO110                            :	out   STD_ULOGIC;
      CMO111                            :	out   STD_ULOGIC;
      CMO112                            :	out   STD_ULOGIC;
      CMO113                            :	out   STD_ULOGIC;
      CMO114                            :	out   STD_ULOGIC;
      CMO115                            :	out   STD_ULOGIC;
      CMO116                            :	out   STD_ULOGIC;
      CMO117                            :	out   STD_ULOGIC;
      CMO118                            :	out   STD_ULOGIC;
      CMO119                            :	out   STD_ULOGIC;
      CMO120                            :	out   STD_ULOGIC;
      CMO121                            :	out   STD_ULOGIC;
      CMO122                            :	out   STD_ULOGIC;
      CMO123                            :	out   STD_ULOGIC;
      CMO124                            :	out   STD_ULOGIC;
      CMO125                            :	out   STD_ULOGIC;
      CMO126                            :	out   STD_ULOGIC;
      CMO127                            :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of CAM128X48CM : entity is FALSE;
end CAM128X48CM;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CAM128X48CM is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_CAMCM_16K

	generic (
		ADDR_WIDTH    : integer :=  7;
		DATA_WIDTH    : integer := 48;
                MEM_INIT_FLAG : integer :=  0;  
	        MEM_INIT_FILE : string  := ""
		);
	port (
		CE        :  in  STD_LOGIC ;
		WE        :  in  STD_LOGIC ;
		CLK       :  in  STD_LOGIC ;
		EN_MASK   :  in  STD_LOGIC ;
		WR_MASK   :  in  STD_LOGIC ;
		WR_DC     :  in  STD_LOGIC ;
		RST       :  in  STD_LOGIC ;
		CS        :  in  STD_LOGIC_VECTOR ( 1 downto 0) ;
		WAD       :  in  STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0);
		WD        :  in  STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0);
                CMI       :  in  STD_LOGIC_VECTOR ( 2**ADDR_WIDTH -1 downto 0);
                CMO       : out  STD_LOGIC_VECTOR ( 2**ADDR_WIDTH -1 downto 0)
		);

	end component ;


      signal CE_ipd        : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal CLK_ipd       : std_ulogic := 'X';
      signal EN_MASK_ipd   : std_ulogic := 'X';
      signal WR_MASK_ipd   : std_ulogic := 'X';
      signal WR_DC_ipd     : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal CS0_ipd       : std_ulogic := 'X';
      signal CS1_ipd       : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';

      signal WD0_ipd       : std_ulogic := 'X';
      signal WD1_ipd       : std_ulogic := 'X';
      signal WD2_ipd       : std_ulogic := 'X';
      signal WD3_ipd       : std_ulogic := 'X';
      signal WD4_ipd       : std_ulogic := 'X';
      signal WD5_ipd       : std_ulogic := 'X';
      signal WD6_ipd       : std_ulogic := 'X';
      signal WD7_ipd       : std_ulogic := 'X';
      signal WD8_ipd       : std_ulogic := 'X';
      signal WD9_ipd       : std_ulogic := 'X';
      signal WD10_ipd       : std_ulogic := 'X';
      signal WD11_ipd       : std_ulogic := 'X';
      signal WD12_ipd       : std_ulogic := 'X';
      signal WD13_ipd       : std_ulogic := 'X';
      signal WD14_ipd       : std_ulogic := 'X';
      signal WD15_ipd       : std_ulogic := 'X';
      signal WD16_ipd       : std_ulogic := 'X';
      signal WD17_ipd       : std_ulogic := 'X';
      signal WD18_ipd       : std_ulogic := 'X';
      signal WD19_ipd       : std_ulogic := 'X';
      signal WD20_ipd       : std_ulogic := 'X';
      signal WD21_ipd       : std_ulogic := 'X';
      signal WD22_ipd       : std_ulogic := 'X';
      signal WD23_ipd       : std_ulogic := 'X';
      signal WD24_ipd       : std_ulogic := 'X';
      signal WD25_ipd       : std_ulogic := 'X';
      signal WD26_ipd       : std_ulogic := 'X';
      signal WD27_ipd       : std_ulogic := 'X';
      signal WD28_ipd       : std_ulogic := 'X';
      signal WD29_ipd       : std_ulogic := 'X';
      signal WD30_ipd       : std_ulogic := 'X';
      signal WD31_ipd       : std_ulogic := 'X';
      signal WD32_ipd       : std_ulogic := 'X';
      signal WD33_ipd       : std_ulogic := 'X';
      signal WD34_ipd       : std_ulogic := 'X';
      signal WD35_ipd       : std_ulogic := 'X';
      signal WD36_ipd       : std_ulogic := 'X';
      signal WD37_ipd       : std_ulogic := 'X';
      signal WD38_ipd       : std_ulogic := 'X';
      signal WD39_ipd       : std_ulogic := 'X';
      signal WD40_ipd       : std_ulogic := 'X';
      signal WD41_ipd       : std_ulogic := 'X';
      signal WD42_ipd       : std_ulogic := 'X';
      signal WD43_ipd       : std_ulogic := 'X';
      signal WD44_ipd       : std_ulogic := 'X';
      signal WD45_ipd       : std_ulogic := 'X';
      signal WD46_ipd       : std_ulogic := 'X';
      signal WD47_ipd       : std_ulogic := 'X';
      signal CMI0_ipd       : std_ulogic := 'X';
      signal CMI1_ipd       : std_ulogic := 'X';
      signal CMI2_ipd       : std_ulogic := 'X';
      signal CMI3_ipd       : std_ulogic := 'X';
      signal CMI4_ipd       : std_ulogic := 'X';
      signal CMI5_ipd       : std_ulogic := 'X';
      signal CMI6_ipd       : std_ulogic := 'X';
      signal CMI7_ipd       : std_ulogic := 'X';
      signal CMI8_ipd       : std_ulogic := 'X';
      signal CMI9_ipd       : std_ulogic := 'X';
      signal CMI10_ipd       : std_ulogic := 'X';
      signal CMI11_ipd       : std_ulogic := 'X';
      signal CMI12_ipd       : std_ulogic := 'X';
      signal CMI13_ipd       : std_ulogic := 'X';
      signal CMI14_ipd       : std_ulogic := 'X';
      signal CMI15_ipd       : std_ulogic := 'X';
      signal CMI16_ipd       : std_ulogic := 'X';
      signal CMI17_ipd       : std_ulogic := 'X';
      signal CMI18_ipd       : std_ulogic := 'X';
      signal CMI19_ipd       : std_ulogic := 'X';
      signal CMI20_ipd       : std_ulogic := 'X';
      signal CMI21_ipd       : std_ulogic := 'X';
      signal CMI22_ipd       : std_ulogic := 'X';
      signal CMI23_ipd       : std_ulogic := 'X';
      signal CMI24_ipd       : std_ulogic := 'X';
      signal CMI25_ipd       : std_ulogic := 'X';
      signal CMI26_ipd       : std_ulogic := 'X';
      signal CMI27_ipd       : std_ulogic := 'X';
      signal CMI28_ipd       : std_ulogic := 'X';
      signal CMI29_ipd       : std_ulogic := 'X';
      signal CMI30_ipd       : std_ulogic := 'X';
      signal CMI31_ipd       : std_ulogic := 'X';
      signal CMI32_ipd       : std_ulogic := 'X';
      signal CMI33_ipd       : std_ulogic := 'X';
      signal CMI34_ipd       : std_ulogic := 'X';
      signal CMI35_ipd       : std_ulogic := 'X';
      signal CMI36_ipd       : std_ulogic := 'X';
      signal CMI37_ipd       : std_ulogic := 'X';
      signal CMI38_ipd       : std_ulogic := 'X';
      signal CMI39_ipd       : std_ulogic := 'X';
      signal CMI40_ipd       : std_ulogic := 'X';
      signal CMI41_ipd       : std_ulogic := 'X';
      signal CMI42_ipd       : std_ulogic := 'X';
      signal CMI43_ipd       : std_ulogic := 'X';
      signal CMI44_ipd       : std_ulogic := 'X';
      signal CMI45_ipd       : std_ulogic := 'X';
      signal CMI46_ipd       : std_ulogic := 'X';
      signal CMI47_ipd       : std_ulogic := 'X';
      signal CMI48_ipd       : std_ulogic := 'X';
      signal CMI49_ipd       : std_ulogic := 'X';
      signal CMI50_ipd       : std_ulogic := 'X';
      signal CMI51_ipd       : std_ulogic := 'X';
      signal CMI52_ipd       : std_ulogic := 'X';
      signal CMI53_ipd       : std_ulogic := 'X';
      signal CMI54_ipd       : std_ulogic := 'X';
      signal CMI55_ipd       : std_ulogic := 'X';
      signal CMI56_ipd       : std_ulogic := 'X';
      signal CMI57_ipd       : std_ulogic := 'X';
      signal CMI58_ipd       : std_ulogic := 'X';
      signal CMI59_ipd       : std_ulogic := 'X';
      signal CMI60_ipd       : std_ulogic := 'X';
      signal CMI61_ipd       : std_ulogic := 'X';
      signal CMI62_ipd       : std_ulogic := 'X';
      signal CMI63_ipd       : std_ulogic := 'X';
      signal CMI64_ipd       : std_ulogic := 'X';
      signal CMI65_ipd       : std_ulogic := 'X';
      signal CMI66_ipd       : std_ulogic := 'X';
      signal CMI67_ipd       : std_ulogic := 'X';
      signal CMI68_ipd       : std_ulogic := 'X';
      signal CMI69_ipd       : std_ulogic := 'X';
      signal CMI70_ipd       : std_ulogic := 'X';
      signal CMI71_ipd       : std_ulogic := 'X';
      signal CMI72_ipd       : std_ulogic := 'X';
      signal CMI73_ipd       : std_ulogic := 'X';
      signal CMI74_ipd       : std_ulogic := 'X';
      signal CMI75_ipd       : std_ulogic := 'X';
      signal CMI76_ipd       : std_ulogic := 'X';
      signal CMI77_ipd       : std_ulogic := 'X';
      signal CMI78_ipd       : std_ulogic := 'X';
      signal CMI79_ipd       : std_ulogic := 'X';
      signal CMI80_ipd       : std_ulogic := 'X';
      signal CMI81_ipd       : std_ulogic := 'X';
      signal CMI82_ipd       : std_ulogic := 'X';
      signal CMI83_ipd       : std_ulogic := 'X';
      signal CMI84_ipd       : std_ulogic := 'X';
      signal CMI85_ipd       : std_ulogic := 'X';
      signal CMI86_ipd       : std_ulogic := 'X';
      signal CMI87_ipd       : std_ulogic := 'X';
      signal CMI88_ipd       : std_ulogic := 'X';
      signal CMI89_ipd       : std_ulogic := 'X';
      signal CMI90_ipd       : std_ulogic := 'X';
      signal CMI91_ipd       : std_ulogic := 'X';
      signal CMI92_ipd       : std_ulogic := 'X';
      signal CMI93_ipd       : std_ulogic := 'X';
      signal CMI94_ipd       : std_ulogic := 'X';
      signal CMI95_ipd       : std_ulogic := 'X';
      signal CMI96_ipd       : std_ulogic := 'X';
      signal CMI97_ipd       : std_ulogic := 'X';
      signal CMI98_ipd       : std_ulogic := 'X';
      signal CMI99_ipd       : std_ulogic := 'X';
      signal CMI100_ipd       : std_ulogic := 'X';
      signal CMI101_ipd       : std_ulogic := 'X';
      signal CMI102_ipd       : std_ulogic := 'X';
      signal CMI103_ipd       : std_ulogic := 'X';
      signal CMI104_ipd       : std_ulogic := 'X';
      signal CMI105_ipd       : std_ulogic := 'X';
      signal CMI106_ipd       : std_ulogic := 'X';
      signal CMI107_ipd       : std_ulogic := 'X';
      signal CMI108_ipd       : std_ulogic := 'X';
      signal CMI109_ipd       : std_ulogic := 'X';
      signal CMI110_ipd       : std_ulogic := 'X';
      signal CMI111_ipd       : std_ulogic := 'X';
      signal CMI112_ipd       : std_ulogic := 'X';
      signal CMI113_ipd       : std_ulogic := 'X';
      signal CMI114_ipd       : std_ulogic := 'X';
      signal CMI115_ipd       : std_ulogic := 'X';
      signal CMI116_ipd       : std_ulogic := 'X';
      signal CMI117_ipd       : std_ulogic := 'X';
      signal CMI118_ipd       : std_ulogic := 'X';
      signal CMI119_ipd       : std_ulogic := 'X';
      signal CMI120_ipd       : std_ulogic := 'X';
      signal CMI121_ipd       : std_ulogic := 'X';
      signal CMI122_ipd       : std_ulogic := 'X';
      signal CMI123_ipd       : std_ulogic := 'X';
      signal CMI124_ipd       : std_ulogic := 'X';
      signal CMI125_ipd       : std_ulogic := 'X';
      signal CMI126_ipd       : std_ulogic := 'X';
      signal CMI127_ipd       : std_ulogic := 'X';

      signal CS             : std_logic_vector (1 downto 0);
      signal WAD             : std_logic_vector (6 downto 0);
      signal WD             : std_logic_vector (47 downto 0);
      signal CMI             : std_logic_vector (127 downto 0);
      signal CMO             : std_logic_vector (127 downto 0);
      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);


begin 

      CS  <= CS1_ipd & CS0_ipd;
      WAD <= WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
      WD  <= WD47_ipd & WD46_ipd & WD45_ipd & WD44_ipd & WD43_ipd & WD42_ipd & WD41_ipd & WD40_ipd & WD39_ipd & WD38_ipd & WD37_ipd & WD36_ipd & WD35_ipd & WD34_ipd & WD33_ipd & WD32_ipd & WD31_ipd & WD30_ipd & WD29_ipd & WD28_ipd & WD27_ipd & WD26_ipd & WD25_ipd & WD24_ipd & WD23_ipd & WD22_ipd & WD21_ipd & WD20_ipd & WD19_ipd & WD18_ipd & WD17_ipd & WD16_ipd & WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
      CMI <= CMI127_ipd & CMI126_ipd & CMI125_ipd & CMI124_ipd & CMI123_ipd & CMI122_ipd & CMI121_ipd & CMI120_ipd & CMI119_ipd & CMI118_ipd & CMI117_ipd & CMI116_ipd & CMI115_ipd & CMI114_ipd & CMI113_ipd & CMI112_ipd & CMI111_ipd & CMI110_ipd & CMI109_ipd & CMI108_ipd & CMI107_ipd & CMI106_ipd & CMI105_ipd & CMI104_ipd & CMI103_ipd & CMI102_ipd & CMI101_ipd & CMI100_ipd & CMI99_ipd & CMI98_ipd & CMI97_ipd & CMI96_ipd & CMI95_ipd & CMI94_ipd & CMI93_ipd & CMI92_ipd & CMI91_ipd & CMI90_ipd & CMI89_ipd & CMI88_ipd & CMI87_ipd & CMI86_ipd & CMI85_ipd & CMI84_ipd & CMI83_ipd & CMI82_ipd & CMI81_ipd & CMI80_ipd & CMI79_ipd & CMI78_ipd & CMI77_ipd & CMI76_ipd & CMI75_ipd & CMI74_ipd & CMI73_ipd & CMI72_ipd & CMI71_ipd & CMI70_ipd & CMI69_ipd & CMI68_ipd & CMI67_ipd & CMI66_ipd & CMI65_ipd & CMI64_ipd & CMI63_ipd & CMI62_ipd & CMI61_ipd & CMI60_ipd & CMI59_ipd & CMI58_ipd & CMI57_ipd & CMI56_ipd & CMI55_ipd & CMI54_ipd & CMI53_ipd & CMI52_ipd & CMI51_ipd & CMI50_ipd & CMI49_ipd & CMI48_ipd & CMI47_ipd & CMI46_ipd & CMI45_ipd & CMI44_ipd & CMI43_ipd & CMI42_ipd & CMI41_ipd & CMI40_ipd & CMI39_ipd & CMI38_ipd & CMI37_ipd & CMI36_ipd & CMI35_ipd & CMI34_ipd & CMI33_ipd & CMI32_ipd & CMI31_ipd & CMI30_ipd & CMI29_ipd & CMI28_ipd & CMI27_ipd & CMI26_ipd & CMI25_ipd & CMI24_ipd & CMI23_ipd & CMI22_ipd & CMI21_ipd & CMI20_ipd & CMI19_ipd & CMI18_ipd & CMI17_ipd & CMI16_ipd & CMI15_ipd & CMI14_ipd & CMI13_ipd & CMI12_ipd & CMI11_ipd & CMI10_ipd & CMI9_ipd & CMI8_ipd & CMI7_ipd & CMI6_ipd & CMI5_ipd & CMI4_ipd & CMI3_ipd & CMI2_ipd & CMI1_ipd & CMI0_ipd;


	CMO0 <= CMO(0);
	CMO1 <= CMO(1);
	CMO2 <= CMO(2);
	CMO3 <= CMO(3);
	CMO4 <= CMO(4);
	CMO5 <= CMO(5);
	CMO6 <= CMO(6);
	CMO7 <= CMO(7);
	CMO8 <= CMO(8);
	CMO9 <= CMO(9);
	CMO10 <= CMO(10);
	CMO11 <= CMO(11);
	CMO12 <= CMO(12);
	CMO13 <= CMO(13);
	CMO14 <= CMO(14);
	CMO15 <= CMO(15);
	CMO16 <= CMO(16);
	CMO17 <= CMO(17);
	CMO18 <= CMO(18);
	CMO19 <= CMO(19);
	CMO20 <= CMO(20);
	CMO21 <= CMO(21);
	CMO22 <= CMO(22);
	CMO23 <= CMO(23);
	CMO24 <= CMO(24);
	CMO25 <= CMO(25);
	CMO26 <= CMO(26);
	CMO27 <= CMO(27);
	CMO28 <= CMO(28);
	CMO29 <= CMO(29);
	CMO30 <= CMO(30);
	CMO31 <= CMO(31);
	CMO32 <= CMO(32);
	CMO33 <= CMO(33);
	CMO34 <= CMO(34);
	CMO35 <= CMO(35);
	CMO36 <= CMO(36);
	CMO37 <= CMO(37);
	CMO38 <= CMO(38);
	CMO39 <= CMO(39);
	CMO40 <= CMO(40);
	CMO41 <= CMO(41);
	CMO42 <= CMO(42);
	CMO43 <= CMO(43);
	CMO44 <= CMO(44);
	CMO45 <= CMO(45);
	CMO46 <= CMO(46);
	CMO47 <= CMO(47);
	CMO48 <= CMO(48);
	CMO49 <= CMO(49);
	CMO50 <= CMO(50);
	CMO51 <= CMO(51);
	CMO52 <= CMO(52);
	CMO53 <= CMO(53);
	CMO54 <= CMO(54);
	CMO55 <= CMO(55);
	CMO56 <= CMO(56);
	CMO57 <= CMO(57);
	CMO58 <= CMO(58);
	CMO59 <= CMO(59);
	CMO60 <= CMO(60);
	CMO61 <= CMO(61);
	CMO62 <= CMO(62);
	CMO63 <= CMO(63);
	CMO64 <= CMO(64);
	CMO65 <= CMO(65);
	CMO66 <= CMO(66);
	CMO67 <= CMO(67);
	CMO68 <= CMO(68);
	CMO69 <= CMO(69);
	CMO70 <= CMO(70);
	CMO71 <= CMO(71);
	CMO72 <= CMO(72);
	CMO73 <= CMO(73);
	CMO74 <= CMO(74);
	CMO75 <= CMO(75);
	CMO76 <= CMO(76);
	CMO77 <= CMO(77);
	CMO78 <= CMO(78);
	CMO79 <= CMO(79);
	CMO80 <= CMO(80);
	CMO81 <= CMO(81);
	CMO82 <= CMO(82);
	CMO83 <= CMO(83);
	CMO84 <= CMO(84);
	CMO85 <= CMO(85);
	CMO86 <= CMO(86);
	CMO87 <= CMO(87);
	CMO88 <= CMO(88);
	CMO89 <= CMO(89);
	CMO90 <= CMO(90);
	CMO91 <= CMO(91);
	CMO92 <= CMO(92);
	CMO93 <= CMO(93);
	CMO94 <= CMO(94);
	CMO95 <= CMO(95);
	CMO96 <= CMO(96);
	CMO97 <= CMO(97);
	CMO98 <= CMO(98);
	CMO99 <= CMO(99);
	CMO100 <= CMO(100);
	CMO101 <= CMO(101);
	CMO102 <= CMO(102);
	CMO103 <= CMO(103);
	CMO104 <= CMO(104);
	CMO105 <= CMO(105);
	CMO106 <= CMO(106);
	CMO107 <= CMO(107);
	CMO108 <= CMO(108);
	CMO109 <= CMO(109);
	CMO110 <= CMO(110);
	CMO111 <= CMO(111);
	CMO112 <= CMO(112);
	CMO113 <= CMO(113);
	CMO114 <= CMO(114);
	CMO115 <= CMO(115);
	CMO116 <= CMO(116);
	CMO117 <= CMO(117);
	CMO118 <= CMO(118);
	CMO119 <= CMO(119);
	CMO120 <= CMO(120);
	CMO121 <= CMO(121);
	CMO122 <= CMO(122);
	CMO123 <= CMO(123);
	CMO124 <= CMO(124);
	CMO125 <= CMO(125);
	CMO126 <= CMO(126);
	CMO127 <= CMO(127);


  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CE_ipd, CE, tipd_CE);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (CLK_ipd, CLK, tipd_CLK);

        VitalWireDelay (EN_MASK_ipd, EN_MASK, tipd_EN_MASK);
        VitalWireDelay (WR_MASK_ipd, WR_MASK, tipd_WR_MASK);

        VitalWireDelay (WR_DC_ipd, WR_DC, tipd_WR_DC);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (CS0_ipd, CS0, tipd_CS0);
        VitalWireDelay (CS1_ipd, CS1, tipd_CS1);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);
        VitalWireDelay (WD16_ipd, WD16, tipd_WD16);
        VitalWireDelay (WD17_ipd, WD17, tipd_WD17);
        VitalWireDelay (WD18_ipd, WD18, tipd_WD18);
        VitalWireDelay (WD19_ipd, WD19, tipd_WD19);
        VitalWireDelay (WD20_ipd, WD20, tipd_WD20);
        VitalWireDelay (WD21_ipd, WD21, tipd_WD21);
        VitalWireDelay (WD22_ipd, WD22, tipd_WD22);
        VitalWireDelay (WD23_ipd, WD23, tipd_WD23);
        VitalWireDelay (WD24_ipd, WD24, tipd_WD24);
        VitalWireDelay (WD25_ipd, WD25, tipd_WD25);
        VitalWireDelay (WD26_ipd, WD26, tipd_WD26);
        VitalWireDelay (WD27_ipd, WD27, tipd_WD27);
        VitalWireDelay (WD28_ipd, WD28, tipd_WD28);
        VitalWireDelay (WD29_ipd, WD29, tipd_WD29);
        VitalWireDelay (WD30_ipd, WD30, tipd_WD30);
        VitalWireDelay (WD31_ipd, WD31, tipd_WD31);
        VitalWireDelay (WD32_ipd, WD32, tipd_WD32);
        VitalWireDelay (WD33_ipd, WD33, tipd_WD33);
        VitalWireDelay (WD34_ipd, WD34, tipd_WD34);
        VitalWireDelay (WD35_ipd, WD35, tipd_WD35);
        VitalWireDelay (WD36_ipd, WD36, tipd_WD36);
        VitalWireDelay (WD37_ipd, WD37, tipd_WD37);
        VitalWireDelay (WD38_ipd, WD38, tipd_WD38);
        VitalWireDelay (WD39_ipd, WD39, tipd_WD39);
        VitalWireDelay (WD40_ipd, WD40, tipd_WD40);
        VitalWireDelay (WD41_ipd, WD41, tipd_WD41);
        VitalWireDelay (WD42_ipd, WD42, tipd_WD42);
        VitalWireDelay (WD43_ipd, WD43, tipd_WD43);
        VitalWireDelay (WD44_ipd, WD44, tipd_WD44);
        VitalWireDelay (WD45_ipd, WD45, tipd_WD45);
        VitalWireDelay (WD46_ipd, WD46, tipd_WD46);
        VitalWireDelay (WD47_ipd, WD47, tipd_WD47);
        VitalWireDelay (CMI0_ipd, CMI0, tipd_CMI0);
        VitalWireDelay (CMI1_ipd, CMI1, tipd_CMI1);
        VitalWireDelay (CMI2_ipd, CMI2, tipd_CMI2);
        VitalWireDelay (CMI3_ipd, CMI3, tipd_CMI3);
        VitalWireDelay (CMI4_ipd, CMI4, tipd_CMI4);
        VitalWireDelay (CMI5_ipd, CMI5, tipd_CMI5);
        VitalWireDelay (CMI6_ipd, CMI6, tipd_CMI6);
        VitalWireDelay (CMI7_ipd, CMI7, tipd_CMI7);
        VitalWireDelay (CMI8_ipd, CMI8, tipd_CMI8);
        VitalWireDelay (CMI9_ipd, CMI9, tipd_CMI9);
        VitalWireDelay (CMI10_ipd, CMI10, tipd_CMI10);
        VitalWireDelay (CMI11_ipd, CMI11, tipd_CMI11);
        VitalWireDelay (CMI12_ipd, CMI12, tipd_CMI12);
        VitalWireDelay (CMI13_ipd, CMI13, tipd_CMI13);
        VitalWireDelay (CMI14_ipd, CMI14, tipd_CMI14);
        VitalWireDelay (CMI15_ipd, CMI15, tipd_CMI15);
        VitalWireDelay (CMI16_ipd, CMI16, tipd_CMI16);
        VitalWireDelay (CMI17_ipd, CMI17, tipd_CMI17);
        VitalWireDelay (CMI18_ipd, CMI18, tipd_CMI18);
        VitalWireDelay (CMI19_ipd, CMI19, tipd_CMI19);
        VitalWireDelay (CMI20_ipd, CMI20, tipd_CMI20);
        VitalWireDelay (CMI21_ipd, CMI21, tipd_CMI21);
        VitalWireDelay (CMI22_ipd, CMI22, tipd_CMI22);
        VitalWireDelay (CMI23_ipd, CMI23, tipd_CMI23);
        VitalWireDelay (CMI24_ipd, CMI24, tipd_CMI24);
        VitalWireDelay (CMI25_ipd, CMI25, tipd_CMI25);
        VitalWireDelay (CMI26_ipd, CMI26, tipd_CMI26);
        VitalWireDelay (CMI27_ipd, CMI27, tipd_CMI27);
        VitalWireDelay (CMI28_ipd, CMI28, tipd_CMI28);
        VitalWireDelay (CMI29_ipd, CMI29, tipd_CMI29);
        VitalWireDelay (CMI30_ipd, CMI30, tipd_CMI30);
        VitalWireDelay (CMI31_ipd, CMI31, tipd_CMI31);
        VitalWireDelay (CMI32_ipd, CMI32, tipd_CMI32);
        VitalWireDelay (CMI33_ipd, CMI33, tipd_CMI33);
        VitalWireDelay (CMI34_ipd, CMI34, tipd_CMI34);
        VitalWireDelay (CMI35_ipd, CMI35, tipd_CMI35);
        VitalWireDelay (CMI36_ipd, CMI36, tipd_CMI36);
        VitalWireDelay (CMI37_ipd, CMI37, tipd_CMI37);
        VitalWireDelay (CMI38_ipd, CMI38, tipd_CMI38);
        VitalWireDelay (CMI39_ipd, CMI39, tipd_CMI39);
        VitalWireDelay (CMI40_ipd, CMI40, tipd_CMI40);
        VitalWireDelay (CMI41_ipd, CMI41, tipd_CMI41);
        VitalWireDelay (CMI42_ipd, CMI42, tipd_CMI42);
        VitalWireDelay (CMI43_ipd, CMI43, tipd_CMI43);
        VitalWireDelay (CMI44_ipd, CMI44, tipd_CMI44);
        VitalWireDelay (CMI45_ipd, CMI45, tipd_CMI45);
        VitalWireDelay (CMI46_ipd, CMI46, tipd_CMI46);
        VitalWireDelay (CMI47_ipd, CMI47, tipd_CMI47);
        VitalWireDelay (CMI48_ipd, CMI48, tipd_CMI48);
        VitalWireDelay (CMI49_ipd, CMI49, tipd_CMI49);
        VitalWireDelay (CMI50_ipd, CMI50, tipd_CMI50);
        VitalWireDelay (CMI51_ipd, CMI51, tipd_CMI51);
        VitalWireDelay (CMI52_ipd, CMI52, tipd_CMI52);
        VitalWireDelay (CMI53_ipd, CMI53, tipd_CMI53);
        VitalWireDelay (CMI54_ipd, CMI54, tipd_CMI54);
        VitalWireDelay (CMI55_ipd, CMI55, tipd_CMI55);
        VitalWireDelay (CMI56_ipd, CMI56, tipd_CMI56);
        VitalWireDelay (CMI57_ipd, CMI57, tipd_CMI57);
        VitalWireDelay (CMI58_ipd, CMI58, tipd_CMI58);
        VitalWireDelay (CMI59_ipd, CMI59, tipd_CMI59);
        VitalWireDelay (CMI60_ipd, CMI60, tipd_CMI60);
        VitalWireDelay (CMI61_ipd, CMI61, tipd_CMI61);
        VitalWireDelay (CMI62_ipd, CMI62, tipd_CMI62);
        VitalWireDelay (CMI63_ipd, CMI63, tipd_CMI63);
        VitalWireDelay (CMI64_ipd, CMI64, tipd_CMI64);
        VitalWireDelay (CMI65_ipd, CMI65, tipd_CMI65);
        VitalWireDelay (CMI66_ipd, CMI66, tipd_CMI66);
        VitalWireDelay (CMI67_ipd, CMI67, tipd_CMI67);
        VitalWireDelay (CMI68_ipd, CMI68, tipd_CMI68);
        VitalWireDelay (CMI69_ipd, CMI69, tipd_CMI69);
        VitalWireDelay (CMI70_ipd, CMI70, tipd_CMI70);
        VitalWireDelay (CMI71_ipd, CMI71, tipd_CMI71);
        VitalWireDelay (CMI72_ipd, CMI72, tipd_CMI72);
        VitalWireDelay (CMI73_ipd, CMI73, tipd_CMI73);
        VitalWireDelay (CMI74_ipd, CMI74, tipd_CMI74);
        VitalWireDelay (CMI75_ipd, CMI75, tipd_CMI75);
        VitalWireDelay (CMI76_ipd, CMI76, tipd_CMI76);
        VitalWireDelay (CMI77_ipd, CMI77, tipd_CMI77);
        VitalWireDelay (CMI78_ipd, CMI78, tipd_CMI78);
        VitalWireDelay (CMI79_ipd, CMI79, tipd_CMI79);
        VitalWireDelay (CMI80_ipd, CMI80, tipd_CMI80);
        VitalWireDelay (CMI81_ipd, CMI81, tipd_CMI81);
        VitalWireDelay (CMI82_ipd, CMI82, tipd_CMI82);
        VitalWireDelay (CMI83_ipd, CMI83, tipd_CMI83);
        VitalWireDelay (CMI84_ipd, CMI84, tipd_CMI84);
        VitalWireDelay (CMI85_ipd, CMI85, tipd_CMI85);
        VitalWireDelay (CMI86_ipd, CMI86, tipd_CMI86);
        VitalWireDelay (CMI87_ipd, CMI87, tipd_CMI87);
        VitalWireDelay (CMI88_ipd, CMI88, tipd_CMI88);
        VitalWireDelay (CMI89_ipd, CMI89, tipd_CMI89);
        VitalWireDelay (CMI90_ipd, CMI90, tipd_CMI90);
        VitalWireDelay (CMI91_ipd, CMI91, tipd_CMI91);
        VitalWireDelay (CMI92_ipd, CMI92, tipd_CMI92);
        VitalWireDelay (CMI93_ipd, CMI93, tipd_CMI93);
        VitalWireDelay (CMI94_ipd, CMI94, tipd_CMI94);
        VitalWireDelay (CMI95_ipd, CMI95, tipd_CMI95);
        VitalWireDelay (CMI96_ipd, CMI96, tipd_CMI96);
        VitalWireDelay (CMI97_ipd, CMI97, tipd_CMI97);
        VitalWireDelay (CMI98_ipd, CMI98, tipd_CMI98);
        VitalWireDelay (CMI99_ipd, CMI99, tipd_CMI99);
        VitalWireDelay (CMI100_ipd, CMI100, tipd_CMI100);
        VitalWireDelay (CMI101_ipd, CMI101, tipd_CMI101);
        VitalWireDelay (CMI102_ipd, CMI102, tipd_CMI102);
        VitalWireDelay (CMI103_ipd, CMI103, tipd_CMI103);
        VitalWireDelay (CMI104_ipd, CMI104, tipd_CMI104);
        VitalWireDelay (CMI105_ipd, CMI105, tipd_CMI105);
        VitalWireDelay (CMI106_ipd, CMI106, tipd_CMI106);
        VitalWireDelay (CMI107_ipd, CMI107, tipd_CMI107);
        VitalWireDelay (CMI108_ipd, CMI108, tipd_CMI108);
        VitalWireDelay (CMI109_ipd, CMI109, tipd_CMI109);
        VitalWireDelay (CMI110_ipd, CMI110, tipd_CMI110);
        VitalWireDelay (CMI111_ipd, CMI111, tipd_CMI111);
        VitalWireDelay (CMI112_ipd, CMI112, tipd_CMI112);
        VitalWireDelay (CMI113_ipd, CMI113, tipd_CMI113);
        VitalWireDelay (CMI114_ipd, CMI114, tipd_CMI114);
        VitalWireDelay (CMI115_ipd, CMI115, tipd_CMI115);
        VitalWireDelay (CMI116_ipd, CMI116, tipd_CMI116);
        VitalWireDelay (CMI117_ipd, CMI117, tipd_CMI117);
        VitalWireDelay (CMI118_ipd, CMI118, tipd_CMI118);
        VitalWireDelay (CMI119_ipd, CMI119, tipd_CMI119);
        VitalWireDelay (CMI120_ipd, CMI120, tipd_CMI120);
        VitalWireDelay (CMI121_ipd, CMI121, tipd_CMI121);
        VitalWireDelay (CMI122_ipd, CMI122, tipd_CMI122);
        VitalWireDelay (CMI123_ipd, CMI123, tipd_CMI123);
        VitalWireDelay (CMI124_ipd, CMI124, tipd_CMI124);
        VitalWireDelay (CMI125_ipd, CMI125, tipd_CMI125);
        VitalWireDelay (CMI126_ipd, CMI126, tipd_CMI126);
        VitalWireDelay (CMI127_ipd, CMI127, tipd_CMI127);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CE_CLK_posedge      : std_ulogic  := '0';
        variable Tviol_WE_CLK_posedge      : std_ulogic  := '0';
        variable Tviol_EN_MASK_CLK_posedge      : std_ulogic  := '0';
        variable Tviol_WR_MASK_CLK_posedge      : std_ulogic  := '0';
        variable Tviol_WR_DC_CLK_posedge        : std_ulogic  := '0';
        variable Tviol_CS0_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_CS1_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WAD0_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD1_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD2_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD3_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD4_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD5_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD6_CLK_posedge         : std_ulogic  := '0';

        variable Tviol_WD0_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD1_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD2_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD3_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD4_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD5_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD6_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD7_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD8_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD9_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD10_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD11_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD12_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD13_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD14_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD15_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD16_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD17_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD18_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD19_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD20_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD21_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD22_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD23_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD24_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD25_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD26_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD27_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD28_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD29_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD30_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD31_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD32_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD33_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD34_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD35_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD36_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD37_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD38_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD39_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD40_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD41_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD42_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD43_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD44_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD45_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD46_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD47_CLK_posedge          : std_ulogic  := '0';

        variable Tviol_RST_CLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_CE_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WE_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EN_MASK_CLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_MASK_CLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_DC_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS0_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS1_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD0_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD16_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD17_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD18_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD19_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD20_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD21_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD22_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD23_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD24_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD25_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD26_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD27_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD28_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD29_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD30_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD31_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD32_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD33_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD34_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD35_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD36_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD37_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD38_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD39_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD40_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD41_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD42_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD43_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD44_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD45_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD46_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD47_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_CLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLK        : std_ulogic := '0';
        variable PInfo_CLK        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable CO0_zd          : std_ulogic := 'X';
        variable CO1_zd          : std_ulogic := 'X';
        variable CO2_zd          : std_ulogic := 'X';
        variable CO3_zd          : std_ulogic := 'X';
        variable CO4_zd          : std_ulogic := 'X';
        variable CO5_zd          : std_ulogic := 'X';
        variable CO6_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_posedge,
          TimingData              => Tmkr_CE_CLK_posedge,
          TestSignal              => CE_ipd,
          TestSignalName          => "CE",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE_CLK_noedge_posedge,
          SetupLow                => tsetup_CE_CLK_noedge_posedge,
          HoldLow                 => thold_CE_CLK_noedge_posedge,
          HoldHigh                => thold_CE_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_CLK_posedge,
          TimingData              => Tmkr_WE_CLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_CLK_noedge_posedge,
          SetupLow                => tsetup_WE_CLK_noedge_posedge,
          HoldLow                 => thold_WE_CLK_noedge_posedge,
          HoldHigh                => thold_WE_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_MASK_CLK_posedge,
          TimingData              => Tmkr_WR_MASK_CLK_posedge,
          TestSignal              => WR_MASK_ipd,
          TestSignalName          => "WR_MASK",
          TestDelay               => 0 ns,
          RefSignal               => CLk_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_MASK_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_MASK_CLK_noedge_posedge,
          HoldLow                 => thold_WR_MASK_CLK_noedge_posedge,
          HoldHigh                => thold_WR_MASK_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_DC_CLK_posedge,
          TimingData              => Tmkr_WR_DC_CLK_posedge,
          TestSignal              => WR_DC_ipd,
          TestSignalName          => "WR_RC",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_DC_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_DC_CLK_noedge_posedge,
          HoldLow                 => thold_WR_DC_CLK_noedge_posedge,
          HoldHigh                => thold_WR_DC_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS0_CLK_posedge,
          TimingData              => Tmkr_CS0_CLK_posedge,
          TestSignal              => CS0_ipd,
          TestSignalName          => "CS0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS0_CLK_noedge_posedge,
          SetupLow                => tsetup_CS0_CLK_noedge_posedge,
          HoldLow                 => thold_CS0_CLK_noedge_posedge,
          HoldHigh                => thold_CS0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS1_CLK_posedge,
          TimingData              => Tmkr_CS1_CLK_posedge,
          TestSignal              => CS1_ipd,
          TestSignalName          => "CS1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS1_CLK_noedge_posedge,
          SetupLow                => tsetup_CS1_CLK_noedge_posedge,
          HoldLow                 => thold_CS1_CLK_noedge_posedge,
          HoldHigh                => thold_CS1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EN_MASK_CLK_posedge,
          TimingData              => Tmkr_EN_MASK_CLK_posedge,
          TestSignal              => EN_MASK_ipd,
          TestSignalName          => "EN_MASK",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EN_MASK_CLK_noedge_posedge,
          SetupLow                => tsetup_EN_MASK_CLK_noedge_posedge,
          HoldLow                 => thold_EN_MASK_CLK_noedge_posedge,
          HoldHigh                => thold_EN_MASK_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_CLK_posedge,
          TimingData              => Tmkr_WAD0_CLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_CLK_noedge_posedge,
          HoldLow                 => thold_WAD0_CLK_noedge_posedge,
          HoldHigh                => thold_WAD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_CLK_posedge,
          TimingData              => Tmkr_WAD1_CLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_CLK_noedge_posedge,
          HoldLow                 => thold_WAD1_CLK_noedge_posedge,
          HoldHigh                => thold_WAD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_CLK_posedge,
          TimingData              => Tmkr_WAD2_CLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_CLK_noedge_posedge,
          HoldLow                 => thold_WAD2_CLK_noedge_posedge,
          HoldHigh                => thold_WAD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_CLK_posedge,
          TimingData              => Tmkr_WAD3_CLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_CLK_noedge_posedge,
          HoldLow                 => thold_WAD3_CLK_noedge_posedge,
          HoldHigh                => thold_WAD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_CLK_posedge,
          TimingData              => Tmkr_WAD4_CLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_CLK_noedge_posedge,
          HoldLow                 => thold_WAD4_CLK_noedge_posedge,
          HoldHigh                => thold_WAD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_CLK_posedge,
          TimingData              => Tmkr_WAD5_CLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_CLK_noedge_posedge,
          HoldLow                 => thold_WAD5_CLK_noedge_posedge,
          HoldHigh                => thold_WAD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_CLK_posedge,
          TimingData              => Tmkr_WAD6_CLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_CLK_noedge_posedge,
          HoldLow                 => thold_WAD6_CLK_noedge_posedge,
          HoldHigh                => thold_WAD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_CLK_posedge,
          TimingData              => Tmkr_WD0_CLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_CLK_noedge_posedge,
          SetupLow                => tsetup_WD0_CLK_noedge_posedge,
          HoldLow                 => thold_WD0_CLK_noedge_posedge,
          HoldHigh                => thold_WD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_CLK_posedge,
          TimingData              => Tmkr_WD1_CLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_CLK_noedge_posedge,
          SetupLow                => tsetup_WD1_CLK_noedge_posedge,
          HoldLow                 => thold_WD1_CLK_noedge_posedge,
          HoldHigh                => thold_WD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_CLK_posedge,
          TimingData              => Tmkr_WD2_CLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_CLK_noedge_posedge,
          SetupLow                => tsetup_WD2_CLK_noedge_posedge,
          HoldLow                 => thold_WD2_CLK_noedge_posedge,
          HoldHigh                => thold_WD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_CLK_posedge,
          TimingData              => Tmkr_WD3_CLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_CLK_noedge_posedge,
          SetupLow                => tsetup_WD3_CLK_noedge_posedge,
          HoldLow                 => thold_WD3_CLK_noedge_posedge,
          HoldHigh                => thold_WD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_CLK_posedge,
          TimingData              => Tmkr_WD4_CLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_CLK_noedge_posedge,
          SetupLow                => tsetup_WD4_CLK_noedge_posedge,
          HoldLow                 => thold_WD4_CLK_noedge_posedge,
          HoldHigh                => thold_WD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_CLK_posedge,
          TimingData              => Tmkr_WD5_CLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_CLK_noedge_posedge,
          SetupLow                => tsetup_WD5_CLK_noedge_posedge,
          HoldLow                 => thold_WD5_CLK_noedge_posedge,
          HoldHigh                => thold_WD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_CLK_posedge,
          TimingData              => Tmkr_WD6_CLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_CLK_noedge_posedge,
          SetupLow                => tsetup_WD6_CLK_noedge_posedge,
          HoldLow                 => thold_WD6_CLK_noedge_posedge,
          HoldHigh                => thold_WD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_CLK_posedge,
          TimingData              => Tmkr_WD7_CLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_CLK_noedge_posedge,
          SetupLow                => tsetup_WD7_CLK_noedge_posedge,
          HoldLow                 => thold_WD7_CLK_noedge_posedge,
          HoldHigh                => thold_WD7_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_CLK_posedge,
          TimingData              => Tmkr_WD8_CLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_CLK_noedge_posedge,
          SetupLow                => tsetup_WD8_CLK_noedge_posedge,
          HoldLow                 => thold_WD8_CLK_noedge_posedge,
          HoldHigh                => thold_WD8_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_CLK_posedge,
          TimingData              => Tmkr_WD9_CLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_CLK_noedge_posedge,
          SetupLow                => tsetup_WD9_CLK_noedge_posedge,
          HoldLow                 => thold_WD9_CLK_noedge_posedge,
          HoldHigh                => thold_WD9_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_CLK_posedge,
          TimingData              => Tmkr_WD10_CLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_CLK_noedge_posedge,
          SetupLow                => tsetup_WD10_CLK_noedge_posedge,
          HoldLow                 => thold_WD10_CLK_noedge_posedge,
          HoldHigh                => thold_WD10_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_CLK_posedge,
          TimingData              => Tmkr_WD11_CLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_CLK_noedge_posedge,
          SetupLow                => tsetup_WD11_CLK_noedge_posedge,
          HoldLow                 => thold_WD11_CLK_noedge_posedge,
          HoldHigh                => thold_WD11_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_CLK_posedge,
          TimingData              => Tmkr_WD12_CLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_CLK_noedge_posedge,
          SetupLow                => tsetup_WD12_CLK_noedge_posedge,
          HoldLow                 => thold_WD12_CLK_noedge_posedge,
          HoldHigh                => thold_WD12_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_CLK_posedge,
          TimingData              => Tmkr_WD13_CLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_CLK_noedge_posedge,
          SetupLow                => tsetup_WD13_CLK_noedge_posedge,
          HoldLow                 => thold_WD13_CLK_noedge_posedge,
          HoldHigh                => thold_WD13_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_CLK_posedge,
          TimingData              => Tmkr_WD14_CLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_CLK_noedge_posedge,
          SetupLow                => tsetup_WD14_CLK_noedge_posedge,
          HoldLow                 => thold_WD14_CLK_noedge_posedge,
          HoldHigh                => thold_WD14_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_CLK_posedge,
          TimingData              => Tmkr_WD15_CLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_CLK_noedge_posedge,
          SetupLow                => tsetup_WD15_CLK_noedge_posedge,
          HoldLow                 => thold_WD15_CLK_noedge_posedge,
          HoldHigh                => thold_WD15_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD16_CLK_posedge,
          TimingData              => Tmkr_WD16_CLK_posedge,
          TestSignal              => WD16_ipd,
          TestSignalName          => "WD16",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD16_CLK_noedge_posedge,
          SetupLow                => tsetup_WD16_CLK_noedge_posedge,
          HoldLow                 => thold_WD16_CLK_noedge_posedge,
          HoldHigh                => thold_WD16_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD17_CLK_posedge,
          TimingData              => Tmkr_WD17_CLK_posedge,
          TestSignal              => WD17_ipd,
          TestSignalName          => "WD17",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD17_CLK_noedge_posedge,
          SetupLow                => tsetup_WD17_CLK_noedge_posedge,
          HoldLow                 => thold_WD17_CLK_noedge_posedge,
          HoldHigh                => thold_WD17_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD18_CLK_posedge,
          TimingData              => Tmkr_WD18_CLK_posedge,
          TestSignal              => WD18_ipd,
          TestSignalName          => "WD18",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD18_CLK_noedge_posedge,
          SetupLow                => tsetup_WD18_CLK_noedge_posedge,
          HoldLow                 => thold_WD18_CLK_noedge_posedge,
          HoldHigh                => thold_WD18_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD19_CLK_posedge,
          TimingData              => Tmkr_WD19_CLK_posedge,
          TestSignal              => WD19_ipd,
          TestSignalName          => "WD19",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD19_CLK_noedge_posedge,
          SetupLow                => tsetup_WD19_CLK_noedge_posedge,
          HoldLow                 => thold_WD19_CLK_noedge_posedge,
          HoldHigh                => thold_WD19_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD20_CLK_posedge,
          TimingData              => Tmkr_WD20_CLK_posedge,
          TestSignal              => WD20_ipd,
          TestSignalName          => "WD20",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD20_CLK_noedge_posedge,
          SetupLow                => tsetup_WD20_CLK_noedge_posedge,
          HoldLow                 => thold_WD20_CLK_noedge_posedge,
          HoldHigh                => thold_WD20_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD21_CLK_posedge,
          TimingData              => Tmkr_WD21_CLK_posedge,
          TestSignal              => WD21_ipd,
          TestSignalName          => "WD21",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD21_CLK_noedge_posedge,
          SetupLow                => tsetup_WD21_CLK_noedge_posedge,
          HoldLow                 => thold_WD21_CLK_noedge_posedge,
          HoldHigh                => thold_WD21_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD22_CLK_posedge,
          TimingData              => Tmkr_WD22_CLK_posedge,
          TestSignal              => WD22_ipd,
          TestSignalName          => "WD22",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD22_CLK_noedge_posedge,
          SetupLow                => tsetup_WD22_CLK_noedge_posedge,
          HoldLow                 => thold_WD22_CLK_noedge_posedge,
          HoldHigh                => thold_WD22_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD23_CLK_posedge,
          TimingData              => Tmkr_WD23_CLK_posedge,
          TestSignal              => WD23_ipd,
          TestSignalName          => "WD23",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD23_CLK_noedge_posedge,
          SetupLow                => tsetup_WD23_CLK_noedge_posedge,
          HoldLow                 => thold_WD23_CLK_noedge_posedge,
          HoldHigh                => thold_WD23_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD24_CLK_posedge,
          TimingData              => Tmkr_WD24_CLK_posedge,
          TestSignal              => WD24_ipd,
          TestSignalName          => "WD24",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD24_CLK_noedge_posedge,
          SetupLow                => tsetup_WD24_CLK_noedge_posedge,
          HoldLow                 => thold_WD24_CLK_noedge_posedge,
          HoldHigh                => thold_WD24_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD25_CLK_posedge,
          TimingData              => Tmkr_WD25_CLK_posedge,
          TestSignal              => WD25_ipd,
          TestSignalName          => "WD25",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD25_CLK_noedge_posedge,
          SetupLow                => tsetup_WD25_CLK_noedge_posedge,
          HoldLow                 => thold_WD25_CLK_noedge_posedge,
          HoldHigh                => thold_WD25_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD26_CLK_posedge,
          TimingData              => Tmkr_WD26_CLK_posedge,
          TestSignal              => WD26_ipd,
          TestSignalName          => "WD26",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD26_CLK_noedge_posedge,
          SetupLow                => tsetup_WD26_CLK_noedge_posedge,
          HoldLow                 => thold_WD26_CLK_noedge_posedge,
          HoldHigh                => thold_WD26_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD27_CLK_posedge,
          TimingData              => Tmkr_WD27_CLK_posedge,
          TestSignal              => WD27_ipd,
          TestSignalName          => "WD27",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD27_CLK_noedge_posedge,
          SetupLow                => tsetup_WD27_CLK_noedge_posedge,
          HoldLow                 => thold_WD27_CLK_noedge_posedge,
          HoldHigh                => thold_WD27_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD28_CLK_posedge,
          TimingData              => Tmkr_WD28_CLK_posedge,
          TestSignal              => WD28_ipd,
          TestSignalName          => "WD28",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD28_CLK_noedge_posedge,
          SetupLow                => tsetup_WD28_CLK_noedge_posedge,
          HoldLow                 => thold_WD28_CLK_noedge_posedge,
          HoldHigh                => thold_WD28_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD29_CLK_posedge,
          TimingData              => Tmkr_WD29_CLK_posedge,
          TestSignal              => WD29_ipd,
          TestSignalName          => "WD29",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD29_CLK_noedge_posedge,
          SetupLow                => tsetup_WD29_CLK_noedge_posedge,
          HoldLow                 => thold_WD29_CLK_noedge_posedge,
          HoldHigh                => thold_WD29_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD30_CLK_posedge,
          TimingData              => Tmkr_WD30_CLK_posedge,
          TestSignal              => WD30_ipd,
          TestSignalName          => "WD30",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD30_CLK_noedge_posedge,
          SetupLow                => tsetup_WD30_CLK_noedge_posedge,
          HoldLow                 => thold_WD30_CLK_noedge_posedge,
          HoldHigh                => thold_WD30_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD31_CLK_posedge,
          TimingData              => Tmkr_WD31_CLK_posedge,
          TestSignal              => WD31_ipd,
          TestSignalName          => "WD31",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD31_CLK_noedge_posedge,
          SetupLow                => tsetup_WD31_CLK_noedge_posedge,
          HoldLow                 => thold_WD31_CLK_noedge_posedge,
          HoldHigh                => thold_WD31_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD32_CLK_posedge,
          TimingData              => Tmkr_WD32_CLK_posedge,
          TestSignal              => WD32_ipd,
          TestSignalName          => "WD32",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD32_CLK_noedge_posedge,
          SetupLow                => tsetup_WD32_CLK_noedge_posedge,
          HoldLow                 => thold_WD32_CLK_noedge_posedge,
          HoldHigh                => thold_WD32_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD33_CLK_posedge,
          TimingData              => Tmkr_WD33_CLK_posedge,
          TestSignal              => WD33_ipd,
          TestSignalName          => "WD33",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD33_CLK_noedge_posedge,
          SetupLow                => tsetup_WD33_CLK_noedge_posedge,
          HoldLow                 => thold_WD33_CLK_noedge_posedge,
          HoldHigh                => thold_WD33_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD34_CLK_posedge,
          TimingData              => Tmkr_WD34_CLK_posedge,
          TestSignal              => WD34_ipd,
          TestSignalName          => "WD34",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD34_CLK_noedge_posedge,
          SetupLow                => tsetup_WD34_CLK_noedge_posedge,
          HoldLow                 => thold_WD34_CLK_noedge_posedge,
          HoldHigh                => thold_WD34_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD35_CLK_posedge,
          TimingData              => Tmkr_WD35_CLK_posedge,
          TestSignal              => WD35_ipd,
          TestSignalName          => "WD35",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD35_CLK_noedge_posedge,
          SetupLow                => tsetup_WD35_CLK_noedge_posedge,
          HoldLow                 => thold_WD35_CLK_noedge_posedge,
          HoldHigh                => thold_WD35_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD36_CLK_posedge,
          TimingData              => Tmkr_WD36_CLK_posedge,
          TestSignal              => WD36_ipd,
          TestSignalName          => "WD36",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD36_CLK_noedge_posedge,
          SetupLow                => tsetup_WD36_CLK_noedge_posedge,
          HoldLow                 => thold_WD36_CLK_noedge_posedge,
          HoldHigh                => thold_WD36_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD37_CLK_posedge,
          TimingData              => Tmkr_WD37_CLK_posedge,
          TestSignal              => WD37_ipd,
          TestSignalName          => "WD37",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD37_CLK_noedge_posedge,
          SetupLow                => tsetup_WD37_CLK_noedge_posedge,
          HoldLow                 => thold_WD37_CLK_noedge_posedge,
          HoldHigh                => thold_WD37_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD38_CLK_posedge,
          TimingData              => Tmkr_WD38_CLK_posedge,
          TestSignal              => WD38_ipd,
          TestSignalName          => "WD38",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD38_CLK_noedge_posedge,
          SetupLow                => tsetup_WD38_CLK_noedge_posedge,
          HoldLow                 => thold_WD38_CLK_noedge_posedge,
          HoldHigh                => thold_WD38_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD39_CLK_posedge,
          TimingData              => Tmkr_WD39_CLK_posedge,
          TestSignal              => WD39_ipd,
          TestSignalName          => "WD39",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD39_CLK_noedge_posedge,
          SetupLow                => tsetup_WD39_CLK_noedge_posedge,
          HoldLow                 => thold_WD39_CLK_noedge_posedge,
          HoldHigh                => thold_WD39_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD40_CLK_posedge,
          TimingData              => Tmkr_WD40_CLK_posedge,
          TestSignal              => WD40_ipd,
          TestSignalName          => "WD40",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD40_CLK_noedge_posedge,
          SetupLow                => tsetup_WD40_CLK_noedge_posedge,
          HoldLow                 => thold_WD40_CLK_noedge_posedge,
          HoldHigh                => thold_WD40_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD41_CLK_posedge,
          TimingData              => Tmkr_WD41_CLK_posedge,
          TestSignal              => WD41_ipd,
          TestSignalName          => "WD41",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD41_CLK_noedge_posedge,
          SetupLow                => tsetup_WD41_CLK_noedge_posedge,
          HoldLow                 => thold_WD41_CLK_noedge_posedge,
          HoldHigh                => thold_WD41_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD42_CLK_posedge,
          TimingData              => Tmkr_WD42_CLK_posedge,
          TestSignal              => WD42_ipd,
          TestSignalName          => "WD42",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD42_CLK_noedge_posedge,
          SetupLow                => tsetup_WD42_CLK_noedge_posedge,
          HoldLow                 => thold_WD42_CLK_noedge_posedge,
          HoldHigh                => thold_WD42_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD43_CLK_posedge,
          TimingData              => Tmkr_WD43_CLK_posedge,
          TestSignal              => WD43_ipd,
          TestSignalName          => "WD43",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD43_CLK_noedge_posedge,
          SetupLow                => tsetup_WD43_CLK_noedge_posedge,
          HoldLow                 => thold_WD43_CLK_noedge_posedge,
          HoldHigh                => thold_WD43_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD44_CLK_posedge,
          TimingData              => Tmkr_WD44_CLK_posedge,
          TestSignal              => WD44_ipd,
          TestSignalName          => "WD44",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD44_CLK_noedge_posedge,
          SetupLow                => tsetup_WD44_CLK_noedge_posedge,
          HoldLow                 => thold_WD44_CLK_noedge_posedge,
          HoldHigh                => thold_WD44_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD45_CLK_posedge,
          TimingData              => Tmkr_WD45_CLK_posedge,
          TestSignal              => WD45_ipd,
          TestSignalName          => "WD45",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD45_CLK_noedge_posedge,
          SetupLow                => tsetup_WD45_CLK_noedge_posedge,
          HoldLow                 => thold_WD45_CLK_noedge_posedge,
          HoldHigh                => thold_WD45_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD46_CLK_posedge,
          TimingData              => Tmkr_WD46_CLK_posedge,
          TestSignal              => WD46_ipd,
          TestSignalName          => "WD46",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD46_CLK_noedge_posedge,
          SetupLow                => tsetup_WD46_CLK_noedge_posedge,
          HoldLow                 => thold_WD46_CLK_noedge_posedge,
          HoldHigh                => thold_WD46_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD47_CLK_posedge,
          TimingData              => Tmkr_WD47_CLK_posedge,
          TestSignal              => WD47_ipd,
          TestSignalName          => "WD47",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD47_CLK_noedge_posedge,
          SetupLow                => tsetup_WD47_CLK_noedge_posedge,
          HoldLow                 => thold_WD47_CLK_noedge_posedge,
          HoldHigh                => thold_WD47_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/CAM128X48CM",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/CAM128X48CM",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_CLK_posedge_posedge,
          TimingData              => Tmkr_RST_CLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_CLK_posedge_posedge,
          Removal                 => thold_RST_CLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48CM",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CE_CLK_posedge or Tviol_WE_CLK_posedge or 
                 Tviol_EN_MASK_CLK_posedge or Tviol_EN_MASK_CLK_posedge or 
                 Tviol_WR_DC_CLK_posedge or Tviol_CS0_CLK_posedge or Tviol_CS1_CLK_posedge or 
                 Tviol_WAD0_CLK_posedge or Tviol_WAD1_CLK_posedge or 
                 Tviol_WAD2_CLK_posedge or Tviol_WAD3_CLK_posedge or 
                 Tviol_WAD4_CLK_posedge or Tviol_WAD4_CLK_posedge or 
                 Tviol_WAD6_CLK_posedge or 
                 Tviol_WD0_CLK_posedge or Tviol_WD1_CLK_posedge or 
                 Tviol_WD2_CLK_posedge or Tviol_WD3_CLK_posedge or 
                 Tviol_WD4_CLK_posedge or Tviol_WD5_CLK_posedge or 
                 Tviol_WD6_CLK_posedge or Tviol_WD7_CLK_posedge or 
                 Tviol_WD8_CLK_posedge or Tviol_WD9_CLK_posedge or 
                 Tviol_WD10_CLK_posedge or Tviol_WD11_CLK_posedge or 
                 Tviol_WD12_CLK_posedge or Tviol_WD13_CLK_posedge or 
                 Tviol_WD14_CLK_posedge or Tviol_WD15_CLK_posedge or 
                 Tviol_WD16_CLK_posedge or Tviol_WD17_CLK_posedge or 
                 Tviol_WD18_CLK_posedge or Tviol_WD19_CLK_posedge or 
                 Tviol_WD20_CLK_posedge or Tviol_WD21_CLK_posedge or 
                 Tviol_WD22_CLK_posedge or Tviol_WD23_CLK_posedge or 
                 Tviol_WD24_CLK_posedge or Tviol_WD25_CLK_posedge or 
                 Tviol_WD26_CLK_posedge or Tviol_WD27_CLK_posedge or 
                 Tviol_WD28_CLK_posedge or Tviol_WD29_CLK_posedge or 
                 Tviol_WD30_CLK_posedge or Tviol_WD31_CLK_posedge or 
                 Tviol_WD32_CLK_posedge or Tviol_WD33_CLK_posedge or 
                 Tviol_WD34_CLK_posedge or Tviol_WD35_CLK_posedge or 
                 Tviol_WD36_CLK_posedge or Tviol_WD37_CLK_posedge or 
                 Tviol_WD38_CLK_posedge or Tviol_WD39_CLK_posedge or 
                 Tviol_WD40_CLK_posedge or Tviol_WD41_CLK_posedge or 
                 Tviol_WD42_CLK_posedge or Tviol_WD43_CLK_posedge or 
                 Tviol_WD44_CLK_posedge or Tviol_WD45_CLK_posedge or 
                 Tviol_WD46_CLK_posedge or Tviol_WD47_CLK_posedge or 
                 Pviol_CLK or Pviol_RST or 
                 Tviol_RST_CLK_posedge_posedge; 

    -------------------------
    --  Functionality Section
    -------------------------

	wait on CE_ipd, WE_ipd, CLK_ipd, EN_MASK_ipd, WR_MASK_ipd, WR_DC_ipd, RST_ipd, CS, WAD, WD, CMI, CMO;

      end process VITALBehavior;

	CAMCM_inst : SC_CAMCM_16K

	generic map (
		ADDR_WIDTH    =>  7,
		DATA_WIDTH    => 48,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
                MEM_INIT_FILE => RAM_INIT_FILE
		)
	port map (
		CE        => CE_ipd ,
		WE        => WE_ipd ,
		CLK       => CLK_ipd ,
		EN_MASK   => EN_MASK_ipd ,
		WR_MASK   => WR_MASK_ipd ,
		WR_DC     => WR_DC_ipd ,
		RST       => RST_ipd ,
		CS        => CS ,
		WAD       => WAD ,
		WD        => WD ,
                CMI       => CMI ,
                CMO       => CMO
		);


end VITAL;

configuration CFG_CAM128X48CM_VITAL of CAM128X48CM is
   for VITAL
   end for;
end CFG_CAM128X48CM_VITAL;



----- CELL CAM128X48CR -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;


-- entity declaration --
entity CAM128X48CR is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_CLK_CO0                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CO1                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CO2                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CO3                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CO4                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CO5                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_CO6                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_CLK_MATCH                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_MUL_MATCH                  :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_CO0                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CO1                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CO2                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CO3                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CO4                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CO5                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_CO6                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_MATCH                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_MUL_MATCH                  :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WE_CLK_noedge_posedge       :	VitalDelayType   := 0.1 ns;
      thold_WE_CLK_noedge_posedge        :	VitalDelayType   := 0.0 ns;

      tsetup_CE_CLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_CE_CLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_EN_MASK_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_EN_MASK_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WR_MASK_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_MASK_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WR_DC_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WR_DC_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CS0_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_CS0_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_CS1_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_CS1_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD0_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD1_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD1_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD2_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD2_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD3_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD3_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD4_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD4_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD5_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD5_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WAD6_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WAD6_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD0_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD1_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD1_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD2_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD2_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD3_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD3_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD4_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD4_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD5_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD5_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD6_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD6_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD7_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD7_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD8_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD8_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD9_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD9_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD10_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD10_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD11_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD11_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD12_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD12_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD13_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD13_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD14_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD14_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD15_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD15_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD16_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD16_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD17_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD17_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD18_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD18_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD19_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD19_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD20_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD20_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD21_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD21_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD22_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD22_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD23_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD23_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD24_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD24_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD25_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD25_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD26_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD26_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD27_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD27_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD28_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD28_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD29_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD29_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD30_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD30_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD31_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD31_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD32_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD32_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD33_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD33_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD34_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD34_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD35_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD35_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD36_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD36_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD37_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD37_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD38_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD38_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD39_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD39_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD40_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD40_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD41_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD41_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD42_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD42_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD43_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD43_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD44_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD44_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD45_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD45_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD46_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD46_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD47_CLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WD47_CLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_CLK_posedge_posedge :	VitalDelayType   := 0.1 ns;
      thold_RST_CLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_CLK_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      tipd_CE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CLK                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_EN_MASK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR_MASK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WR_DC                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CS0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CS1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD16                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD17                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD18                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD19                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD20                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD21                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD22                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD23                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD24                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD25                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD26                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD27                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD28                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD29                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD30                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD31                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD32                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD33                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD34                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD35                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD36                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD37                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD38                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD39                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD40                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD41                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD42                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD43                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD44                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD45                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD46                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD47                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI6                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI7                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI8                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI9                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI16                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI17                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI18                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI19                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI20                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI21                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI22                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI23                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI24                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI25                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI26                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI27                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI28                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI29                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI30                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI31                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI32                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI33                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI34                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI35                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI36                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI37                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI38                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI39                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI40                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI41                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI42                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI43                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI44                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI45                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI46                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI47                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI48                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI49                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI50                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI51                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI52                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI53                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI54                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI55                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI56                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI57                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI58                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI59                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI60                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI61                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI62                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI63                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI64                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI65                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI66                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI67                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI68                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI69                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI70                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI71                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI72                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI73                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI74                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI75                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI76                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI77                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI78                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI79                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI80                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI81                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI82                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI83                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI84                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI85                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI86                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI87                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI88                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI89                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI90                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI91                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI92                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI93                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI94                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI95                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI96                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI97                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI98                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI99                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI100                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI101                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI102                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI103                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI104                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI105                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI106                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI107                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI108                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI109                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI110                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI111                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI112                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI113                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI114                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI115                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI116                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI117                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI118                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI119                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI120                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI121                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI122                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI123                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI124                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI125                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI126                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CMI127                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                              :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      CLK                             :	in    STD_ULOGIC;
      EN_MASK                         :	in    STD_ULOGIC;
      WR_MASK                         :	in    STD_ULOGIC;
      WR_DC                           :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      CS0                             :	in    STD_ULOGIC;
      CS1                             :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WD0                             :	in    STD_ULOGIC;
      WD1                             :	in    STD_ULOGIC;
      WD2                             :	in    STD_ULOGIC;
      WD3                             :	in    STD_ULOGIC;
      WD4                             :	in    STD_ULOGIC;
      WD5                             :	in    STD_ULOGIC;
      WD6                             :	in    STD_ULOGIC;
      WD7                             :	in    STD_ULOGIC;
      WD8                             :	in    STD_ULOGIC;
      WD9                             :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WD16                            :	in    STD_ULOGIC;
      WD17                            :	in    STD_ULOGIC;
      WD18                            :	in    STD_ULOGIC;
      WD19                            :	in    STD_ULOGIC;
      WD20                            :	in    STD_ULOGIC;
      WD21                            :	in    STD_ULOGIC;
      WD22                            :	in    STD_ULOGIC;
      WD23                            :	in    STD_ULOGIC;
      WD24                            :	in    STD_ULOGIC;
      WD25                            :	in    STD_ULOGIC;
      WD26                            :	in    STD_ULOGIC;
      WD27                            :	in    STD_ULOGIC;
      WD28                            :	in    STD_ULOGIC;
      WD29                            :	in    STD_ULOGIC;
      WD30                            :	in    STD_ULOGIC;
      WD31                            :	in    STD_ULOGIC;
      WD32                            :	in    STD_ULOGIC;
      WD33                            :	in    STD_ULOGIC;
      WD34                            :	in    STD_ULOGIC;
      WD35                            :	in    STD_ULOGIC;
      WD36                            :	in    STD_ULOGIC;
      WD37                            :	in    STD_ULOGIC;
      WD38                            :	in    STD_ULOGIC;
      WD39                            :	in    STD_ULOGIC;
      WD40                            :	in    STD_ULOGIC;
      WD41                            :	in    STD_ULOGIC;
      WD42                            :	in    STD_ULOGIC;
      WD43                            :	in    STD_ULOGIC;
      WD44                            :	in    STD_ULOGIC;
      WD45                            :	in    STD_ULOGIC;
      WD46                            :	in    STD_ULOGIC;
      WD47                            :	in    STD_ULOGIC;
      CMI0                            :	in   STD_ULOGIC;
      CMI1                            :	in   STD_ULOGIC;
      CMI2                            :	in   STD_ULOGIC;
      CMI3                            :	in   STD_ULOGIC;
      CMI4                            :	in   STD_ULOGIC;
      CMI5                            :	in   STD_ULOGIC;
      CMI6                            :	in   STD_ULOGIC;
      CMI7                            :	in   STD_ULOGIC;
      CMI8                            :	in   STD_ULOGIC;
      CMI9                            :	in   STD_ULOGIC;
      CMI10                            :	in   STD_ULOGIC;
      CMI11                            :	in   STD_ULOGIC;
      CMI12                            :	in   STD_ULOGIC;
      CMI13                            :	in   STD_ULOGIC;
      CMI14                            :	in   STD_ULOGIC;
      CMI15                            :	in   STD_ULOGIC;
      CMI16                            :	in   STD_ULOGIC;
      CMI17                            :	in   STD_ULOGIC;
      CMI18                            :	in   STD_ULOGIC;
      CMI19                            :	in   STD_ULOGIC;
      CMI20                            :	in   STD_ULOGIC;
      CMI21                            :	in   STD_ULOGIC;
      CMI22                            :	in   STD_ULOGIC;
      CMI23                            :	in   STD_ULOGIC;
      CMI24                            :	in   STD_ULOGIC;
      CMI25                            :	in   STD_ULOGIC;
      CMI26                            :	in   STD_ULOGIC;
      CMI27                            :	in   STD_ULOGIC;
      CMI28                            :	in   STD_ULOGIC;
      CMI29                            :	in   STD_ULOGIC;
      CMI30                            :	in   STD_ULOGIC;
      CMI31                            :	in   STD_ULOGIC;
      CMI32                            :	in   STD_ULOGIC;
      CMI33                            :	in   STD_ULOGIC;
      CMI34                            :	in   STD_ULOGIC;
      CMI35                            :	in   STD_ULOGIC;
      CMI36                            :	in   STD_ULOGIC;
      CMI37                            :	in   STD_ULOGIC;
      CMI38                            :	in   STD_ULOGIC;
      CMI39                            :	in   STD_ULOGIC;
      CMI40                            :	in   STD_ULOGIC;
      CMI41                            :	in   STD_ULOGIC;
      CMI42                            :	in   STD_ULOGIC;
      CMI43                            :	in   STD_ULOGIC;
      CMI44                            :	in   STD_ULOGIC;
      CMI45                            :	in   STD_ULOGIC;
      CMI46                            :	in   STD_ULOGIC;
      CMI47                            :	in   STD_ULOGIC;
      CMI48                            :	in   STD_ULOGIC;
      CMI49                            :	in   STD_ULOGIC;
      CMI50                            :	in   STD_ULOGIC;
      CMI51                            :	in   STD_ULOGIC;
      CMI52                            :	in   STD_ULOGIC;
      CMI53                            :	in   STD_ULOGIC;
      CMI54                            :	in   STD_ULOGIC;
      CMI55                            :	in   STD_ULOGIC;
      CMI56                            :	in   STD_ULOGIC;
      CMI57                            :	in   STD_ULOGIC;
      CMI58                            :	in   STD_ULOGIC;
      CMI59                            :	in   STD_ULOGIC;
      CMI60                            :	in   STD_ULOGIC;
      CMI61                            :	in   STD_ULOGIC;
      CMI62                            :	in   STD_ULOGIC;
      CMI63                            :	in   STD_ULOGIC;
      CMI64                            :	in   STD_ULOGIC;
      CMI65                            :	in   STD_ULOGIC;
      CMI66                            :	in   STD_ULOGIC;
      CMI67                            :	in   STD_ULOGIC;
      CMI68                            :	in   STD_ULOGIC;
      CMI69                            :	in   STD_ULOGIC;
      CMI70                            :	in   STD_ULOGIC;
      CMI71                            :	in   STD_ULOGIC;
      CMI72                            :	in   STD_ULOGIC;
      CMI73                            :	in   STD_ULOGIC;
      CMI74                            :	in   STD_ULOGIC;
      CMI75                            :	in   STD_ULOGIC;
      CMI76                            :	in   STD_ULOGIC;
      CMI77                            :	in   STD_ULOGIC;
      CMI78                            :	in   STD_ULOGIC;
      CMI79                            :	in   STD_ULOGIC;
      CMI80                            :	in   STD_ULOGIC;
      CMI81                            :	in   STD_ULOGIC;
      CMI82                            :	in   STD_ULOGIC;
      CMI83                            :	in   STD_ULOGIC;
      CMI84                            :	in   STD_ULOGIC;
      CMI85                            :	in   STD_ULOGIC;
      CMI86                            :	in   STD_ULOGIC;
      CMI87                            :	in   STD_ULOGIC;
      CMI88                            :	in   STD_ULOGIC;
      CMI89                            :	in   STD_ULOGIC;
      CMI90                            :	in   STD_ULOGIC;
      CMI91                            :	in   STD_ULOGIC;
      CMI92                            :	in   STD_ULOGIC;
      CMI93                            :	in   STD_ULOGIC;
      CMI94                            :	in   STD_ULOGIC;
      CMI95                            :	in   STD_ULOGIC;
      CMI96                            :	in   STD_ULOGIC;
      CMI97                            :	in   STD_ULOGIC;
      CMI98                            :	in   STD_ULOGIC;
      CMI99                            :	in   STD_ULOGIC;
      CMI100                            :	in   STD_ULOGIC;
      CMI101                            :	in   STD_ULOGIC;
      CMI102                            :	in   STD_ULOGIC;
      CMI103                            :	in   STD_ULOGIC;
      CMI104                            :	in   STD_ULOGIC;
      CMI105                            :	in   STD_ULOGIC;
      CMI106                            :	in   STD_ULOGIC;
      CMI107                            :	in   STD_ULOGIC;
      CMI108                            :	in   STD_ULOGIC;
      CMI109                            :	in   STD_ULOGIC;
      CMI110                            :	in   STD_ULOGIC;
      CMI111                            :	in   STD_ULOGIC;
      CMI112                            :	in   STD_ULOGIC;
      CMI113                            :	in   STD_ULOGIC;
      CMI114                            :	in   STD_ULOGIC;
      CMI115                            :	in   STD_ULOGIC;
      CMI116                            :	in   STD_ULOGIC;
      CMI117                            :	in   STD_ULOGIC;
      CMI118                            :	in   STD_ULOGIC;
      CMI119                            :	in   STD_ULOGIC;
      CMI120                            :	in   STD_ULOGIC;
      CMI121                            :	in   STD_ULOGIC;
      CMI122                            :	in   STD_ULOGIC;
      CMI123                            :	in   STD_ULOGIC;
      CMI124                            :	in   STD_ULOGIC;
      CMI125                            :	in   STD_ULOGIC;
      CMI126                            :	in   STD_ULOGIC;
      CMI127                            :	in   STD_ULOGIC;
      CO0                            :	out   STD_ULOGIC;
      CO1                            :	out   STD_ULOGIC;
      CO2                            :	out   STD_ULOGIC;
      CO3                            :	out   STD_ULOGIC;
      CO4                            :	out   STD_ULOGIC;
      CO5                            :	out   STD_ULOGIC;
      CO6                            :	out   STD_ULOGIC;
      MATCH                          :	out   STD_ULOGIC;
      MUL_MATCH                      :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of CAM128X48CR : entity is FALSE;
end CAM128X48CR;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CAM128X48CR is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_CAMCR_16K

	generic (
		ADDR_WIDTH    : integer :=  7;
		DATA_WIDTH    : integer := 48;
                MEM_INIT_FLAG : integer :=  0;  
	        MEM_INIT_FILE : string  := ""
		);
	port (
		CE        :  in  STD_LOGIC ;
		WE        :  in  STD_LOGIC ;
		CLK       :  in  STD_LOGIC ;
		EN_MASK   :  in  STD_LOGIC ;
		WR_MASK   :  in  STD_LOGIC ;
		WR_DC     :  in  STD_LOGIC ;
		RST       :  in  STD_LOGIC ;
		CS        :  in  STD_LOGIC_VECTOR ( 1 downto 0) ;
		WAD       :  in  STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0);
		WD        :  in  STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0);
                CMI       :  in  STD_LOGIC_VECTOR ( 2**ADDR_WIDTH -1 downto 0);
		CO        :  out STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0);
		MATCH     :  out STD_LOGIC;
		MUL_MATCH :  out STD_LOGIC
                );

	end component ;

      signal CE_ipd        : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal CLK_ipd       : std_ulogic := 'X';
      signal EN_MASK_ipd   : std_ulogic := 'X';
      signal WR_MASK_ipd   : std_ulogic := 'X';
      signal WR_DC_ipd     : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal CS0_ipd       : std_ulogic := 'X';
      signal CS1_ipd       : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';

      signal WD0_ipd       : std_ulogic := 'X';
      signal WD1_ipd       : std_ulogic := 'X';
      signal WD2_ipd       : std_ulogic := 'X';
      signal WD3_ipd       : std_ulogic := 'X';
      signal WD4_ipd       : std_ulogic := 'X';
      signal WD5_ipd       : std_ulogic := 'X';
      signal WD6_ipd       : std_ulogic := 'X';
      signal WD7_ipd       : std_ulogic := 'X';
      signal WD8_ipd       : std_ulogic := 'X';
      signal WD9_ipd       : std_ulogic := 'X';
      signal WD10_ipd       : std_ulogic := 'X';
      signal WD11_ipd       : std_ulogic := 'X';
      signal WD12_ipd       : std_ulogic := 'X';
      signal WD13_ipd       : std_ulogic := 'X';
      signal WD14_ipd       : std_ulogic := 'X';
      signal WD15_ipd       : std_ulogic := 'X';
      signal WD16_ipd       : std_ulogic := 'X';
      signal WD17_ipd       : std_ulogic := 'X';
      signal WD18_ipd       : std_ulogic := 'X';
      signal WD19_ipd       : std_ulogic := 'X';
      signal WD20_ipd       : std_ulogic := 'X';
      signal WD21_ipd       : std_ulogic := 'X';
      signal WD22_ipd       : std_ulogic := 'X';
      signal WD23_ipd       : std_ulogic := 'X';
      signal WD24_ipd       : std_ulogic := 'X';
      signal WD25_ipd       : std_ulogic := 'X';
      signal WD26_ipd       : std_ulogic := 'X';
      signal WD27_ipd       : std_ulogic := 'X';
      signal WD28_ipd       : std_ulogic := 'X';
      signal WD29_ipd       : std_ulogic := 'X';
      signal WD30_ipd       : std_ulogic := 'X';
      signal WD31_ipd       : std_ulogic := 'X';
      signal WD32_ipd       : std_ulogic := 'X';
      signal WD33_ipd       : std_ulogic := 'X';
      signal WD34_ipd       : std_ulogic := 'X';
      signal WD35_ipd       : std_ulogic := 'X';
      signal WD36_ipd       : std_ulogic := 'X';
      signal WD37_ipd       : std_ulogic := 'X';
      signal WD38_ipd       : std_ulogic := 'X';
      signal WD39_ipd       : std_ulogic := 'X';
      signal WD40_ipd       : std_ulogic := 'X';
      signal WD41_ipd       : std_ulogic := 'X';
      signal WD42_ipd       : std_ulogic := 'X';
      signal WD43_ipd       : std_ulogic := 'X';
      signal WD44_ipd       : std_ulogic := 'X';
      signal WD45_ipd       : std_ulogic := 'X';
      signal WD46_ipd       : std_ulogic := 'X';
      signal WD47_ipd       : std_ulogic := 'X';
      signal CMI0_ipd       : std_ulogic := 'X';
      signal CMI1_ipd       : std_ulogic := 'X';
      signal CMI2_ipd       : std_ulogic := 'X';
      signal CMI3_ipd       : std_ulogic := 'X';
      signal CMI4_ipd       : std_ulogic := 'X';
      signal CMI5_ipd       : std_ulogic := 'X';
      signal CMI6_ipd       : std_ulogic := 'X';
      signal CMI7_ipd       : std_ulogic := 'X';
      signal CMI8_ipd       : std_ulogic := 'X';
      signal CMI9_ipd       : std_ulogic := 'X';
      signal CMI10_ipd       : std_ulogic := 'X';
      signal CMI11_ipd       : std_ulogic := 'X';
      signal CMI12_ipd       : std_ulogic := 'X';
      signal CMI13_ipd       : std_ulogic := 'X';
      signal CMI14_ipd       : std_ulogic := 'X';
      signal CMI15_ipd       : std_ulogic := 'X';
      signal CMI16_ipd       : std_ulogic := 'X';
      signal CMI17_ipd       : std_ulogic := 'X';
      signal CMI18_ipd       : std_ulogic := 'X';
      signal CMI19_ipd       : std_ulogic := 'X';
      signal CMI20_ipd       : std_ulogic := 'X';
      signal CMI21_ipd       : std_ulogic := 'X';
      signal CMI22_ipd       : std_ulogic := 'X';
      signal CMI23_ipd       : std_ulogic := 'X';
      signal CMI24_ipd       : std_ulogic := 'X';
      signal CMI25_ipd       : std_ulogic := 'X';
      signal CMI26_ipd       : std_ulogic := 'X';
      signal CMI27_ipd       : std_ulogic := 'X';
      signal CMI28_ipd       : std_ulogic := 'X';
      signal CMI29_ipd       : std_ulogic := 'X';
      signal CMI30_ipd       : std_ulogic := 'X';
      signal CMI31_ipd       : std_ulogic := 'X';
      signal CMI32_ipd       : std_ulogic := 'X';
      signal CMI33_ipd       : std_ulogic := 'X';
      signal CMI34_ipd       : std_ulogic := 'X';
      signal CMI35_ipd       : std_ulogic := 'X';
      signal CMI36_ipd       : std_ulogic := 'X';
      signal CMI37_ipd       : std_ulogic := 'X';
      signal CMI38_ipd       : std_ulogic := 'X';
      signal CMI39_ipd       : std_ulogic := 'X';
      signal CMI40_ipd       : std_ulogic := 'X';
      signal CMI41_ipd       : std_ulogic := 'X';
      signal CMI42_ipd       : std_ulogic := 'X';
      signal CMI43_ipd       : std_ulogic := 'X';
      signal CMI44_ipd       : std_ulogic := 'X';
      signal CMI45_ipd       : std_ulogic := 'X';
      signal CMI46_ipd       : std_ulogic := 'X';
      signal CMI47_ipd       : std_ulogic := 'X';
      signal CMI48_ipd       : std_ulogic := 'X';
      signal CMI49_ipd       : std_ulogic := 'X';
      signal CMI50_ipd       : std_ulogic := 'X';
      signal CMI51_ipd       : std_ulogic := 'X';
      signal CMI52_ipd       : std_ulogic := 'X';
      signal CMI53_ipd       : std_ulogic := 'X';
      signal CMI54_ipd       : std_ulogic := 'X';
      signal CMI55_ipd       : std_ulogic := 'X';
      signal CMI56_ipd       : std_ulogic := 'X';
      signal CMI57_ipd       : std_ulogic := 'X';
      signal CMI58_ipd       : std_ulogic := 'X';
      signal CMI59_ipd       : std_ulogic := 'X';
      signal CMI60_ipd       : std_ulogic := 'X';
      signal CMI61_ipd       : std_ulogic := 'X';
      signal CMI62_ipd       : std_ulogic := 'X';
      signal CMI63_ipd       : std_ulogic := 'X';
      signal CMI64_ipd       : std_ulogic := 'X';
      signal CMI65_ipd       : std_ulogic := 'X';
      signal CMI66_ipd       : std_ulogic := 'X';
      signal CMI67_ipd       : std_ulogic := 'X';
      signal CMI68_ipd       : std_ulogic := 'X';
      signal CMI69_ipd       : std_ulogic := 'X';
      signal CMI70_ipd       : std_ulogic := 'X';
      signal CMI71_ipd       : std_ulogic := 'X';
      signal CMI72_ipd       : std_ulogic := 'X';
      signal CMI73_ipd       : std_ulogic := 'X';
      signal CMI74_ipd       : std_ulogic := 'X';
      signal CMI75_ipd       : std_ulogic := 'X';
      signal CMI76_ipd       : std_ulogic := 'X';
      signal CMI77_ipd       : std_ulogic := 'X';
      signal CMI78_ipd       : std_ulogic := 'X';
      signal CMI79_ipd       : std_ulogic := 'X';
      signal CMI80_ipd       : std_ulogic := 'X';
      signal CMI81_ipd       : std_ulogic := 'X';
      signal CMI82_ipd       : std_ulogic := 'X';
      signal CMI83_ipd       : std_ulogic := 'X';
      signal CMI84_ipd       : std_ulogic := 'X';
      signal CMI85_ipd       : std_ulogic := 'X';
      signal CMI86_ipd       : std_ulogic := 'X';
      signal CMI87_ipd       : std_ulogic := 'X';
      signal CMI88_ipd       : std_ulogic := 'X';
      signal CMI89_ipd       : std_ulogic := 'X';
      signal CMI90_ipd       : std_ulogic := 'X';
      signal CMI91_ipd       : std_ulogic := 'X';
      signal CMI92_ipd       : std_ulogic := 'X';
      signal CMI93_ipd       : std_ulogic := 'X';
      signal CMI94_ipd       : std_ulogic := 'X';
      signal CMI95_ipd       : std_ulogic := 'X';
      signal CMI96_ipd       : std_ulogic := 'X';
      signal CMI97_ipd       : std_ulogic := 'X';
      signal CMI98_ipd       : std_ulogic := 'X';
      signal CMI99_ipd       : std_ulogic := 'X';
      signal CMI100_ipd       : std_ulogic := 'X';
      signal CMI101_ipd       : std_ulogic := 'X';
      signal CMI102_ipd       : std_ulogic := 'X';
      signal CMI103_ipd       : std_ulogic := 'X';
      signal CMI104_ipd       : std_ulogic := 'X';
      signal CMI105_ipd       : std_ulogic := 'X';
      signal CMI106_ipd       : std_ulogic := 'X';
      signal CMI107_ipd       : std_ulogic := 'X';
      signal CMI108_ipd       : std_ulogic := 'X';
      signal CMI109_ipd       : std_ulogic := 'X';
      signal CMI110_ipd       : std_ulogic := 'X';
      signal CMI111_ipd       : std_ulogic := 'X';
      signal CMI112_ipd       : std_ulogic := 'X';
      signal CMI113_ipd       : std_ulogic := 'X';
      signal CMI114_ipd       : std_ulogic := 'X';
      signal CMI115_ipd       : std_ulogic := 'X';
      signal CMI116_ipd       : std_ulogic := 'X';
      signal CMI117_ipd       : std_ulogic := 'X';
      signal CMI118_ipd       : std_ulogic := 'X';
      signal CMI119_ipd       : std_ulogic := 'X';
      signal CMI120_ipd       : std_ulogic := 'X';
      signal CMI121_ipd       : std_ulogic := 'X';
      signal CMI122_ipd       : std_ulogic := 'X';
      signal CMI123_ipd       : std_ulogic := 'X';
      signal CMI124_ipd       : std_ulogic := 'X';
      signal CMI125_ipd       : std_ulogic := 'X';
      signal CMI126_ipd       : std_ulogic := 'X';
      signal CMI127_ipd       : std_ulogic := 'X';
      signal MATCH_ipd      : std_ulogic := 'X'; --QQ05
      signal MUL_MATCH_ipd  : std_ulogic := 'X'; --QQ05
      signal CS             : std_logic_vector (1 downto 0);
      signal WAD            : std_logic_vector (6 downto 0);
      signal WD             : std_logic_vector (47 downto 0);
      signal CMI            : std_logic_vector (127 downto 0);
      signal CO             : std_logic_vector (6 downto 0);
      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);

begin 

      CS  <= CS1_ipd & CS0_ipd;
      WAD <= WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
      WD  <= WD47_ipd & WD46_ipd & WD45_ipd & WD44_ipd & WD43_ipd & WD42_ipd & WD41_ipd & WD40_ipd & WD39_ipd & WD38_ipd & WD37_ipd & WD36_ipd & WD35_ipd & WD34_ipd & WD33_ipd & WD32_ipd & WD31_ipd & WD30_ipd & WD29_ipd & WD28_ipd & WD27_ipd & WD26_ipd & WD25_ipd & WD24_ipd & WD23_ipd & WD22_ipd & WD21_ipd & WD20_ipd & WD19_ipd & WD18_ipd & WD17_ipd & WD16_ipd & WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
      CMI <= CMI127_ipd & CMI126_ipd & CMI125_ipd & CMI124_ipd & CMI123_ipd & CMI122_ipd & CMI121_ipd & CMI120_ipd & CMI119_ipd & CMI118_ipd & CMI117_ipd & CMI116_ipd & CMI115_ipd & CMI114_ipd & CMI113_ipd & CMI112_ipd & CMI111_ipd & CMI110_ipd & CMI109_ipd & CMI108_ipd & CMI107_ipd & CMI106_ipd & CMI105_ipd & CMI104_ipd & CMI103_ipd & CMI102_ipd & CMI101_ipd & CMI100_ipd & CMI99_ipd & CMI98_ipd & CMI97_ipd & CMI96_ipd & CMI95_ipd & CMI94_ipd & CMI93_ipd & CMI92_ipd & CMI91_ipd & CMI90_ipd & CMI89_ipd & CMI88_ipd & CMI87_ipd & CMI86_ipd & CMI85_ipd & CMI84_ipd & CMI83_ipd & CMI82_ipd & CMI81_ipd & CMI80_ipd & CMI79_ipd & CMI78_ipd & CMI77_ipd & CMI76_ipd & CMI75_ipd & CMI74_ipd & CMI73_ipd & CMI72_ipd & CMI71_ipd & CMI70_ipd & CMI69_ipd & CMI68_ipd & CMI67_ipd & CMI66_ipd & CMI65_ipd & CMI64_ipd & CMI63_ipd & CMI62_ipd & CMI61_ipd & CMI60_ipd & CMI59_ipd & CMI58_ipd & CMI57_ipd & CMI56_ipd & CMI55_ipd & CMI54_ipd & CMI53_ipd & CMI52_ipd & CMI51_ipd & CMI50_ipd & CMI49_ipd & CMI48_ipd & CMI47_ipd & CMI46_ipd & CMI45_ipd & CMI44_ipd & CMI43_ipd & CMI42_ipd & CMI41_ipd & CMI40_ipd & CMI39_ipd & CMI38_ipd & CMI37_ipd & CMI36_ipd & CMI35_ipd & CMI34_ipd & CMI33_ipd & CMI32_ipd & CMI31_ipd & CMI30_ipd & CMI29_ipd & CMI28_ipd & CMI27_ipd & CMI26_ipd & CMI25_ipd & CMI24_ipd & CMI23_ipd & CMI22_ipd & CMI21_ipd & CMI20_ipd & CMI19_ipd & CMI18_ipd & CMI17_ipd & CMI16_ipd & CMI15_ipd & CMI14_ipd & CMI13_ipd & CMI12_ipd & CMI11_ipd & CMI10_ipd & CMI9_ipd & CMI8_ipd & CMI7_ipd & CMI6_ipd & CMI5_ipd & CMI4_ipd & CMI3_ipd & CMI2_ipd & CMI1_ipd & CMI0_ipd;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (CE_ipd, CE, tipd_CE);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (CLK_ipd, CLK, tipd_CLK);

        VitalWireDelay (EN_MASK_ipd, EN_MASK, tipd_EN_MASK);
        VitalWireDelay (WR_MASK_ipd, WR_MASK, tipd_WR_MASK);

        VitalWireDelay (WR_DC_ipd, WR_DC, tipd_WR_DC);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (CS0_ipd, CS0, tipd_CS0);
        VitalWireDelay (CS1_ipd, CS1, tipd_CS1);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);
        VitalWireDelay (WD16_ipd, WD16, tipd_WD16);
        VitalWireDelay (WD17_ipd, WD17, tipd_WD17);
        VitalWireDelay (WD18_ipd, WD18, tipd_WD18);
        VitalWireDelay (WD19_ipd, WD19, tipd_WD19);
        VitalWireDelay (WD20_ipd, WD20, tipd_WD20);
        VitalWireDelay (WD21_ipd, WD21, tipd_WD21);
        VitalWireDelay (WD22_ipd, WD22, tipd_WD22);
        VitalWireDelay (WD23_ipd, WD23, tipd_WD23);
        VitalWireDelay (WD24_ipd, WD24, tipd_WD24);
        VitalWireDelay (WD25_ipd, WD25, tipd_WD25);
        VitalWireDelay (WD26_ipd, WD26, tipd_WD26);
        VitalWireDelay (WD27_ipd, WD27, tipd_WD27);
        VitalWireDelay (WD28_ipd, WD28, tipd_WD28);
        VitalWireDelay (WD29_ipd, WD29, tipd_WD29);
        VitalWireDelay (WD30_ipd, WD30, tipd_WD30);
        VitalWireDelay (WD31_ipd, WD31, tipd_WD31);
        VitalWireDelay (WD32_ipd, WD32, tipd_WD32);
        VitalWireDelay (WD33_ipd, WD33, tipd_WD33);
        VitalWireDelay (WD34_ipd, WD34, tipd_WD34);
        VitalWireDelay (WD35_ipd, WD35, tipd_WD35);
        VitalWireDelay (WD36_ipd, WD36, tipd_WD36);
        VitalWireDelay (WD37_ipd, WD37, tipd_WD37);
        VitalWireDelay (WD38_ipd, WD38, tipd_WD38);
        VitalWireDelay (WD39_ipd, WD39, tipd_WD39);
        VitalWireDelay (WD40_ipd, WD40, tipd_WD40);
        VitalWireDelay (WD41_ipd, WD41, tipd_WD41);
        VitalWireDelay (WD42_ipd, WD42, tipd_WD42);
        VitalWireDelay (WD43_ipd, WD43, tipd_WD43);
        VitalWireDelay (WD44_ipd, WD44, tipd_WD44);
        VitalWireDelay (WD45_ipd, WD45, tipd_WD45);
        VitalWireDelay (WD46_ipd, WD46, tipd_WD46);
        VitalWireDelay (WD47_ipd, WD47, tipd_WD47);
        VitalWireDelay (CMI0_ipd, CMI0, tipd_CMI0);
        VitalWireDelay (CMI1_ipd, CMI1, tipd_CMI1);
        VitalWireDelay (CMI2_ipd, CMI2, tipd_CMI2);
        VitalWireDelay (CMI3_ipd, CMI3, tipd_CMI3);
        VitalWireDelay (CMI4_ipd, CMI4, tipd_CMI4);
        VitalWireDelay (CMI5_ipd, CMI5, tipd_CMI5);
        VitalWireDelay (CMI6_ipd, CMI6, tipd_CMI6);
        VitalWireDelay (CMI7_ipd, CMI7, tipd_CMI7);
        VitalWireDelay (CMI8_ipd, CMI8, tipd_CMI8);
        VitalWireDelay (CMI9_ipd, CMI9, tipd_CMI9);
        VitalWireDelay (CMI10_ipd, CMI10, tipd_CMI10);
        VitalWireDelay (CMI11_ipd, CMI11, tipd_CMI11);
        VitalWireDelay (CMI12_ipd, CMI12, tipd_CMI12);
        VitalWireDelay (CMI13_ipd, CMI13, tipd_CMI13);
        VitalWireDelay (CMI14_ipd, CMI14, tipd_CMI14);
        VitalWireDelay (CMI15_ipd, CMI15, tipd_CMI15);
        VitalWireDelay (CMI16_ipd, CMI16, tipd_CMI16);
        VitalWireDelay (CMI17_ipd, CMI17, tipd_CMI17);
        VitalWireDelay (CMI18_ipd, CMI18, tipd_CMI18);
        VitalWireDelay (CMI19_ipd, CMI19, tipd_CMI19);
        VitalWireDelay (CMI20_ipd, CMI20, tipd_CMI20);
        VitalWireDelay (CMI21_ipd, CMI21, tipd_CMI21);
        VitalWireDelay (CMI22_ipd, CMI22, tipd_CMI22);
        VitalWireDelay (CMI23_ipd, CMI23, tipd_CMI23);
        VitalWireDelay (CMI24_ipd, CMI24, tipd_CMI24);
        VitalWireDelay (CMI25_ipd, CMI25, tipd_CMI25);
        VitalWireDelay (CMI26_ipd, CMI26, tipd_CMI26);
        VitalWireDelay (CMI27_ipd, CMI27, tipd_CMI27);
        VitalWireDelay (CMI28_ipd, CMI28, tipd_CMI28);
        VitalWireDelay (CMI29_ipd, CMI29, tipd_CMI29);
        VitalWireDelay (CMI30_ipd, CMI30, tipd_CMI30);
        VitalWireDelay (CMI31_ipd, CMI31, tipd_CMI31);
        VitalWireDelay (CMI32_ipd, CMI32, tipd_CMI32);
        VitalWireDelay (CMI33_ipd, CMI33, tipd_CMI33);
        VitalWireDelay (CMI34_ipd, CMI34, tipd_CMI34);
        VitalWireDelay (CMI35_ipd, CMI35, tipd_CMI35);
        VitalWireDelay (CMI36_ipd, CMI36, tipd_CMI36);
        VitalWireDelay (CMI37_ipd, CMI37, tipd_CMI37);
        VitalWireDelay (CMI38_ipd, CMI38, tipd_CMI38);
        VitalWireDelay (CMI39_ipd, CMI39, tipd_CMI39);
        VitalWireDelay (CMI40_ipd, CMI40, tipd_CMI40);
        VitalWireDelay (CMI41_ipd, CMI41, tipd_CMI41);
        VitalWireDelay (CMI42_ipd, CMI42, tipd_CMI42);
        VitalWireDelay (CMI43_ipd, CMI43, tipd_CMI43);
        VitalWireDelay (CMI44_ipd, CMI44, tipd_CMI44);
        VitalWireDelay (CMI45_ipd, CMI45, tipd_CMI45);
        VitalWireDelay (CMI46_ipd, CMI46, tipd_CMI46);
        VitalWireDelay (CMI47_ipd, CMI47, tipd_CMI47);
        VitalWireDelay (CMI48_ipd, CMI48, tipd_CMI48);
        VitalWireDelay (CMI49_ipd, CMI49, tipd_CMI49);
        VitalWireDelay (CMI50_ipd, CMI50, tipd_CMI50);
        VitalWireDelay (CMI51_ipd, CMI51, tipd_CMI51);
        VitalWireDelay (CMI52_ipd, CMI52, tipd_CMI52);
        VitalWireDelay (CMI53_ipd, CMI53, tipd_CMI53);
        VitalWireDelay (CMI54_ipd, CMI54, tipd_CMI54);
        VitalWireDelay (CMI55_ipd, CMI55, tipd_CMI55);
        VitalWireDelay (CMI56_ipd, CMI56, tipd_CMI56);
        VitalWireDelay (CMI57_ipd, CMI57, tipd_CMI57);
        VitalWireDelay (CMI58_ipd, CMI58, tipd_CMI58);
        VitalWireDelay (CMI59_ipd, CMI59, tipd_CMI59);
        VitalWireDelay (CMI60_ipd, CMI60, tipd_CMI60);
        VitalWireDelay (CMI61_ipd, CMI61, tipd_CMI61);
        VitalWireDelay (CMI62_ipd, CMI62, tipd_CMI62);
        VitalWireDelay (CMI63_ipd, CMI63, tipd_CMI63);
        VitalWireDelay (CMI64_ipd, CMI64, tipd_CMI64);
        VitalWireDelay (CMI65_ipd, CMI65, tipd_CMI65);
        VitalWireDelay (CMI66_ipd, CMI66, tipd_CMI66);
        VitalWireDelay (CMI67_ipd, CMI67, tipd_CMI67);
        VitalWireDelay (CMI68_ipd, CMI68, tipd_CMI68);
        VitalWireDelay (CMI69_ipd, CMI69, tipd_CMI69);
        VitalWireDelay (CMI70_ipd, CMI70, tipd_CMI70);
        VitalWireDelay (CMI71_ipd, CMI71, tipd_CMI71);
        VitalWireDelay (CMI72_ipd, CMI72, tipd_CMI72);
        VitalWireDelay (CMI73_ipd, CMI73, tipd_CMI73);
        VitalWireDelay (CMI74_ipd, CMI74, tipd_CMI74);
        VitalWireDelay (CMI75_ipd, CMI75, tipd_CMI75);
        VitalWireDelay (CMI76_ipd, CMI76, tipd_CMI76);
        VitalWireDelay (CMI77_ipd, CMI77, tipd_CMI77);
        VitalWireDelay (CMI78_ipd, CMI78, tipd_CMI78);
        VitalWireDelay (CMI79_ipd, CMI79, tipd_CMI79);
        VitalWireDelay (CMI80_ipd, CMI80, tipd_CMI80);
        VitalWireDelay (CMI81_ipd, CMI81, tipd_CMI81);
        VitalWireDelay (CMI82_ipd, CMI82, tipd_CMI82);
        VitalWireDelay (CMI83_ipd, CMI83, tipd_CMI83);
        VitalWireDelay (CMI84_ipd, CMI84, tipd_CMI84);
        VitalWireDelay (CMI85_ipd, CMI85, tipd_CMI85);
        VitalWireDelay (CMI86_ipd, CMI86, tipd_CMI86);
        VitalWireDelay (CMI87_ipd, CMI87, tipd_CMI87);
        VitalWireDelay (CMI88_ipd, CMI88, tipd_CMI88);
        VitalWireDelay (CMI89_ipd, CMI89, tipd_CMI89);
        VitalWireDelay (CMI90_ipd, CMI90, tipd_CMI90);
        VitalWireDelay (CMI91_ipd, CMI91, tipd_CMI91);
        VitalWireDelay (CMI92_ipd, CMI92, tipd_CMI92);
        VitalWireDelay (CMI93_ipd, CMI93, tipd_CMI93);
        VitalWireDelay (CMI94_ipd, CMI94, tipd_CMI94);
        VitalWireDelay (CMI95_ipd, CMI95, tipd_CMI95);
        VitalWireDelay (CMI96_ipd, CMI96, tipd_CMI96);
        VitalWireDelay (CMI97_ipd, CMI97, tipd_CMI97);
        VitalWireDelay (CMI98_ipd, CMI98, tipd_CMI98);
        VitalWireDelay (CMI99_ipd, CMI99, tipd_CMI99);
        VitalWireDelay (CMI100_ipd, CMI100, tipd_CMI100);
        VitalWireDelay (CMI101_ipd, CMI101, tipd_CMI101);
        VitalWireDelay (CMI102_ipd, CMI102, tipd_CMI102);
        VitalWireDelay (CMI103_ipd, CMI103, tipd_CMI103);
        VitalWireDelay (CMI104_ipd, CMI104, tipd_CMI104);
        VitalWireDelay (CMI105_ipd, CMI105, tipd_CMI105);
        VitalWireDelay (CMI106_ipd, CMI106, tipd_CMI106);
        VitalWireDelay (CMI107_ipd, CMI107, tipd_CMI107);
        VitalWireDelay (CMI108_ipd, CMI108, tipd_CMI108);
        VitalWireDelay (CMI109_ipd, CMI109, tipd_CMI109);
        VitalWireDelay (CMI110_ipd, CMI110, tipd_CMI110);
        VitalWireDelay (CMI111_ipd, CMI111, tipd_CMI111);
        VitalWireDelay (CMI112_ipd, CMI112, tipd_CMI112);
        VitalWireDelay (CMI113_ipd, CMI113, tipd_CMI113);
        VitalWireDelay (CMI114_ipd, CMI114, tipd_CMI114);
        VitalWireDelay (CMI115_ipd, CMI115, tipd_CMI115);
        VitalWireDelay (CMI116_ipd, CMI116, tipd_CMI116);
        VitalWireDelay (CMI117_ipd, CMI117, tipd_CMI117);
        VitalWireDelay (CMI118_ipd, CMI118, tipd_CMI118);
        VitalWireDelay (CMI119_ipd, CMI119, tipd_CMI119);
        VitalWireDelay (CMI120_ipd, CMI120, tipd_CMI120);
        VitalWireDelay (CMI121_ipd, CMI121, tipd_CMI121);
        VitalWireDelay (CMI122_ipd, CMI122, tipd_CMI122);
        VitalWireDelay (CMI123_ipd, CMI123, tipd_CMI123);
        VitalWireDelay (CMI124_ipd, CMI124, tipd_CMI124);
        VitalWireDelay (CMI125_ipd, CMI125, tipd_CMI125);
        VitalWireDelay (CMI126_ipd, CMI126, tipd_CMI126);
        VitalWireDelay (CMI127_ipd, CMI127, tipd_CMI127);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_CE_CLK_posedge      : std_ulogic  := '0';
        variable Tviol_WE_CLK_posedge      : std_ulogic  := '0';
        variable Tviol_EN_MASK_CLK_posedge      : std_ulogic  := '0';
        variable Tviol_WR_MASK_CLK_posedge      : std_ulogic  := '0';
        variable Tviol_WR_DC_CLK_posedge        : std_ulogic  := '0';
        variable Tviol_CS0_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_CS1_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WAD0_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD1_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD2_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD3_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD4_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD5_CLK_posedge         : std_ulogic  := '0';
        variable Tviol_WAD6_CLK_posedge         : std_ulogic  := '0';

        variable Tviol_WD0_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD1_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD2_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD3_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD4_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD5_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD6_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD7_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD8_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD9_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD10_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD11_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD12_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD13_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD14_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD15_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD16_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD17_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD18_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD19_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD20_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD21_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD22_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD23_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD24_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD25_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD26_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD27_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD28_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD29_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD30_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD31_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD32_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD33_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD34_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD35_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD36_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD37_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD38_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD39_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD40_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD41_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD42_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD43_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD44_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD45_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD46_CLK_posedge          : std_ulogic  := '0';
        variable Tviol_WD47_CLK_posedge          : std_ulogic  := '0';

        variable Tviol_RST_CLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_CE_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WE_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EN_MASK_CLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_MASK_CLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WR_DC_CLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS0_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CS1_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD0_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_CLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD16_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD17_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD18_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD19_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD20_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD21_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD22_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD23_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD24_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD25_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD26_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD27_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD28_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD29_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD30_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD31_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD32_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD33_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD34_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD35_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD36_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD37_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD38_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD39_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD40_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD41_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD42_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD43_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD44_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD45_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD46_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD47_CLK_posedge       : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_CLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_CLK        : std_ulogic := '0';
        variable PInfo_CLK        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable CO0_zd          : std_ulogic := 'X';
        variable CO1_zd          : std_ulogic := 'X';
        variable CO2_zd          : std_ulogic := 'X';
        variable CO3_zd          : std_ulogic := 'X';
        variable CO4_zd          : std_ulogic := 'X';
        variable CO5_zd          : std_ulogic := 'X';
        variable CO6_zd          : std_ulogic := 'X';
        variable MATCH_zd        : std_ulogic := 'X'; --QQ05
        variable MUL_MATCH_zd    : std_ulogic := 'X'; --QQ05
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_posedge,
          TimingData              => Tmkr_CE_CLK_posedge,
          TestSignal              => CE_ipd,
          TestSignalName          => "CE",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE_CLK_noedge_posedge,
          SetupLow                => tsetup_CE_CLK_noedge_posedge,
          HoldLow                 => thold_CE_CLK_noedge_posedge,
          HoldHigh                => thold_CE_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_CLK_posedge,
          TimingData              => Tmkr_WE_CLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_CLK_noedge_posedge,
          SetupLow                => tsetup_WE_CLK_noedge_posedge,
          HoldLow                 => thold_WE_CLK_noedge_posedge,
          HoldHigh                => thold_WE_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_MASK_CLK_posedge,
          TimingData              => Tmkr_WR_MASK_CLK_posedge,
          TestSignal              => WR_MASK_ipd,
          TestSignalName          => "WR_MASK",
          TestDelay               => 0 ns,
          RefSignal               => CLk_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_MASK_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_MASK_CLK_noedge_posedge,
          HoldLow                 => thold_WR_MASK_CLK_noedge_posedge,
          HoldHigh                => thold_WR_MASK_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WR_DC_CLK_posedge,
          TimingData              => Tmkr_WR_DC_CLK_posedge,
          TestSignal              => WR_DC_ipd,
          TestSignalName          => "WR_RC",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WR_DC_CLK_noedge_posedge,
          SetupLow                => tsetup_WR_DC_CLK_noedge_posedge,
          HoldLow                 => thold_WR_DC_CLK_noedge_posedge,
          HoldHigh                => thold_WR_DC_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS0_CLK_posedge,
          TimingData              => Tmkr_CS0_CLK_posedge,
          TestSignal              => CS0_ipd,
          TestSignalName          => "CS0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS0_CLK_noedge_posedge,
          SetupLow                => tsetup_CS0_CLK_noedge_posedge,
          HoldLow                 => thold_CS0_CLK_noedge_posedge,
          HoldHigh                => thold_CS0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CS1_CLK_posedge,
          TimingData              => Tmkr_CS1_CLK_posedge,
          TestSignal              => CS1_ipd,
          TestSignalName          => "CS1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CS1_CLK_noedge_posedge,
          SetupLow                => tsetup_CS1_CLK_noedge_posedge,
          HoldLow                 => thold_CS1_CLK_noedge_posedge,
          HoldHigh                => thold_CS1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EN_MASK_CLK_posedge,
          TimingData              => Tmkr_EN_MASK_CLK_posedge,
          TestSignal              => EN_MASK_ipd,
          TestSignalName          => "EN_MASK",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EN_MASK_CLK_noedge_posedge,
          SetupLow                => tsetup_EN_MASK_CLK_noedge_posedge,
          HoldLow                 => thold_EN_MASK_CLK_noedge_posedge,
          HoldHigh                => thold_EN_MASK_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_CLK_posedge,
          TimingData              => Tmkr_WAD0_CLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_CLK_noedge_posedge,
          HoldLow                 => thold_WAD0_CLK_noedge_posedge,
          HoldHigh                => thold_WAD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_CLK_posedge,
          TimingData              => Tmkr_WAD1_CLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_CLK_noedge_posedge,
          HoldLow                 => thold_WAD1_CLK_noedge_posedge,
          HoldHigh                => thold_WAD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_CLK_posedge,
          TimingData              => Tmkr_WAD2_CLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_CLK_noedge_posedge,
          HoldLow                 => thold_WAD2_CLK_noedge_posedge,
          HoldHigh                => thold_WAD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_CLK_posedge,
          TimingData              => Tmkr_WAD3_CLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_CLK_noedge_posedge,
          HoldLow                 => thold_WAD3_CLK_noedge_posedge,
          HoldHigh                => thold_WAD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_CLK_posedge,
          TimingData              => Tmkr_WAD4_CLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_CLK_noedge_posedge,
          HoldLow                 => thold_WAD4_CLK_noedge_posedge,
          HoldHigh                => thold_WAD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_CLK_posedge,
          TimingData              => Tmkr_WAD5_CLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_CLK_noedge_posedge,
          HoldLow                 => thold_WAD5_CLK_noedge_posedge,
          HoldHigh                => thold_WAD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_CLK_posedge,
          TimingData              => Tmkr_WAD6_CLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_CLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_CLK_noedge_posedge,
          HoldLow                 => thold_WAD6_CLK_noedge_posedge,
          HoldHigh                => thold_WAD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_CLK_posedge,
          TimingData              => Tmkr_WD0_CLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_CLK_noedge_posedge,
          SetupLow                => tsetup_WD0_CLK_noedge_posedge,
          HoldLow                 => thold_WD0_CLK_noedge_posedge,
          HoldHigh                => thold_WD0_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_CLK_posedge,
          TimingData              => Tmkr_WD1_CLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_CLK_noedge_posedge,
          SetupLow                => tsetup_WD1_CLK_noedge_posedge,
          HoldLow                 => thold_WD1_CLK_noedge_posedge,
          HoldHigh                => thold_WD1_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_CLK_posedge,
          TimingData              => Tmkr_WD2_CLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_CLK_noedge_posedge,
          SetupLow                => tsetup_WD2_CLK_noedge_posedge,
          HoldLow                 => thold_WD2_CLK_noedge_posedge,
          HoldHigh                => thold_WD2_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_CLK_posedge,
          TimingData              => Tmkr_WD3_CLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_CLK_noedge_posedge,
          SetupLow                => tsetup_WD3_CLK_noedge_posedge,
          HoldLow                 => thold_WD3_CLK_noedge_posedge,
          HoldHigh                => thold_WD3_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_CLK_posedge,
          TimingData              => Tmkr_WD4_CLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_CLK_noedge_posedge,
          SetupLow                => tsetup_WD4_CLK_noedge_posedge,
          HoldLow                 => thold_WD4_CLK_noedge_posedge,
          HoldHigh                => thold_WD4_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_CLK_posedge,
          TimingData              => Tmkr_WD5_CLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_CLK_noedge_posedge,
          SetupLow                => tsetup_WD5_CLK_noedge_posedge,
          HoldLow                 => thold_WD5_CLK_noedge_posedge,
          HoldHigh                => thold_WD5_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_CLK_posedge,
          TimingData              => Tmkr_WD6_CLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_CLK_noedge_posedge,
          SetupLow                => tsetup_WD6_CLK_noedge_posedge,
          HoldLow                 => thold_WD6_CLK_noedge_posedge,
          HoldHigh                => thold_WD6_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_CLK_posedge,
          TimingData              => Tmkr_WD7_CLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_CLK_noedge_posedge,
          SetupLow                => tsetup_WD7_CLK_noedge_posedge,
          HoldLow                 => thold_WD7_CLK_noedge_posedge,
          HoldHigh                => thold_WD7_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_CLK_posedge,
          TimingData              => Tmkr_WD8_CLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_CLK_noedge_posedge,
          SetupLow                => tsetup_WD8_CLK_noedge_posedge,
          HoldLow                 => thold_WD8_CLK_noedge_posedge,
          HoldHigh                => thold_WD8_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_CLK_posedge,
          TimingData              => Tmkr_WD9_CLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_CLK_noedge_posedge,
          SetupLow                => tsetup_WD9_CLK_noedge_posedge,
          HoldLow                 => thold_WD9_CLK_noedge_posedge,
          HoldHigh                => thold_WD9_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_CLK_posedge,
          TimingData              => Tmkr_WD10_CLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_CLK_noedge_posedge,
          SetupLow                => tsetup_WD10_CLK_noedge_posedge,
          HoldLow                 => thold_WD10_CLK_noedge_posedge,
          HoldHigh                => thold_WD10_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_CLK_posedge,
          TimingData              => Tmkr_WD11_CLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_CLK_noedge_posedge,
          SetupLow                => tsetup_WD11_CLK_noedge_posedge,
          HoldLow                 => thold_WD11_CLK_noedge_posedge,
          HoldHigh                => thold_WD11_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_CLK_posedge,
          TimingData              => Tmkr_WD12_CLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_CLK_noedge_posedge,
          SetupLow                => tsetup_WD12_CLK_noedge_posedge,
          HoldLow                 => thold_WD12_CLK_noedge_posedge,
          HoldHigh                => thold_WD12_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_CLK_posedge,
          TimingData              => Tmkr_WD13_CLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_CLK_noedge_posedge,
          SetupLow                => tsetup_WD13_CLK_noedge_posedge,
          HoldLow                 => thold_WD13_CLK_noedge_posedge,
          HoldHigh                => thold_WD13_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_CLK_posedge,
          TimingData              => Tmkr_WD14_CLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_CLK_noedge_posedge,
          SetupLow                => tsetup_WD14_CLK_noedge_posedge,
          HoldLow                 => thold_WD14_CLK_noedge_posedge,
          HoldHigh                => thold_WD14_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_CLK_posedge,
          TimingData              => Tmkr_WD15_CLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_CLK_noedge_posedge,
          SetupLow                => tsetup_WD15_CLK_noedge_posedge,
          HoldLow                 => thold_WD15_CLK_noedge_posedge,
          HoldHigh                => thold_WD15_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD16_CLK_posedge,
          TimingData              => Tmkr_WD16_CLK_posedge,
          TestSignal              => WD16_ipd,
          TestSignalName          => "WD16",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD16_CLK_noedge_posedge,
          SetupLow                => tsetup_WD16_CLK_noedge_posedge,
          HoldLow                 => thold_WD16_CLK_noedge_posedge,
          HoldHigh                => thold_WD16_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD17_CLK_posedge,
          TimingData              => Tmkr_WD17_CLK_posedge,
          TestSignal              => WD17_ipd,
          TestSignalName          => "WD17",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD17_CLK_noedge_posedge,
          SetupLow                => tsetup_WD17_CLK_noedge_posedge,
          HoldLow                 => thold_WD17_CLK_noedge_posedge,
          HoldHigh                => thold_WD17_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD18_CLK_posedge,
          TimingData              => Tmkr_WD18_CLK_posedge,
          TestSignal              => WD18_ipd,
          TestSignalName          => "WD18",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD18_CLK_noedge_posedge,
          SetupLow                => tsetup_WD18_CLK_noedge_posedge,
          HoldLow                 => thold_WD18_CLK_noedge_posedge,
          HoldHigh                => thold_WD18_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD19_CLK_posedge,
          TimingData              => Tmkr_WD19_CLK_posedge,
          TestSignal              => WD19_ipd,
          TestSignalName          => "WD19",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD19_CLK_noedge_posedge,
          SetupLow                => tsetup_WD19_CLK_noedge_posedge,
          HoldLow                 => thold_WD19_CLK_noedge_posedge,
          HoldHigh                => thold_WD19_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD20_CLK_posedge,
          TimingData              => Tmkr_WD20_CLK_posedge,
          TestSignal              => WD20_ipd,
          TestSignalName          => "WD20",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD20_CLK_noedge_posedge,
          SetupLow                => tsetup_WD20_CLK_noedge_posedge,
          HoldLow                 => thold_WD20_CLK_noedge_posedge,
          HoldHigh                => thold_WD20_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD21_CLK_posedge,
          TimingData              => Tmkr_WD21_CLK_posedge,
          TestSignal              => WD21_ipd,
          TestSignalName          => "WD21",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD21_CLK_noedge_posedge,
          SetupLow                => tsetup_WD21_CLK_noedge_posedge,
          HoldLow                 => thold_WD21_CLK_noedge_posedge,
          HoldHigh                => thold_WD21_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD22_CLK_posedge,
          TimingData              => Tmkr_WD22_CLK_posedge,
          TestSignal              => WD22_ipd,
          TestSignalName          => "WD22",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD22_CLK_noedge_posedge,
          SetupLow                => tsetup_WD22_CLK_noedge_posedge,
          HoldLow                 => thold_WD22_CLK_noedge_posedge,
          HoldHigh                => thold_WD22_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD23_CLK_posedge,
          TimingData              => Tmkr_WD23_CLK_posedge,
          TestSignal              => WD23_ipd,
          TestSignalName          => "WD23",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD23_CLK_noedge_posedge,
          SetupLow                => tsetup_WD23_CLK_noedge_posedge,
          HoldLow                 => thold_WD23_CLK_noedge_posedge,
          HoldHigh                => thold_WD23_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD24_CLK_posedge,
          TimingData              => Tmkr_WD24_CLK_posedge,
          TestSignal              => WD24_ipd,
          TestSignalName          => "WD24",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD24_CLK_noedge_posedge,
          SetupLow                => tsetup_WD24_CLK_noedge_posedge,
          HoldLow                 => thold_WD24_CLK_noedge_posedge,
          HoldHigh                => thold_WD24_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD25_CLK_posedge,
          TimingData              => Tmkr_WD25_CLK_posedge,
          TestSignal              => WD25_ipd,
          TestSignalName          => "WD25",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD25_CLK_noedge_posedge,
          SetupLow                => tsetup_WD25_CLK_noedge_posedge,
          HoldLow                 => thold_WD25_CLK_noedge_posedge,
          HoldHigh                => thold_WD25_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD26_CLK_posedge,
          TimingData              => Tmkr_WD26_CLK_posedge,
          TestSignal              => WD26_ipd,
          TestSignalName          => "WD26",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD26_CLK_noedge_posedge,
          SetupLow                => tsetup_WD26_CLK_noedge_posedge,
          HoldLow                 => thold_WD26_CLK_noedge_posedge,
          HoldHigh                => thold_WD26_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD27_CLK_posedge,
          TimingData              => Tmkr_WD27_CLK_posedge,
          TestSignal              => WD27_ipd,
          TestSignalName          => "WD27",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD27_CLK_noedge_posedge,
          SetupLow                => tsetup_WD27_CLK_noedge_posedge,
          HoldLow                 => thold_WD27_CLK_noedge_posedge,
          HoldHigh                => thold_WD27_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD28_CLK_posedge,
          TimingData              => Tmkr_WD28_CLK_posedge,
          TestSignal              => WD28_ipd,
          TestSignalName          => "WD28",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD28_CLK_noedge_posedge,
          SetupLow                => tsetup_WD28_CLK_noedge_posedge,
          HoldLow                 => thold_WD28_CLK_noedge_posedge,
          HoldHigh                => thold_WD28_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD29_CLK_posedge,
          TimingData              => Tmkr_WD29_CLK_posedge,
          TestSignal              => WD29_ipd,
          TestSignalName          => "WD29",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD29_CLK_noedge_posedge,
          SetupLow                => tsetup_WD29_CLK_noedge_posedge,
          HoldLow                 => thold_WD29_CLK_noedge_posedge,
          HoldHigh                => thold_WD29_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD30_CLK_posedge,
          TimingData              => Tmkr_WD30_CLK_posedge,
          TestSignal              => WD30_ipd,
          TestSignalName          => "WD30",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD30_CLK_noedge_posedge,
          SetupLow                => tsetup_WD30_CLK_noedge_posedge,
          HoldLow                 => thold_WD30_CLK_noedge_posedge,
          HoldHigh                => thold_WD30_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD31_CLK_posedge,
          TimingData              => Tmkr_WD31_CLK_posedge,
          TestSignal              => WD31_ipd,
          TestSignalName          => "WD31",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD31_CLK_noedge_posedge,
          SetupLow                => tsetup_WD31_CLK_noedge_posedge,
          HoldLow                 => thold_WD31_CLK_noedge_posedge,
          HoldHigh                => thold_WD31_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD32_CLK_posedge,
          TimingData              => Tmkr_WD32_CLK_posedge,
          TestSignal              => WD32_ipd,
          TestSignalName          => "WD32",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD32_CLK_noedge_posedge,
          SetupLow                => tsetup_WD32_CLK_noedge_posedge,
          HoldLow                 => thold_WD32_CLK_noedge_posedge,
          HoldHigh                => thold_WD32_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD33_CLK_posedge,
          TimingData              => Tmkr_WD33_CLK_posedge,
          TestSignal              => WD33_ipd,
          TestSignalName          => "WD33",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD33_CLK_noedge_posedge,
          SetupLow                => tsetup_WD33_CLK_noedge_posedge,
          HoldLow                 => thold_WD33_CLK_noedge_posedge,
          HoldHigh                => thold_WD33_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD34_CLK_posedge,
          TimingData              => Tmkr_WD34_CLK_posedge,
          TestSignal              => WD34_ipd,
          TestSignalName          => "WD34",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD34_CLK_noedge_posedge,
          SetupLow                => tsetup_WD34_CLK_noedge_posedge,
          HoldLow                 => thold_WD34_CLK_noedge_posedge,
          HoldHigh                => thold_WD34_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD35_CLK_posedge,
          TimingData              => Tmkr_WD35_CLK_posedge,
          TestSignal              => WD35_ipd,
          TestSignalName          => "WD35",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD35_CLK_noedge_posedge,
          SetupLow                => tsetup_WD35_CLK_noedge_posedge,
          HoldLow                 => thold_WD35_CLK_noedge_posedge,
          HoldHigh                => thold_WD35_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD36_CLK_posedge,
          TimingData              => Tmkr_WD36_CLK_posedge,
          TestSignal              => WD36_ipd,
          TestSignalName          => "WD36",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD36_CLK_noedge_posedge,
          SetupLow                => tsetup_WD36_CLK_noedge_posedge,
          HoldLow                 => thold_WD36_CLK_noedge_posedge,
          HoldHigh                => thold_WD36_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD37_CLK_posedge,
          TimingData              => Tmkr_WD37_CLK_posedge,
          TestSignal              => WD37_ipd,
          TestSignalName          => "WD37",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD37_CLK_noedge_posedge,
          SetupLow                => tsetup_WD37_CLK_noedge_posedge,
          HoldLow                 => thold_WD37_CLK_noedge_posedge,
          HoldHigh                => thold_WD37_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD38_CLK_posedge,
          TimingData              => Tmkr_WD38_CLK_posedge,
          TestSignal              => WD38_ipd,
          TestSignalName          => "WD38",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD38_CLK_noedge_posedge,
          SetupLow                => tsetup_WD38_CLK_noedge_posedge,
          HoldLow                 => thold_WD38_CLK_noedge_posedge,
          HoldHigh                => thold_WD38_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD39_CLK_posedge,
          TimingData              => Tmkr_WD39_CLK_posedge,
          TestSignal              => WD39_ipd,
          TestSignalName          => "WD39",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD39_CLK_noedge_posedge,
          SetupLow                => tsetup_WD39_CLK_noedge_posedge,
          HoldLow                 => thold_WD39_CLK_noedge_posedge,
          HoldHigh                => thold_WD39_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD40_CLK_posedge,
          TimingData              => Tmkr_WD40_CLK_posedge,
          TestSignal              => WD40_ipd,
          TestSignalName          => "WD40",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD40_CLK_noedge_posedge,
          SetupLow                => tsetup_WD40_CLK_noedge_posedge,
          HoldLow                 => thold_WD40_CLK_noedge_posedge,
          HoldHigh                => thold_WD40_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD41_CLK_posedge,
          TimingData              => Tmkr_WD41_CLK_posedge,
          TestSignal              => WD41_ipd,
          TestSignalName          => "WD41",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD41_CLK_noedge_posedge,
          SetupLow                => tsetup_WD41_CLK_noedge_posedge,
          HoldLow                 => thold_WD41_CLK_noedge_posedge,
          HoldHigh                => thold_WD41_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD42_CLK_posedge,
          TimingData              => Tmkr_WD42_CLK_posedge,
          TestSignal              => WD42_ipd,
          TestSignalName          => "WD42",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD42_CLK_noedge_posedge,
          SetupLow                => tsetup_WD42_CLK_noedge_posedge,
          HoldLow                 => thold_WD42_CLK_noedge_posedge,
          HoldHigh                => thold_WD42_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD43_CLK_posedge,
          TimingData              => Tmkr_WD43_CLK_posedge,
          TestSignal              => WD43_ipd,
          TestSignalName          => "WD43",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD43_CLK_noedge_posedge,
          SetupLow                => tsetup_WD43_CLK_noedge_posedge,
          HoldLow                 => thold_WD43_CLK_noedge_posedge,
          HoldHigh                => thold_WD43_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD44_CLK_posedge,
          TimingData              => Tmkr_WD44_CLK_posedge,
          TestSignal              => WD44_ipd,
          TestSignalName          => "WD44",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD44_CLK_noedge_posedge,
          SetupLow                => tsetup_WD44_CLK_noedge_posedge,
          HoldLow                 => thold_WD44_CLK_noedge_posedge,
          HoldHigh                => thold_WD44_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD45_CLK_posedge,
          TimingData              => Tmkr_WD45_CLK_posedge,
          TestSignal              => WD45_ipd,
          TestSignalName          => "WD45",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD45_CLK_noedge_posedge,
          SetupLow                => tsetup_WD45_CLK_noedge_posedge,
          HoldLow                 => thold_WD45_CLK_noedge_posedge,
          HoldHigh                => thold_WD45_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD46_CLK_posedge,
          TimingData              => Tmkr_WD46_CLK_posedge,
          TestSignal              => WD46_ipd,
          TestSignalName          => "WD46",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD46_CLK_noedge_posedge,
          SetupLow                => tsetup_WD46_CLK_noedge_posedge,
          HoldLow                 => thold_WD46_CLK_noedge_posedge,
          HoldHigh                => thold_WD46_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD47_CLK_posedge,
          TimingData              => Tmkr_WD47_CLK_posedge,
          TestSignal              => WD47_ipd,
          TestSignalName          => "WD47",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD47_CLK_noedge_posedge,
          SetupLow                => tsetup_WD47_CLK_noedge_posedge,
          HoldLow                 => thold_WD47_CLK_noedge_posedge,
          HoldHigh                => thold_WD47_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/CAM128X48CR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/CAM128X48CR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_CLK_posedge_posedge,
          TimingData              => Tmkr_RST_CLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_CLK_posedge_posedge,
          Removal                 => thold_RST_CLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/CAM128X48CR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_CE_CLK_posedge or Tviol_WE_CLK_posedge or 
                 Tviol_EN_MASK_CLK_posedge or Tviol_EN_MASK_CLK_posedge or 
                 Tviol_WR_DC_CLK_posedge or Tviol_CS0_CLK_posedge or Tviol_CS1_CLK_posedge or 
                 Tviol_WAD0_CLK_posedge or Tviol_WAD1_CLK_posedge or 
                 Tviol_WAD2_CLK_posedge or Tviol_WAD3_CLK_posedge or 
                 Tviol_WAD4_CLK_posedge or Tviol_WAD4_CLK_posedge or 
                 Tviol_WAD6_CLK_posedge or 
                 Tviol_WD0_CLK_posedge or Tviol_WD1_CLK_posedge or 
                 Tviol_WD2_CLK_posedge or Tviol_WD3_CLK_posedge or 
                 Tviol_WD4_CLK_posedge or Tviol_WD5_CLK_posedge or 
                 Tviol_WD6_CLK_posedge or Tviol_WD7_CLK_posedge or 
                 Tviol_WD8_CLK_posedge or Tviol_WD9_CLK_posedge or 
                 Tviol_WD10_CLK_posedge or Tviol_WD11_CLK_posedge or 
                 Tviol_WD12_CLK_posedge or Tviol_WD13_CLK_posedge or 
                 Tviol_WD14_CLK_posedge or Tviol_WD15_CLK_posedge or 
                 Tviol_WD16_CLK_posedge or Tviol_WD17_CLK_posedge or 
                 Tviol_WD18_CLK_posedge or Tviol_WD19_CLK_posedge or 
                 Tviol_WD20_CLK_posedge or Tviol_WD21_CLK_posedge or 
                 Tviol_WD22_CLK_posedge or Tviol_WD23_CLK_posedge or 
                 Tviol_WD24_CLK_posedge or Tviol_WD25_CLK_posedge or 
                 Tviol_WD26_CLK_posedge or Tviol_WD27_CLK_posedge or 
                 Tviol_WD28_CLK_posedge or Tviol_WD29_CLK_posedge or 
                 Tviol_WD30_CLK_posedge or Tviol_WD31_CLK_posedge or 
                 Tviol_WD32_CLK_posedge or Tviol_WD33_CLK_posedge or 
                 Tviol_WD34_CLK_posedge or Tviol_WD35_CLK_posedge or 
                 Tviol_WD36_CLK_posedge or Tviol_WD37_CLK_posedge or 
                 Tviol_WD38_CLK_posedge or Tviol_WD39_CLK_posedge or 
                 Tviol_WD40_CLK_posedge or Tviol_WD41_CLK_posedge or 
                 Tviol_WD42_CLK_posedge or Tviol_WD43_CLK_posedge or 
                 Tviol_WD44_CLK_posedge or Tviol_WD45_CLK_posedge or 
                 Tviol_WD46_CLK_posedge or Tviol_WD47_CLK_posedge or 
                 Pviol_CLK or Pviol_RST or 
                 Tviol_RST_CLK_posedge_posedge; 

    -------------------------
    --  Functionality Section
    -------------------------

wait on CE_ipd, WE_ipd, CLK_ipd, EN_MASK_ipd, WR_MASK_ipd, WR_DC_ipd, CS, WAD, WD, CMI;

      end process VITALBehavior;

      VITALBehavior_C0 : process
        variable CO0_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;
      begin
    -------------------------
    --  Functionality Section
    -------------------------
    CO0_zd := CO(0);

    VitalPathDelay01 (
      OutSignal => CO0,
      GlitchData => O_GlitchData,
      OutSignalName => "CO0",
      OutTemp => CO0_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_CO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_CO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on CO(0);
      end process VITALBehavior_C0;

      VITALBehavior_C1 : process
        variable CO1_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;
      begin
    -------------------------
    --  Functionality Section
    -------------------------
    CO1_zd := CO(1);

    VitalPathDelay01 (
      OutSignal => CO1,
      GlitchData => O_GlitchData,
      OutSignalName => "CO1",
      OutTemp => CO1_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_CO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_CO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on CO(1);
      end process VITALBehavior_C1;

      VITALBehavior_C2 : process
        variable CO2_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;
      begin
    -------------------------
    --  Functionality Section
    -------------------------
    CO2_zd := CO(2);

    VitalPathDelay01 (
      OutSignal => CO2,
      GlitchData => O_GlitchData,
      OutSignalName => "CO2",
      OutTemp => CO2_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_CO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_CO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on CO(2);
      end process VITALBehavior_C2;

      VITALBehavior_C3 : process
        variable CO3_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;
      begin
    -------------------------
    --  Functionality Section
    -------------------------
    CO3_zd := CO(3);

    VitalPathDelay01 (
      OutSignal => CO3,
      GlitchData => O_GlitchData,
      OutSignalName => "CO3",
      OutTemp => CO3_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_CO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_CO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on CO(3);
      end process VITALBehavior_C3;

      VITALBehavior_C4 : process
        variable CO4_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;
      begin
    -------------------------
    --  Functionality Section
    -------------------------
    CO4_zd := CO(4);

    VitalPathDelay01 (
      OutSignal => CO4,
      GlitchData => O_GlitchData,
      OutSignalName => "CO4",
      OutTemp => CO4_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_CO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_CO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on CO(4);
      end process VITALBehavior_C4;

      VITALBehavior_C5 : process
        variable CO5_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;
      begin
    -------------------------
    --  Functionality Section
    -------------------------
    CO5_zd := CO(5);

    VitalPathDelay01 (
      OutSignal => CO5,
      GlitchData => O_GlitchData,
      OutSignalName => "CO5",
      OutTemp => CO5_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_CO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_CO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on CO(5);
      end process VITALBehavior_C5;

      VITALBehavior_C6 : process
        variable CO6_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;
      begin
    -------------------------
    --  Functionality Section
    -------------------------
    CO6_zd := CO(6);

    VitalPathDelay01 (
      OutSignal => CO6,
      GlitchData => O_GlitchData,
      OutSignalName => "CO6",
      OutTemp => CO6_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_CO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_CO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on CO(6);
      end process VITALBehavior_C6;
--QQ05
    VITALBehavior_MATCH : process
        variable MATCH_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;
      begin
    -------------------------
    --  Functionality Section
    -------------------------
    MATCH_zd := MATCH_ipd;

    VitalPathDelay01 (
      OutSignal => MATCH,
      GlitchData => O_GlitchData,
      OutSignalName => "MATCH",
      OutTemp => MATCH_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_MATCH, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_MATCH, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on MATCH_ipd;
      end process VITALBehavior_MATCH;

    VITALBehavior_MUL_MATCH : process
        variable MUL_MATCH_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;
      begin
    -------------------------
    --  Functionality Section
    -------------------------
    MUL_MATCH_zd := MUL_MATCH_ipd;

    VitalPathDelay01 (
      OutSignal => MUL_MATCH,
      GlitchData => O_GlitchData,
      OutSignalName => "MUL_MATCH",
      OutTemp => MUL_MATCH_zd,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_MUL_MATCH, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_MUL_MATCH, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on MUL_MATCH_ipd;
      end process VITALBehavior_MUL_MATCH;
--QQ05
	CAMCR_inst : SC_CAMCR_16K

	generic map (
		ADDR_WIDTH    =>  7,
		DATA_WIDTH    =>  48,
		MEM_INIT_FLAG => RAM_INIT_FLAG,
                MEM_INIT_FILE => RAM_INIT_FILE
		)
	port map (
		CE        => CE_ipd,
		WE        => WE_ipd,
		CLK       => CLK_ipd,
		EN_MASK   => EN_MASK_ipd,
		WR_MASK   => WR_MASK_ipd,
		WR_DC     => WR_DC_ipd,
		RST       => RST_ipd,
		CS        => CS,
		WAD       => WAD,
		WD        => WD,
                CMI       => CMI,
		CO        => CO,
		MATCH     => MATCH_ipd,
		MUL_MATCH => MUL_MATCH_ipd
                );

end VITAL;

configuration CFG_CAM128X48CR_VITAL of CAM128X48CR is
   for VITAL
   end for;
end CFG_CAM128X48CR_VITAL;


-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
-- L_CAM
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

entity l_cam is
  generic (
	    lpm_type               : string  := "LPM_CAM";
	    lpm_width              : integer := 1;
	    lpm_numwords           : integer := 1;
	    lpm_widthad            : integer := 1;
            lpm_init_file          : string := "";
	    lpm_hint               : string  := "UNUSED");
   port(
      ClockEn                      :	in    STD_ULOGIC;
      WE                           :	in    STD_ULOGIC;
      Clock                        :	in    STD_ULOGIC;
      EnMask                       :	in    STD_ULOGIC;
      WrMask                       :	in    STD_ULOGIC;
      WrDC                         :	in    STD_ULOGIC;
      Reset                        :	in    STD_ULOGIC;
      WrAddress                    :	in    STD_LOGIC_VECTOR(lpm_widthad-1 downto 0);
      Data                         :	in    STD_LOGIC_VECTOR(lpm_width-1 downto 0);
      Address                      :	out   STD_LOGIC_VECTOR(lpm_widthad-1 downto 0);
      Match                        :	out   STD_ULOGIC;
      MulMatch                     :	out   STD_ULOGIC);

end l_cam;

architecture fun_simulation of l_cam is

	component SC_CAM_16K

	generic (
		ADDR_WIDTH    : integer :=  7;
		DATA_WIDTH    : integer := 48;
                MEM_INIT_FLAG : integer :=  0;  
	        MEM_INIT_FILE : string  := ""
		);
	port (
		CE        :  in  STD_LOGIC ;
		WE        :  in  STD_LOGIC ;
		CLK       :  in  STD_LOGIC ;
		EN_MASK   :  in  STD_LOGIC ;
		WR_MASK   :  in  STD_LOGIC ;
		WR_DC     :  in  STD_LOGIC ;
		RST       :  in  STD_LOGIC ;
		CS        :  in  STD_LOGIC_VECTOR ( 1 downto 0) ;
		WAD       :  in  STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0);
		WD        :  in  STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0);
		CO        :  out STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0);
		MATCH     :  out STD_LOGIC;
		MUL_MATCH :  out STD_LOGIC
		);

	end component ;
--------------------------------------------------------------------------
--signal cs : std_logic_vector ( 1 downto 0);
	signal cs0 : std_logic_vector (3 downto 0);
	signal cs_0 : std_logic_vector (1 downto 0);
	signal cs_1 : std_logic_vector (1 downto 0);
	signal cs_2 : std_logic_vector (1 downto 0);
	signal cs_3 : std_logic_vector (1 downto 0);
	signal Address_0 : std_logic_vector (6 downto 0);
	signal Address_1 : std_logic_vector (6 downto 0);
	signal Address_2 : std_logic_vector (6 downto 0);
	signal Address_3 : std_logic_vector (6 downto 0);
	signal match_address : std_logic_vector (6 downto 0);
	signal match_address_ff : std_logic_vector (6 downto 0);
	signal match_bit : std_logic;
	signal Match_0 : std_logic;
	signal Match_1 : std_logic;
	signal Match_2 : std_logic;
	signal Match_3 : std_logic;
	signal MulMatch_0 : std_logic;
	signal MulMatch_1 : std_logic;
	signal MulMatch_2 : std_logic;
	signal MulMatch_3 : std_logic;
	
        CONSTANT  lpm_init_flag       :  integer := init_flag(lpm_init_file);

begin
        --cs <= "11";

   cs_0 <= "1" & cs0(0);
   cs_1 <= "1" & cs0(1);
   cs_2 <= "1" & cs0(2);
   cs_3 <= "1" & cs0(3);
   Match <= match_bit;
   ------------------------------------------------------------------
   CAM_inst_0 : SC_CAM_16K
      generic map (
	 ADDR_WIDTH    => 7, DATA_WIDTH    => lpm_width,
         MEM_INIT_FILE => lpm_init_file, MEM_INIT_FLAG => lpm_init_flag )
      port map (
	 CE => ClockEn, WE => We, CLK => Clock, EN_MASK => EnMask, 
         WR_MASK => WrMask, WR_DC => WrDc, RST => Reset, CS => cs_0,
         WAD => WrAddress(6 downto 0), WD => Data, CO => Address_0,
	 MATCH => Match_0, MUL_MATCH => MulMatch_0 );
   ------------------------------------------------------------------
   CAM_inst_1  : SC_CAM_16K
      generic map (
	 ADDR_WIDTH    => 7, DATA_WIDTH    => lpm_width,
         MEM_INIT_FILE => lpm_init_file, MEM_INIT_FLAG => lpm_init_flag )
      port map (
	 CE => ClockEn, WE => We, CLK => Clock, EN_MASK => EnMask, 
         WR_MASK => WrMask, WR_DC => WrDc, RST => Reset, CS => cs_1,
         WAD => WrAddress(6 downto 0), WD => Data, CO => Address_1,
	 MATCH => Match_1, MUL_MATCH => MulMatch_1 );
	 
   ------------------------------------------------------------------
   CAM_inst_2 : SC_CAM_16K
      generic map (
	 ADDR_WIDTH    => 7, DATA_WIDTH    => lpm_width,
         MEM_INIT_FILE => lpm_init_file, MEM_INIT_FLAG => lpm_init_flag )
      port map (
	 CE => ClockEn, WE => We, CLK => Clock, EN_MASK => EnMask, 
         WR_MASK => WrMask, WR_DC => WrDc, RST => Reset, CS => cs_2,
         WAD => WrAddress(6 downto 0), WD => Data, CO => Address_2,
	 MATCH => Match_2, MUL_MATCH => MulMatch_2 );
   ------------------------------------------------------------------
   CAM_inst_3 : SC_CAM_16K
      generic map (
	 ADDR_WIDTH    => 7, DATA_WIDTH    => lpm_width,
         MEM_INIT_FILE => lpm_init_file, MEM_INIT_FLAG => lpm_init_flag )
      port map (
	 CE => ClockEn, WE => We, CLK => Clock, EN_MASK => EnMask, 
         WR_MASK => WrMask, WR_DC => WrDc, RST => Reset, CS => cs_3,
         WAD => WrAddress(6 downto 0), WD => Data, CO => Address_3,
	 MATCH => Match_3, MUL_MATCH => MulMatch_3 );
   ------------------------------------------------------------------
   
   ------------------------------------------------------------------
 
   process (WrAddress, Match_0, Match_1, Match_2, Match_3, 
      MulMatch_0, MulMatch_1, MulMatch_2, MulMatch_3,
      Address_0, Address_1, Address_2, Address_3,
	match_address, match_address_ff)
   begin
      ----------------------------------------
      if (lpm_widthad = 7) then --128
         cs0 (3 downto 0) <= "0001";
         match_bit <= Match_0;
         MulMatch <= MulMatch_0;
         match_address(6 downto 0) <= Address_0; 
         Address <= Address_0;
      ----------------------------------------
      elsif (lpm_widthad = 8) then --256
         cs0(0) <= not(WrAddress(lpm_widthad - 1));
         cs0(1) <= WrAddress(lpm_widthad - 1);
         cs0(3 downto 2) <= "00";
         match_bit <= Match_0 or Match_1;
         MulMatch <= MulMatch_0 or MulMatch_1 or (Match_0 and Match_1); 
         if Match_0 = '1' then 
            match_address(6 downto 0) <= Address_0; 
         elsif Match_1 = '1' then
            match_address(6 downto 0) <= Address_1;
         else 
            match_address(6 downto 0) <= "0000000";
         end if;
         if match_bit = '1' then 
           Address(6 downto 0 ) <= match_address;
         else
           Address(6 downto 0 ) <= match_address_ff;
         end if;
         Address(lpm_widthad - 1) <= not(Match_0) and Match_1;
      ----------------------------------------
      elsif (lpm_widthad = 9) then  --512 (1024 not valid)
         cs0(0) <= not(WrAddress(lpm_widthad-1)) and not(WrAddress(lpm_widthad-2));
         cs0(1) <= not(WrAddress(lpm_widthad-1)) and    (WrAddress(lpm_widthad-2));
         cs0(2) <=    (WrAddress(lpm_widthad-1)) and not(WrAddress(lpm_widthad-2));
         cs0(3) <=    (WrAddress(lpm_widthad-1)) and    (WrAddress(lpm_widthad-2));
         match_bit <= Match_0 or Match_1 or Match_2 or Match_3;
         MulMatch <= MulMatch_0 or MulMatch_1 or MulMatch_2 or MulMatch_3 or
            (Match_0 and Match_1) or (Match_0 and Match_2) or
            (Match_0 and Match_3) or (Match_1 and Match_2) or
            (Match_1 and Match_3) or (Match_2 and Match_3) ;
         if Match_0 = '1' then 
            match_address(6 downto 0) <= Address_0; 
         elsif Match_1 = '1' then
            match_address(6 downto 0) <= Address_1;
         elsif Match_2 = '1' then
            match_address(6 downto 0) <= Address_2;
         elsif Match_3 = '1' then
            match_address(6 downto 0) <= Address_3;
         else 
            match_address(6 downto 0) <= "0000000";
         end if;
         if match_bit = '1' then 
           Address(6 downto 0 ) <= match_address;
         else
           Address(6 downto 0 ) <= match_address_ff;
         end if;
         Address(lpm_widthad - 2) <= 
            (not(Match_0) and Match_1) or  
            (not(Match_0) and not(Match_1) and not(Match_2) and Match_3);
         Address(lpm_widthad - 1) <=  
            (not(Match_0) and not(Match_1) and Match_2) or  
            (not(Match_0) and not(Match_1) and not(Match_2) and Match_3);
      end if;
   end process;
   
   process (Clock, Reset)
   begin
      if (Reset = '1') then
         match_address_ff (6 downto 0 ) <= "0000000";
      elsif rising_edge(Clock) and match_bit = '1' then
         match_address_ff <= match_address;
      end if;
   end process;
end;


-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
-- L_FIFO
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>


library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

entity l_fifo is
  generic (
	 lpm_type      : string  := "LPM_FIFO_DC";
	 lpm_width     : integer := 1;
	 lpm_widthu    : integer := 1;
	 lpm_numwords  : integer := 2;
         lpm_amfull_flag : integer := 1;
         lpm_amempty_flag : integer := 1;
	 lpm_hint      : string  := "UNUSED");

  port (
	 Data          :  in  std_logic_vector (lpm_width-1 downto 0);
	 WrClock       :  in  std_logic;
	 WrEn          :  in  std_logic;
	 RdClock       :  in  std_logic;
	 RdEn          :  in  std_logic;
	 Reset          :  in  std_logic;
	 RPReset       :  in  std_logic;
	 Q             :  out std_logic_vector (lpm_width-1 downto 0);
	 Full          :  out std_logic;
	 Empty         :  out std_logic;
	 AlmostFull    :  out std_logic;
	 AlmostEmpty   :  out std_logic);

end l_fifo;

architecture fun_simulation of l_fifo is

  component SC_FIFO_16K_L

    generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0; 
        TERMINAL_COUNT : integer := 511; 
        MEM_INIT_FILE  : string  := "mem_init_file"

         );

    port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);

        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)

        ); 

end component;

     signal Rst, FullIn, EmptyIn : std_logic;


  begin

      Rst     <= '1';
      FullIn  <= '0';
      EmptyIn <= '1';


  SC_FIFO_inst : SC_FIFO_16K_L

    generic map (

        DEVICE_FAMILY   =>  open,
        WADDR_WIDTH     =>  lpm_widthu,
        WDATA_WIDTH     =>  lpm_width,
        RADDR_WIDTH     =>  lpm_widthu,
        RDATA_WIDTH     =>  lpm_width,
        ALMOST_FULL_X   =>  lpm_amfull_flag,
        ALMOST_EMPTY_Y  =>  lpm_amempty_flag,
        MEM_INIT_FLAG   =>  0,
        TERMINAL_COUNT  =>  lpm_numwords - 1,
        MEM_INIT_FILE   => open )

    port map (
        WE         => WrEn, 
        WCLK       => WrClock,
        RST        => Reset, 
        RPRST      => RPReset, 
        RE         => RdEn, 
        RCLK       => RdClock, 
        FULLIN     => FullIn, 
        EMPTYIN    => EmptyIn, 
        DI         => Data, 

        FULL       => Full, 
        EMPTY      => Empty, 
        AMFULL     => AlmostFull, 
        AMEMPTY    => AlmostEmpty, 
        DO         => Q
        ); 

end;



library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

entity l_ramdp is 
generic (
              LPM_TYPE      : string := "LPM_RAM_DP";
              LPM_WIDTHA    : positive;
              LPM_WIDTHADA  : positive;
              LPM_NUMWORDSA : positive;
              LPM_WIDTHB    : positive;
              LPM_WIDTHADB  : positive;
              LPM_NUMWORDSB : positive;
              LPM_INDATA    : string :="REGISTERED";
              LPM_OUTDATA   : string :="UNREGISTERED";
              LPM_ADDRESSA_CONTROL   : string :="REGISTERED";
              LPM_ADDRESSB_CONTROL   : string :="REGISTERED";
              lpm_init_file        : string := "";
              LPM_HINT      : string :="UNUSED");
      port (  
              DataInA       : in std_logic_vector(LPM_WIDTHA-1 downto 0);
              AddressA      : in std_logic_vector(LPM_WIDTHADA-1 downto 0);
              DataInB       : in std_logic_vector(LPM_WIDTHB-1 downto 0);
              AddressB      : in std_logic_vector(LPM_WIDTHADB-1 downto 0);
              ClockA        : in std_logic := '0';
              ClockEnA      : in std_logic := '0';
              ClockB        : in std_logic := '0';
              ClockEnB      : in std_logic := '0';
              WrA           : in std_logic;
              WrB           : in std_logic;
              ResetA        : in std_logic;
              ResetB        : in std_logic;
              QA            : out std_logic_vector(LPM_WIDTHA-1 downto 0);
              QB            : out std_logic_vector(LPM_WIDTHB-1 downto 0));
end l_ramdp;

architecture fun_simulation of l_ramdp is

component SC_DPRAM_16K_L
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
        ADDR_WIDTH_A     : integer := 13;
        DATA_WIDTH_A     : integer := 2;
        ADDR_WIDTH_B     : integer := 14;
        DATA_WIDTH_B     : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        ARRAY_SIZE     : integer := 511; 
	MEM_INIT_FILE  : string  := "mem_init_file"
        );
  port (
        CENA : in  STD_LOGIC ;
        CLKA : in  STD_LOGIC ;
        WRA  : in  STD_LOGIC ;
        CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
        RSTA : in  STD_LOGIC ;
        DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
        ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
        DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

        CENB : in  STD_LOGIC ;
        CLKB : in  STD_LOGIC ;
        WRB  : in  STD_LOGIC ;
        CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
        RSTB : in  STD_LOGIC ;
        DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
        ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
        DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
        ); 

end component;

      signal CS : std_logic_vector ( 1 downto 0);
      signal QA_int, QA_int_reg  : std_logic_vector(LPM_WIDTHA-1 downto 0);
      signal QB_int, QB_int_reg  : std_logic_vector(LPM_WIDTHB-1 downto 0);
      CONSTANT  lpm_init_flag       :  integer := init_flag(lpm_init_file);

begin

      CS <= "11";

      OutRegisterA : process(ClockA, ResetA)
       begin
           if(ResetA = '1') then QA_int_reg <= (others => '0');
           elsif (ClockA'EVENT and ClockA = '1') then
              if (ClockEnA = '1') then
               QA_int_reg <= QA_int;
              elsif (ClockEnA /= '0') then
               QA_int_reg <= (others => 'X');
              end if;
           end if;
       end process;

      OutRegisterB : process(ClockB, ResetB)
       begin
           if(ResetB = '1') then QB_int_reg <= (others => '0');
           elsif (ClockB'EVENT and ClockB = '1') then
              if (ClockEnB = '1') then
               QB_int_reg <= QB_int;
              elsif (ClockEnB /= '0') then
               QB_int_reg <= (others => 'X');
              end if;
           end if;
       end process;

      SelectA   : process (QA_int , QA_int_reg)
        begin
              if(lpm_outdata = "UNREGISTERED" and lpm_addressa_control = "REGISTERED") then
                     QA <= QA_int;
              elsif(lpm_outdata = "REGISTERED" and lpm_addressa_control = "REGISTERED") then
                     QA <= QA_int_reg;
              end if;
        end process;

      SelectB   : process (QB_int , QB_int_reg)
        begin
              if(lpm_outdata = "UNREGISTERED" and lpm_addressb_control = "REGISTERED") then
                     QB <= QB_int;
              elsif(lpm_outdata = "REGISTERED" and lpm_addressb_control = "REGISTERED") then
                     QB <= QB_int_reg;
              end if;
       end process;

RAM_DP_INST : SC_DPRAM_16K_L

    generic map(
         DEVICE_FAMILY  => open ,
         ADDR_WIDTH_A  => LPM_WIDTHADA,
         DATA_WIDTH_A  => LPM_WIDTHA,
         ADDR_WIDTH_B  => LPM_WIDTHADB,
         DATA_WIDTH_B  => LPM_WIDTHB,
  	 MEM_INIT_FLAG => lpm_init_flag,  
         ARRAY_SIZE    => lpm_numwordsa*lpm_widtha,
	 MEM_INIT_FILE  => lpm_init_file
       )
    port map (
         CENA => ClockEnA,
         CLKA => ClockA,
         WRA  => WrA,
         CSA  => CS,
         RSTA => ResetA,
         DIA  => DataInA,
         ADA  => AddressA,
         DOA  => QA_int,

         CENB => ClockEnB,
         CLKB => ClockB,
         WRB  => WrB,
         CSB  => CS,
         RSTB => ResetB,
         DIB  => DataInB,
         ADB  => AddressB,
         DOB  => QB_int
      );
end;



library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;
    
entity l_ramdps is
  generic(
	   lpm_type             : string := "LPM_RAM_DP_PSEUDO";
	   lpm_widthw           : integer := 1;
	   lpm_widthr           : integer := 1;
	   lpm_numwordsw        : integer := 1;
	   lpm_widthadw         : integer := 1;
	   lpm_widthadr         : integer := 1;
   	   lpm_numwordsr        : integer := 1;
  	   lpm_indata           : string := "REGISTERED";
	   lpm_outdata          : string := "UNREGISTERED";
    	   lpm_addressw_control : string := "REGISTERED";
	   lpm_addressr_control : string := "REGISTERED";
	   lpm_hint             : string := "UNUSED";
           lpm_init_file        : string := "");


  port(
           Data        : in  std_logic_vector (lpm_widthw-1 downto 0);
           WrAddress   : in  std_logic_vector (lpm_widthadw-1 downto 0);
           RdAddress   : in  std_logic_vector (lpm_widthadr-1 downto 0);
           WrClock     : in std_logic;
           WrClockEn   : in std_logic;
           RdClock     : in std_logic;
           RdClockEn   : in std_logic;
           WE          : in std_logic;
           Reset       : in std_logic;
           Q           : out std_logic_vector (lpm_widthr-1 downto 0));

end l_ramdps;

architecture fun_simulation of l_ramdps is

component SC_PDPRAM_16K_L

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        WADDR_WIDTH    : integer := 13;
        WDATA_WIDTH    : integer := 2;
        RADDR_WIDTH    : integer := 13;
        RDATA_WIDTH    : integer := 2;
        ARRAY_SIZE     : integer := 511; 
        MEM_INIT_FLAG  : integer := 0;  
	MEM_INIT_FILE  : string  := "mem_init_file"

        );

  port (
        WCEN : in  STD_LOGIC ;
        WCLK : in  STD_LOGIC ;
        WE   : in  STD_LOGIC ;
        WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
        RCLK : in  STD_LOGIC;
        RCEN : in  STD_LOGIC;
        RST  : in  STD_LOGIC ;

        WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
        RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);  
        RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
       ); 

end component;

component SC_PDPRAMA_16K_L

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        WADDR_WIDTH    : integer := 13;
        WDATA_WIDTH    : integer := 2;
        RADDR_WIDTH    : integer := 13;
        RDATA_WIDTH    : integer := 2;
        ARRAY_SIZE     : integer := 16384;
        MEM_INIT_FLAG  : integer := 1;  
	MEM_INIT_FILE  : string  := "mem_init_file"

        );

  port (
        WCEN : in  STD_LOGIC ;
        WCLK : in  STD_LOGIC ;
        WE   : in  STD_LOGIC ;
        WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
        RST  : in  STD_LOGIC ;

        WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
        RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);  
        RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
       ); 

end component ;


     signal cs        : std_logic_vector ( 1 downto 0);
     signal Q_K       : std_logic_vector (lpm_widthr-1 downto 0);
     signal Q_KA      : std_logic_vector (lpm_widthr-1 downto 0);
     signal Q_K_reg   : std_logic_vector (lpm_widthr-1 downto 0);
     signal Q_KA_reg   : std_logic_vector (lpm_widthr-1 downto 0);
     CONSTANT  lpm_init_flag       :  integer := init_flag(lpm_init_file);

  begin

     cs <= "11";

      OutRegister : process(RdClock, Reset)
       begin
           if (Reset = '1') then 
                Q_K_reg <= (others => '0');
                Q_KA_reg <= (others => '0');
           elsif (RdClock'EVENT and RdClock = '1') then
              if (RdClockEn = '1') then
                Q_K_reg <= Q_K;
                Q_KA_reg <= Q_KA;
              elsif (RdClockEn /= '0') then
                Q_K_reg <= (others => 'X');
                Q_KA_reg <= (others => 'X');
              end if;
           end if;
       end process;

      SelectOut  : process (Q_K , Q_KA , Q_K_reg, Q_KA_reg)
        begin
              if(lpm_outdata = "UNREGISTERED" and lpm_addressr_control = "UNREGISTERED") then
                     Q <= Q_KA;
              elsif(lpm_outdata = "UNREGISTERED" and lpm_addressr_control = "REGISTERED") then 
                     Q <= Q_K;
              elsif(lpm_outdata = "REGISTERED" and lpm_addressr_control = "UNREGISTERED")  then
                     Q <= Q_KA_reg;
              elsif(lpm_outdata = "REGISTERED" and lpm_addressr_control = "REGISTERED") then
                     Q <= Q_K_reg;
              end if;
        end process;


   PDPRAM_inst : SC_PDPRAM_16K_L

  generic map(

        DEVICE_FAMILY  => open,
        WADDR_WIDTH    => lpm_widthadw,
        WDATA_WIDTH    => lpm_widthw,
        RADDR_WIDTH    => lpm_widthadr,
        RDATA_WIDTH    => lpm_widthr,
        MEM_INIT_FLAG  => lpm_init_flag,  
        ARRAY_SIZE     => lpm_numwordsw*lpm_widthw,
	MEM_INIT_FILE  => lpm_init_file)

  port map(
        WCEN =>  WrClockEn,
        WCLK =>  WrClock,
        WE   =>  WE,
        WCS  =>  cs,
        RCLK =>  RdClock,
        RCEN =>  RdClockEn,
        RST  =>  Reset,

        WD   =>  Data,
        WAD  =>  WrAddress,
        RAD  =>  RdAddress,
        RD   => Q_K 
       ); 

   PDPRAM_instA : SC_PDPRAMA_16K_L

  generic map(

        DEVICE_FAMILY  => open,
        WADDR_WIDTH    => lpm_widthadw,
        WDATA_WIDTH    => lpm_widthw,
        RADDR_WIDTH    => lpm_widthadr,
        RDATA_WIDTH    => lpm_widthr,
        MEM_INIT_FLAG  => lpm_init_flag,  
        ARRAY_SIZE     => lpm_numwordsw*lpm_widthw,
	MEM_INIT_FILE  => lpm_init_file)

  port map(
        WCEN =>  WrClockEn,
        WCLK =>  WrClock,
        WE   =>  WE,
        WCS  =>  cs,
        RST  =>  Reset,

        WD   =>  Data,
        WAD  =>  WrAddress,
        RAD  =>  RdAddress,
        RD   => Q_KA 
       ); 
end;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

entity l_ramdq  is
  generic(
	   lpm_type            : string  := "LPM_RAM_DQ";
	   lpm_width           : integer := 1;
	   lpm_numwords        : integer := 1;
	   lpm_widthad         : integer := 1;
  	   lpm_indata          : string  := "REGISTERED";
	   lpm_outdata         : string  := "UNREGISTERED";
	   lpm_address_control : string  := "REGISTERED";
           lpm_init_file       : string := "";
	   lpm_hint            : string  := "UNUSED");

  port(

           Data                : in  std_logic_vector (lpm_width-1 downto 0);
           Address             : in  std_logic_vector (lpm_widthad-1 downto 0);
           Clock               : in  std_logic;
           ClockEn             : in  std_logic;
           WE                  : in  std_logic;
           Reset               : in  std_logic;
           Q                   : out std_logic_vector (lpm_width-1 downto 0));
  end l_ramdq;


architecture fun_simulation of l_ramdq is


  component SC_SPRAM_16K_L

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        MEM_INIT_FLAG  : integer := 1; 
        ARRAY_SIZE     : integer := 511; 
	MEM_INIT_FILE  : string  := "qq.dat"

	);

  port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

end component;

component SC_SPRAMA_16K_L

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        ARRAY_SIZE     : integer := 16384;
        MEM_INIT_FLAG  : integer := 1;  
	MEM_INIT_FILE  : string  := "mem_init_file"

	);

  port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

end component ;

    signal cs   : std_logic_vector (1 downto 0);
    signal Q_K       : std_logic_vector (lpm_width-1 downto 0);
    signal Q_KA      : std_logic_vector (lpm_width-1 downto 0);
    signal Q_K_reg   : std_logic_vector (lpm_width-1 downto 0);
    signal Q_KA_reg   : std_logic_vector (lpm_width-1 downto 0);
    CONSTANT  lpm_init_flag       :  integer := init_flag(lpm_init_file);

  begin

      cs <= "11";

      OutRegister : process(Clock, Reset)
       begin
           if (Reset = '1') then 
               Q_K_reg <= (others => '0');
               Q_KA_reg <= (others => '0');
           elsif (Clock'EVENT and Clock = '1') then
              if (ClockEn = '1') then
               Q_K_reg <= Q_K;
               Q_KA_reg <= Q_KA;
              elsif (ClockEn /= '0') then
               Q_K_reg <= (others => 'X');
               Q_KA_reg <= (others => 'X');
              end if;
           end if;
       end process;

      SelectOut  : process (Q_K , Q_KA , Q_K_reg, Q_KA_reg)
        begin
              if(lpm_outdata = "UNREGISTERED" and lpm_address_control = "UNREGISTERED") then
                     Q <= Q_KA;
              elsif(lpm_outdata = "UNREGISTERED" and lpm_address_control = "REGISTERED") then
                     Q <= Q_K;
              elsif(lpm_outdata = "REGISTERED" and lpm_address_control = "UNREGISTERED") then
                     Q <= Q_KA_reg;
              elsif(lpm_outdata = "REGISTERED" and lpm_address_control = "REGISTERED") then
                     Q <= Q_K_reg;
              end if;
        end process;

  SPRAM_inst : SC_SPRAM_16K_L

  generic map (

        DEVICE_FAMILY  => open,
        ADDR_WIDTH     => lpm_widthad,
        DATA_WIDTH     => lpm_width,
        MEM_INIT_FLAG  => lpm_init_flag,
        ARRAY_SIZE     => lpm_numwords * lpm_width,
	MEM_INIT_FILE  => lpm_init_file)

  port map (
        CEN  => ClockEn, 
        CLK  => Clock, 
         WR  => WE, 
         CS  => cs,
        RST  => Reset,
         DI  => Data,
         AD  => Address,
         DO  => Q_K
       ); 

  SPRAMA_inst : SC_SPRAMA_16K_L

  generic map (

        DEVICE_FAMILY  => open,
        ADDR_WIDTH     => lpm_widthad,
        DATA_WIDTH     => lpm_width,
        MEM_INIT_FLAG  => lpm_init_flag,
        ARRAY_SIZE     => lpm_numwords * lpm_width,
	MEM_INIT_FILE  => lpm_init_file)

  port map (
        CEN  => ClockEn, 
        CLK  => Clock, 
         WR  => WE, 
         CS  => cs,
        RST  => Reset,
         DI  => Data,
         AD  => Address,
         DO  => Q_KA
       ); 
end;



library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

entity l_rom is
  generic (
	    lpm_type               : string  := "LPM_ROM";
	    lpm_width              : integer := 1;
	    lpm_numwords           : integer := 1;
	    lpm_widthad            : integer := 1;
	    lpm_outdata            : string  := "REGISTERED";
	    lpm_address_control    : string  := "UNREGISTERED";
            lpm_init_file          : string := "init_file";
	    lpm_hint               : string  := "UNUSED");
  port (
            Address       : in  std_logic_vector (lpm_widthad-1 downto 0);
            OutClock      : in  std_logic;
            OutClockEn    : in  std_logic;
            Reset         : in  std_logic;
            Q             : out std_logic_vector (lpm_width-1 downto 0));
end l_rom;

architecture fun_simulation of l_rom is

  component  SC_SPRAM_16K_L

    generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        ARRAY_SIZE     : integer := 511; 
        MEM_INIT_FLAG  : integer := 1;  
	MEM_INIT_FILE  : string  := "qq.dat"

	);

    port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

  end component;

component SC_SPRAMA_16K_L

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        ARRAY_SIZE     : integer := 16384;
        MEM_INIT_FLAG  : integer := 1;  
	MEM_INIT_FILE  : string  := "mem_init_file"

	);

  port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

end component ;

        signal cs : std_logic_vector ( 1 downto 0);
        signal DI_sig : std_logic_vector (lpm_width-1 downto 0);
        signal WE_sig : std_logic;

        signal Q_K       : std_logic_vector (lpm_width-1 downto 0);
        signal Q_KA      : std_logic_vector (lpm_width-1 downto 0);
        signal Q_K_reg   : std_logic_vector (lpm_width-1 downto 0);
        signal Q_KA_reg   : std_logic_vector (lpm_width-1 downto 0);

  begin

        cs <= "11";
        WE_sig <= '0';

      OutRegister : process(OutClock, Reset)
       begin
           if (Reset = '1') then 
               Q_K_reg <= (others => '0');
               Q_KA_reg <= (others => '0');
           elsif (OutClock'EVENT and OutClock = '1') then
              if(OutClockEn = '1') then
               Q_K_reg <= Q_K;
               Q_KA_reg <= Q_KA;
              elsif(OutClockEn /= '0') then
               Q_K_reg <= (others => 'X' );
               Q_KA_reg <= (others => 'X' );
              end if;
           end if;
       end process;

      SelectOut  : process (Q_K, Q_KA, Q_K_reg, Q_KA_reg)
        begin
              if(lpm_outdata = "UNREGISTERED" and lpm_address_control = "UNREGISTERED") then
                     Q <= Q_KA;
              elsif(lpm_outdata = "UNREGISTERED" and lpm_address_control = "REGISTERED") then
                     Q <= Q_K;
              elsif(lpm_outdata = "REGISTERED" and lpm_address_control = "UNREGISTERED") then
                     Q <= Q_KA_reg;
              elsif(lpm_outdata = "REGISTERED" and lpm_address_control = "REGISTERED") then
                     Q <= Q_K_reg;
              end if;
        end process;

    SPRAM_inst :  SC_SPRAM_16K_L

      generic map(

           DEVICE_FAMILY  =>  open,
           ADDR_WIDTH     =>  lpm_widthad,
           DATA_WIDTH     =>  lpm_width, 
           MEM_INIT_FLAG  =>  1,
           ARRAY_SIZE     =>  lpm_numwords * lpm_width,
	   MEM_INIT_FILE  =>  lpm_init_file)

      port map(
           CEN    =>  OutClockEn,
           CLK    =>  OutClock,
           WR     =>  WE_sig,
           CS     =>  cs,
           RST    =>  Reset,
           DI     =>  DI_sig,
           AD     =>  Address,
           DO     =>  Q_K
       ); 

  SPRAMA_inst : SC_SPRAMA_16K_L

      generic map(

           DEVICE_FAMILY  =>  open,
           ADDR_WIDTH     =>  lpm_widthad,
           DATA_WIDTH     =>  lpm_width, 
           MEM_INIT_FLAG  =>  1,
           ARRAY_SIZE     =>  lpm_numwords * lpm_width,
	   MEM_INIT_FILE  =>  lpm_init_file)

      port map(
           CEN    =>  OutClockEn,
           CLK    =>  OutClock,
           WR     =>  WE_sig,
           CS     =>  cs,
           RST    =>  Reset,
           DI     =>  DI_sig,
           AD     =>  Address,
           DO     =>  Q_KA
       ); 
end;




-- ************************************************************************
--
--  FIFO V2: Behavioral Model
--  VHDL
--  
-- ************************************************************************
--
--  Init: Oct. 2002
--  Written by: Zhou Xiao-qiu (Sean ZHOU)
--  Email: xqzhou@lscsh.latticesemi.com
--  Tel: 86-21-64852865 ext. 226
--
-- ************************************************************************
--
--  Filename:  SC_FIFO_V2.vhd
--  Description: FIFO behavioral model. 
--     
-- ************************************************************************

-- ************************************************************************
-- History: 
-- 1. Reset EMPTY & AMEMPTY to '0', '0' means 'Ture';   
-- 2. May. 30, 2002 Read memory initialization file feature
-- 3. Add control signal RE WE to BlockRAM 
-- 4. Add programable TERMINAL_COUNT
-- 5. Fix the Write 1-5, Read 2-6 issue
-- 6. Data bus width conversion
--  
-- ************************************************************************

-- ************************************************************************
-- FIFO COMPONENTS READ_POINTER_CTRL_V2
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity READ_POINTER_CTRL_V2 is
	generic (
              RPOINTER_WIDTH : integer := 9
		);
	port (
                TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
		GLOBAL_RST   : in STD_LOGIC ;
                RESET_RP     : in STD_LOGIC ;
                READ_EN      : in STD_LOGIC ;
                READ_CLK     : in STD_LOGIC ;
	        EMPTY_FLAG   : in STD_LOGIC ;
		READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
	     );
end READ_POINTER_CTRL_V2;

architecture LATTICE_BEHAV of READ_POINTER_CTRL_V2 is

  signal s_READ_POINTER : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');

begin

  READ_POINTER <= s_READ_POINTER; 

process  (GLOBAL_RST, RESET_RP, READ_EN, READ_CLK)

	variable v_READ_POINTER: STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0');

begin

	if GLOBAL_RST = '1'  or RESET_RP = '1' then 

        s_READ_POINTER <= TERMINAL_COUNT; 

	elsif (READ_CLK'EVENT and READ_CLK = '1') then
		if (READ_EN = '1' and EMPTY_FLAG = '1') then
                  v_READ_POINTER := s_READ_POINTER + '1';
		  
                else  
                  v_READ_POINTER := s_READ_POINTER;
		end if;

		if (v_READ_POINTER = TERMINAL_COUNT + 1) then
		   s_READ_POINTER <= (others => '0');
		else
		   s_READ_POINTER <= v_READ_POINTER;
		end if;
	end if;

end process;
end LATTICE_BEHAV;

-- ************************************************************************
-- FIFO COMPONENTS WRITE_POINTER_CTRL_V2
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity WRITE_POINTER_CTRL_V2 is
        generic (
                WPOINTER_WIDTH : integer := 9;
                WDATA_WIDTH : integer := 32
		);
        port (
		TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
		GLOBAL_RST    : in STD_LOGIC ;
                WRITE_EN      : in STD_LOGIC ;
                WRITE_CLK     : in STD_LOGIC ;
                FULL_FLAG     : in STD_LOGIC ;
                WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
            
	     );
end WRITE_POINTER_CTRL_V2;

architecture LATTICE_BEHAV of WRITE_POINTER_CTRL_V2 is

 signal s_WRITE_POINTER : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');

begin 

  WRITE_POINTER <= s_WRITE_POINTER;

  process  (GLOBAL_RST, WRITE_EN, WRITE_CLK)

    variable v_WRITE_POINTER: STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');

begin
	if GLOBAL_RST = '1'  then 
		s_WRITE_POINTER <= TERMINAL_COUNT ; 

	elsif (WRITE_CLK'EVENT and WRITE_CLK = '1') then
		if (WRITE_EN = '1' and FULL_FLAG /= '1') then
		   v_WRITE_POINTER := s_WRITE_POINTER + '1';
                else
		   v_WRITE_POINTER := s_WRITE_POINTER ;
                end if; 

		if (v_WRITE_POINTER = TERMINAL_COUNT + 1) then
		   s_WRITE_POINTER <= (others => '0');
		else
		   s_WRITE_POINTER <= v_WRITE_POINTER ;
		end if;
	end if;
end process;
end LATTICE_BEHAV;

-- ************************************************************************
-- FIFO V2 COMPONENTS FLAG LOGIC
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;

entity FLAG_LOGIC_V2 is
 	generic (
                WDATA_WIDTH    : integer := 32; 
                RDATA_WIDTH    : integer := 32; 
                AMFULL_X      : integer := 1;
                AMEMPTY_Y     : integer := 1
		);
	port (
                GLOBAL_RST : in STD_LOGIC ;
		FIFO_CAP   : in integer ; 	
                FIFO_PTR   : in integer ;
                FULL_D     : out STD_LOGIC ;
                EMPTY_D    : out STD_LOGIC ;
                AMFULL_D   : out STD_LOGIC ;
                AMEMPTY_D  : out STD_LOGIC 
	);
end FLAG_LOGIC_V2;

architecture LATTICE_BEHAV of FLAG_LOGIC_V2 is

begin 
--------------------------------------------------------------------------
-- Function: Main Process 
-- Description: 
--------------------------------------------------------------------------
FULL_AMFULL_EMPTY_AMEMPTY: process  (GLOBAL_RST, FIFO_CAP, FIFO_PTR)

begin

	if GLOBAL_RST = '1'  then 
	    FULL_D    <= '0';
	    AMFULL_D  <= '0';
	    EMPTY_D   <= '0';
            AMEMPTY_D <= '0';
	else
		if (FIFO_CAP - FIFO_PTR < WDATA_WIDTH) then
		     FULL_D <= '1';
		else
		     FULL_D <= '0';	
	        end if;

		if (FIFO_CAP - FIFO_PTR < WDATA_WIDTH + AMFULL_X * WDATA_WIDTH) then
		     AMFULL_D <= '1';
		else
		     AMFULL_D <= '0';	
	        end if;

		if (FIFO_PTR < RDATA_WIDTH) then
		     EMPTY_D <= '0';
	        else
		     EMPTY_D <= '1';	
	        end if;

		if (FIFO_PTR < RDATA_WIDTH + AMEMPTY_Y * RDATA_WIDTH) then
		     AMEMPTY_D <= '0';
	        else
		     AMEMPTY_D <= '1';	
		end if;
	end if;

end process FULL_AMFULL_EMPTY_AMEMPTY;

end LATTICE_BEHAV;


--**********************************************************************
-- SC_FIFO_V2_16K
--**********************************************************************
--**********************************************************************
-- Top Design Entity definition  
--**********************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;

--USE ieee.numeric_std.all;

 entity SC_FIFO_V2_16K is 
  generic (
	DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer := 511; --QQ: Word number < 2**WADDR_WIDTH
	WADDR_WIDTH    : integer :=   9;
        WDATA_WIDTH    : integer :=  32;
        RADDR_WIDTH    : integer :=   8;
        RDATA_WIDTH    : integer :=  64;
        ALMOST_FULL_X  : integer :=   2;
        ALMOST_EMPTY_Y : integer :=   2;
        MEM_INIT_FLAG  : integer :=   0;  
        MEM_INIT_FILE  : string  := "mem_init_file"

         );

  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);

        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)

        ); 

end SC_FIFO_V2_16K; 


-- ************************************************************************
-- ARCHITECTURE
-- ************************************************************************
architecture LATTICE_BEHAV of SC_FIFO_V2_16K is 

-- ************************************************************************
-- COMPONENT DECLARATIONS
-- ************************************************************************
component SC_BRAM_16K_SYNC 

  generic (
 	     
         DEVICE_FAMILY : string  := "SuperCool";
         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
         MEM_INIT_FLAG : integer := 0;  
         MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
	 WCLK : in  STD_LOGIC;
	 RCLK : in  STD_LOGIC
        ); 
 end component;

-- ************************************************************************
-- SIGNAL DECLARATIONS
-- ************************************************************************
signal we_ram : STD_LOGIC := '0';
signal re_ram : STD_LOGIC := '0';
signal full_bit : STD_LOGIC := '0';
signal empty_bit : STD_LOGIC := '0';
signal wptr_wrap_bit : STD_LOGIC := '0';
signal rptr_wrap_bit : STD_LOGIC := '0';
signal wptr : STD_LOGIC_VECTOR (WADDR_WIDTH - 1 downto 0) := (others => '0');
signal rptr : STD_LOGIC_VECTOR (RADDR_WIDTH - 1 downto 0) := (others => '0');
signal wptr_wrap_appended : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
				:= (others => '0');
signal rptr_wrap_appended : STD_LOGIC_VECTOR (RADDR_WIDTH downto 0) 
				:= (others => '0');
signal next_wptr_wrap_appended : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
				:= (others => '0');

signal next_rptr_wrap_appended : STD_LOGIC_VECTOR (RADDR_WIDTH downto 0) 
				:= (others => '0');


signal num_unread_loc_wdomain : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
				:= (others => '0');
signal num_unread_loc_rdomain : STD_LOGIC_VECTOR (RADDR_WIDTH downto 0) 
				:= (others => '0');
				
signal TERM_CNT_VEC_W : STD_LOGIC_VECTOR (WADDR_WIDTH  downto 0);
signal TERM_CNT_VEC_R : STD_LOGIC_VECTOR (RADDR_WIDTH  downto 0);

signal DEPTH_W : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0);   
signal DEPTH_R : STD_LOGIC_VECTOR (RADDR_WIDTH downto 0); --ct093004  

signal wptr_rdomain : STD_LOGIC_VECTOR (WADDR_WIDTH - 1 downto 0) := (others => '0');
signal rptr_wdomain : STD_LOGIC_VECTOR (RADDR_WIDTH - 1 downto 0) := (others => '0');

--ct092904
signal rptr_wdomain_cmp : STD_LOGIC_VECTOR (WADDR_WIDTH - 1 downto 0) := (others => '0');
signal wptr_rdomain_cmp : STD_LOGIC_VECTOR (RADDR_WIDTH - 1 downto 0) := (others => '0');

signal wptr_wrap_bit_rdomain : STD_LOGIC := '0';
signal rptr_wrap_bit_wdomain : STD_LOGIC := '0';

signal wptr_wrap_appended_rdomain : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
				  := (others => '0');
signal rptr_wrap_appended_wdomain : STD_LOGIC_VECTOR (RADDR_WIDTH downto 0) --ct092704
				  := (others => '0');


signal rden_p1, empty_p1: std_logic; --ct092804
signal do_ram: STD_LOGIC_VECTOR (RDATA_WIDTH - 1 downto 0); --ct092804

-- ************************************************************************
-- FUNCTIONS
-- ************************************************************************
------------------------------------------------------------------------
function next_ptr (
   ptr_wrap_bit :  STD_LOGIC;
   ptr :  STD_LOGIC_VECTOR;
   TERMINAL_COUNT :  STD_LOGIC_VECTOR;
   ADDR_WIDTH: integer)

  return STD_LOGIC_VECTOR is

  variable result_ptr : STD_LOGIC_VECTOR (ADDR_WIDTH downto 0); 
  variable tmp_ptr : STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0);
  
begin
   if (ptr = TERMINAL_COUNT) then
      tmp_ptr := (others => '1');
   else
      tmp_ptr :=  ptr;
   end if;
   result_ptr := (ptr_wrap_bit & tmp_ptr) + 1;
  
   return result_ptr;

end next_ptr;
------------------------------------------------------------------------
function INT_TO_VEC ( INPUT_INT : integer; INPUT_LENGTH: integer)
 return std_logic_vector is

   variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
   variable vTRANS: integer := 0;
   variable vQUOTIENT: integer := 0;
 
 begin 
    vQUOTIENT := INPUT_INT;

    for i in 0 to INPUT_LENGTH -1 loop
	vTRANS := 0;
	while vQUOTIENT >1 loop
	    vQUOTIENT := vQUOTIENT - 2;
            vTRANS := vTRANS + 1;
	end loop;
        case vQUOTIENT is
              when 1 =>
                 vDATA_STD_VEC(i) := '1';
              when 0 =>
                 vDATA_STD_VEC(i) := '0';
              when others =>
                 null;
        end case;
        vQUOTIENT := vTRANS; 
    end loop;
  return vDATA_STD_VEC; 	  
 end INT_TO_VEC; 

-- ************************************************************************
-- BODY
-- ************************************************************************

begin 

-- ************************************************************************
-- INSTANTIATIONS
-- ************************************************************************

FIFO_BRAM_INST: SC_BRAM_16K_SYNC

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => WADDR_WIDTH, 
         RADDR_WIDTH_A  => RADDR_WIDTH, 
         WADDR_WIDTH_B  => WADDR_WIDTH, 
         RADDR_WIDTH_B  => RADDR_WIDTH, 
         WDATA_WIDTH_A  => WDATA_WIDTH, 
         RDATA_WIDTH_A  => RDATA_WIDTH, 
         WDATA_WIDTH_B  => WDATA_WIDTH, 
         RDATA_WIDTH_B  => RDATA_WIDTH, 
         ARRAY_SIZE     => open,
    	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE

       )
    port map (
         WADA => wptr,
         WEA  => we_ram,
         WDA  => DI, 
         RADA => rptr,
         REA  => re_ram,
         --ct092804 RDA  => DO, 
         RDA  => do_ram, --ct092804
         
         WADB => wptr, 
         WEB  => '0', 
         WDB  => DI, 
         RADB => rptr, 
         REB  => '0', 
         RDB  => open,
	 WCLK => WCLK,
	 RCLK => RCLK
      );


-- ************************************************************************
-- CONCURRENT ASSIGNMENTS
-- ************************************************************************
--TERM_CNT_VEC (WADDR_WIDTH downto 0) <= INT_TO_VEC(TERMINAL_COUNT, WADDR_WIDTH + 1);

TERM_CNT_VEC_W (WADDR_WIDTH downto 0) <= 
  INT_TO_VEC(TERMINAL_COUNT, WADDR_WIDTH + 1);
TERM_CNT_VEC_R (RADDR_WIDTH downto 0) <=
  INT_TO_VEC( (((TERMINAL_COUNT + 1)* WDATA_WIDTH) / RDATA_WIDTH) - 1, RADDR_WIDTH + 1);
  
DEPTH_W (WADDR_WIDTH downto 0)  <= TERM_CNT_VEC_W  + 1;
DEPTH_R (RADDR_WIDTH downto 0)  <= TERM_CNT_VEC_R  + 1; 
  
DEPTH_W (WADDR_WIDTH downto 0)  <= TERM_CNT_VEC_W  + 1;
DEPTH_R (RADDR_WIDTH downto 0)  <= TERM_CNT_VEC_R  + 1;

we_ram  <= WE and not(full_bit);
re_ram <= RE and not(empty_bit);

wptr <= wptr_wrap_appended(WADDR_WIDTH - 1 downto 0);
rptr <= rptr_wrap_appended(RADDR_WIDTH - 1 downto 0);
wptr_rdomain <= wptr_wrap_appended_rdomain(WADDR_WIDTH - 1 downto 0);
rptr_wdomain <= rptr_wrap_appended_wdomain(RADDR_WIDTH - 1 downto 0);

wptr_wrap_bit <= wptr_wrap_appended(WADDR_WIDTH);
rptr_wrap_bit <= rptr_wrap_appended(RADDR_WIDTH);
wptr_wrap_bit_rdomain  <= wptr_wrap_appended_rdomain (WADDR_WIDTH);
rptr_wrap_bit_wdomain  <= rptr_wrap_appended_wdomain (RADDR_WIDTH);

next_wptr_wrap_appended <= next_ptr(wptr_wrap_bit, wptr, TERM_CNT_VEC_W, WADDR_WIDTH);
next_rptr_wrap_appended <= next_ptr(rptr_wrap_bit, rptr, TERM_CNT_VEC_R, RADDR_WIDTH);


process(rptr_wdomain, wptr_rdomain)--, wptr_wrap_bit_rdomain
   variable MAX_ADDR_WIDTH: integer;
   variable MIN_ADDR_WIDTH: integer;
   variable ADDR_WIDTH_DIFF: integer;
begin
   -------------------------------------------------------------------
   if (WADDR_WIDTH > RADDR_WIDTH) then
      MAX_ADDR_WIDTH := WADDR_WIDTH;
      MIN_ADDR_WIDTH := RADDR_WIDTH;
   else
      MAX_ADDR_WIDTH := RADDR_WIDTH;
      MIN_ADDR_WIDTH := WADDR_WIDTH;
   end if;

   ADDR_WIDTH_DIFF := MAX_ADDR_WIDTH - MIN_ADDR_WIDTH;
   -------------------------------------------------------------------
   if (WADDR_WIDTH > RADDR_WIDTH) then
      -- Given wptr[2:0], rptr[1:0]
      -- Then wptr_rdomain_cmp = wtpr[2:1]
      -- and  rptr_wdomain_cmp = {rptr[1:0], 1'b0}
      rptr_wdomain_cmp (MAX_ADDR_WIDTH - 1 downto ADDR_WIDTH_DIFF ) <=
         rptr_wdomain (MIN_ADDR_WIDTH - 1 downto 0 );
      rptr_wdomain_cmp (ADDR_WIDTH_DIFF - 1 downto 0 ) <=
         (others => '0');
      wptr_rdomain_cmp <= 
         wptr_rdomain(MAX_ADDR_WIDTH - 1 downto ADDR_WIDTH_DIFF);
   -------------------------------------------------------------------
   elsif (RADDR_WIDTH > WADDR_WIDTH) then
      wptr_rdomain_cmp (MAX_ADDR_WIDTH - 1 downto ADDR_WIDTH_DIFF ) <=
         wptr_rdomain (MIN_ADDR_WIDTH - 1 downto 0 );
      wptr_rdomain_cmp (ADDR_WIDTH_DIFF - 1 downto 0 ) <=
         (others => '0');
      rptr_wdomain_cmp <= 
         rptr_wdomain(MAX_ADDR_WIDTH - 1 downto ADDR_WIDTH_DIFF);
   -------------------------------------------------------------------    
   else -- RADDR_WIDTH = WADDR_WIDTH
      wptr_rdomain_cmp <= wptr_rdomain;
      rptr_wdomain_cmp <= rptr_wdomain;

   end if;   
end process;

process (rptr_wdomain_cmp, rptr_wrap_bit_wdomain, wptr, wptr_wrap_bit)
begin
   if (rptr_wrap_bit_wdomain /= wptr_wrap_bit) then
      -- An improper use of RPRST could cause num_unread_loc >= DEPTH,
      -- when the wrap bits are different but wptr > rptr
      num_unread_loc_wdomain <=  ( DEPTH_W + wptr) - rptr_wdomain_cmp;
   else 
      num_unread_loc_wdomain <= "0" & (wptr -  rptr_wdomain_cmp);
   end if;
end process;

process (wptr_rdomain_cmp, wptr_wrap_bit_rdomain, rptr, rptr_wrap_bit)
begin
   if (wptr_wrap_bit_rdomain /= rptr_wrap_bit) then
      -- An improper use of RPRST could cause num_unread_loc >= DEPTH,
      -- when the wrap bits are different but wptr > rptr
      num_unread_loc_rdomain <=  ( DEPTH_R + wptr_rdomain_cmp) - rptr;
   else 
      num_unread_loc_rdomain <= "0" & (wptr_rdomain_cmp - rptr  );
   end if;
end process;
full_bit <= '1' when (num_unread_loc_wdomain >= DEPTH_W) else '0';
FULL <= full_bit;
AMFULL <= '1' when (num_unread_loc_wdomain >= DEPTH_W - ALMOST_FULL_X) else '0';

-- AMEMPTY/EMPTY  are ACTIVE LOW !!!!!!!!!!!!!!!!!!!!!!!!!!!!
empty_bit <= '1' when (num_unread_loc_rdomain = 0 ) else '0';
EMPTY <= not(empty_bit); 
AMEMPTY <= '0' when (num_unread_loc_rdomain <= ALMOST_EMPTY_Y) else '1';

-- ************************************************************************
-- DO LATCH
-- ************************************************************************
process (RCLK)
begin
   if (rising_edge (RCLK)) then 
      rden_p1 <= RE;
      empty_p1 <= empty_bit;
   end if;
end process;

process (do_ram, RST, rden_p1, empty_p1)
begin
   if (RST = '1') then
      DO <= (others => '0');
   elsif (rden_p1 = '1' and empty_p1 = '0') then
      DO <= do_ram;
   end if;
end process;
-- ************************************************************************
-- WRITE READ POINTERS
-- ************************************************************************
process (RST, WCLK)
begin

   if (RST = '1')  then
      wptr_wrap_appended <= (others => '0');
   elsif ( WCLK'event and WCLK = '1') then
      if (WE = '1' and full_bit = '0') then
         wptr_wrap_appended <= next_wptr_wrap_appended after 1 ns;
      end if;
   end if;
end process;

--ct092804
process (RST, RPRST, RCLK)
begin

   if (RST = '1'or RPRST = '1')  then
      rptr_wrap_appended <= (others => '0') ;
   elsif ( RCLK'event and RCLK = '1') then
      if ( (RE and not(empty_bit)) = '1') then
         rptr_wrap_appended <= next_rptr_wrap_appended after 1 ns;
      end if;
   end if ;   
end process;



-- ************************************************************************
-- POINTER SYNCHRONIZATIONS (SIMPLY DONE TO MATCH THE GATE-LEVEL MODEL)
-- ************************************************************************

process (RST, WCLK)
begin
   if (RST = '1')  then
      rptr_wrap_appended_wdomain <= (others => '0');
   elsif ( WCLK'event and WCLK = '1') then
      rptr_wrap_appended_wdomain <= rptr_wrap_appended after 1 ns;
   end if;
end process;


process (RST, RCLK)
begin
   if (RST = '1')  then
      wptr_wrap_appended_rdomain <= (others => '0');
   elsif ( RCLK'event and RCLK = '1') then
      wptr_wrap_appended_rdomain <= wptr_wrap_appended after 1 ns;
   end if;
end process;

-- **********************************************************************
-- END ARCHITECTURE: SC_FIFO_V2_16K
-- **********************************************************************
end LATTICE_BEHAV; 






library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

entity l_fifodcx is
  generic (
	 lpm_type      : string  := "LPM_FIFO_DCX";
	 lpm_widthw     : integer := 1;
	 lpm_widthr     : integer := 1;
	 lpm_widthuw    : integer := 1;
	 lpm_widthur    : integer := 1;
	 lpm_numwordsw  : integer := 2;
	 lpm_numwordsr  : integer := 2;
         lpm_amfull_flag : integer := 1;
         lpm_amempty_flag : integer := 1;
	 lpm_hint      : string  := "UNUSED");

  port (
	 Data          :  in  std_logic_vector (lpm_widthw-1 downto 0);
	 WrClock       :  in  std_logic;
	 WrEn          :  in  std_logic;
	 RdClock       :  in  std_logic;
	 RdEn          :  in  std_logic;
	 Reset          :  in  std_logic;
	 RPReset       :  in  std_logic;
	 Q             :  out std_logic_vector (lpm_widthr-1 downto 0);
	 Full          :  out std_logic;
	 Empty         :  out std_logic;
	 AlmostFull    :  out std_logic;
	 AlmostEmpty   :  out std_logic);

end l_fifodcx;

architecture fun_simulation of l_fifodcx is

  component SC_FIFO_V2_16K

    generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0; 
        TERMINAL_COUNT : integer := 511; 
        MEM_INIT_FILE  : string  := "mem_init_file"

         );

    port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);

        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)

        ); 

end component;

     signal FullIn, EmptyIn : std_logic;


  begin

      FullIn  <= '0';
      EmptyIn <= '1';


  SC_FIFO_inst : SC_FIFO_V2_16K

    generic map (

        DEVICE_FAMILY   =>  open,
        WADDR_WIDTH     =>  lpm_widthuw,
        WDATA_WIDTH     =>  lpm_widthw,
        RADDR_WIDTH     =>  lpm_widthur,
        RDATA_WIDTH     =>  lpm_widthr,
        ALMOST_FULL_X   =>  lpm_amfull_flag,
        ALMOST_EMPTY_Y  =>  lpm_amempty_flag,
        MEM_INIT_FLAG   =>  0,
        TERMINAL_COUNT  =>  lpm_numwordsw - 1,
        MEM_INIT_FILE   => open )

    port map (
        WE         => WrEn, 
        WCLK       => WrClock,
        RST        => Reset, 
        RPRST      => RPReset, 
        RE         => RdEn, 
        RCLK       => RdClock, 
        FULLIN     => FullIn, 
        EMPTYIN    => EmptyIn, 
        DI         => Data, 

        FULL       => Full, 
        EMPTY      => Empty, 
        AMFULL     => AlmostFull, 
        AMEMPTY    => AlmostEmpty, 
        DO         => Q
        ); 

end;



----- CELL RAMBFIFO16KA_WX32_RX16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX32_RX16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 512;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI4_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI5_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI6_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI7_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI8_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI8_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI9_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI9_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI10_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI10_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI11_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI11_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI12_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI12_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI13_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI13_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI14_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI14_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI15_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI15_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI16_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI16_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI17_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI17_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI18_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI18_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI19_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI19_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI20_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI20_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI21_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI21_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI22_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI22_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI23_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI23_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI24_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI24_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI25_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI25_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI26_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI26_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI27_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI27_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI28_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI28_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI29_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI29_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI30_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI30_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI31_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI31_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI8                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI9                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI10                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI11                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI12                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI13                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI14                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI15                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI16                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI17                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI18                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI19                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI20                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI21                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI22                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI23                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI24                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI25                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI26                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI27                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI28                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI29                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI30                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI31                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DI4                             : in    STD_ULOGIC;
      DI5                             : in    STD_ULOGIC;
      DI6                             : in    STD_ULOGIC;
      DI7                             : in    STD_ULOGIC;
      DI8                             : in    STD_ULOGIC;
      DI9                             : in    STD_ULOGIC;
      DI10                             : in    STD_ULOGIC;
      DI11                             : in    STD_ULOGIC;
      DI12                             : in    STD_ULOGIC;
      DI13                             : in    STD_ULOGIC;
      DI14                             : in    STD_ULOGIC;
      DI15                             : in    STD_ULOGIC;
      DI16                             : in    STD_ULOGIC;
      DI17                             : in    STD_ULOGIC;
      DI18                             : in    STD_ULOGIC;
      DI19                             : in    STD_ULOGIC;
      DI20                             : in    STD_ULOGIC;
      DI21                             : in    STD_ULOGIC;
      DI22                             : in    STD_ULOGIC;
      DI23                             : in    STD_ULOGIC;
      DI24                             : in    STD_ULOGIC;
      DI25                             : in    STD_ULOGIC;
      DI26                             : in    STD_ULOGIC;
      DI27                             : in    STD_ULOGIC;
      DI28                             : in    STD_ULOGIC;
      DI29                             : in    STD_ULOGIC;
      DI30                             : in    STD_ULOGIC;
      DI31                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      DO4                             : out    STD_ULOGIC;
      DO5                             : out    STD_ULOGIC;
      DO6                             : out    STD_ULOGIC;
      DO7                             : out    STD_ULOGIC;
      DO8                             : out    STD_ULOGIC;
      DO9                             : out    STD_ULOGIC;
      DO10                             : out    STD_ULOGIC;
      DO11                             : out    STD_ULOGIC;
      DO12                             : out    STD_ULOGIC;
      DO13                             : out    STD_ULOGIC;
      DO14                             : out    STD_ULOGIC;
      DO15                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX32_RX16 : entity is FALSE;
end RAMBFIFO16KA_WX32_RX16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX32_RX16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI4_ipd       : std_ulogic := 'X';
      signal DI5_ipd       : std_ulogic := 'X';
      signal DI6_ipd       : std_ulogic := 'X';
      signal DI7_ipd       : std_ulogic := 'X';
      signal DI8_ipd       : std_ulogic := 'X';
      signal DI9_ipd       : std_ulogic := 'X';
      signal DI10_ipd       : std_ulogic := 'X';
      signal DI11_ipd       : std_ulogic := 'X';
      signal DI12_ipd       : std_ulogic := 'X';
      signal DI13_ipd       : std_ulogic := 'X';
      signal DI14_ipd       : std_ulogic := 'X';
      signal DI15_ipd       : std_ulogic := 'X';
      signal DI16_ipd       : std_ulogic := 'X';
      signal DI17_ipd       : std_ulogic := 'X';
      signal DI18_ipd       : std_ulogic := 'X';
      signal DI19_ipd       : std_ulogic := 'X';
      signal DI20_ipd       : std_ulogic := 'X';
      signal DI21_ipd       : std_ulogic := 'X';
      signal DI22_ipd       : std_ulogic := 'X';
      signal DI23_ipd       : std_ulogic := 'X';
      signal DI24_ipd       : std_ulogic := 'X';
      signal DI25_ipd       : std_ulogic := 'X';
      signal DI26_ipd       : std_ulogic := 'X';
      signal DI27_ipd       : std_ulogic := 'X';
      signal DI28_ipd       : std_ulogic := 'X';
      signal DI29_ipd       : std_ulogic := 'X';
      signal DI30_ipd       : std_ulogic := 'X';
      signal DI31_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(31 downto 0);
      signal DO             : std_logic_vector(15 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI31_ipd & DI30_ipd & DI29_ipd & DI28_ipd & DI27_ipd & DI26_ipd & DI25_ipd & DI24_ipd & DI23_ipd & DI22_ipd & DI21_ipd & DI20_ipd & DI19_ipd & DI18_ipd & DI17_ipd & DI16_ipd & DI15_ipd & DI14_ipd & DI13_ipd & DI12_ipd & DI11_ipd & DI10_ipd & DI9_ipd & DI8_ipd & DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);
        VitalWireDelay (DI8_ipd, DI8, tipd_DI8);
        VitalWireDelay (DI9_ipd, DI9, tipd_DI9);
        VitalWireDelay (DI10_ipd, DI10, tipd_DI10);
        VitalWireDelay (DI11_ipd, DI11, tipd_DI11);
        VitalWireDelay (DI12_ipd, DI12, tipd_DI12);
        VitalWireDelay (DI13_ipd, DI13, tipd_DI13);
        VitalWireDelay (DI14_ipd, DI14, tipd_DI14);
        VitalWireDelay (DI15_ipd, DI15, tipd_DI15);
        VitalWireDelay (DI16_ipd, DI16, tipd_DI16);
        VitalWireDelay (DI17_ipd, DI17, tipd_DI17);
        VitalWireDelay (DI18_ipd, DI18, tipd_DI18);
        VitalWireDelay (DI19_ipd, DI19, tipd_DI19);
        VitalWireDelay (DI20_ipd, DI20, tipd_DI20);
        VitalWireDelay (DI21_ipd, DI21, tipd_DI21);
        VitalWireDelay (DI22_ipd, DI22, tipd_DI22);
        VitalWireDelay (DI23_ipd, DI23, tipd_DI23);
        VitalWireDelay (DI24_ipd, DI24, tipd_DI24);
        VitalWireDelay (DI25_ipd, DI25, tipd_DI25);
        VitalWireDelay (DI26_ipd, DI26, tipd_DI26);
        VitalWireDelay (DI27_ipd, DI27, tipd_DI27);
        VitalWireDelay (DI28_ipd, DI28, tipd_DI28);
        VitalWireDelay (DI29_ipd, DI29, tipd_DI29);
        VitalWireDelay (DI30_ipd, DI30, tipd_DI30);
        VitalWireDelay (DI31_ipd, DI31, tipd_DI31);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI4_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI5_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI6_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI7_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI8_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI9_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI10_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI11_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI12_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI13_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI14_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI15_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI16_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI17_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI18_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI19_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI20_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI21_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI22_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI23_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI24_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI25_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI26_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI27_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI28_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI29_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI30_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI31_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI8_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI9_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI10_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI11_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI12_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI13_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI14_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI15_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI16_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI17_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI18_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI19_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI20_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI21_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI22_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI23_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI24_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI25_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI26_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI27_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI28_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI29_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI30_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI31_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable DO8_zd          : std_ulogic := 'X';
        variable DO9_zd          : std_ulogic := 'X';
        variable DO10_zd          : std_ulogic := 'X';
        variable DO11_zd          : std_ulogic := 'X';
        variable DO12_zd          : std_ulogic := 'X';
        variable DO13_zd          : std_ulogic := 'X';
        variable DO14_zd          : std_ulogic := 'X';
        variable DO15_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_WCLK_posedge,
          TimingData              => Tmkr_DI4_WCLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI4_WCLK_noedge_posedge,
          HoldLow                 => thold_DI4_WCLK_noedge_posedge,
          HoldHigh                => thold_DI4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_WCLK_posedge,
          TimingData              => Tmkr_DI5_WCLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI5_WCLK_noedge_posedge,
          HoldLow                 => thold_DI5_WCLK_noedge_posedge,
          HoldHigh                => thold_DI5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_WCLK_posedge,
          TimingData              => Tmkr_DI6_WCLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI6_WCLK_noedge_posedge,
          HoldLow                 => thold_DI6_WCLK_noedge_posedge,
          HoldHigh                => thold_DI6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_WCLK_posedge,
          TimingData              => Tmkr_DI7_WCLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI7_WCLK_noedge_posedge,
          HoldLow                 => thold_DI7_WCLK_noedge_posedge,
          HoldHigh                => thold_DI7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI8_WCLK_posedge,
          TimingData              => Tmkr_DI8_WCLK_posedge,
          TestSignal              => DI8_ipd,
          TestSignalName          => "DI8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI8_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI8_WCLK_noedge_posedge,
          HoldLow                 => thold_DI8_WCLK_noedge_posedge,
          HoldHigh                => thold_DI8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI9_WCLK_posedge,
          TimingData              => Tmkr_DI9_WCLK_posedge,
          TestSignal              => DI9_ipd,
          TestSignalName          => "DI9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI9_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI9_WCLK_noedge_posedge,
          HoldLow                 => thold_DI9_WCLK_noedge_posedge,
          HoldHigh                => thold_DI9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI10_WCLK_posedge,
          TimingData              => Tmkr_DI10_WCLK_posedge,
          TestSignal              => DI10_ipd,
          TestSignalName          => "DI10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI10_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI10_WCLK_noedge_posedge,
          HoldLow                 => thold_DI10_WCLK_noedge_posedge,
          HoldHigh                => thold_DI10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI11_WCLK_posedge,
          TimingData              => Tmkr_DI11_WCLK_posedge,
          TestSignal              => DI11_ipd,
          TestSignalName          => "DI11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI11_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI11_WCLK_noedge_posedge,
          HoldLow                 => thold_DI11_WCLK_noedge_posedge,
          HoldHigh                => thold_DI11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI12_WCLK_posedge,
          TimingData              => Tmkr_DI12_WCLK_posedge,
          TestSignal              => DI12_ipd,
          TestSignalName          => "DI12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI12_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI12_WCLK_noedge_posedge,
          HoldLow                 => thold_DI12_WCLK_noedge_posedge,
          HoldHigh                => thold_DI12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI13_WCLK_posedge,
          TimingData              => Tmkr_DI13_WCLK_posedge,
          TestSignal              => DI13_ipd,
          TestSignalName          => "DI13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI13_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI13_WCLK_noedge_posedge,
          HoldLow                 => thold_DI13_WCLK_noedge_posedge,
          HoldHigh                => thold_DI13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI14_WCLK_posedge,
          TimingData              => Tmkr_DI14_WCLK_posedge,
          TestSignal              => DI14_ipd,
          TestSignalName          => "DI14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI14_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI14_WCLK_noedge_posedge,
          HoldLow                 => thold_DI14_WCLK_noedge_posedge,
          HoldHigh                => thold_DI14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI15_WCLK_posedge,
          TimingData              => Tmkr_DI15_WCLK_posedge,
          TestSignal              => DI15_ipd,
          TestSignalName          => "DI15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI15_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI15_WCLK_noedge_posedge,
          HoldLow                 => thold_DI15_WCLK_noedge_posedge,
          HoldHigh                => thold_DI15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI16_WCLK_posedge,
          TimingData              => Tmkr_DI16_WCLK_posedge,
          TestSignal              => DI16_ipd,
          TestSignalName          => "DI16",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI16_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI16_WCLK_noedge_posedge,
          HoldLow                 => thold_DI16_WCLK_noedge_posedge,
          HoldHigh                => thold_DI16_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI17_WCLK_posedge,
          TimingData              => Tmkr_DI17_WCLK_posedge,
          TestSignal              => DI17_ipd,
          TestSignalName          => "DI17",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI17_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI17_WCLK_noedge_posedge,
          HoldLow                 => thold_DI17_WCLK_noedge_posedge,
          HoldHigh                => thold_DI17_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI18_WCLK_posedge,
          TimingData              => Tmkr_DI18_WCLK_posedge,
          TestSignal              => DI18_ipd,
          TestSignalName          => "DI18",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI18_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI18_WCLK_noedge_posedge,
          HoldLow                 => thold_DI18_WCLK_noedge_posedge,
          HoldHigh                => thold_DI18_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI19_WCLK_posedge,
          TimingData              => Tmkr_DI19_WCLK_posedge,
          TestSignal              => DI19_ipd,
          TestSignalName          => "DI19",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI19_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI19_WCLK_noedge_posedge,
          HoldLow                 => thold_DI19_WCLK_noedge_posedge,
          HoldHigh                => thold_DI19_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI20_WCLK_posedge,
          TimingData              => Tmkr_DI20_WCLK_posedge,
          TestSignal              => DI20_ipd,
          TestSignalName          => "DI20",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI20_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI20_WCLK_noedge_posedge,
          HoldLow                 => thold_DI20_WCLK_noedge_posedge,
          HoldHigh                => thold_DI20_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI21_WCLK_posedge,
          TimingData              => Tmkr_DI21_WCLK_posedge,
          TestSignal              => DI21_ipd,
          TestSignalName          => "DI21",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI21_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI21_WCLK_noedge_posedge,
          HoldLow                 => thold_DI21_WCLK_noedge_posedge,
          HoldHigh                => thold_DI21_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI22_WCLK_posedge,
          TimingData              => Tmkr_DI22_WCLK_posedge,
          TestSignal              => DI22_ipd,
          TestSignalName          => "DI22",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI22_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI22_WCLK_noedge_posedge,
          HoldLow                 => thold_DI22_WCLK_noedge_posedge,
          HoldHigh                => thold_DI22_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI23_WCLK_posedge,
          TimingData              => Tmkr_DI23_WCLK_posedge,
          TestSignal              => DI23_ipd,
          TestSignalName          => "DI23",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI23_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI23_WCLK_noedge_posedge,
          HoldLow                 => thold_DI23_WCLK_noedge_posedge,
          HoldHigh                => thold_DI23_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI24_WCLK_posedge,
          TimingData              => Tmkr_DI24_WCLK_posedge,
          TestSignal              => DI24_ipd,
          TestSignalName          => "DI24",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI24_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI24_WCLK_noedge_posedge,
          HoldLow                 => thold_DI24_WCLK_noedge_posedge,
          HoldHigh                => thold_DI24_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI25_WCLK_posedge,
          TimingData              => Tmkr_DI25_WCLK_posedge,
          TestSignal              => DI25_ipd,
          TestSignalName          => "DI25",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI25_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI25_WCLK_noedge_posedge,
          HoldLow                 => thold_DI25_WCLK_noedge_posedge,
          HoldHigh                => thold_DI25_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI26_WCLK_posedge,
          TimingData              => Tmkr_DI26_WCLK_posedge,
          TestSignal              => DI26_ipd,
          TestSignalName          => "DI26",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI26_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI26_WCLK_noedge_posedge,
          HoldLow                 => thold_DI26_WCLK_noedge_posedge,
          HoldHigh                => thold_DI26_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI27_WCLK_posedge,
          TimingData              => Tmkr_DI27_WCLK_posedge,
          TestSignal              => DI27_ipd,
          TestSignalName          => "DI27",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI27_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI27_WCLK_noedge_posedge,
          HoldLow                 => thold_DI27_WCLK_noedge_posedge,
          HoldHigh                => thold_DI27_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI28_WCLK_posedge,
          TimingData              => Tmkr_DI28_WCLK_posedge,
          TestSignal              => DI28_ipd,
          TestSignalName          => "DI28",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI28_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI28_WCLK_noedge_posedge,
          HoldLow                 => thold_DI28_WCLK_noedge_posedge,
          HoldHigh                => thold_DI28_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI29_WCLK_posedge,
          TimingData              => Tmkr_DI29_WCLK_posedge,
          TestSignal              => DI29_ipd,
          TestSignalName          => "DI29",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI29_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI29_WCLK_noedge_posedge,
          HoldLow                 => thold_DI29_WCLK_noedge_posedge,
          HoldHigh                => thold_DI29_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI30_WCLK_posedge,
          TimingData              => Tmkr_DI30_WCLK_posedge,
          TestSignal              => DI30_ipd,
          TestSignalName          => "DI30",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI30_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI30_WCLK_noedge_posedge,
          HoldLow                 => thold_DI30_WCLK_noedge_posedge,
          HoldHigh                => thold_DI30_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI31_WCLK_posedge,
          TimingData              => Tmkr_DI31_WCLK_posedge,
          TestSignal              => DI31_ipd,
          TestSignalName          => "DI31",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI31_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI31_WCLK_noedge_posedge,
          HoldLow                 => thold_DI31_WCLK_noedge_posedge,
          HoldHigh                => thold_DI31_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Tviol_DI4_WCLK_posedge or 
                 Tviol_DI5_WCLK_posedge or 
                 Tviol_DI6_WCLK_posedge or 
                 Tviol_DI7_WCLK_posedge or 
                 Tviol_DI8_WCLK_posedge or 
                 Tviol_DI9_WCLK_posedge or 
                 Tviol_DI10_WCLK_posedge or 
                 Tviol_DI11_WCLK_posedge or 
                 Tviol_DI12_WCLK_posedge or 
                 Tviol_DI13_WCLK_posedge or 
                 Tviol_DI14_WCLK_posedge or 
                 Tviol_DI15_WCLK_posedge or 
                 Tviol_DI16_WCLK_posedge or 
                 Tviol_DI17_WCLK_posedge or 
                 Tviol_DI18_WCLK_posedge or 
                 Tviol_DI19_WCLK_posedge or 
                 Tviol_DI20_WCLK_posedge or 
                 Tviol_DI21_WCLK_posedge or 
                 Tviol_DI22_WCLK_posedge or 
                 Tviol_DI23_WCLK_posedge or 
                 Tviol_DI24_WCLK_posedge or 
                 Tviol_DI25_WCLK_posedge or 
                 Tviol_DI26_WCLK_posedge or 
                 Tviol_DI27_WCLK_posedge or 
                 Tviol_DI28_WCLK_posedge or 
                 Tviol_DI29_WCLK_posedge or 
                 Tviol_DI30_WCLK_posedge or 
                 Tviol_DI31_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_DO8  : process
      variable DO8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO8_zd := DO(8);

    VitalPathDelay01 (
      OutSignal => DO8,
      GlitchData => O_GlitchData,
      OutSignalName => "DO8",
      OutTemp => DO8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(8);
      end process;

    VitalBehavior_DO9  : process
      variable DO9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO9_zd := DO(9);

    VitalPathDelay01 (
      OutSignal => DO9,
      GlitchData => O_GlitchData,
      OutSignalName => "DO9",
      OutTemp => DO9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(9);
      end process;

    VitalBehavior_DO10  : process
      variable DO10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO10_zd := DO(10);

    VitalPathDelay01 (
      OutSignal => DO10,
      GlitchData => O_GlitchData,
      OutSignalName => "DO10",
      OutTemp => DO10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(10);
      end process;

    VitalBehavior_DO11  : process
      variable DO11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO11_zd := DO(11);

    VitalPathDelay01 (
      OutSignal => DO11,
      GlitchData => O_GlitchData,
      OutSignalName => "DO11",
      OutTemp => DO11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(11);
      end process;

    VitalBehavior_DO12  : process
      variable DO12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO12_zd := DO(12);

    VitalPathDelay01 (
      OutSignal => DO12,
      GlitchData => O_GlitchData,
      OutSignalName => "DO12",
      OutTemp => DO12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(12);
      end process;

    VitalBehavior_DO13  : process
      variable DO13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO13_zd := DO(13);

    VitalPathDelay01 (
      OutSignal => DO13,
      GlitchData => O_GlitchData,
      OutSignalName => "DO13",
      OutTemp => DO13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(13);
      end process;

    VitalBehavior_DO14  : process
      variable DO14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO14_zd := DO(14);

    VitalPathDelay01 (
      OutSignal => DO14,
      GlitchData => O_GlitchData,
      OutSignalName => "DO14",
      OutTemp => DO14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(14);
      end process;

    VitalBehavior_DO15  : process
      variable DO15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO15_zd := DO(15);

    VitalPathDelay01 (
      OutSignal => DO15,
      GlitchData => O_GlitchData,
      OutSignalName => "DO15",
      OutTemp => DO15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(15);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 9,
        WDATA_WIDTH    => 32,
        RADDR_WIDTH    => 10,
        RDATA_WIDTH    => 16,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX32_RX16_VITAL of RAMBFIFO16KA_WX32_RX16 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX32_RX16_VITAL;

----- CELL RAMBFIFO16KA_WX32_RX8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX32_RX8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 512;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI4_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI5_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI6_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI7_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI8_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI8_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI9_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI9_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI10_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI10_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI11_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI11_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI12_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI12_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI13_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI13_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI14_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI14_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI15_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI15_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI16_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI16_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI17_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI17_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI18_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI18_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI19_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI19_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI20_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI20_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI21_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI21_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI22_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI22_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI23_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI23_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI24_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI24_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI25_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI25_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI26_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI26_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI27_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI27_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI28_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI28_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI29_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI29_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI30_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI30_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI31_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI31_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI8                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI9                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI10                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI11                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI12                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI13                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI14                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI15                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI16                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI17                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI18                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI19                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI20                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI21                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI22                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI23                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI24                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI25                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI26                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI27                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI28                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI29                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI30                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI31                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DI4                             : in    STD_ULOGIC;
      DI5                             : in    STD_ULOGIC;
      DI6                             : in    STD_ULOGIC;
      DI7                             : in    STD_ULOGIC;
      DI8                             : in    STD_ULOGIC;
      DI9                             : in    STD_ULOGIC;
      DI10                             : in    STD_ULOGIC;
      DI11                             : in    STD_ULOGIC;
      DI12                             : in    STD_ULOGIC;
      DI13                             : in    STD_ULOGIC;
      DI14                             : in    STD_ULOGIC;
      DI15                             : in    STD_ULOGIC;
      DI16                             : in    STD_ULOGIC;
      DI17                             : in    STD_ULOGIC;
      DI18                             : in    STD_ULOGIC;
      DI19                             : in    STD_ULOGIC;
      DI20                             : in    STD_ULOGIC;
      DI21                             : in    STD_ULOGIC;
      DI22                             : in    STD_ULOGIC;
      DI23                             : in    STD_ULOGIC;
      DI24                             : in    STD_ULOGIC;
      DI25                             : in    STD_ULOGIC;
      DI26                             : in    STD_ULOGIC;
      DI27                             : in    STD_ULOGIC;
      DI28                             : in    STD_ULOGIC;
      DI29                             : in    STD_ULOGIC;
      DI30                             : in    STD_ULOGIC;
      DI31                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      DO4                             : out    STD_ULOGIC;
      DO5                             : out    STD_ULOGIC;
      DO6                             : out    STD_ULOGIC;
      DO7                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX32_RX8 : entity is FALSE;
end RAMBFIFO16KA_WX32_RX8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX32_RX8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI4_ipd       : std_ulogic := 'X';
      signal DI5_ipd       : std_ulogic := 'X';
      signal DI6_ipd       : std_ulogic := 'X';
      signal DI7_ipd       : std_ulogic := 'X';
      signal DI8_ipd       : std_ulogic := 'X';
      signal DI9_ipd       : std_ulogic := 'X';
      signal DI10_ipd       : std_ulogic := 'X';
      signal DI11_ipd       : std_ulogic := 'X';
      signal DI12_ipd       : std_ulogic := 'X';
      signal DI13_ipd       : std_ulogic := 'X';
      signal DI14_ipd       : std_ulogic := 'X';
      signal DI15_ipd       : std_ulogic := 'X';
      signal DI16_ipd       : std_ulogic := 'X';
      signal DI17_ipd       : std_ulogic := 'X';
      signal DI18_ipd       : std_ulogic := 'X';
      signal DI19_ipd       : std_ulogic := 'X';
      signal DI20_ipd       : std_ulogic := 'X';
      signal DI21_ipd       : std_ulogic := 'X';
      signal DI22_ipd       : std_ulogic := 'X';
      signal DI23_ipd       : std_ulogic := 'X';
      signal DI24_ipd       : std_ulogic := 'X';
      signal DI25_ipd       : std_ulogic := 'X';
      signal DI26_ipd       : std_ulogic := 'X';
      signal DI27_ipd       : std_ulogic := 'X';
      signal DI28_ipd       : std_ulogic := 'X';
      signal DI29_ipd       : std_ulogic := 'X';
      signal DI30_ipd       : std_ulogic := 'X';
      signal DI31_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(31 downto 0);
      signal DO             : std_logic_vector(7 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI31_ipd & DI30_ipd & DI29_ipd & DI28_ipd & DI27_ipd & DI26_ipd & DI25_ipd & DI24_ipd & DI23_ipd & DI22_ipd & DI21_ipd & DI20_ipd & DI19_ipd & DI18_ipd & DI17_ipd & DI16_ipd & DI15_ipd & DI14_ipd & DI13_ipd & DI12_ipd & DI11_ipd & DI10_ipd & DI9_ipd & DI8_ipd & DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);
        VitalWireDelay (DI8_ipd, DI8, tipd_DI8);
        VitalWireDelay (DI9_ipd, DI9, tipd_DI9);
        VitalWireDelay (DI10_ipd, DI10, tipd_DI10);
        VitalWireDelay (DI11_ipd, DI11, tipd_DI11);
        VitalWireDelay (DI12_ipd, DI12, tipd_DI12);
        VitalWireDelay (DI13_ipd, DI13, tipd_DI13);
        VitalWireDelay (DI14_ipd, DI14, tipd_DI14);
        VitalWireDelay (DI15_ipd, DI15, tipd_DI15);
        VitalWireDelay (DI16_ipd, DI16, tipd_DI16);
        VitalWireDelay (DI17_ipd, DI17, tipd_DI17);
        VitalWireDelay (DI18_ipd, DI18, tipd_DI18);
        VitalWireDelay (DI19_ipd, DI19, tipd_DI19);
        VitalWireDelay (DI20_ipd, DI20, tipd_DI20);
        VitalWireDelay (DI21_ipd, DI21, tipd_DI21);
        VitalWireDelay (DI22_ipd, DI22, tipd_DI22);
        VitalWireDelay (DI23_ipd, DI23, tipd_DI23);
        VitalWireDelay (DI24_ipd, DI24, tipd_DI24);
        VitalWireDelay (DI25_ipd, DI25, tipd_DI25);
        VitalWireDelay (DI26_ipd, DI26, tipd_DI26);
        VitalWireDelay (DI27_ipd, DI27, tipd_DI27);
        VitalWireDelay (DI28_ipd, DI28, tipd_DI28);
        VitalWireDelay (DI29_ipd, DI29, tipd_DI29);
        VitalWireDelay (DI30_ipd, DI30, tipd_DI30);
        VitalWireDelay (DI31_ipd, DI31, tipd_DI31);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI4_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI5_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI6_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI7_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI8_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI9_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI10_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI11_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI12_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI13_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI14_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI15_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI16_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI17_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI18_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI19_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI20_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI21_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI22_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI23_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI24_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI25_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI26_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI27_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI28_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI29_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI30_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI31_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI8_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI9_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI10_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI11_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI12_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI13_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI14_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI15_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI16_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI17_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI18_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI19_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI20_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI21_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI22_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI23_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI24_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI25_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI26_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI27_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI28_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI29_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI30_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI31_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_WCLK_posedge,
          TimingData              => Tmkr_DI4_WCLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI4_WCLK_noedge_posedge,
          HoldLow                 => thold_DI4_WCLK_noedge_posedge,
          HoldHigh                => thold_DI4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_WCLK_posedge,
          TimingData              => Tmkr_DI5_WCLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI5_WCLK_noedge_posedge,
          HoldLow                 => thold_DI5_WCLK_noedge_posedge,
          HoldHigh                => thold_DI5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_WCLK_posedge,
          TimingData              => Tmkr_DI6_WCLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI6_WCLK_noedge_posedge,
          HoldLow                 => thold_DI6_WCLK_noedge_posedge,
          HoldHigh                => thold_DI6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_WCLK_posedge,
          TimingData              => Tmkr_DI7_WCLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI7_WCLK_noedge_posedge,
          HoldLow                 => thold_DI7_WCLK_noedge_posedge,
          HoldHigh                => thold_DI7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI8_WCLK_posedge,
          TimingData              => Tmkr_DI8_WCLK_posedge,
          TestSignal              => DI8_ipd,
          TestSignalName          => "DI8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI8_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI8_WCLK_noedge_posedge,
          HoldLow                 => thold_DI8_WCLK_noedge_posedge,
          HoldHigh                => thold_DI8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI9_WCLK_posedge,
          TimingData              => Tmkr_DI9_WCLK_posedge,
          TestSignal              => DI9_ipd,
          TestSignalName          => "DI9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI9_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI9_WCLK_noedge_posedge,
          HoldLow                 => thold_DI9_WCLK_noedge_posedge,
          HoldHigh                => thold_DI9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI10_WCLK_posedge,
          TimingData              => Tmkr_DI10_WCLK_posedge,
          TestSignal              => DI10_ipd,
          TestSignalName          => "DI10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI10_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI10_WCLK_noedge_posedge,
          HoldLow                 => thold_DI10_WCLK_noedge_posedge,
          HoldHigh                => thold_DI10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI11_WCLK_posedge,
          TimingData              => Tmkr_DI11_WCLK_posedge,
          TestSignal              => DI11_ipd,
          TestSignalName          => "DI11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI11_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI11_WCLK_noedge_posedge,
          HoldLow                 => thold_DI11_WCLK_noedge_posedge,
          HoldHigh                => thold_DI11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI12_WCLK_posedge,
          TimingData              => Tmkr_DI12_WCLK_posedge,
          TestSignal              => DI12_ipd,
          TestSignalName          => "DI12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI12_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI12_WCLK_noedge_posedge,
          HoldLow                 => thold_DI12_WCLK_noedge_posedge,
          HoldHigh                => thold_DI12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI13_WCLK_posedge,
          TimingData              => Tmkr_DI13_WCLK_posedge,
          TestSignal              => DI13_ipd,
          TestSignalName          => "DI13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI13_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI13_WCLK_noedge_posedge,
          HoldLow                 => thold_DI13_WCLK_noedge_posedge,
          HoldHigh                => thold_DI13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI14_WCLK_posedge,
          TimingData              => Tmkr_DI14_WCLK_posedge,
          TestSignal              => DI14_ipd,
          TestSignalName          => "DI14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI14_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI14_WCLK_noedge_posedge,
          HoldLow                 => thold_DI14_WCLK_noedge_posedge,
          HoldHigh                => thold_DI14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI15_WCLK_posedge,
          TimingData              => Tmkr_DI15_WCLK_posedge,
          TestSignal              => DI15_ipd,
          TestSignalName          => "DI15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI15_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI15_WCLK_noedge_posedge,
          HoldLow                 => thold_DI15_WCLK_noedge_posedge,
          HoldHigh                => thold_DI15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI16_WCLK_posedge,
          TimingData              => Tmkr_DI16_WCLK_posedge,
          TestSignal              => DI16_ipd,
          TestSignalName          => "DI16",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI16_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI16_WCLK_noedge_posedge,
          HoldLow                 => thold_DI16_WCLK_noedge_posedge,
          HoldHigh                => thold_DI16_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI17_WCLK_posedge,
          TimingData              => Tmkr_DI17_WCLK_posedge,
          TestSignal              => DI17_ipd,
          TestSignalName          => "DI17",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI17_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI17_WCLK_noedge_posedge,
          HoldLow                 => thold_DI17_WCLK_noedge_posedge,
          HoldHigh                => thold_DI17_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI18_WCLK_posedge,
          TimingData              => Tmkr_DI18_WCLK_posedge,
          TestSignal              => DI18_ipd,
          TestSignalName          => "DI18",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI18_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI18_WCLK_noedge_posedge,
          HoldLow                 => thold_DI18_WCLK_noedge_posedge,
          HoldHigh                => thold_DI18_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI19_WCLK_posedge,
          TimingData              => Tmkr_DI19_WCLK_posedge,
          TestSignal              => DI19_ipd,
          TestSignalName          => "DI19",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI19_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI19_WCLK_noedge_posedge,
          HoldLow                 => thold_DI19_WCLK_noedge_posedge,
          HoldHigh                => thold_DI19_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI20_WCLK_posedge,
          TimingData              => Tmkr_DI20_WCLK_posedge,
          TestSignal              => DI20_ipd,
          TestSignalName          => "DI20",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI20_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI20_WCLK_noedge_posedge,
          HoldLow                 => thold_DI20_WCLK_noedge_posedge,
          HoldHigh                => thold_DI20_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI21_WCLK_posedge,
          TimingData              => Tmkr_DI21_WCLK_posedge,
          TestSignal              => DI21_ipd,
          TestSignalName          => "DI21",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI21_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI21_WCLK_noedge_posedge,
          HoldLow                 => thold_DI21_WCLK_noedge_posedge,
          HoldHigh                => thold_DI21_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI22_WCLK_posedge,
          TimingData              => Tmkr_DI22_WCLK_posedge,
          TestSignal              => DI22_ipd,
          TestSignalName          => "DI22",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI22_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI22_WCLK_noedge_posedge,
          HoldLow                 => thold_DI22_WCLK_noedge_posedge,
          HoldHigh                => thold_DI22_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI23_WCLK_posedge,
          TimingData              => Tmkr_DI23_WCLK_posedge,
          TestSignal              => DI23_ipd,
          TestSignalName          => "DI23",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI23_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI23_WCLK_noedge_posedge,
          HoldLow                 => thold_DI23_WCLK_noedge_posedge,
          HoldHigh                => thold_DI23_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI24_WCLK_posedge,
          TimingData              => Tmkr_DI24_WCLK_posedge,
          TestSignal              => DI24_ipd,
          TestSignalName          => "DI24",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI24_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI24_WCLK_noedge_posedge,
          HoldLow                 => thold_DI24_WCLK_noedge_posedge,
          HoldHigh                => thold_DI24_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI25_WCLK_posedge,
          TimingData              => Tmkr_DI25_WCLK_posedge,
          TestSignal              => DI25_ipd,
          TestSignalName          => "DI25",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI25_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI25_WCLK_noedge_posedge,
          HoldLow                 => thold_DI25_WCLK_noedge_posedge,
          HoldHigh                => thold_DI25_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI26_WCLK_posedge,
          TimingData              => Tmkr_DI26_WCLK_posedge,
          TestSignal              => DI26_ipd,
          TestSignalName          => "DI26",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI26_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI26_WCLK_noedge_posedge,
          HoldLow                 => thold_DI26_WCLK_noedge_posedge,
          HoldHigh                => thold_DI26_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI27_WCLK_posedge,
          TimingData              => Tmkr_DI27_WCLK_posedge,
          TestSignal              => DI27_ipd,
          TestSignalName          => "DI27",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI27_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI27_WCLK_noedge_posedge,
          HoldLow                 => thold_DI27_WCLK_noedge_posedge,
          HoldHigh                => thold_DI27_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI28_WCLK_posedge,
          TimingData              => Tmkr_DI28_WCLK_posedge,
          TestSignal              => DI28_ipd,
          TestSignalName          => "DI28",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI28_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI28_WCLK_noedge_posedge,
          HoldLow                 => thold_DI28_WCLK_noedge_posedge,
          HoldHigh                => thold_DI28_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI29_WCLK_posedge,
          TimingData              => Tmkr_DI29_WCLK_posedge,
          TestSignal              => DI29_ipd,
          TestSignalName          => "DI29",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI29_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI29_WCLK_noedge_posedge,
          HoldLow                 => thold_DI29_WCLK_noedge_posedge,
          HoldHigh                => thold_DI29_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI30_WCLK_posedge,
          TimingData              => Tmkr_DI30_WCLK_posedge,
          TestSignal              => DI30_ipd,
          TestSignalName          => "DI30",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI30_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI30_WCLK_noedge_posedge,
          HoldLow                 => thold_DI30_WCLK_noedge_posedge,
          HoldHigh                => thold_DI30_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI31_WCLK_posedge,
          TimingData              => Tmkr_DI31_WCLK_posedge,
          TestSignal              => DI31_ipd,
          TestSignalName          => "DI31",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI31_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI31_WCLK_noedge_posedge,
          HoldLow                 => thold_DI31_WCLK_noedge_posedge,
          HoldHigh                => thold_DI31_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Tviol_DI4_WCLK_posedge or 
                 Tviol_DI5_WCLK_posedge or 
                 Tviol_DI6_WCLK_posedge or 
                 Tviol_DI7_WCLK_posedge or 
                 Tviol_DI8_WCLK_posedge or 
                 Tviol_DI9_WCLK_posedge or 
                 Tviol_DI10_WCLK_posedge or 
                 Tviol_DI11_WCLK_posedge or 
                 Tviol_DI12_WCLK_posedge or 
                 Tviol_DI13_WCLK_posedge or 
                 Tviol_DI14_WCLK_posedge or 
                 Tviol_DI15_WCLK_posedge or 
                 Tviol_DI16_WCLK_posedge or 
                 Tviol_DI17_WCLK_posedge or 
                 Tviol_DI18_WCLK_posedge or 
                 Tviol_DI19_WCLK_posedge or 
                 Tviol_DI20_WCLK_posedge or 
                 Tviol_DI21_WCLK_posedge or 
                 Tviol_DI22_WCLK_posedge or 
                 Tviol_DI23_WCLK_posedge or 
                 Tviol_DI24_WCLK_posedge or 
                 Tviol_DI25_WCLK_posedge or 
                 Tviol_DI26_WCLK_posedge or 
                 Tviol_DI27_WCLK_posedge or 
                 Tviol_DI28_WCLK_posedge or 
                 Tviol_DI29_WCLK_posedge or 
                 Tviol_DI30_WCLK_posedge or 
                 Tviol_DI31_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 9,
        WDATA_WIDTH    => 32,
        RADDR_WIDTH    => 11,
        RDATA_WIDTH    => 8,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX32_RX8_VITAL of RAMBFIFO16KA_WX32_RX8 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX32_RX8_VITAL;

----- CELL RAMBFIFO16KA_WX32_RX4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX32_RX4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 512;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI4_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI5_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI6_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI7_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI8_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI8_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI9_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI9_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI10_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI10_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI11_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI11_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI12_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI12_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI13_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI13_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI14_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI14_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI15_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI15_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI16_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI16_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI17_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI17_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI18_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI18_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI19_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI19_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI20_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI20_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI21_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI21_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI22_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI22_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI23_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI23_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI24_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI24_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI25_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI25_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI26_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI26_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI27_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI27_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI28_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI28_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI29_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI29_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI30_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI30_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI31_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI31_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI8                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI9                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI10                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI11                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI12                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI13                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI14                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI15                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI16                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI17                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI18                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI19                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI20                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI21                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI22                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI23                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI24                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI25                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI26                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI27                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI28                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI29                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI30                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI31                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DI4                             : in    STD_ULOGIC;
      DI5                             : in    STD_ULOGIC;
      DI6                             : in    STD_ULOGIC;
      DI7                             : in    STD_ULOGIC;
      DI8                             : in    STD_ULOGIC;
      DI9                             : in    STD_ULOGIC;
      DI10                             : in    STD_ULOGIC;
      DI11                             : in    STD_ULOGIC;
      DI12                             : in    STD_ULOGIC;
      DI13                             : in    STD_ULOGIC;
      DI14                             : in    STD_ULOGIC;
      DI15                             : in    STD_ULOGIC;
      DI16                             : in    STD_ULOGIC;
      DI17                             : in    STD_ULOGIC;
      DI18                             : in    STD_ULOGIC;
      DI19                             : in    STD_ULOGIC;
      DI20                             : in    STD_ULOGIC;
      DI21                             : in    STD_ULOGIC;
      DI22                             : in    STD_ULOGIC;
      DI23                             : in    STD_ULOGIC;
      DI24                             : in    STD_ULOGIC;
      DI25                             : in    STD_ULOGIC;
      DI26                             : in    STD_ULOGIC;
      DI27                             : in    STD_ULOGIC;
      DI28                             : in    STD_ULOGIC;
      DI29                             : in    STD_ULOGIC;
      DI30                             : in    STD_ULOGIC;
      DI31                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX32_RX4 : entity is FALSE;
end RAMBFIFO16KA_WX32_RX4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX32_RX4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI4_ipd       : std_ulogic := 'X';
      signal DI5_ipd       : std_ulogic := 'X';
      signal DI6_ipd       : std_ulogic := 'X';
      signal DI7_ipd       : std_ulogic := 'X';
      signal DI8_ipd       : std_ulogic := 'X';
      signal DI9_ipd       : std_ulogic := 'X';
      signal DI10_ipd       : std_ulogic := 'X';
      signal DI11_ipd       : std_ulogic := 'X';
      signal DI12_ipd       : std_ulogic := 'X';
      signal DI13_ipd       : std_ulogic := 'X';
      signal DI14_ipd       : std_ulogic := 'X';
      signal DI15_ipd       : std_ulogic := 'X';
      signal DI16_ipd       : std_ulogic := 'X';
      signal DI17_ipd       : std_ulogic := 'X';
      signal DI18_ipd       : std_ulogic := 'X';
      signal DI19_ipd       : std_ulogic := 'X';
      signal DI20_ipd       : std_ulogic := 'X';
      signal DI21_ipd       : std_ulogic := 'X';
      signal DI22_ipd       : std_ulogic := 'X';
      signal DI23_ipd       : std_ulogic := 'X';
      signal DI24_ipd       : std_ulogic := 'X';
      signal DI25_ipd       : std_ulogic := 'X';
      signal DI26_ipd       : std_ulogic := 'X';
      signal DI27_ipd       : std_ulogic := 'X';
      signal DI28_ipd       : std_ulogic := 'X';
      signal DI29_ipd       : std_ulogic := 'X';
      signal DI30_ipd       : std_ulogic := 'X';
      signal DI31_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(31 downto 0);
      signal DO             : std_logic_vector(3 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI31_ipd & DI30_ipd & DI29_ipd & DI28_ipd & DI27_ipd & DI26_ipd & DI25_ipd & DI24_ipd & DI23_ipd & DI22_ipd & DI21_ipd & DI20_ipd & DI19_ipd & DI18_ipd & DI17_ipd & DI16_ipd & DI15_ipd & DI14_ipd & DI13_ipd & DI12_ipd & DI11_ipd & DI10_ipd & DI9_ipd & DI8_ipd & DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);
        VitalWireDelay (DI8_ipd, DI8, tipd_DI8);
        VitalWireDelay (DI9_ipd, DI9, tipd_DI9);
        VitalWireDelay (DI10_ipd, DI10, tipd_DI10);
        VitalWireDelay (DI11_ipd, DI11, tipd_DI11);
        VitalWireDelay (DI12_ipd, DI12, tipd_DI12);
        VitalWireDelay (DI13_ipd, DI13, tipd_DI13);
        VitalWireDelay (DI14_ipd, DI14, tipd_DI14);
        VitalWireDelay (DI15_ipd, DI15, tipd_DI15);
        VitalWireDelay (DI16_ipd, DI16, tipd_DI16);
        VitalWireDelay (DI17_ipd, DI17, tipd_DI17);
        VitalWireDelay (DI18_ipd, DI18, tipd_DI18);
        VitalWireDelay (DI19_ipd, DI19, tipd_DI19);
        VitalWireDelay (DI20_ipd, DI20, tipd_DI20);
        VitalWireDelay (DI21_ipd, DI21, tipd_DI21);
        VitalWireDelay (DI22_ipd, DI22, tipd_DI22);
        VitalWireDelay (DI23_ipd, DI23, tipd_DI23);
        VitalWireDelay (DI24_ipd, DI24, tipd_DI24);
        VitalWireDelay (DI25_ipd, DI25, tipd_DI25);
        VitalWireDelay (DI26_ipd, DI26, tipd_DI26);
        VitalWireDelay (DI27_ipd, DI27, tipd_DI27);
        VitalWireDelay (DI28_ipd, DI28, tipd_DI28);
        VitalWireDelay (DI29_ipd, DI29, tipd_DI29);
        VitalWireDelay (DI30_ipd, DI30, tipd_DI30);
        VitalWireDelay (DI31_ipd, DI31, tipd_DI31);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI4_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI5_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI6_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI7_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI8_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI9_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI10_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI11_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI12_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI13_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI14_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI15_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI16_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI17_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI18_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI19_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI20_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI21_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI22_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI23_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI24_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI25_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI26_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI27_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI28_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI29_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI30_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI31_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI8_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI9_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI10_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI11_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI12_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI13_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI14_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI15_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI16_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI17_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI18_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI19_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI20_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI21_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI22_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI23_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI24_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI25_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI26_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI27_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI28_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI29_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI30_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI31_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_WCLK_posedge,
          TimingData              => Tmkr_DI4_WCLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI4_WCLK_noedge_posedge,
          HoldLow                 => thold_DI4_WCLK_noedge_posedge,
          HoldHigh                => thold_DI4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_WCLK_posedge,
          TimingData              => Tmkr_DI5_WCLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI5_WCLK_noedge_posedge,
          HoldLow                 => thold_DI5_WCLK_noedge_posedge,
          HoldHigh                => thold_DI5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_WCLK_posedge,
          TimingData              => Tmkr_DI6_WCLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI6_WCLK_noedge_posedge,
          HoldLow                 => thold_DI6_WCLK_noedge_posedge,
          HoldHigh                => thold_DI6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_WCLK_posedge,
          TimingData              => Tmkr_DI7_WCLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI7_WCLK_noedge_posedge,
          HoldLow                 => thold_DI7_WCLK_noedge_posedge,
          HoldHigh                => thold_DI7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI8_WCLK_posedge,
          TimingData              => Tmkr_DI8_WCLK_posedge,
          TestSignal              => DI8_ipd,
          TestSignalName          => "DI8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI8_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI8_WCLK_noedge_posedge,
          HoldLow                 => thold_DI8_WCLK_noedge_posedge,
          HoldHigh                => thold_DI8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI9_WCLK_posedge,
          TimingData              => Tmkr_DI9_WCLK_posedge,
          TestSignal              => DI9_ipd,
          TestSignalName          => "DI9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI9_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI9_WCLK_noedge_posedge,
          HoldLow                 => thold_DI9_WCLK_noedge_posedge,
          HoldHigh                => thold_DI9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI10_WCLK_posedge,
          TimingData              => Tmkr_DI10_WCLK_posedge,
          TestSignal              => DI10_ipd,
          TestSignalName          => "DI10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI10_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI10_WCLK_noedge_posedge,
          HoldLow                 => thold_DI10_WCLK_noedge_posedge,
          HoldHigh                => thold_DI10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI11_WCLK_posedge,
          TimingData              => Tmkr_DI11_WCLK_posedge,
          TestSignal              => DI11_ipd,
          TestSignalName          => "DI11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI11_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI11_WCLK_noedge_posedge,
          HoldLow                 => thold_DI11_WCLK_noedge_posedge,
          HoldHigh                => thold_DI11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI12_WCLK_posedge,
          TimingData              => Tmkr_DI12_WCLK_posedge,
          TestSignal              => DI12_ipd,
          TestSignalName          => "DI12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI12_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI12_WCLK_noedge_posedge,
          HoldLow                 => thold_DI12_WCLK_noedge_posedge,
          HoldHigh                => thold_DI12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI13_WCLK_posedge,
          TimingData              => Tmkr_DI13_WCLK_posedge,
          TestSignal              => DI13_ipd,
          TestSignalName          => "DI13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI13_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI13_WCLK_noedge_posedge,
          HoldLow                 => thold_DI13_WCLK_noedge_posedge,
          HoldHigh                => thold_DI13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI14_WCLK_posedge,
          TimingData              => Tmkr_DI14_WCLK_posedge,
          TestSignal              => DI14_ipd,
          TestSignalName          => "DI14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI14_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI14_WCLK_noedge_posedge,
          HoldLow                 => thold_DI14_WCLK_noedge_posedge,
          HoldHigh                => thold_DI14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI15_WCLK_posedge,
          TimingData              => Tmkr_DI15_WCLK_posedge,
          TestSignal              => DI15_ipd,
          TestSignalName          => "DI15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI15_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI15_WCLK_noedge_posedge,
          HoldLow                 => thold_DI15_WCLK_noedge_posedge,
          HoldHigh                => thold_DI15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI16_WCLK_posedge,
          TimingData              => Tmkr_DI16_WCLK_posedge,
          TestSignal              => DI16_ipd,
          TestSignalName          => "DI16",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI16_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI16_WCLK_noedge_posedge,
          HoldLow                 => thold_DI16_WCLK_noedge_posedge,
          HoldHigh                => thold_DI16_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI17_WCLK_posedge,
          TimingData              => Tmkr_DI17_WCLK_posedge,
          TestSignal              => DI17_ipd,
          TestSignalName          => "DI17",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI17_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI17_WCLK_noedge_posedge,
          HoldLow                 => thold_DI17_WCLK_noedge_posedge,
          HoldHigh                => thold_DI17_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI18_WCLK_posedge,
          TimingData              => Tmkr_DI18_WCLK_posedge,
          TestSignal              => DI18_ipd,
          TestSignalName          => "DI18",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI18_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI18_WCLK_noedge_posedge,
          HoldLow                 => thold_DI18_WCLK_noedge_posedge,
          HoldHigh                => thold_DI18_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI19_WCLK_posedge,
          TimingData              => Tmkr_DI19_WCLK_posedge,
          TestSignal              => DI19_ipd,
          TestSignalName          => "DI19",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI19_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI19_WCLK_noedge_posedge,
          HoldLow                 => thold_DI19_WCLK_noedge_posedge,
          HoldHigh                => thold_DI19_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI20_WCLK_posedge,
          TimingData              => Tmkr_DI20_WCLK_posedge,
          TestSignal              => DI20_ipd,
          TestSignalName          => "DI20",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI20_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI20_WCLK_noedge_posedge,
          HoldLow                 => thold_DI20_WCLK_noedge_posedge,
          HoldHigh                => thold_DI20_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI21_WCLK_posedge,
          TimingData              => Tmkr_DI21_WCLK_posedge,
          TestSignal              => DI21_ipd,
          TestSignalName          => "DI21",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI21_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI21_WCLK_noedge_posedge,
          HoldLow                 => thold_DI21_WCLK_noedge_posedge,
          HoldHigh                => thold_DI21_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI22_WCLK_posedge,
          TimingData              => Tmkr_DI22_WCLK_posedge,
          TestSignal              => DI22_ipd,
          TestSignalName          => "DI22",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI22_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI22_WCLK_noedge_posedge,
          HoldLow                 => thold_DI22_WCLK_noedge_posedge,
          HoldHigh                => thold_DI22_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI23_WCLK_posedge,
          TimingData              => Tmkr_DI23_WCLK_posedge,
          TestSignal              => DI23_ipd,
          TestSignalName          => "DI23",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI23_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI23_WCLK_noedge_posedge,
          HoldLow                 => thold_DI23_WCLK_noedge_posedge,
          HoldHigh                => thold_DI23_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI24_WCLK_posedge,
          TimingData              => Tmkr_DI24_WCLK_posedge,
          TestSignal              => DI24_ipd,
          TestSignalName          => "DI24",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI24_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI24_WCLK_noedge_posedge,
          HoldLow                 => thold_DI24_WCLK_noedge_posedge,
          HoldHigh                => thold_DI24_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI25_WCLK_posedge,
          TimingData              => Tmkr_DI25_WCLK_posedge,
          TestSignal              => DI25_ipd,
          TestSignalName          => "DI25",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI25_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI25_WCLK_noedge_posedge,
          HoldLow                 => thold_DI25_WCLK_noedge_posedge,
          HoldHigh                => thold_DI25_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI26_WCLK_posedge,
          TimingData              => Tmkr_DI26_WCLK_posedge,
          TestSignal              => DI26_ipd,
          TestSignalName          => "DI26",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI26_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI26_WCLK_noedge_posedge,
          HoldLow                 => thold_DI26_WCLK_noedge_posedge,
          HoldHigh                => thold_DI26_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI27_WCLK_posedge,
          TimingData              => Tmkr_DI27_WCLK_posedge,
          TestSignal              => DI27_ipd,
          TestSignalName          => "DI27",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI27_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI27_WCLK_noedge_posedge,
          HoldLow                 => thold_DI27_WCLK_noedge_posedge,
          HoldHigh                => thold_DI27_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI28_WCLK_posedge,
          TimingData              => Tmkr_DI28_WCLK_posedge,
          TestSignal              => DI28_ipd,
          TestSignalName          => "DI28",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI28_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI28_WCLK_noedge_posedge,
          HoldLow                 => thold_DI28_WCLK_noedge_posedge,
          HoldHigh                => thold_DI28_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI29_WCLK_posedge,
          TimingData              => Tmkr_DI29_WCLK_posedge,
          TestSignal              => DI29_ipd,
          TestSignalName          => "DI29",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI29_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI29_WCLK_noedge_posedge,
          HoldLow                 => thold_DI29_WCLK_noedge_posedge,
          HoldHigh                => thold_DI29_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI30_WCLK_posedge,
          TimingData              => Tmkr_DI30_WCLK_posedge,
          TestSignal              => DI30_ipd,
          TestSignalName          => "DI30",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI30_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI30_WCLK_noedge_posedge,
          HoldLow                 => thold_DI30_WCLK_noedge_posedge,
          HoldHigh                => thold_DI30_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI31_WCLK_posedge,
          TimingData              => Tmkr_DI31_WCLK_posedge,
          TestSignal              => DI31_ipd,
          TestSignalName          => "DI31",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI31_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI31_WCLK_noedge_posedge,
          HoldLow                 => thold_DI31_WCLK_noedge_posedge,
          HoldHigh                => thold_DI31_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Tviol_DI4_WCLK_posedge or 
                 Tviol_DI5_WCLK_posedge or 
                 Tviol_DI6_WCLK_posedge or 
                 Tviol_DI7_WCLK_posedge or 
                 Tviol_DI8_WCLK_posedge or 
                 Tviol_DI9_WCLK_posedge or 
                 Tviol_DI10_WCLK_posedge or 
                 Tviol_DI11_WCLK_posedge or 
                 Tviol_DI12_WCLK_posedge or 
                 Tviol_DI13_WCLK_posedge or 
                 Tviol_DI14_WCLK_posedge or 
                 Tviol_DI15_WCLK_posedge or 
                 Tviol_DI16_WCLK_posedge or 
                 Tviol_DI17_WCLK_posedge or 
                 Tviol_DI18_WCLK_posedge or 
                 Tviol_DI19_WCLK_posedge or 
                 Tviol_DI20_WCLK_posedge or 
                 Tviol_DI21_WCLK_posedge or 
                 Tviol_DI22_WCLK_posedge or 
                 Tviol_DI23_WCLK_posedge or 
                 Tviol_DI24_WCLK_posedge or 
                 Tviol_DI25_WCLK_posedge or 
                 Tviol_DI26_WCLK_posedge or 
                 Tviol_DI27_WCLK_posedge or 
                 Tviol_DI28_WCLK_posedge or 
                 Tviol_DI29_WCLK_posedge or 
                 Tviol_DI30_WCLK_posedge or 
                 Tviol_DI31_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 9,
        WDATA_WIDTH    => 32,
        RADDR_WIDTH    => 12,
        RDATA_WIDTH    => 4,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX32_RX4_VITAL of RAMBFIFO16KA_WX32_RX4 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX32_RX4_VITAL;

----- CELL RAMBFIFO16KA_WX32_RX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX32_RX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 512;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI4_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI5_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI6_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI7_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI8_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI8_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI9_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI9_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI10_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI10_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI11_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI11_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI12_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI12_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI13_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI13_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI14_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI14_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI15_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI15_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI16_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI16_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI17_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI17_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI18_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI18_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI19_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI19_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI20_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI20_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI21_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI21_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI22_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI22_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI23_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI23_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI24_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI24_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI25_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI25_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI26_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI26_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI27_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI27_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI28_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI28_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI29_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI29_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI30_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI30_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI31_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI31_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI8                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI9                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI10                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI11                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI12                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI13                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI14                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI15                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI16                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI17                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI18                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI19                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI20                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI21                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI22                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI23                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI24                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI25                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI26                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI27                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI28                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI29                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI30                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI31                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DI4                             : in    STD_ULOGIC;
      DI5                             : in    STD_ULOGIC;
      DI6                             : in    STD_ULOGIC;
      DI7                             : in    STD_ULOGIC;
      DI8                             : in    STD_ULOGIC;
      DI9                             : in    STD_ULOGIC;
      DI10                             : in    STD_ULOGIC;
      DI11                             : in    STD_ULOGIC;
      DI12                             : in    STD_ULOGIC;
      DI13                             : in    STD_ULOGIC;
      DI14                             : in    STD_ULOGIC;
      DI15                             : in    STD_ULOGIC;
      DI16                             : in    STD_ULOGIC;
      DI17                             : in    STD_ULOGIC;
      DI18                             : in    STD_ULOGIC;
      DI19                             : in    STD_ULOGIC;
      DI20                             : in    STD_ULOGIC;
      DI21                             : in    STD_ULOGIC;
      DI22                             : in    STD_ULOGIC;
      DI23                             : in    STD_ULOGIC;
      DI24                             : in    STD_ULOGIC;
      DI25                             : in    STD_ULOGIC;
      DI26                             : in    STD_ULOGIC;
      DI27                             : in    STD_ULOGIC;
      DI28                             : in    STD_ULOGIC;
      DI29                             : in    STD_ULOGIC;
      DI30                             : in    STD_ULOGIC;
      DI31                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX32_RX2 : entity is FALSE;
end RAMBFIFO16KA_WX32_RX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX32_RX2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI4_ipd       : std_ulogic := 'X';
      signal DI5_ipd       : std_ulogic := 'X';
      signal DI6_ipd       : std_ulogic := 'X';
      signal DI7_ipd       : std_ulogic := 'X';
      signal DI8_ipd       : std_ulogic := 'X';
      signal DI9_ipd       : std_ulogic := 'X';
      signal DI10_ipd       : std_ulogic := 'X';
      signal DI11_ipd       : std_ulogic := 'X';
      signal DI12_ipd       : std_ulogic := 'X';
      signal DI13_ipd       : std_ulogic := 'X';
      signal DI14_ipd       : std_ulogic := 'X';
      signal DI15_ipd       : std_ulogic := 'X';
      signal DI16_ipd       : std_ulogic := 'X';
      signal DI17_ipd       : std_ulogic := 'X';
      signal DI18_ipd       : std_ulogic := 'X';
      signal DI19_ipd       : std_ulogic := 'X';
      signal DI20_ipd       : std_ulogic := 'X';
      signal DI21_ipd       : std_ulogic := 'X';
      signal DI22_ipd       : std_ulogic := 'X';
      signal DI23_ipd       : std_ulogic := 'X';
      signal DI24_ipd       : std_ulogic := 'X';
      signal DI25_ipd       : std_ulogic := 'X';
      signal DI26_ipd       : std_ulogic := 'X';
      signal DI27_ipd       : std_ulogic := 'X';
      signal DI28_ipd       : std_ulogic := 'X';
      signal DI29_ipd       : std_ulogic := 'X';
      signal DI30_ipd       : std_ulogic := 'X';
      signal DI31_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(31 downto 0);
      signal DO             : std_logic_vector(1 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI31_ipd & DI30_ipd & DI29_ipd & DI28_ipd & DI27_ipd & DI26_ipd & DI25_ipd & DI24_ipd & DI23_ipd & DI22_ipd & DI21_ipd & DI20_ipd & DI19_ipd & DI18_ipd & DI17_ipd & DI16_ipd & DI15_ipd & DI14_ipd & DI13_ipd & DI12_ipd & DI11_ipd & DI10_ipd & DI9_ipd & DI8_ipd & DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);
        VitalWireDelay (DI8_ipd, DI8, tipd_DI8);
        VitalWireDelay (DI9_ipd, DI9, tipd_DI9);
        VitalWireDelay (DI10_ipd, DI10, tipd_DI10);
        VitalWireDelay (DI11_ipd, DI11, tipd_DI11);
        VitalWireDelay (DI12_ipd, DI12, tipd_DI12);
        VitalWireDelay (DI13_ipd, DI13, tipd_DI13);
        VitalWireDelay (DI14_ipd, DI14, tipd_DI14);
        VitalWireDelay (DI15_ipd, DI15, tipd_DI15);
        VitalWireDelay (DI16_ipd, DI16, tipd_DI16);
        VitalWireDelay (DI17_ipd, DI17, tipd_DI17);
        VitalWireDelay (DI18_ipd, DI18, tipd_DI18);
        VitalWireDelay (DI19_ipd, DI19, tipd_DI19);
        VitalWireDelay (DI20_ipd, DI20, tipd_DI20);
        VitalWireDelay (DI21_ipd, DI21, tipd_DI21);
        VitalWireDelay (DI22_ipd, DI22, tipd_DI22);
        VitalWireDelay (DI23_ipd, DI23, tipd_DI23);
        VitalWireDelay (DI24_ipd, DI24, tipd_DI24);
        VitalWireDelay (DI25_ipd, DI25, tipd_DI25);
        VitalWireDelay (DI26_ipd, DI26, tipd_DI26);
        VitalWireDelay (DI27_ipd, DI27, tipd_DI27);
        VitalWireDelay (DI28_ipd, DI28, tipd_DI28);
        VitalWireDelay (DI29_ipd, DI29, tipd_DI29);
        VitalWireDelay (DI30_ipd, DI30, tipd_DI30);
        VitalWireDelay (DI31_ipd, DI31, tipd_DI31);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI4_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI5_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI6_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI7_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI8_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI9_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI10_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI11_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI12_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI13_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI14_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI15_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI16_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI17_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI18_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI19_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI20_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI21_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI22_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI23_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI24_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI25_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI26_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI27_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI28_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI29_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI30_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI31_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI8_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI9_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI10_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI11_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI12_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI13_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI14_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI15_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI16_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI17_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI18_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI19_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI20_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI21_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI22_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI23_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI24_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI25_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI26_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI27_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI28_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI29_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI30_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI31_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_WCLK_posedge,
          TimingData              => Tmkr_DI4_WCLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI4_WCLK_noedge_posedge,
          HoldLow                 => thold_DI4_WCLK_noedge_posedge,
          HoldHigh                => thold_DI4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_WCLK_posedge,
          TimingData              => Tmkr_DI5_WCLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI5_WCLK_noedge_posedge,
          HoldLow                 => thold_DI5_WCLK_noedge_posedge,
          HoldHigh                => thold_DI5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_WCLK_posedge,
          TimingData              => Tmkr_DI6_WCLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI6_WCLK_noedge_posedge,
          HoldLow                 => thold_DI6_WCLK_noedge_posedge,
          HoldHigh                => thold_DI6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_WCLK_posedge,
          TimingData              => Tmkr_DI7_WCLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI7_WCLK_noedge_posedge,
          HoldLow                 => thold_DI7_WCLK_noedge_posedge,
          HoldHigh                => thold_DI7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI8_WCLK_posedge,
          TimingData              => Tmkr_DI8_WCLK_posedge,
          TestSignal              => DI8_ipd,
          TestSignalName          => "DI8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI8_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI8_WCLK_noedge_posedge,
          HoldLow                 => thold_DI8_WCLK_noedge_posedge,
          HoldHigh                => thold_DI8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI9_WCLK_posedge,
          TimingData              => Tmkr_DI9_WCLK_posedge,
          TestSignal              => DI9_ipd,
          TestSignalName          => "DI9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI9_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI9_WCLK_noedge_posedge,
          HoldLow                 => thold_DI9_WCLK_noedge_posedge,
          HoldHigh                => thold_DI9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI10_WCLK_posedge,
          TimingData              => Tmkr_DI10_WCLK_posedge,
          TestSignal              => DI10_ipd,
          TestSignalName          => "DI10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI10_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI10_WCLK_noedge_posedge,
          HoldLow                 => thold_DI10_WCLK_noedge_posedge,
          HoldHigh                => thold_DI10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI11_WCLK_posedge,
          TimingData              => Tmkr_DI11_WCLK_posedge,
          TestSignal              => DI11_ipd,
          TestSignalName          => "DI11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI11_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI11_WCLK_noedge_posedge,
          HoldLow                 => thold_DI11_WCLK_noedge_posedge,
          HoldHigh                => thold_DI11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI12_WCLK_posedge,
          TimingData              => Tmkr_DI12_WCLK_posedge,
          TestSignal              => DI12_ipd,
          TestSignalName          => "DI12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI12_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI12_WCLK_noedge_posedge,
          HoldLow                 => thold_DI12_WCLK_noedge_posedge,
          HoldHigh                => thold_DI12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI13_WCLK_posedge,
          TimingData              => Tmkr_DI13_WCLK_posedge,
          TestSignal              => DI13_ipd,
          TestSignalName          => "DI13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI13_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI13_WCLK_noedge_posedge,
          HoldLow                 => thold_DI13_WCLK_noedge_posedge,
          HoldHigh                => thold_DI13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI14_WCLK_posedge,
          TimingData              => Tmkr_DI14_WCLK_posedge,
          TestSignal              => DI14_ipd,
          TestSignalName          => "DI14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI14_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI14_WCLK_noedge_posedge,
          HoldLow                 => thold_DI14_WCLK_noedge_posedge,
          HoldHigh                => thold_DI14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI15_WCLK_posedge,
          TimingData              => Tmkr_DI15_WCLK_posedge,
          TestSignal              => DI15_ipd,
          TestSignalName          => "DI15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI15_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI15_WCLK_noedge_posedge,
          HoldLow                 => thold_DI15_WCLK_noedge_posedge,
          HoldHigh                => thold_DI15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI16_WCLK_posedge,
          TimingData              => Tmkr_DI16_WCLK_posedge,
          TestSignal              => DI16_ipd,
          TestSignalName          => "DI16",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI16_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI16_WCLK_noedge_posedge,
          HoldLow                 => thold_DI16_WCLK_noedge_posedge,
          HoldHigh                => thold_DI16_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI17_WCLK_posedge,
          TimingData              => Tmkr_DI17_WCLK_posedge,
          TestSignal              => DI17_ipd,
          TestSignalName          => "DI17",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI17_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI17_WCLK_noedge_posedge,
          HoldLow                 => thold_DI17_WCLK_noedge_posedge,
          HoldHigh                => thold_DI17_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI18_WCLK_posedge,
          TimingData              => Tmkr_DI18_WCLK_posedge,
          TestSignal              => DI18_ipd,
          TestSignalName          => "DI18",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI18_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI18_WCLK_noedge_posedge,
          HoldLow                 => thold_DI18_WCLK_noedge_posedge,
          HoldHigh                => thold_DI18_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI19_WCLK_posedge,
          TimingData              => Tmkr_DI19_WCLK_posedge,
          TestSignal              => DI19_ipd,
          TestSignalName          => "DI19",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI19_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI19_WCLK_noedge_posedge,
          HoldLow                 => thold_DI19_WCLK_noedge_posedge,
          HoldHigh                => thold_DI19_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI20_WCLK_posedge,
          TimingData              => Tmkr_DI20_WCLK_posedge,
          TestSignal              => DI20_ipd,
          TestSignalName          => "DI20",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI20_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI20_WCLK_noedge_posedge,
          HoldLow                 => thold_DI20_WCLK_noedge_posedge,
          HoldHigh                => thold_DI20_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI21_WCLK_posedge,
          TimingData              => Tmkr_DI21_WCLK_posedge,
          TestSignal              => DI21_ipd,
          TestSignalName          => "DI21",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI21_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI21_WCLK_noedge_posedge,
          HoldLow                 => thold_DI21_WCLK_noedge_posedge,
          HoldHigh                => thold_DI21_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI22_WCLK_posedge,
          TimingData              => Tmkr_DI22_WCLK_posedge,
          TestSignal              => DI22_ipd,
          TestSignalName          => "DI22",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI22_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI22_WCLK_noedge_posedge,
          HoldLow                 => thold_DI22_WCLK_noedge_posedge,
          HoldHigh                => thold_DI22_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI23_WCLK_posedge,
          TimingData              => Tmkr_DI23_WCLK_posedge,
          TestSignal              => DI23_ipd,
          TestSignalName          => "DI23",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI23_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI23_WCLK_noedge_posedge,
          HoldLow                 => thold_DI23_WCLK_noedge_posedge,
          HoldHigh                => thold_DI23_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI24_WCLK_posedge,
          TimingData              => Tmkr_DI24_WCLK_posedge,
          TestSignal              => DI24_ipd,
          TestSignalName          => "DI24",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI24_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI24_WCLK_noedge_posedge,
          HoldLow                 => thold_DI24_WCLK_noedge_posedge,
          HoldHigh                => thold_DI24_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI25_WCLK_posedge,
          TimingData              => Tmkr_DI25_WCLK_posedge,
          TestSignal              => DI25_ipd,
          TestSignalName          => "DI25",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI25_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI25_WCLK_noedge_posedge,
          HoldLow                 => thold_DI25_WCLK_noedge_posedge,
          HoldHigh                => thold_DI25_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI26_WCLK_posedge,
          TimingData              => Tmkr_DI26_WCLK_posedge,
          TestSignal              => DI26_ipd,
          TestSignalName          => "DI26",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI26_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI26_WCLK_noedge_posedge,
          HoldLow                 => thold_DI26_WCLK_noedge_posedge,
          HoldHigh                => thold_DI26_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI27_WCLK_posedge,
          TimingData              => Tmkr_DI27_WCLK_posedge,
          TestSignal              => DI27_ipd,
          TestSignalName          => "DI27",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI27_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI27_WCLK_noedge_posedge,
          HoldLow                 => thold_DI27_WCLK_noedge_posedge,
          HoldHigh                => thold_DI27_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI28_WCLK_posedge,
          TimingData              => Tmkr_DI28_WCLK_posedge,
          TestSignal              => DI28_ipd,
          TestSignalName          => "DI28",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI28_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI28_WCLK_noedge_posedge,
          HoldLow                 => thold_DI28_WCLK_noedge_posedge,
          HoldHigh                => thold_DI28_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI29_WCLK_posedge,
          TimingData              => Tmkr_DI29_WCLK_posedge,
          TestSignal              => DI29_ipd,
          TestSignalName          => "DI29",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI29_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI29_WCLK_noedge_posedge,
          HoldLow                 => thold_DI29_WCLK_noedge_posedge,
          HoldHigh                => thold_DI29_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI30_WCLK_posedge,
          TimingData              => Tmkr_DI30_WCLK_posedge,
          TestSignal              => DI30_ipd,
          TestSignalName          => "DI30",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI30_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI30_WCLK_noedge_posedge,
          HoldLow                 => thold_DI30_WCLK_noedge_posedge,
          HoldHigh                => thold_DI30_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI31_WCLK_posedge,
          TimingData              => Tmkr_DI31_WCLK_posedge,
          TestSignal              => DI31_ipd,
          TestSignalName          => "DI31",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI31_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI31_WCLK_noedge_posedge,
          HoldLow                 => thold_DI31_WCLK_noedge_posedge,
          HoldHigh                => thold_DI31_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Tviol_DI4_WCLK_posedge or 
                 Tviol_DI5_WCLK_posedge or 
                 Tviol_DI6_WCLK_posedge or 
                 Tviol_DI7_WCLK_posedge or 
                 Tviol_DI8_WCLK_posedge or 
                 Tviol_DI9_WCLK_posedge or 
                 Tviol_DI10_WCLK_posedge or 
                 Tviol_DI11_WCLK_posedge or 
                 Tviol_DI12_WCLK_posedge or 
                 Tviol_DI13_WCLK_posedge or 
                 Tviol_DI14_WCLK_posedge or 
                 Tviol_DI15_WCLK_posedge or 
                 Tviol_DI16_WCLK_posedge or 
                 Tviol_DI17_WCLK_posedge or 
                 Tviol_DI18_WCLK_posedge or 
                 Tviol_DI19_WCLK_posedge or 
                 Tviol_DI20_WCLK_posedge or 
                 Tviol_DI21_WCLK_posedge or 
                 Tviol_DI22_WCLK_posedge or 
                 Tviol_DI23_WCLK_posedge or 
                 Tviol_DI24_WCLK_posedge or 
                 Tviol_DI25_WCLK_posedge or 
                 Tviol_DI26_WCLK_posedge or 
                 Tviol_DI27_WCLK_posedge or 
                 Tviol_DI28_WCLK_posedge or 
                 Tviol_DI29_WCLK_posedge or 
                 Tviol_DI30_WCLK_posedge or 
                 Tviol_DI31_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 9,
        WDATA_WIDTH    => 32,
        RADDR_WIDTH    => 13,
        RDATA_WIDTH    => 2,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX32_RX2_VITAL of RAMBFIFO16KA_WX32_RX2 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX32_RX2_VITAL;

----- CELL RAMBFIFO16KA_WX32_RX1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX32_RX1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 512;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI4_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI5_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI6_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI7_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI8_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI8_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI9_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI9_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI10_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI10_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI11_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI11_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI12_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI12_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI13_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI13_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI14_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI14_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI15_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI15_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI16_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI16_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI17_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI17_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI18_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI18_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI19_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI19_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI20_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI20_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI21_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI21_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI22_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI22_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI23_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI23_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI24_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI24_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI25_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI25_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI26_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI26_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI27_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI27_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI28_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI28_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI29_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI29_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI30_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI30_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI31_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI31_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI8                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI9                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI10                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI11                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI12                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI13                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI14                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI15                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI16                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI17                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI18                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI19                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI20                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI21                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI22                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI23                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI24                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI25                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI26                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI27                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI28                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI29                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI30                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI31                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DI4                             : in    STD_ULOGIC;
      DI5                             : in    STD_ULOGIC;
      DI6                             : in    STD_ULOGIC;
      DI7                             : in    STD_ULOGIC;
      DI8                             : in    STD_ULOGIC;
      DI9                             : in    STD_ULOGIC;
      DI10                             : in    STD_ULOGIC;
      DI11                             : in    STD_ULOGIC;
      DI12                             : in    STD_ULOGIC;
      DI13                             : in    STD_ULOGIC;
      DI14                             : in    STD_ULOGIC;
      DI15                             : in    STD_ULOGIC;
      DI16                             : in    STD_ULOGIC;
      DI17                             : in    STD_ULOGIC;
      DI18                             : in    STD_ULOGIC;
      DI19                             : in    STD_ULOGIC;
      DI20                             : in    STD_ULOGIC;
      DI21                             : in    STD_ULOGIC;
      DI22                             : in    STD_ULOGIC;
      DI23                             : in    STD_ULOGIC;
      DI24                             : in    STD_ULOGIC;
      DI25                             : in    STD_ULOGIC;
      DI26                             : in    STD_ULOGIC;
      DI27                             : in    STD_ULOGIC;
      DI28                             : in    STD_ULOGIC;
      DI29                             : in    STD_ULOGIC;
      DI30                             : in    STD_ULOGIC;
      DI31                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX32_RX1 : entity is FALSE;
end RAMBFIFO16KA_WX32_RX1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX32_RX1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI4_ipd       : std_ulogic := 'X';
      signal DI5_ipd       : std_ulogic := 'X';
      signal DI6_ipd       : std_ulogic := 'X';
      signal DI7_ipd       : std_ulogic := 'X';
      signal DI8_ipd       : std_ulogic := 'X';
      signal DI9_ipd       : std_ulogic := 'X';
      signal DI10_ipd       : std_ulogic := 'X';
      signal DI11_ipd       : std_ulogic := 'X';
      signal DI12_ipd       : std_ulogic := 'X';
      signal DI13_ipd       : std_ulogic := 'X';
      signal DI14_ipd       : std_ulogic := 'X';
      signal DI15_ipd       : std_ulogic := 'X';
      signal DI16_ipd       : std_ulogic := 'X';
      signal DI17_ipd       : std_ulogic := 'X';
      signal DI18_ipd       : std_ulogic := 'X';
      signal DI19_ipd       : std_ulogic := 'X';
      signal DI20_ipd       : std_ulogic := 'X';
      signal DI21_ipd       : std_ulogic := 'X';
      signal DI22_ipd       : std_ulogic := 'X';
      signal DI23_ipd       : std_ulogic := 'X';
      signal DI24_ipd       : std_ulogic := 'X';
      signal DI25_ipd       : std_ulogic := 'X';
      signal DI26_ipd       : std_ulogic := 'X';
      signal DI27_ipd       : std_ulogic := 'X';
      signal DI28_ipd       : std_ulogic := 'X';
      signal DI29_ipd       : std_ulogic := 'X';
      signal DI30_ipd       : std_ulogic := 'X';
      signal DI31_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(31 downto 0);
      signal DO             : std_logic_vector(0 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI31_ipd & DI30_ipd & DI29_ipd & DI28_ipd & DI27_ipd & DI26_ipd & DI25_ipd & DI24_ipd & DI23_ipd & DI22_ipd & DI21_ipd & DI20_ipd & DI19_ipd & DI18_ipd & DI17_ipd & DI16_ipd & DI15_ipd & DI14_ipd & DI13_ipd & DI12_ipd & DI11_ipd & DI10_ipd & DI9_ipd & DI8_ipd & DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);
        VitalWireDelay (DI8_ipd, DI8, tipd_DI8);
        VitalWireDelay (DI9_ipd, DI9, tipd_DI9);
        VitalWireDelay (DI10_ipd, DI10, tipd_DI10);
        VitalWireDelay (DI11_ipd, DI11, tipd_DI11);
        VitalWireDelay (DI12_ipd, DI12, tipd_DI12);
        VitalWireDelay (DI13_ipd, DI13, tipd_DI13);
        VitalWireDelay (DI14_ipd, DI14, tipd_DI14);
        VitalWireDelay (DI15_ipd, DI15, tipd_DI15);
        VitalWireDelay (DI16_ipd, DI16, tipd_DI16);
        VitalWireDelay (DI17_ipd, DI17, tipd_DI17);
        VitalWireDelay (DI18_ipd, DI18, tipd_DI18);
        VitalWireDelay (DI19_ipd, DI19, tipd_DI19);
        VitalWireDelay (DI20_ipd, DI20, tipd_DI20);
        VitalWireDelay (DI21_ipd, DI21, tipd_DI21);
        VitalWireDelay (DI22_ipd, DI22, tipd_DI22);
        VitalWireDelay (DI23_ipd, DI23, tipd_DI23);
        VitalWireDelay (DI24_ipd, DI24, tipd_DI24);
        VitalWireDelay (DI25_ipd, DI25, tipd_DI25);
        VitalWireDelay (DI26_ipd, DI26, tipd_DI26);
        VitalWireDelay (DI27_ipd, DI27, tipd_DI27);
        VitalWireDelay (DI28_ipd, DI28, tipd_DI28);
        VitalWireDelay (DI29_ipd, DI29, tipd_DI29);
        VitalWireDelay (DI30_ipd, DI30, tipd_DI30);
        VitalWireDelay (DI31_ipd, DI31, tipd_DI31);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI4_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI5_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI6_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI7_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI8_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI9_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI10_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI11_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI12_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI13_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI14_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI15_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI16_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI17_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI18_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI19_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI20_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI21_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI22_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI23_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI24_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI25_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI26_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI27_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI28_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI29_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI30_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI31_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI8_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI9_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI10_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI11_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI12_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI13_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI14_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI15_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI16_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI17_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI18_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI19_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI20_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI21_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI22_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI23_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI24_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI25_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI26_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI27_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI28_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI29_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI30_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI31_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_WCLK_posedge,
          TimingData              => Tmkr_DI4_WCLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI4_WCLK_noedge_posedge,
          HoldLow                 => thold_DI4_WCLK_noedge_posedge,
          HoldHigh                => thold_DI4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_WCLK_posedge,
          TimingData              => Tmkr_DI5_WCLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI5_WCLK_noedge_posedge,
          HoldLow                 => thold_DI5_WCLK_noedge_posedge,
          HoldHigh                => thold_DI5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_WCLK_posedge,
          TimingData              => Tmkr_DI6_WCLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI6_WCLK_noedge_posedge,
          HoldLow                 => thold_DI6_WCLK_noedge_posedge,
          HoldHigh                => thold_DI6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_WCLK_posedge,
          TimingData              => Tmkr_DI7_WCLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI7_WCLK_noedge_posedge,
          HoldLow                 => thold_DI7_WCLK_noedge_posedge,
          HoldHigh                => thold_DI7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI8_WCLK_posedge,
          TimingData              => Tmkr_DI8_WCLK_posedge,
          TestSignal              => DI8_ipd,
          TestSignalName          => "DI8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI8_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI8_WCLK_noedge_posedge,
          HoldLow                 => thold_DI8_WCLK_noedge_posedge,
          HoldHigh                => thold_DI8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI9_WCLK_posedge,
          TimingData              => Tmkr_DI9_WCLK_posedge,
          TestSignal              => DI9_ipd,
          TestSignalName          => "DI9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI9_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI9_WCLK_noedge_posedge,
          HoldLow                 => thold_DI9_WCLK_noedge_posedge,
          HoldHigh                => thold_DI9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI10_WCLK_posedge,
          TimingData              => Tmkr_DI10_WCLK_posedge,
          TestSignal              => DI10_ipd,
          TestSignalName          => "DI10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI10_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI10_WCLK_noedge_posedge,
          HoldLow                 => thold_DI10_WCLK_noedge_posedge,
          HoldHigh                => thold_DI10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI11_WCLK_posedge,
          TimingData              => Tmkr_DI11_WCLK_posedge,
          TestSignal              => DI11_ipd,
          TestSignalName          => "DI11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI11_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI11_WCLK_noedge_posedge,
          HoldLow                 => thold_DI11_WCLK_noedge_posedge,
          HoldHigh                => thold_DI11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI12_WCLK_posedge,
          TimingData              => Tmkr_DI12_WCLK_posedge,
          TestSignal              => DI12_ipd,
          TestSignalName          => "DI12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI12_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI12_WCLK_noedge_posedge,
          HoldLow                 => thold_DI12_WCLK_noedge_posedge,
          HoldHigh                => thold_DI12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI13_WCLK_posedge,
          TimingData              => Tmkr_DI13_WCLK_posedge,
          TestSignal              => DI13_ipd,
          TestSignalName          => "DI13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI13_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI13_WCLK_noedge_posedge,
          HoldLow                 => thold_DI13_WCLK_noedge_posedge,
          HoldHigh                => thold_DI13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI14_WCLK_posedge,
          TimingData              => Tmkr_DI14_WCLK_posedge,
          TestSignal              => DI14_ipd,
          TestSignalName          => "DI14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI14_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI14_WCLK_noedge_posedge,
          HoldLow                 => thold_DI14_WCLK_noedge_posedge,
          HoldHigh                => thold_DI14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI15_WCLK_posedge,
          TimingData              => Tmkr_DI15_WCLK_posedge,
          TestSignal              => DI15_ipd,
          TestSignalName          => "DI15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI15_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI15_WCLK_noedge_posedge,
          HoldLow                 => thold_DI15_WCLK_noedge_posedge,
          HoldHigh                => thold_DI15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI16_WCLK_posedge,
          TimingData              => Tmkr_DI16_WCLK_posedge,
          TestSignal              => DI16_ipd,
          TestSignalName          => "DI16",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI16_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI16_WCLK_noedge_posedge,
          HoldLow                 => thold_DI16_WCLK_noedge_posedge,
          HoldHigh                => thold_DI16_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI17_WCLK_posedge,
          TimingData              => Tmkr_DI17_WCLK_posedge,
          TestSignal              => DI17_ipd,
          TestSignalName          => "DI17",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI17_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI17_WCLK_noedge_posedge,
          HoldLow                 => thold_DI17_WCLK_noedge_posedge,
          HoldHigh                => thold_DI17_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI18_WCLK_posedge,
          TimingData              => Tmkr_DI18_WCLK_posedge,
          TestSignal              => DI18_ipd,
          TestSignalName          => "DI18",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI18_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI18_WCLK_noedge_posedge,
          HoldLow                 => thold_DI18_WCLK_noedge_posedge,
          HoldHigh                => thold_DI18_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI19_WCLK_posedge,
          TimingData              => Tmkr_DI19_WCLK_posedge,
          TestSignal              => DI19_ipd,
          TestSignalName          => "DI19",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI19_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI19_WCLK_noedge_posedge,
          HoldLow                 => thold_DI19_WCLK_noedge_posedge,
          HoldHigh                => thold_DI19_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI20_WCLK_posedge,
          TimingData              => Tmkr_DI20_WCLK_posedge,
          TestSignal              => DI20_ipd,
          TestSignalName          => "DI20",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI20_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI20_WCLK_noedge_posedge,
          HoldLow                 => thold_DI20_WCLK_noedge_posedge,
          HoldHigh                => thold_DI20_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI21_WCLK_posedge,
          TimingData              => Tmkr_DI21_WCLK_posedge,
          TestSignal              => DI21_ipd,
          TestSignalName          => "DI21",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI21_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI21_WCLK_noedge_posedge,
          HoldLow                 => thold_DI21_WCLK_noedge_posedge,
          HoldHigh                => thold_DI21_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI22_WCLK_posedge,
          TimingData              => Tmkr_DI22_WCLK_posedge,
          TestSignal              => DI22_ipd,
          TestSignalName          => "DI22",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI22_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI22_WCLK_noedge_posedge,
          HoldLow                 => thold_DI22_WCLK_noedge_posedge,
          HoldHigh                => thold_DI22_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI23_WCLK_posedge,
          TimingData              => Tmkr_DI23_WCLK_posedge,
          TestSignal              => DI23_ipd,
          TestSignalName          => "DI23",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI23_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI23_WCLK_noedge_posedge,
          HoldLow                 => thold_DI23_WCLK_noedge_posedge,
          HoldHigh                => thold_DI23_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI24_WCLK_posedge,
          TimingData              => Tmkr_DI24_WCLK_posedge,
          TestSignal              => DI24_ipd,
          TestSignalName          => "DI24",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI24_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI24_WCLK_noedge_posedge,
          HoldLow                 => thold_DI24_WCLK_noedge_posedge,
          HoldHigh                => thold_DI24_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI25_WCLK_posedge,
          TimingData              => Tmkr_DI25_WCLK_posedge,
          TestSignal              => DI25_ipd,
          TestSignalName          => "DI25",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI25_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI25_WCLK_noedge_posedge,
          HoldLow                 => thold_DI25_WCLK_noedge_posedge,
          HoldHigh                => thold_DI25_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI26_WCLK_posedge,
          TimingData              => Tmkr_DI26_WCLK_posedge,
          TestSignal              => DI26_ipd,
          TestSignalName          => "DI26",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI26_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI26_WCLK_noedge_posedge,
          HoldLow                 => thold_DI26_WCLK_noedge_posedge,
          HoldHigh                => thold_DI26_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI27_WCLK_posedge,
          TimingData              => Tmkr_DI27_WCLK_posedge,
          TestSignal              => DI27_ipd,
          TestSignalName          => "DI27",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI27_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI27_WCLK_noedge_posedge,
          HoldLow                 => thold_DI27_WCLK_noedge_posedge,
          HoldHigh                => thold_DI27_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI28_WCLK_posedge,
          TimingData              => Tmkr_DI28_WCLK_posedge,
          TestSignal              => DI28_ipd,
          TestSignalName          => "DI28",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI28_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI28_WCLK_noedge_posedge,
          HoldLow                 => thold_DI28_WCLK_noedge_posedge,
          HoldHigh                => thold_DI28_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI29_WCLK_posedge,
          TimingData              => Tmkr_DI29_WCLK_posedge,
          TestSignal              => DI29_ipd,
          TestSignalName          => "DI29",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI29_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI29_WCLK_noedge_posedge,
          HoldLow                 => thold_DI29_WCLK_noedge_posedge,
          HoldHigh                => thold_DI29_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI30_WCLK_posedge,
          TimingData              => Tmkr_DI30_WCLK_posedge,
          TestSignal              => DI30_ipd,
          TestSignalName          => "DI30",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI30_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI30_WCLK_noedge_posedge,
          HoldLow                 => thold_DI30_WCLK_noedge_posedge,
          HoldHigh                => thold_DI30_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI31_WCLK_posedge,
          TimingData              => Tmkr_DI31_WCLK_posedge,
          TestSignal              => DI31_ipd,
          TestSignalName          => "DI31",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI31_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI31_WCLK_noedge_posedge,
          HoldLow                 => thold_DI31_WCLK_noedge_posedge,
          HoldHigh                => thold_DI31_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Tviol_DI4_WCLK_posedge or 
                 Tviol_DI5_WCLK_posedge or 
                 Tviol_DI6_WCLK_posedge or 
                 Tviol_DI7_WCLK_posedge or 
                 Tviol_DI8_WCLK_posedge or 
                 Tviol_DI9_WCLK_posedge or 
                 Tviol_DI10_WCLK_posedge or 
                 Tviol_DI11_WCLK_posedge or 
                 Tviol_DI12_WCLK_posedge or 
                 Tviol_DI13_WCLK_posedge or 
                 Tviol_DI14_WCLK_posedge or 
                 Tviol_DI15_WCLK_posedge or 
                 Tviol_DI16_WCLK_posedge or 
                 Tviol_DI17_WCLK_posedge or 
                 Tviol_DI18_WCLK_posedge or 
                 Tviol_DI19_WCLK_posedge or 
                 Tviol_DI20_WCLK_posedge or 
                 Tviol_DI21_WCLK_posedge or 
                 Tviol_DI22_WCLK_posedge or 
                 Tviol_DI23_WCLK_posedge or 
                 Tviol_DI24_WCLK_posedge or 
                 Tviol_DI25_WCLK_posedge or 
                 Tviol_DI26_WCLK_posedge or 
                 Tviol_DI27_WCLK_posedge or 
                 Tviol_DI28_WCLK_posedge or 
                 Tviol_DI29_WCLK_posedge or 
                 Tviol_DI30_WCLK_posedge or 
                 Tviol_DI31_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 9,
        WDATA_WIDTH    => 32,
        RADDR_WIDTH    => 14,
        RDATA_WIDTH    => 1,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX32_RX1_VITAL of RAMBFIFO16KA_WX32_RX1 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX32_RX1_VITAL;

----- CELL RAMBFIFO16KA_WX16_RX8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX16_RX8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 1024;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI4_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI5_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI6_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI7_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI8_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI8_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI9_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI9_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI10_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI10_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI11_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI11_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI12_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI12_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI13_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI13_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI14_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI14_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI15_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI15_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI8                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI9                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI10                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI11                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI12                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI13                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI14                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI15                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DI4                             : in    STD_ULOGIC;
      DI5                             : in    STD_ULOGIC;
      DI6                             : in    STD_ULOGIC;
      DI7                             : in    STD_ULOGIC;
      DI8                             : in    STD_ULOGIC;
      DI9                             : in    STD_ULOGIC;
      DI10                             : in    STD_ULOGIC;
      DI11                             : in    STD_ULOGIC;
      DI12                             : in    STD_ULOGIC;
      DI13                             : in    STD_ULOGIC;
      DI14                             : in    STD_ULOGIC;
      DI15                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      DO4                             : out    STD_ULOGIC;
      DO5                             : out    STD_ULOGIC;
      DO6                             : out    STD_ULOGIC;
      DO7                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX16_RX8 : entity is FALSE;
end RAMBFIFO16KA_WX16_RX8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX16_RX8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI4_ipd       : std_ulogic := 'X';
      signal DI5_ipd       : std_ulogic := 'X';
      signal DI6_ipd       : std_ulogic := 'X';
      signal DI7_ipd       : std_ulogic := 'X';
      signal DI8_ipd       : std_ulogic := 'X';
      signal DI9_ipd       : std_ulogic := 'X';
      signal DI10_ipd       : std_ulogic := 'X';
      signal DI11_ipd       : std_ulogic := 'X';
      signal DI12_ipd       : std_ulogic := 'X';
      signal DI13_ipd       : std_ulogic := 'X';
      signal DI14_ipd       : std_ulogic := 'X';
      signal DI15_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(15 downto 0);
      signal DO             : std_logic_vector(7 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI15_ipd & DI14_ipd & DI13_ipd & DI12_ipd & DI11_ipd & DI10_ipd & DI9_ipd & DI8_ipd & DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);
        VitalWireDelay (DI8_ipd, DI8, tipd_DI8);
        VitalWireDelay (DI9_ipd, DI9, tipd_DI9);
        VitalWireDelay (DI10_ipd, DI10, tipd_DI10);
        VitalWireDelay (DI11_ipd, DI11, tipd_DI11);
        VitalWireDelay (DI12_ipd, DI12, tipd_DI12);
        VitalWireDelay (DI13_ipd, DI13, tipd_DI13);
        VitalWireDelay (DI14_ipd, DI14, tipd_DI14);
        VitalWireDelay (DI15_ipd, DI15, tipd_DI15);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI4_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI5_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI6_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI7_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI8_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI9_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI10_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI11_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI12_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI13_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI14_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI15_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI8_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI9_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI10_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI11_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI12_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI13_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI14_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI15_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_WCLK_posedge,
          TimingData              => Tmkr_DI4_WCLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI4_WCLK_noedge_posedge,
          HoldLow                 => thold_DI4_WCLK_noedge_posedge,
          HoldHigh                => thold_DI4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_WCLK_posedge,
          TimingData              => Tmkr_DI5_WCLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI5_WCLK_noedge_posedge,
          HoldLow                 => thold_DI5_WCLK_noedge_posedge,
          HoldHigh                => thold_DI5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_WCLK_posedge,
          TimingData              => Tmkr_DI6_WCLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI6_WCLK_noedge_posedge,
          HoldLow                 => thold_DI6_WCLK_noedge_posedge,
          HoldHigh                => thold_DI6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_WCLK_posedge,
          TimingData              => Tmkr_DI7_WCLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI7_WCLK_noedge_posedge,
          HoldLow                 => thold_DI7_WCLK_noedge_posedge,
          HoldHigh                => thold_DI7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI8_WCLK_posedge,
          TimingData              => Tmkr_DI8_WCLK_posedge,
          TestSignal              => DI8_ipd,
          TestSignalName          => "DI8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI8_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI8_WCLK_noedge_posedge,
          HoldLow                 => thold_DI8_WCLK_noedge_posedge,
          HoldHigh                => thold_DI8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI9_WCLK_posedge,
          TimingData              => Tmkr_DI9_WCLK_posedge,
          TestSignal              => DI9_ipd,
          TestSignalName          => "DI9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI9_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI9_WCLK_noedge_posedge,
          HoldLow                 => thold_DI9_WCLK_noedge_posedge,
          HoldHigh                => thold_DI9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI10_WCLK_posedge,
          TimingData              => Tmkr_DI10_WCLK_posedge,
          TestSignal              => DI10_ipd,
          TestSignalName          => "DI10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI10_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI10_WCLK_noedge_posedge,
          HoldLow                 => thold_DI10_WCLK_noedge_posedge,
          HoldHigh                => thold_DI10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI11_WCLK_posedge,
          TimingData              => Tmkr_DI11_WCLK_posedge,
          TestSignal              => DI11_ipd,
          TestSignalName          => "DI11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI11_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI11_WCLK_noedge_posedge,
          HoldLow                 => thold_DI11_WCLK_noedge_posedge,
          HoldHigh                => thold_DI11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI12_WCLK_posedge,
          TimingData              => Tmkr_DI12_WCLK_posedge,
          TestSignal              => DI12_ipd,
          TestSignalName          => "DI12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI12_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI12_WCLK_noedge_posedge,
          HoldLow                 => thold_DI12_WCLK_noedge_posedge,
          HoldHigh                => thold_DI12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI13_WCLK_posedge,
          TimingData              => Tmkr_DI13_WCLK_posedge,
          TestSignal              => DI13_ipd,
          TestSignalName          => "DI13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI13_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI13_WCLK_noedge_posedge,
          HoldLow                 => thold_DI13_WCLK_noedge_posedge,
          HoldHigh                => thold_DI13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI14_WCLK_posedge,
          TimingData              => Tmkr_DI14_WCLK_posedge,
          TestSignal              => DI14_ipd,
          TestSignalName          => "DI14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI14_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI14_WCLK_noedge_posedge,
          HoldLow                 => thold_DI14_WCLK_noedge_posedge,
          HoldHigh                => thold_DI14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI15_WCLK_posedge,
          TimingData              => Tmkr_DI15_WCLK_posedge,
          TestSignal              => DI15_ipd,
          TestSignalName          => "DI15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI15_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI15_WCLK_noedge_posedge,
          HoldLow                 => thold_DI15_WCLK_noedge_posedge,
          HoldHigh                => thold_DI15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Tviol_DI4_WCLK_posedge or 
                 Tviol_DI5_WCLK_posedge or 
                 Tviol_DI6_WCLK_posedge or 
                 Tviol_DI7_WCLK_posedge or 
                 Tviol_DI8_WCLK_posedge or 
                 Tviol_DI9_WCLK_posedge or 
                 Tviol_DI10_WCLK_posedge or 
                 Tviol_DI11_WCLK_posedge or 
                 Tviol_DI12_WCLK_posedge or 
                 Tviol_DI13_WCLK_posedge or 
                 Tviol_DI14_WCLK_posedge or 
                 Tviol_DI15_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 10,
        WDATA_WIDTH    => 16,
        RADDR_WIDTH    => 11,
        RDATA_WIDTH    => 8,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX16_RX8_VITAL of RAMBFIFO16KA_WX16_RX8 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX16_RX8_VITAL;

----- CELL RAMBFIFO16KA_WX16_RX4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX16_RX4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 1024;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI4_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI5_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI6_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI7_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI8_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI8_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI9_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI9_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI10_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI10_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI11_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI11_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI12_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI12_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI13_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI13_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI14_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI14_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI15_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI15_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI8                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI9                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI10                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI11                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI12                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI13                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI14                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI15                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DI4                             : in    STD_ULOGIC;
      DI5                             : in    STD_ULOGIC;
      DI6                             : in    STD_ULOGIC;
      DI7                             : in    STD_ULOGIC;
      DI8                             : in    STD_ULOGIC;
      DI9                             : in    STD_ULOGIC;
      DI10                             : in    STD_ULOGIC;
      DI11                             : in    STD_ULOGIC;
      DI12                             : in    STD_ULOGIC;
      DI13                             : in    STD_ULOGIC;
      DI14                             : in    STD_ULOGIC;
      DI15                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX16_RX4 : entity is FALSE;
end RAMBFIFO16KA_WX16_RX4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX16_RX4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI4_ipd       : std_ulogic := 'X';
      signal DI5_ipd       : std_ulogic := 'X';
      signal DI6_ipd       : std_ulogic := 'X';
      signal DI7_ipd       : std_ulogic := 'X';
      signal DI8_ipd       : std_ulogic := 'X';
      signal DI9_ipd       : std_ulogic := 'X';
      signal DI10_ipd       : std_ulogic := 'X';
      signal DI11_ipd       : std_ulogic := 'X';
      signal DI12_ipd       : std_ulogic := 'X';
      signal DI13_ipd       : std_ulogic := 'X';
      signal DI14_ipd       : std_ulogic := 'X';
      signal DI15_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(15 downto 0);
      signal DO             : std_logic_vector(3 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI15_ipd & DI14_ipd & DI13_ipd & DI12_ipd & DI11_ipd & DI10_ipd & DI9_ipd & DI8_ipd & DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);
        VitalWireDelay (DI8_ipd, DI8, tipd_DI8);
        VitalWireDelay (DI9_ipd, DI9, tipd_DI9);
        VitalWireDelay (DI10_ipd, DI10, tipd_DI10);
        VitalWireDelay (DI11_ipd, DI11, tipd_DI11);
        VitalWireDelay (DI12_ipd, DI12, tipd_DI12);
        VitalWireDelay (DI13_ipd, DI13, tipd_DI13);
        VitalWireDelay (DI14_ipd, DI14, tipd_DI14);
        VitalWireDelay (DI15_ipd, DI15, tipd_DI15);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI4_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI5_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI6_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI7_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI8_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI9_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI10_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI11_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI12_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI13_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI14_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI15_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI8_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI9_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI10_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI11_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI12_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI13_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI14_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI15_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_WCLK_posedge,
          TimingData              => Tmkr_DI4_WCLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI4_WCLK_noedge_posedge,
          HoldLow                 => thold_DI4_WCLK_noedge_posedge,
          HoldHigh                => thold_DI4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_WCLK_posedge,
          TimingData              => Tmkr_DI5_WCLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI5_WCLK_noedge_posedge,
          HoldLow                 => thold_DI5_WCLK_noedge_posedge,
          HoldHigh                => thold_DI5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_WCLK_posedge,
          TimingData              => Tmkr_DI6_WCLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI6_WCLK_noedge_posedge,
          HoldLow                 => thold_DI6_WCLK_noedge_posedge,
          HoldHigh                => thold_DI6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_WCLK_posedge,
          TimingData              => Tmkr_DI7_WCLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI7_WCLK_noedge_posedge,
          HoldLow                 => thold_DI7_WCLK_noedge_posedge,
          HoldHigh                => thold_DI7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI8_WCLK_posedge,
          TimingData              => Tmkr_DI8_WCLK_posedge,
          TestSignal              => DI8_ipd,
          TestSignalName          => "DI8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI8_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI8_WCLK_noedge_posedge,
          HoldLow                 => thold_DI8_WCLK_noedge_posedge,
          HoldHigh                => thold_DI8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI9_WCLK_posedge,
          TimingData              => Tmkr_DI9_WCLK_posedge,
          TestSignal              => DI9_ipd,
          TestSignalName          => "DI9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI9_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI9_WCLK_noedge_posedge,
          HoldLow                 => thold_DI9_WCLK_noedge_posedge,
          HoldHigh                => thold_DI9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI10_WCLK_posedge,
          TimingData              => Tmkr_DI10_WCLK_posedge,
          TestSignal              => DI10_ipd,
          TestSignalName          => "DI10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI10_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI10_WCLK_noedge_posedge,
          HoldLow                 => thold_DI10_WCLK_noedge_posedge,
          HoldHigh                => thold_DI10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI11_WCLK_posedge,
          TimingData              => Tmkr_DI11_WCLK_posedge,
          TestSignal              => DI11_ipd,
          TestSignalName          => "DI11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI11_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI11_WCLK_noedge_posedge,
          HoldLow                 => thold_DI11_WCLK_noedge_posedge,
          HoldHigh                => thold_DI11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI12_WCLK_posedge,
          TimingData              => Tmkr_DI12_WCLK_posedge,
          TestSignal              => DI12_ipd,
          TestSignalName          => "DI12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI12_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI12_WCLK_noedge_posedge,
          HoldLow                 => thold_DI12_WCLK_noedge_posedge,
          HoldHigh                => thold_DI12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI13_WCLK_posedge,
          TimingData              => Tmkr_DI13_WCLK_posedge,
          TestSignal              => DI13_ipd,
          TestSignalName          => "DI13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI13_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI13_WCLK_noedge_posedge,
          HoldLow                 => thold_DI13_WCLK_noedge_posedge,
          HoldHigh                => thold_DI13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI14_WCLK_posedge,
          TimingData              => Tmkr_DI14_WCLK_posedge,
          TestSignal              => DI14_ipd,
          TestSignalName          => "DI14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI14_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI14_WCLK_noedge_posedge,
          HoldLow                 => thold_DI14_WCLK_noedge_posedge,
          HoldHigh                => thold_DI14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI15_WCLK_posedge,
          TimingData              => Tmkr_DI15_WCLK_posedge,
          TestSignal              => DI15_ipd,
          TestSignalName          => "DI15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI15_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI15_WCLK_noedge_posedge,
          HoldLow                 => thold_DI15_WCLK_noedge_posedge,
          HoldHigh                => thold_DI15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Tviol_DI4_WCLK_posedge or 
                 Tviol_DI5_WCLK_posedge or 
                 Tviol_DI6_WCLK_posedge or 
                 Tviol_DI7_WCLK_posedge or 
                 Tviol_DI8_WCLK_posedge or 
                 Tviol_DI9_WCLK_posedge or 
                 Tviol_DI10_WCLK_posedge or 
                 Tviol_DI11_WCLK_posedge or 
                 Tviol_DI12_WCLK_posedge or 
                 Tviol_DI13_WCLK_posedge or 
                 Tviol_DI14_WCLK_posedge or 
                 Tviol_DI15_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 10,
        WDATA_WIDTH    => 16,
        RADDR_WIDTH    => 12,
        RDATA_WIDTH    => 4,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX16_RX4_VITAL of RAMBFIFO16KA_WX16_RX4 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX16_RX4_VITAL;

----- CELL RAMBFIFO16KA_WX16_RX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX16_RX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 1024;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI4_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI5_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI6_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI7_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI8_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI8_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI9_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI9_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI10_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI10_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI11_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI11_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI12_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI12_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI13_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI13_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI14_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI14_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI15_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI15_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI8                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI9                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI10                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI11                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI12                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI13                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI14                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI15                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DI4                             : in    STD_ULOGIC;
      DI5                             : in    STD_ULOGIC;
      DI6                             : in    STD_ULOGIC;
      DI7                             : in    STD_ULOGIC;
      DI8                             : in    STD_ULOGIC;
      DI9                             : in    STD_ULOGIC;
      DI10                             : in    STD_ULOGIC;
      DI11                             : in    STD_ULOGIC;
      DI12                             : in    STD_ULOGIC;
      DI13                             : in    STD_ULOGIC;
      DI14                             : in    STD_ULOGIC;
      DI15                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX16_RX2 : entity is FALSE;
end RAMBFIFO16KA_WX16_RX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX16_RX2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI4_ipd       : std_ulogic := 'X';
      signal DI5_ipd       : std_ulogic := 'X';
      signal DI6_ipd       : std_ulogic := 'X';
      signal DI7_ipd       : std_ulogic := 'X';
      signal DI8_ipd       : std_ulogic := 'X';
      signal DI9_ipd       : std_ulogic := 'X';
      signal DI10_ipd       : std_ulogic := 'X';
      signal DI11_ipd       : std_ulogic := 'X';
      signal DI12_ipd       : std_ulogic := 'X';
      signal DI13_ipd       : std_ulogic := 'X';
      signal DI14_ipd       : std_ulogic := 'X';
      signal DI15_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(15 downto 0);
      signal DO             : std_logic_vector(1 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI15_ipd & DI14_ipd & DI13_ipd & DI12_ipd & DI11_ipd & DI10_ipd & DI9_ipd & DI8_ipd & DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);
        VitalWireDelay (DI8_ipd, DI8, tipd_DI8);
        VitalWireDelay (DI9_ipd, DI9, tipd_DI9);
        VitalWireDelay (DI10_ipd, DI10, tipd_DI10);
        VitalWireDelay (DI11_ipd, DI11, tipd_DI11);
        VitalWireDelay (DI12_ipd, DI12, tipd_DI12);
        VitalWireDelay (DI13_ipd, DI13, tipd_DI13);
        VitalWireDelay (DI14_ipd, DI14, tipd_DI14);
        VitalWireDelay (DI15_ipd, DI15, tipd_DI15);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI4_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI5_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI6_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI7_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI8_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI9_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI10_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI11_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI12_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI13_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI14_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI15_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI8_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI9_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI10_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI11_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI12_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI13_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI14_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI15_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_WCLK_posedge,
          TimingData              => Tmkr_DI4_WCLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI4_WCLK_noedge_posedge,
          HoldLow                 => thold_DI4_WCLK_noedge_posedge,
          HoldHigh                => thold_DI4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_WCLK_posedge,
          TimingData              => Tmkr_DI5_WCLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI5_WCLK_noedge_posedge,
          HoldLow                 => thold_DI5_WCLK_noedge_posedge,
          HoldHigh                => thold_DI5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_WCLK_posedge,
          TimingData              => Tmkr_DI6_WCLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI6_WCLK_noedge_posedge,
          HoldLow                 => thold_DI6_WCLK_noedge_posedge,
          HoldHigh                => thold_DI6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_WCLK_posedge,
          TimingData              => Tmkr_DI7_WCLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI7_WCLK_noedge_posedge,
          HoldLow                 => thold_DI7_WCLK_noedge_posedge,
          HoldHigh                => thold_DI7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI8_WCLK_posedge,
          TimingData              => Tmkr_DI8_WCLK_posedge,
          TestSignal              => DI8_ipd,
          TestSignalName          => "DI8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI8_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI8_WCLK_noedge_posedge,
          HoldLow                 => thold_DI8_WCLK_noedge_posedge,
          HoldHigh                => thold_DI8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI9_WCLK_posedge,
          TimingData              => Tmkr_DI9_WCLK_posedge,
          TestSignal              => DI9_ipd,
          TestSignalName          => "DI9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI9_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI9_WCLK_noedge_posedge,
          HoldLow                 => thold_DI9_WCLK_noedge_posedge,
          HoldHigh                => thold_DI9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI10_WCLK_posedge,
          TimingData              => Tmkr_DI10_WCLK_posedge,
          TestSignal              => DI10_ipd,
          TestSignalName          => "DI10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI10_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI10_WCLK_noedge_posedge,
          HoldLow                 => thold_DI10_WCLK_noedge_posedge,
          HoldHigh                => thold_DI10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI11_WCLK_posedge,
          TimingData              => Tmkr_DI11_WCLK_posedge,
          TestSignal              => DI11_ipd,
          TestSignalName          => "DI11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI11_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI11_WCLK_noedge_posedge,
          HoldLow                 => thold_DI11_WCLK_noedge_posedge,
          HoldHigh                => thold_DI11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI12_WCLK_posedge,
          TimingData              => Tmkr_DI12_WCLK_posedge,
          TestSignal              => DI12_ipd,
          TestSignalName          => "DI12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI12_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI12_WCLK_noedge_posedge,
          HoldLow                 => thold_DI12_WCLK_noedge_posedge,
          HoldHigh                => thold_DI12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI13_WCLK_posedge,
          TimingData              => Tmkr_DI13_WCLK_posedge,
          TestSignal              => DI13_ipd,
          TestSignalName          => "DI13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI13_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI13_WCLK_noedge_posedge,
          HoldLow                 => thold_DI13_WCLK_noedge_posedge,
          HoldHigh                => thold_DI13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI14_WCLK_posedge,
          TimingData              => Tmkr_DI14_WCLK_posedge,
          TestSignal              => DI14_ipd,
          TestSignalName          => "DI14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI14_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI14_WCLK_noedge_posedge,
          HoldLow                 => thold_DI14_WCLK_noedge_posedge,
          HoldHigh                => thold_DI14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI15_WCLK_posedge,
          TimingData              => Tmkr_DI15_WCLK_posedge,
          TestSignal              => DI15_ipd,
          TestSignalName          => "DI15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI15_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI15_WCLK_noedge_posedge,
          HoldLow                 => thold_DI15_WCLK_noedge_posedge,
          HoldHigh                => thold_DI15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Tviol_DI4_WCLK_posedge or 
                 Tviol_DI5_WCLK_posedge or 
                 Tviol_DI6_WCLK_posedge or 
                 Tviol_DI7_WCLK_posedge or 
                 Tviol_DI8_WCLK_posedge or 
                 Tviol_DI9_WCLK_posedge or 
                 Tviol_DI10_WCLK_posedge or 
                 Tviol_DI11_WCLK_posedge or 
                 Tviol_DI12_WCLK_posedge or 
                 Tviol_DI13_WCLK_posedge or 
                 Tviol_DI14_WCLK_posedge or 
                 Tviol_DI15_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 10,
        WDATA_WIDTH    => 16,
        RADDR_WIDTH    => 13,
        RDATA_WIDTH    => 2,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX16_RX2_VITAL of RAMBFIFO16KA_WX16_RX2 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX16_RX2_VITAL;

----- CELL RAMBFIFO16KA_WX16_RX1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX16_RX1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 1024;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI4_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI5_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI6_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI7_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI8_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI8_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI9_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI9_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI10_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI10_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI11_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI11_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI12_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI12_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI13_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI13_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI14_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI14_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI15_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI15_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI8                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI9                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI10                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI11                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI12                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI13                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI14                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI15                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DI4                             : in    STD_ULOGIC;
      DI5                             : in    STD_ULOGIC;
      DI6                             : in    STD_ULOGIC;
      DI7                             : in    STD_ULOGIC;
      DI8                             : in    STD_ULOGIC;
      DI9                             : in    STD_ULOGIC;
      DI10                             : in    STD_ULOGIC;
      DI11                             : in    STD_ULOGIC;
      DI12                             : in    STD_ULOGIC;
      DI13                             : in    STD_ULOGIC;
      DI14                             : in    STD_ULOGIC;
      DI15                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX16_RX1 : entity is FALSE;
end RAMBFIFO16KA_WX16_RX1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX16_RX1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI4_ipd       : std_ulogic := 'X';
      signal DI5_ipd       : std_ulogic := 'X';
      signal DI6_ipd       : std_ulogic := 'X';
      signal DI7_ipd       : std_ulogic := 'X';
      signal DI8_ipd       : std_ulogic := 'X';
      signal DI9_ipd       : std_ulogic := 'X';
      signal DI10_ipd       : std_ulogic := 'X';
      signal DI11_ipd       : std_ulogic := 'X';
      signal DI12_ipd       : std_ulogic := 'X';
      signal DI13_ipd       : std_ulogic := 'X';
      signal DI14_ipd       : std_ulogic := 'X';
      signal DI15_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(15 downto 0);
      signal DO             : std_logic_vector(0 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI15_ipd & DI14_ipd & DI13_ipd & DI12_ipd & DI11_ipd & DI10_ipd & DI9_ipd & DI8_ipd & DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);
        VitalWireDelay (DI8_ipd, DI8, tipd_DI8);
        VitalWireDelay (DI9_ipd, DI9, tipd_DI9);
        VitalWireDelay (DI10_ipd, DI10, tipd_DI10);
        VitalWireDelay (DI11_ipd, DI11, tipd_DI11);
        VitalWireDelay (DI12_ipd, DI12, tipd_DI12);
        VitalWireDelay (DI13_ipd, DI13, tipd_DI13);
        VitalWireDelay (DI14_ipd, DI14, tipd_DI14);
        VitalWireDelay (DI15_ipd, DI15, tipd_DI15);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI4_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI5_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI6_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI7_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI8_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI9_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI10_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI11_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI12_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI13_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI14_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI15_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI8_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI9_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI10_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI11_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI12_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI13_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI14_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI15_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_WCLK_posedge,
          TimingData              => Tmkr_DI4_WCLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI4_WCLK_noedge_posedge,
          HoldLow                 => thold_DI4_WCLK_noedge_posedge,
          HoldHigh                => thold_DI4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_WCLK_posedge,
          TimingData              => Tmkr_DI5_WCLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI5_WCLK_noedge_posedge,
          HoldLow                 => thold_DI5_WCLK_noedge_posedge,
          HoldHigh                => thold_DI5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_WCLK_posedge,
          TimingData              => Tmkr_DI6_WCLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI6_WCLK_noedge_posedge,
          HoldLow                 => thold_DI6_WCLK_noedge_posedge,
          HoldHigh                => thold_DI6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_WCLK_posedge,
          TimingData              => Tmkr_DI7_WCLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI7_WCLK_noedge_posedge,
          HoldLow                 => thold_DI7_WCLK_noedge_posedge,
          HoldHigh                => thold_DI7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI8_WCLK_posedge,
          TimingData              => Tmkr_DI8_WCLK_posedge,
          TestSignal              => DI8_ipd,
          TestSignalName          => "DI8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI8_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI8_WCLK_noedge_posedge,
          HoldLow                 => thold_DI8_WCLK_noedge_posedge,
          HoldHigh                => thold_DI8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI9_WCLK_posedge,
          TimingData              => Tmkr_DI9_WCLK_posedge,
          TestSignal              => DI9_ipd,
          TestSignalName          => "DI9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI9_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI9_WCLK_noedge_posedge,
          HoldLow                 => thold_DI9_WCLK_noedge_posedge,
          HoldHigh                => thold_DI9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI10_WCLK_posedge,
          TimingData              => Tmkr_DI10_WCLK_posedge,
          TestSignal              => DI10_ipd,
          TestSignalName          => "DI10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI10_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI10_WCLK_noedge_posedge,
          HoldLow                 => thold_DI10_WCLK_noedge_posedge,
          HoldHigh                => thold_DI10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI11_WCLK_posedge,
          TimingData              => Tmkr_DI11_WCLK_posedge,
          TestSignal              => DI11_ipd,
          TestSignalName          => "DI11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI11_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI11_WCLK_noedge_posedge,
          HoldLow                 => thold_DI11_WCLK_noedge_posedge,
          HoldHigh                => thold_DI11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI12_WCLK_posedge,
          TimingData              => Tmkr_DI12_WCLK_posedge,
          TestSignal              => DI12_ipd,
          TestSignalName          => "DI12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI12_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI12_WCLK_noedge_posedge,
          HoldLow                 => thold_DI12_WCLK_noedge_posedge,
          HoldHigh                => thold_DI12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI13_WCLK_posedge,
          TimingData              => Tmkr_DI13_WCLK_posedge,
          TestSignal              => DI13_ipd,
          TestSignalName          => "DI13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI13_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI13_WCLK_noedge_posedge,
          HoldLow                 => thold_DI13_WCLK_noedge_posedge,
          HoldHigh                => thold_DI13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI14_WCLK_posedge,
          TimingData              => Tmkr_DI14_WCLK_posedge,
          TestSignal              => DI14_ipd,
          TestSignalName          => "DI14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI14_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI14_WCLK_noedge_posedge,
          HoldLow                 => thold_DI14_WCLK_noedge_posedge,
          HoldHigh                => thold_DI14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI15_WCLK_posedge,
          TimingData              => Tmkr_DI15_WCLK_posedge,
          TestSignal              => DI15_ipd,
          TestSignalName          => "DI15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI15_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI15_WCLK_noedge_posedge,
          HoldLow                 => thold_DI15_WCLK_noedge_posedge,
          HoldHigh                => thold_DI15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Tviol_DI4_WCLK_posedge or 
                 Tviol_DI5_WCLK_posedge or 
                 Tviol_DI6_WCLK_posedge or 
                 Tviol_DI7_WCLK_posedge or 
                 Tviol_DI8_WCLK_posedge or 
                 Tviol_DI9_WCLK_posedge or 
                 Tviol_DI10_WCLK_posedge or 
                 Tviol_DI11_WCLK_posedge or 
                 Tviol_DI12_WCLK_posedge or 
                 Tviol_DI13_WCLK_posedge or 
                 Tviol_DI14_WCLK_posedge or 
                 Tviol_DI15_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 10,
        WDATA_WIDTH    => 16,
        RADDR_WIDTH    => 14,
        RDATA_WIDTH    => 1,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX16_RX1_VITAL of RAMBFIFO16KA_WX16_RX1 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX16_RX1_VITAL;

----- CELL RAMBFIFO16KA_WX8_RX4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX8_RX4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 2048;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI4_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI5_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI6_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI7_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DI4                             : in    STD_ULOGIC;
      DI5                             : in    STD_ULOGIC;
      DI6                             : in    STD_ULOGIC;
      DI7                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX8_RX4 : entity is FALSE;
end RAMBFIFO16KA_WX8_RX4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX8_RX4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI4_ipd       : std_ulogic := 'X';
      signal DI5_ipd       : std_ulogic := 'X';
      signal DI6_ipd       : std_ulogic := 'X';
      signal DI7_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(7 downto 0);
      signal DO             : std_logic_vector(3 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI4_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI5_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI6_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI7_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_WCLK_posedge,
          TimingData              => Tmkr_DI4_WCLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI4_WCLK_noedge_posedge,
          HoldLow                 => thold_DI4_WCLK_noedge_posedge,
          HoldHigh                => thold_DI4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_WCLK_posedge,
          TimingData              => Tmkr_DI5_WCLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI5_WCLK_noedge_posedge,
          HoldLow                 => thold_DI5_WCLK_noedge_posedge,
          HoldHigh                => thold_DI5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_WCLK_posedge,
          TimingData              => Tmkr_DI6_WCLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI6_WCLK_noedge_posedge,
          HoldLow                 => thold_DI6_WCLK_noedge_posedge,
          HoldHigh                => thold_DI6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_WCLK_posedge,
          TimingData              => Tmkr_DI7_WCLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI7_WCLK_noedge_posedge,
          HoldLow                 => thold_DI7_WCLK_noedge_posedge,
          HoldHigh                => thold_DI7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Tviol_DI4_WCLK_posedge or 
                 Tviol_DI5_WCLK_posedge or 
                 Tviol_DI6_WCLK_posedge or 
                 Tviol_DI7_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 11,
        WDATA_WIDTH    => 8,
        RADDR_WIDTH    => 12,
        RDATA_WIDTH    => 4,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX8_RX4_VITAL of RAMBFIFO16KA_WX8_RX4 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX8_RX4_VITAL;

----- CELL RAMBFIFO16KA_WX8_RX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX8_RX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 2048;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI4_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI5_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI6_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI7_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DI4                             : in    STD_ULOGIC;
      DI5                             : in    STD_ULOGIC;
      DI6                             : in    STD_ULOGIC;
      DI7                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX8_RX2 : entity is FALSE;
end RAMBFIFO16KA_WX8_RX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX8_RX2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI4_ipd       : std_ulogic := 'X';
      signal DI5_ipd       : std_ulogic := 'X';
      signal DI6_ipd       : std_ulogic := 'X';
      signal DI7_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(7 downto 0);
      signal DO             : std_logic_vector(1 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI4_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI5_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI6_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI7_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_WCLK_posedge,
          TimingData              => Tmkr_DI4_WCLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI4_WCLK_noedge_posedge,
          HoldLow                 => thold_DI4_WCLK_noedge_posedge,
          HoldHigh                => thold_DI4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_WCLK_posedge,
          TimingData              => Tmkr_DI5_WCLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI5_WCLK_noedge_posedge,
          HoldLow                 => thold_DI5_WCLK_noedge_posedge,
          HoldHigh                => thold_DI5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_WCLK_posedge,
          TimingData              => Tmkr_DI6_WCLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI6_WCLK_noedge_posedge,
          HoldLow                 => thold_DI6_WCLK_noedge_posedge,
          HoldHigh                => thold_DI6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_WCLK_posedge,
          TimingData              => Tmkr_DI7_WCLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI7_WCLK_noedge_posedge,
          HoldLow                 => thold_DI7_WCLK_noedge_posedge,
          HoldHigh                => thold_DI7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Tviol_DI4_WCLK_posedge or 
                 Tviol_DI5_WCLK_posedge or 
                 Tviol_DI6_WCLK_posedge or 
                 Tviol_DI7_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 11,
        WDATA_WIDTH    => 8,
        RADDR_WIDTH    => 13,
        RDATA_WIDTH    => 2,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX8_RX2_VITAL of RAMBFIFO16KA_WX8_RX2 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX8_RX2_VITAL;

----- CELL RAMBFIFO16KA_WX8_RX1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX8_RX1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 2048;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI4_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI5_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI6_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI7_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DI4                             : in    STD_ULOGIC;
      DI5                             : in    STD_ULOGIC;
      DI6                             : in    STD_ULOGIC;
      DI7                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX8_RX1 : entity is FALSE;
end RAMBFIFO16KA_WX8_RX1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX8_RX1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI4_ipd       : std_ulogic := 'X';
      signal DI5_ipd       : std_ulogic := 'X';
      signal DI6_ipd       : std_ulogic := 'X';
      signal DI7_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(7 downto 0);
      signal DO             : std_logic_vector(0 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI4_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI5_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI6_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI7_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_WCLK_posedge,
          TimingData              => Tmkr_DI4_WCLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI4_WCLK_noedge_posedge,
          HoldLow                 => thold_DI4_WCLK_noedge_posedge,
          HoldHigh                => thold_DI4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_WCLK_posedge,
          TimingData              => Tmkr_DI5_WCLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI5_WCLK_noedge_posedge,
          HoldLow                 => thold_DI5_WCLK_noedge_posedge,
          HoldHigh                => thold_DI5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_WCLK_posedge,
          TimingData              => Tmkr_DI6_WCLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI6_WCLK_noedge_posedge,
          HoldLow                 => thold_DI6_WCLK_noedge_posedge,
          HoldHigh                => thold_DI6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_WCLK_posedge,
          TimingData              => Tmkr_DI7_WCLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI7_WCLK_noedge_posedge,
          HoldLow                 => thold_DI7_WCLK_noedge_posedge,
          HoldHigh                => thold_DI7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Tviol_DI4_WCLK_posedge or 
                 Tviol_DI5_WCLK_posedge or 
                 Tviol_DI6_WCLK_posedge or 
                 Tviol_DI7_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 11,
        WDATA_WIDTH    => 8,
        RADDR_WIDTH    => 14,
        RDATA_WIDTH    => 1,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX8_RX1_VITAL of RAMBFIFO16KA_WX8_RX1 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX8_RX1_VITAL;

----- CELL RAMBFIFO16KA_WX4_RX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX4_RX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 4096;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX4_RX2 : entity is FALSE;
end RAMBFIFO16KA_WX4_RX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX4_RX2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(3 downto 0);
      signal DO             : std_logic_vector(1 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 12,
        WDATA_WIDTH    => 4,
        RADDR_WIDTH    => 13,
        RDATA_WIDTH    => 2,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX4_RX2_VITAL of RAMBFIFO16KA_WX4_RX2 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX4_RX2_VITAL;

----- CELL RAMBFIFO16KA_WX4_RX1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX4_RX1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 4096;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX4_RX1 : entity is FALSE;
end RAMBFIFO16KA_WX4_RX1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX4_RX1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(3 downto 0);
      signal DO             : std_logic_vector(0 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 12,
        WDATA_WIDTH    => 4,
        RADDR_WIDTH    => 14,
        RDATA_WIDTH    => 1,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX4_RX1_VITAL of RAMBFIFO16KA_WX4_RX1 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX4_RX1_VITAL;

----- CELL RAMBFIFO16KA_WX2_RX1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX2_RX1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 8192;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX2_RX1 : entity is FALSE;
end RAMBFIFO16KA_WX2_RX1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX2_RX1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(1 downto 0);
      signal DO             : std_logic_vector(0 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 13,
        WDATA_WIDTH    => 2,
        RADDR_WIDTH    => 14,
        RDATA_WIDTH    => 1,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX2_RX1_VITAL of RAMBFIFO16KA_WX2_RX1 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX2_RX1_VITAL;

----- CELL RAMBFIFO16KA_WX16_RX32 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX16_RX32 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 1024;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO16                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO17                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO18                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO19                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO20                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO21                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO22                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO23                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO24                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO25                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO26                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO27                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO28                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO29                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO30                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO31                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO16                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO17                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO18                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO19                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO20                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO21                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO22                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO23                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO24                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO25                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO26                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO27                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO28                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO29                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO30                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO31                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI4_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI5_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI6_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI7_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI8_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI8_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI9_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI9_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI10_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI10_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI11_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI11_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI12_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI12_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI13_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI13_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI14_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI14_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI15_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI15_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI8                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI9                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI10                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI11                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI12                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI13                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI14                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI15                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DI4                             : in    STD_ULOGIC;
      DI5                             : in    STD_ULOGIC;
      DI6                             : in    STD_ULOGIC;
      DI7                             : in    STD_ULOGIC;
      DI8                             : in    STD_ULOGIC;
      DI9                             : in    STD_ULOGIC;
      DI10                             : in    STD_ULOGIC;
      DI11                             : in    STD_ULOGIC;
      DI12                             : in    STD_ULOGIC;
      DI13                             : in    STD_ULOGIC;
      DI14                             : in    STD_ULOGIC;
      DI15                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      DO4                             : out    STD_ULOGIC;
      DO5                             : out    STD_ULOGIC;
      DO6                             : out    STD_ULOGIC;
      DO7                             : out    STD_ULOGIC;
      DO8                             : out    STD_ULOGIC;
      DO9                             : out    STD_ULOGIC;
      DO10                             : out    STD_ULOGIC;
      DO11                             : out    STD_ULOGIC;
      DO12                             : out    STD_ULOGIC;
      DO13                             : out    STD_ULOGIC;
      DO14                             : out    STD_ULOGIC;
      DO15                             : out    STD_ULOGIC;
      DO16                             : out    STD_ULOGIC;
      DO17                             : out    STD_ULOGIC;
      DO18                             : out    STD_ULOGIC;
      DO19                             : out    STD_ULOGIC;
      DO20                             : out    STD_ULOGIC;
      DO21                             : out    STD_ULOGIC;
      DO22                             : out    STD_ULOGIC;
      DO23                             : out    STD_ULOGIC;
      DO24                             : out    STD_ULOGIC;
      DO25                             : out    STD_ULOGIC;
      DO26                             : out    STD_ULOGIC;
      DO27                             : out    STD_ULOGIC;
      DO28                             : out    STD_ULOGIC;
      DO29                             : out    STD_ULOGIC;
      DO30                             : out    STD_ULOGIC;
      DO31                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX16_RX32 : entity is FALSE;
end RAMBFIFO16KA_WX16_RX32;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX16_RX32 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI4_ipd       : std_ulogic := 'X';
      signal DI5_ipd       : std_ulogic := 'X';
      signal DI6_ipd       : std_ulogic := 'X';
      signal DI7_ipd       : std_ulogic := 'X';
      signal DI8_ipd       : std_ulogic := 'X';
      signal DI9_ipd       : std_ulogic := 'X';
      signal DI10_ipd       : std_ulogic := 'X';
      signal DI11_ipd       : std_ulogic := 'X';
      signal DI12_ipd       : std_ulogic := 'X';
      signal DI13_ipd       : std_ulogic := 'X';
      signal DI14_ipd       : std_ulogic := 'X';
      signal DI15_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(15 downto 0);
      signal DO             : std_logic_vector(31 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI15_ipd & DI14_ipd & DI13_ipd & DI12_ipd & DI11_ipd & DI10_ipd & DI9_ipd & DI8_ipd & DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);
        VitalWireDelay (DI8_ipd, DI8, tipd_DI8);
        VitalWireDelay (DI9_ipd, DI9, tipd_DI9);
        VitalWireDelay (DI10_ipd, DI10, tipd_DI10);
        VitalWireDelay (DI11_ipd, DI11, tipd_DI11);
        VitalWireDelay (DI12_ipd, DI12, tipd_DI12);
        VitalWireDelay (DI13_ipd, DI13, tipd_DI13);
        VitalWireDelay (DI14_ipd, DI14, tipd_DI14);
        VitalWireDelay (DI15_ipd, DI15, tipd_DI15);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI4_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI5_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI6_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI7_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI8_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI9_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI10_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI11_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI12_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI13_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI14_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI15_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI8_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI9_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI10_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI11_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI12_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI13_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI14_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI15_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable DO8_zd          : std_ulogic := 'X';
        variable DO9_zd          : std_ulogic := 'X';
        variable DO10_zd          : std_ulogic := 'X';
        variable DO11_zd          : std_ulogic := 'X';
        variable DO12_zd          : std_ulogic := 'X';
        variable DO13_zd          : std_ulogic := 'X';
        variable DO14_zd          : std_ulogic := 'X';
        variable DO15_zd          : std_ulogic := 'X';
        variable DO16_zd          : std_ulogic := 'X';
        variable DO17_zd          : std_ulogic := 'X';
        variable DO18_zd          : std_ulogic := 'X';
        variable DO19_zd          : std_ulogic := 'X';
        variable DO20_zd          : std_ulogic := 'X';
        variable DO21_zd          : std_ulogic := 'X';
        variable DO22_zd          : std_ulogic := 'X';
        variable DO23_zd          : std_ulogic := 'X';
        variable DO24_zd          : std_ulogic := 'X';
        variable DO25_zd          : std_ulogic := 'X';
        variable DO26_zd          : std_ulogic := 'X';
        variable DO27_zd          : std_ulogic := 'X';
        variable DO28_zd          : std_ulogic := 'X';
        variable DO29_zd          : std_ulogic := 'X';
        variable DO30_zd          : std_ulogic := 'X';
        variable DO31_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_WCLK_posedge,
          TimingData              => Tmkr_DI4_WCLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI4_WCLK_noedge_posedge,
          HoldLow                 => thold_DI4_WCLK_noedge_posedge,
          HoldHigh                => thold_DI4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_WCLK_posedge,
          TimingData              => Tmkr_DI5_WCLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI5_WCLK_noedge_posedge,
          HoldLow                 => thold_DI5_WCLK_noedge_posedge,
          HoldHigh                => thold_DI5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_WCLK_posedge,
          TimingData              => Tmkr_DI6_WCLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI6_WCLK_noedge_posedge,
          HoldLow                 => thold_DI6_WCLK_noedge_posedge,
          HoldHigh                => thold_DI6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_WCLK_posedge,
          TimingData              => Tmkr_DI7_WCLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI7_WCLK_noedge_posedge,
          HoldLow                 => thold_DI7_WCLK_noedge_posedge,
          HoldHigh                => thold_DI7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI8_WCLK_posedge,
          TimingData              => Tmkr_DI8_WCLK_posedge,
          TestSignal              => DI8_ipd,
          TestSignalName          => "DI8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI8_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI8_WCLK_noedge_posedge,
          HoldLow                 => thold_DI8_WCLK_noedge_posedge,
          HoldHigh                => thold_DI8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI9_WCLK_posedge,
          TimingData              => Tmkr_DI9_WCLK_posedge,
          TestSignal              => DI9_ipd,
          TestSignalName          => "DI9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI9_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI9_WCLK_noedge_posedge,
          HoldLow                 => thold_DI9_WCLK_noedge_posedge,
          HoldHigh                => thold_DI9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI10_WCLK_posedge,
          TimingData              => Tmkr_DI10_WCLK_posedge,
          TestSignal              => DI10_ipd,
          TestSignalName          => "DI10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI10_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI10_WCLK_noedge_posedge,
          HoldLow                 => thold_DI10_WCLK_noedge_posedge,
          HoldHigh                => thold_DI10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI11_WCLK_posedge,
          TimingData              => Tmkr_DI11_WCLK_posedge,
          TestSignal              => DI11_ipd,
          TestSignalName          => "DI11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI11_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI11_WCLK_noedge_posedge,
          HoldLow                 => thold_DI11_WCLK_noedge_posedge,
          HoldHigh                => thold_DI11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI12_WCLK_posedge,
          TimingData              => Tmkr_DI12_WCLK_posedge,
          TestSignal              => DI12_ipd,
          TestSignalName          => "DI12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI12_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI12_WCLK_noedge_posedge,
          HoldLow                 => thold_DI12_WCLK_noedge_posedge,
          HoldHigh                => thold_DI12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI13_WCLK_posedge,
          TimingData              => Tmkr_DI13_WCLK_posedge,
          TestSignal              => DI13_ipd,
          TestSignalName          => "DI13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI13_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI13_WCLK_noedge_posedge,
          HoldLow                 => thold_DI13_WCLK_noedge_posedge,
          HoldHigh                => thold_DI13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI14_WCLK_posedge,
          TimingData              => Tmkr_DI14_WCLK_posedge,
          TestSignal              => DI14_ipd,
          TestSignalName          => "DI14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI14_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI14_WCLK_noedge_posedge,
          HoldLow                 => thold_DI14_WCLK_noedge_posedge,
          HoldHigh                => thold_DI14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI15_WCLK_posedge,
          TimingData              => Tmkr_DI15_WCLK_posedge,
          TestSignal              => DI15_ipd,
          TestSignalName          => "DI15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI15_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI15_WCLK_noedge_posedge,
          HoldLow                 => thold_DI15_WCLK_noedge_posedge,
          HoldHigh                => thold_DI15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX16_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Tviol_DI4_WCLK_posedge or 
                 Tviol_DI5_WCLK_posedge or 
                 Tviol_DI6_WCLK_posedge or 
                 Tviol_DI7_WCLK_posedge or 
                 Tviol_DI8_WCLK_posedge or 
                 Tviol_DI9_WCLK_posedge or 
                 Tviol_DI10_WCLK_posedge or 
                 Tviol_DI11_WCLK_posedge or 
                 Tviol_DI12_WCLK_posedge or 
                 Tviol_DI13_WCLK_posedge or 
                 Tviol_DI14_WCLK_posedge or 
                 Tviol_DI15_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_DO8  : process
      variable DO8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO8_zd := DO(8);

    VitalPathDelay01 (
      OutSignal => DO8,
      GlitchData => O_GlitchData,
      OutSignalName => "DO8",
      OutTemp => DO8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(8);
      end process;

    VitalBehavior_DO9  : process
      variable DO9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO9_zd := DO(9);

    VitalPathDelay01 (
      OutSignal => DO9,
      GlitchData => O_GlitchData,
      OutSignalName => "DO9",
      OutTemp => DO9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(9);
      end process;

    VitalBehavior_DO10  : process
      variable DO10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO10_zd := DO(10);

    VitalPathDelay01 (
      OutSignal => DO10,
      GlitchData => O_GlitchData,
      OutSignalName => "DO10",
      OutTemp => DO10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(10);
      end process;

    VitalBehavior_DO11  : process
      variable DO11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO11_zd := DO(11);

    VitalPathDelay01 (
      OutSignal => DO11,
      GlitchData => O_GlitchData,
      OutSignalName => "DO11",
      OutTemp => DO11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(11);
      end process;

    VitalBehavior_DO12  : process
      variable DO12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO12_zd := DO(12);

    VitalPathDelay01 (
      OutSignal => DO12,
      GlitchData => O_GlitchData,
      OutSignalName => "DO12",
      OutTemp => DO12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(12);
      end process;

    VitalBehavior_DO13  : process
      variable DO13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO13_zd := DO(13);

    VitalPathDelay01 (
      OutSignal => DO13,
      GlitchData => O_GlitchData,
      OutSignalName => "DO13",
      OutTemp => DO13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(13);
      end process;

    VitalBehavior_DO14  : process
      variable DO14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO14_zd := DO(14);

    VitalPathDelay01 (
      OutSignal => DO14,
      GlitchData => O_GlitchData,
      OutSignalName => "DO14",
      OutTemp => DO14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(14);
      end process;

    VitalBehavior_DO15  : process
      variable DO15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO15_zd := DO(15);

    VitalPathDelay01 (
      OutSignal => DO15,
      GlitchData => O_GlitchData,
      OutSignalName => "DO15",
      OutTemp => DO15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(15);
      end process;

    VitalBehavior_DO16  : process
      variable DO16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO16_zd := DO(16);

    VitalPathDelay01 (
      OutSignal => DO16,
      GlitchData => O_GlitchData,
      OutSignalName => "DO16",
      OutTemp => DO16_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO16, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(16);
      end process;

    VitalBehavior_DO17  : process
      variable DO17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO17_zd := DO(17);

    VitalPathDelay01 (
      OutSignal => DO17,
      GlitchData => O_GlitchData,
      OutSignalName => "DO17",
      OutTemp => DO17_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO17, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(17);
      end process;

    VitalBehavior_DO18  : process
      variable DO18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO18_zd := DO(18);

    VitalPathDelay01 (
      OutSignal => DO18,
      GlitchData => O_GlitchData,
      OutSignalName => "DO18",
      OutTemp => DO18_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO18, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(18);
      end process;

    VitalBehavior_DO19  : process
      variable DO19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO19_zd := DO(19);

    VitalPathDelay01 (
      OutSignal => DO19,
      GlitchData => O_GlitchData,
      OutSignalName => "DO19",
      OutTemp => DO19_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO19, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(19);
      end process;

    VitalBehavior_DO20  : process
      variable DO20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO20_zd := DO(20);

    VitalPathDelay01 (
      OutSignal => DO20,
      GlitchData => O_GlitchData,
      OutSignalName => "DO20",
      OutTemp => DO20_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO20, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(20);
      end process;

    VitalBehavior_DO21  : process
      variable DO21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO21_zd := DO(21);

    VitalPathDelay01 (
      OutSignal => DO21,
      GlitchData => O_GlitchData,
      OutSignalName => "DO21",
      OutTemp => DO21_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO21, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(21);
      end process;

    VitalBehavior_DO22  : process
      variable DO22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO22_zd := DO(22);

    VitalPathDelay01 (
      OutSignal => DO22,
      GlitchData => O_GlitchData,
      OutSignalName => "DO22",
      OutTemp => DO22_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO22, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(22);
      end process;

    VitalBehavior_DO23  : process
      variable DO23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO23_zd := DO(23);

    VitalPathDelay01 (
      OutSignal => DO23,
      GlitchData => O_GlitchData,
      OutSignalName => "DO23",
      OutTemp => DO23_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO23, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(23);
      end process;

    VitalBehavior_DO24  : process
      variable DO24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO24_zd := DO(24);

    VitalPathDelay01 (
      OutSignal => DO24,
      GlitchData => O_GlitchData,
      OutSignalName => "DO24",
      OutTemp => DO24_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO24, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(24);
      end process;

    VitalBehavior_DO25  : process
      variable DO25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO25_zd := DO(25);

    VitalPathDelay01 (
      OutSignal => DO25,
      GlitchData => O_GlitchData,
      OutSignalName => "DO25",
      OutTemp => DO25_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO25, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(25);
      end process;

    VitalBehavior_DO26  : process
      variable DO26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO26_zd := DO(26);

    VitalPathDelay01 (
      OutSignal => DO26,
      GlitchData => O_GlitchData,
      OutSignalName => "DO26",
      OutTemp => DO26_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO26, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(26);
      end process;

    VitalBehavior_DO27  : process
      variable DO27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO27_zd := DO(27);

    VitalPathDelay01 (
      OutSignal => DO27,
      GlitchData => O_GlitchData,
      OutSignalName => "DO27",
      OutTemp => DO27_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO27, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(27);
      end process;

    VitalBehavior_DO28  : process
      variable DO28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO28_zd := DO(28);

    VitalPathDelay01 (
      OutSignal => DO28,
      GlitchData => O_GlitchData,
      OutSignalName => "DO28",
      OutTemp => DO28_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO28, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(28);
      end process;

    VitalBehavior_DO29  : process
      variable DO29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO29_zd := DO(29);

    VitalPathDelay01 (
      OutSignal => DO29,
      GlitchData => O_GlitchData,
      OutSignalName => "DO29",
      OutTemp => DO29_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO29, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(29);
      end process;

    VitalBehavior_DO30  : process
      variable DO30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO30_zd := DO(30);

    VitalPathDelay01 (
      OutSignal => DO30,
      GlitchData => O_GlitchData,
      OutSignalName => "DO30",
      OutTemp => DO30_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO30, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(30);
      end process;

    VitalBehavior_DO31  : process
      variable DO31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO31_zd := DO(31);

    VitalPathDelay01 (
      OutSignal => DO31,
      GlitchData => O_GlitchData,
      OutSignalName => "DO31",
      OutTemp => DO31_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO31, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(31);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 10,
        WDATA_WIDTH    => 16,
        RADDR_WIDTH    => 9,
        RDATA_WIDTH    => 32,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX16_RX32_VITAL of RAMBFIFO16KA_WX16_RX32 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX16_RX32_VITAL;

----- CELL RAMBFIFO16KA_WX8_RX32 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX8_RX32 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 2048;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO16                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO17                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO18                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO19                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO20                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO21                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO22                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO23                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO24                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO25                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO26                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO27                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO28                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO29                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO30                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO31                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO16                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO17                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO18                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO19                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO20                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO21                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO22                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO23                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO24                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO25                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO26                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO27                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO28                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO29                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO30                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO31                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI4_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI5_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI6_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI7_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DI4                             : in    STD_ULOGIC;
      DI5                             : in    STD_ULOGIC;
      DI6                             : in    STD_ULOGIC;
      DI7                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      DO4                             : out    STD_ULOGIC;
      DO5                             : out    STD_ULOGIC;
      DO6                             : out    STD_ULOGIC;
      DO7                             : out    STD_ULOGIC;
      DO8                             : out    STD_ULOGIC;
      DO9                             : out    STD_ULOGIC;
      DO10                             : out    STD_ULOGIC;
      DO11                             : out    STD_ULOGIC;
      DO12                             : out    STD_ULOGIC;
      DO13                             : out    STD_ULOGIC;
      DO14                             : out    STD_ULOGIC;
      DO15                             : out    STD_ULOGIC;
      DO16                             : out    STD_ULOGIC;
      DO17                             : out    STD_ULOGIC;
      DO18                             : out    STD_ULOGIC;
      DO19                             : out    STD_ULOGIC;
      DO20                             : out    STD_ULOGIC;
      DO21                             : out    STD_ULOGIC;
      DO22                             : out    STD_ULOGIC;
      DO23                             : out    STD_ULOGIC;
      DO24                             : out    STD_ULOGIC;
      DO25                             : out    STD_ULOGIC;
      DO26                             : out    STD_ULOGIC;
      DO27                             : out    STD_ULOGIC;
      DO28                             : out    STD_ULOGIC;
      DO29                             : out    STD_ULOGIC;
      DO30                             : out    STD_ULOGIC;
      DO31                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX8_RX32 : entity is FALSE;
end RAMBFIFO16KA_WX8_RX32;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX8_RX32 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI4_ipd       : std_ulogic := 'X';
      signal DI5_ipd       : std_ulogic := 'X';
      signal DI6_ipd       : std_ulogic := 'X';
      signal DI7_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(7 downto 0);
      signal DO             : std_logic_vector(31 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI4_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI5_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI6_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI7_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable DO8_zd          : std_ulogic := 'X';
        variable DO9_zd          : std_ulogic := 'X';
        variable DO10_zd          : std_ulogic := 'X';
        variable DO11_zd          : std_ulogic := 'X';
        variable DO12_zd          : std_ulogic := 'X';
        variable DO13_zd          : std_ulogic := 'X';
        variable DO14_zd          : std_ulogic := 'X';
        variable DO15_zd          : std_ulogic := 'X';
        variable DO16_zd          : std_ulogic := 'X';
        variable DO17_zd          : std_ulogic := 'X';
        variable DO18_zd          : std_ulogic := 'X';
        variable DO19_zd          : std_ulogic := 'X';
        variable DO20_zd          : std_ulogic := 'X';
        variable DO21_zd          : std_ulogic := 'X';
        variable DO22_zd          : std_ulogic := 'X';
        variable DO23_zd          : std_ulogic := 'X';
        variable DO24_zd          : std_ulogic := 'X';
        variable DO25_zd          : std_ulogic := 'X';
        variable DO26_zd          : std_ulogic := 'X';
        variable DO27_zd          : std_ulogic := 'X';
        variable DO28_zd          : std_ulogic := 'X';
        variable DO29_zd          : std_ulogic := 'X';
        variable DO30_zd          : std_ulogic := 'X';
        variable DO31_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_WCLK_posedge,
          TimingData              => Tmkr_DI4_WCLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI4_WCLK_noedge_posedge,
          HoldLow                 => thold_DI4_WCLK_noedge_posedge,
          HoldHigh                => thold_DI4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_WCLK_posedge,
          TimingData              => Tmkr_DI5_WCLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI5_WCLK_noedge_posedge,
          HoldLow                 => thold_DI5_WCLK_noedge_posedge,
          HoldHigh                => thold_DI5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_WCLK_posedge,
          TimingData              => Tmkr_DI6_WCLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI6_WCLK_noedge_posedge,
          HoldLow                 => thold_DI6_WCLK_noedge_posedge,
          HoldHigh                => thold_DI6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_WCLK_posedge,
          TimingData              => Tmkr_DI7_WCLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI7_WCLK_noedge_posedge,
          HoldLow                 => thold_DI7_WCLK_noedge_posedge,
          HoldHigh                => thold_DI7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Tviol_DI4_WCLK_posedge or 
                 Tviol_DI5_WCLK_posedge or 
                 Tviol_DI6_WCLK_posedge or 
                 Tviol_DI7_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_DO8  : process
      variable DO8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO8_zd := DO(8);

    VitalPathDelay01 (
      OutSignal => DO8,
      GlitchData => O_GlitchData,
      OutSignalName => "DO8",
      OutTemp => DO8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(8);
      end process;

    VitalBehavior_DO9  : process
      variable DO9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO9_zd := DO(9);

    VitalPathDelay01 (
      OutSignal => DO9,
      GlitchData => O_GlitchData,
      OutSignalName => "DO9",
      OutTemp => DO9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(9);
      end process;

    VitalBehavior_DO10  : process
      variable DO10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO10_zd := DO(10);

    VitalPathDelay01 (
      OutSignal => DO10,
      GlitchData => O_GlitchData,
      OutSignalName => "DO10",
      OutTemp => DO10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(10);
      end process;

    VitalBehavior_DO11  : process
      variable DO11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO11_zd := DO(11);

    VitalPathDelay01 (
      OutSignal => DO11,
      GlitchData => O_GlitchData,
      OutSignalName => "DO11",
      OutTemp => DO11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(11);
      end process;

    VitalBehavior_DO12  : process
      variable DO12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO12_zd := DO(12);

    VitalPathDelay01 (
      OutSignal => DO12,
      GlitchData => O_GlitchData,
      OutSignalName => "DO12",
      OutTemp => DO12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(12);
      end process;

    VitalBehavior_DO13  : process
      variable DO13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO13_zd := DO(13);

    VitalPathDelay01 (
      OutSignal => DO13,
      GlitchData => O_GlitchData,
      OutSignalName => "DO13",
      OutTemp => DO13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(13);
      end process;

    VitalBehavior_DO14  : process
      variable DO14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO14_zd := DO(14);

    VitalPathDelay01 (
      OutSignal => DO14,
      GlitchData => O_GlitchData,
      OutSignalName => "DO14",
      OutTemp => DO14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(14);
      end process;

    VitalBehavior_DO15  : process
      variable DO15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO15_zd := DO(15);

    VitalPathDelay01 (
      OutSignal => DO15,
      GlitchData => O_GlitchData,
      OutSignalName => "DO15",
      OutTemp => DO15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(15);
      end process;

    VitalBehavior_DO16  : process
      variable DO16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO16_zd := DO(16);

    VitalPathDelay01 (
      OutSignal => DO16,
      GlitchData => O_GlitchData,
      OutSignalName => "DO16",
      OutTemp => DO16_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO16, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(16);
      end process;

    VitalBehavior_DO17  : process
      variable DO17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO17_zd := DO(17);

    VitalPathDelay01 (
      OutSignal => DO17,
      GlitchData => O_GlitchData,
      OutSignalName => "DO17",
      OutTemp => DO17_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO17, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(17);
      end process;

    VitalBehavior_DO18  : process
      variable DO18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO18_zd := DO(18);

    VitalPathDelay01 (
      OutSignal => DO18,
      GlitchData => O_GlitchData,
      OutSignalName => "DO18",
      OutTemp => DO18_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO18, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(18);
      end process;

    VitalBehavior_DO19  : process
      variable DO19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO19_zd := DO(19);

    VitalPathDelay01 (
      OutSignal => DO19,
      GlitchData => O_GlitchData,
      OutSignalName => "DO19",
      OutTemp => DO19_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO19, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(19);
      end process;

    VitalBehavior_DO20  : process
      variable DO20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO20_zd := DO(20);

    VitalPathDelay01 (
      OutSignal => DO20,
      GlitchData => O_GlitchData,
      OutSignalName => "DO20",
      OutTemp => DO20_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO20, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(20);
      end process;

    VitalBehavior_DO21  : process
      variable DO21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO21_zd := DO(21);

    VitalPathDelay01 (
      OutSignal => DO21,
      GlitchData => O_GlitchData,
      OutSignalName => "DO21",
      OutTemp => DO21_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO21, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(21);
      end process;

    VitalBehavior_DO22  : process
      variable DO22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO22_zd := DO(22);

    VitalPathDelay01 (
      OutSignal => DO22,
      GlitchData => O_GlitchData,
      OutSignalName => "DO22",
      OutTemp => DO22_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO22, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(22);
      end process;

    VitalBehavior_DO23  : process
      variable DO23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO23_zd := DO(23);

    VitalPathDelay01 (
      OutSignal => DO23,
      GlitchData => O_GlitchData,
      OutSignalName => "DO23",
      OutTemp => DO23_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO23, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(23);
      end process;

    VitalBehavior_DO24  : process
      variable DO24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO24_zd := DO(24);

    VitalPathDelay01 (
      OutSignal => DO24,
      GlitchData => O_GlitchData,
      OutSignalName => "DO24",
      OutTemp => DO24_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO24, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(24);
      end process;

    VitalBehavior_DO25  : process
      variable DO25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO25_zd := DO(25);

    VitalPathDelay01 (
      OutSignal => DO25,
      GlitchData => O_GlitchData,
      OutSignalName => "DO25",
      OutTemp => DO25_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO25, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(25);
      end process;

    VitalBehavior_DO26  : process
      variable DO26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO26_zd := DO(26);

    VitalPathDelay01 (
      OutSignal => DO26,
      GlitchData => O_GlitchData,
      OutSignalName => "DO26",
      OutTemp => DO26_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO26, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(26);
      end process;

    VitalBehavior_DO27  : process
      variable DO27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO27_zd := DO(27);

    VitalPathDelay01 (
      OutSignal => DO27,
      GlitchData => O_GlitchData,
      OutSignalName => "DO27",
      OutTemp => DO27_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO27, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(27);
      end process;

    VitalBehavior_DO28  : process
      variable DO28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO28_zd := DO(28);

    VitalPathDelay01 (
      OutSignal => DO28,
      GlitchData => O_GlitchData,
      OutSignalName => "DO28",
      OutTemp => DO28_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO28, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(28);
      end process;

    VitalBehavior_DO29  : process
      variable DO29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO29_zd := DO(29);

    VitalPathDelay01 (
      OutSignal => DO29,
      GlitchData => O_GlitchData,
      OutSignalName => "DO29",
      OutTemp => DO29_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO29, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(29);
      end process;

    VitalBehavior_DO30  : process
      variable DO30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO30_zd := DO(30);

    VitalPathDelay01 (
      OutSignal => DO30,
      GlitchData => O_GlitchData,
      OutSignalName => "DO30",
      OutTemp => DO30_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO30, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(30);
      end process;

    VitalBehavior_DO31  : process
      variable DO31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO31_zd := DO(31);

    VitalPathDelay01 (
      OutSignal => DO31,
      GlitchData => O_GlitchData,
      OutSignalName => "DO31",
      OutTemp => DO31_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO31, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(31);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 11,
        WDATA_WIDTH    => 8,
        RADDR_WIDTH    => 9,
        RDATA_WIDTH    => 32,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX8_RX32_VITAL of RAMBFIFO16KA_WX8_RX32 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX8_RX32_VITAL;

----- CELL RAMBFIFO16KA_WX4_RX32 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX4_RX32 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 4096;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO16                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO17                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO18                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO19                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO20                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO21                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO22                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO23                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO24                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO25                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO26                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO27                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO28                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO29                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO30                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO31                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO16                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO17                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO18                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO19                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO20                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO21                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO22                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO23                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO24                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO25                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO26                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO27                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO28                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO29                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO30                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO31                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      DO4                             : out    STD_ULOGIC;
      DO5                             : out    STD_ULOGIC;
      DO6                             : out    STD_ULOGIC;
      DO7                             : out    STD_ULOGIC;
      DO8                             : out    STD_ULOGIC;
      DO9                             : out    STD_ULOGIC;
      DO10                             : out    STD_ULOGIC;
      DO11                             : out    STD_ULOGIC;
      DO12                             : out    STD_ULOGIC;
      DO13                             : out    STD_ULOGIC;
      DO14                             : out    STD_ULOGIC;
      DO15                             : out    STD_ULOGIC;
      DO16                             : out    STD_ULOGIC;
      DO17                             : out    STD_ULOGIC;
      DO18                             : out    STD_ULOGIC;
      DO19                             : out    STD_ULOGIC;
      DO20                             : out    STD_ULOGIC;
      DO21                             : out    STD_ULOGIC;
      DO22                             : out    STD_ULOGIC;
      DO23                             : out    STD_ULOGIC;
      DO24                             : out    STD_ULOGIC;
      DO25                             : out    STD_ULOGIC;
      DO26                             : out    STD_ULOGIC;
      DO27                             : out    STD_ULOGIC;
      DO28                             : out    STD_ULOGIC;
      DO29                             : out    STD_ULOGIC;
      DO30                             : out    STD_ULOGIC;
      DO31                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX4_RX32 : entity is FALSE;
end RAMBFIFO16KA_WX4_RX32;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX4_RX32 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(3 downto 0);
      signal DO             : std_logic_vector(31 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable DO8_zd          : std_ulogic := 'X';
        variable DO9_zd          : std_ulogic := 'X';
        variable DO10_zd          : std_ulogic := 'X';
        variable DO11_zd          : std_ulogic := 'X';
        variable DO12_zd          : std_ulogic := 'X';
        variable DO13_zd          : std_ulogic := 'X';
        variable DO14_zd          : std_ulogic := 'X';
        variable DO15_zd          : std_ulogic := 'X';
        variable DO16_zd          : std_ulogic := 'X';
        variable DO17_zd          : std_ulogic := 'X';
        variable DO18_zd          : std_ulogic := 'X';
        variable DO19_zd          : std_ulogic := 'X';
        variable DO20_zd          : std_ulogic := 'X';
        variable DO21_zd          : std_ulogic := 'X';
        variable DO22_zd          : std_ulogic := 'X';
        variable DO23_zd          : std_ulogic := 'X';
        variable DO24_zd          : std_ulogic := 'X';
        variable DO25_zd          : std_ulogic := 'X';
        variable DO26_zd          : std_ulogic := 'X';
        variable DO27_zd          : std_ulogic := 'X';
        variable DO28_zd          : std_ulogic := 'X';
        variable DO29_zd          : std_ulogic := 'X';
        variable DO30_zd          : std_ulogic := 'X';
        variable DO31_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_DO8  : process
      variable DO8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO8_zd := DO(8);

    VitalPathDelay01 (
      OutSignal => DO8,
      GlitchData => O_GlitchData,
      OutSignalName => "DO8",
      OutTemp => DO8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(8);
      end process;

    VitalBehavior_DO9  : process
      variable DO9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO9_zd := DO(9);

    VitalPathDelay01 (
      OutSignal => DO9,
      GlitchData => O_GlitchData,
      OutSignalName => "DO9",
      OutTemp => DO9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(9);
      end process;

    VitalBehavior_DO10  : process
      variable DO10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO10_zd := DO(10);

    VitalPathDelay01 (
      OutSignal => DO10,
      GlitchData => O_GlitchData,
      OutSignalName => "DO10",
      OutTemp => DO10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(10);
      end process;

    VitalBehavior_DO11  : process
      variable DO11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO11_zd := DO(11);

    VitalPathDelay01 (
      OutSignal => DO11,
      GlitchData => O_GlitchData,
      OutSignalName => "DO11",
      OutTemp => DO11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(11);
      end process;

    VitalBehavior_DO12  : process
      variable DO12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO12_zd := DO(12);

    VitalPathDelay01 (
      OutSignal => DO12,
      GlitchData => O_GlitchData,
      OutSignalName => "DO12",
      OutTemp => DO12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(12);
      end process;

    VitalBehavior_DO13  : process
      variable DO13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO13_zd := DO(13);

    VitalPathDelay01 (
      OutSignal => DO13,
      GlitchData => O_GlitchData,
      OutSignalName => "DO13",
      OutTemp => DO13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(13);
      end process;

    VitalBehavior_DO14  : process
      variable DO14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO14_zd := DO(14);

    VitalPathDelay01 (
      OutSignal => DO14,
      GlitchData => O_GlitchData,
      OutSignalName => "DO14",
      OutTemp => DO14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(14);
      end process;

    VitalBehavior_DO15  : process
      variable DO15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO15_zd := DO(15);

    VitalPathDelay01 (
      OutSignal => DO15,
      GlitchData => O_GlitchData,
      OutSignalName => "DO15",
      OutTemp => DO15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(15);
      end process;

    VitalBehavior_DO16  : process
      variable DO16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO16_zd := DO(16);

    VitalPathDelay01 (
      OutSignal => DO16,
      GlitchData => O_GlitchData,
      OutSignalName => "DO16",
      OutTemp => DO16_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO16, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(16);
      end process;

    VitalBehavior_DO17  : process
      variable DO17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO17_zd := DO(17);

    VitalPathDelay01 (
      OutSignal => DO17,
      GlitchData => O_GlitchData,
      OutSignalName => "DO17",
      OutTemp => DO17_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO17, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(17);
      end process;

    VitalBehavior_DO18  : process
      variable DO18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO18_zd := DO(18);

    VitalPathDelay01 (
      OutSignal => DO18,
      GlitchData => O_GlitchData,
      OutSignalName => "DO18",
      OutTemp => DO18_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO18, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(18);
      end process;

    VitalBehavior_DO19  : process
      variable DO19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO19_zd := DO(19);

    VitalPathDelay01 (
      OutSignal => DO19,
      GlitchData => O_GlitchData,
      OutSignalName => "DO19",
      OutTemp => DO19_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO19, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(19);
      end process;

    VitalBehavior_DO20  : process
      variable DO20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO20_zd := DO(20);

    VitalPathDelay01 (
      OutSignal => DO20,
      GlitchData => O_GlitchData,
      OutSignalName => "DO20",
      OutTemp => DO20_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO20, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(20);
      end process;

    VitalBehavior_DO21  : process
      variable DO21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO21_zd := DO(21);

    VitalPathDelay01 (
      OutSignal => DO21,
      GlitchData => O_GlitchData,
      OutSignalName => "DO21",
      OutTemp => DO21_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO21, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(21);
      end process;

    VitalBehavior_DO22  : process
      variable DO22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO22_zd := DO(22);

    VitalPathDelay01 (
      OutSignal => DO22,
      GlitchData => O_GlitchData,
      OutSignalName => "DO22",
      OutTemp => DO22_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO22, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(22);
      end process;

    VitalBehavior_DO23  : process
      variable DO23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO23_zd := DO(23);

    VitalPathDelay01 (
      OutSignal => DO23,
      GlitchData => O_GlitchData,
      OutSignalName => "DO23",
      OutTemp => DO23_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO23, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(23);
      end process;

    VitalBehavior_DO24  : process
      variable DO24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO24_zd := DO(24);

    VitalPathDelay01 (
      OutSignal => DO24,
      GlitchData => O_GlitchData,
      OutSignalName => "DO24",
      OutTemp => DO24_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO24, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(24);
      end process;

    VitalBehavior_DO25  : process
      variable DO25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO25_zd := DO(25);

    VitalPathDelay01 (
      OutSignal => DO25,
      GlitchData => O_GlitchData,
      OutSignalName => "DO25",
      OutTemp => DO25_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO25, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(25);
      end process;

    VitalBehavior_DO26  : process
      variable DO26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO26_zd := DO(26);

    VitalPathDelay01 (
      OutSignal => DO26,
      GlitchData => O_GlitchData,
      OutSignalName => "DO26",
      OutTemp => DO26_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO26, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(26);
      end process;

    VitalBehavior_DO27  : process
      variable DO27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO27_zd := DO(27);

    VitalPathDelay01 (
      OutSignal => DO27,
      GlitchData => O_GlitchData,
      OutSignalName => "DO27",
      OutTemp => DO27_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO27, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(27);
      end process;

    VitalBehavior_DO28  : process
      variable DO28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO28_zd := DO(28);

    VitalPathDelay01 (
      OutSignal => DO28,
      GlitchData => O_GlitchData,
      OutSignalName => "DO28",
      OutTemp => DO28_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO28, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(28);
      end process;

    VitalBehavior_DO29  : process
      variable DO29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO29_zd := DO(29);

    VitalPathDelay01 (
      OutSignal => DO29,
      GlitchData => O_GlitchData,
      OutSignalName => "DO29",
      OutTemp => DO29_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO29, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(29);
      end process;

    VitalBehavior_DO30  : process
      variable DO30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO30_zd := DO(30);

    VitalPathDelay01 (
      OutSignal => DO30,
      GlitchData => O_GlitchData,
      OutSignalName => "DO30",
      OutTemp => DO30_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO30, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(30);
      end process;

    VitalBehavior_DO31  : process
      variable DO31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO31_zd := DO(31);

    VitalPathDelay01 (
      OutSignal => DO31,
      GlitchData => O_GlitchData,
      OutSignalName => "DO31",
      OutTemp => DO31_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO31, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(31);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 12,
        WDATA_WIDTH    => 4,
        RADDR_WIDTH    => 9,
        RDATA_WIDTH    => 32,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX4_RX32_VITAL of RAMBFIFO16KA_WX4_RX32 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX4_RX32_VITAL;

----- CELL RAMBFIFO16KA_WX2_RX32 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX2_RX32 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 8192;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO16                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO17                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO18                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO19                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO20                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO21                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO22                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO23                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO24                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO25                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO26                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO27                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO28                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO29                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO30                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO31                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO16                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO17                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO18                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO19                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO20                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO21                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO22                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO23                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO24                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO25                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO26                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO27                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO28                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO29                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO30                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO31                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      DO4                             : out    STD_ULOGIC;
      DO5                             : out    STD_ULOGIC;
      DO6                             : out    STD_ULOGIC;
      DO7                             : out    STD_ULOGIC;
      DO8                             : out    STD_ULOGIC;
      DO9                             : out    STD_ULOGIC;
      DO10                             : out    STD_ULOGIC;
      DO11                             : out    STD_ULOGIC;
      DO12                             : out    STD_ULOGIC;
      DO13                             : out    STD_ULOGIC;
      DO14                             : out    STD_ULOGIC;
      DO15                             : out    STD_ULOGIC;
      DO16                             : out    STD_ULOGIC;
      DO17                             : out    STD_ULOGIC;
      DO18                             : out    STD_ULOGIC;
      DO19                             : out    STD_ULOGIC;
      DO20                             : out    STD_ULOGIC;
      DO21                             : out    STD_ULOGIC;
      DO22                             : out    STD_ULOGIC;
      DO23                             : out    STD_ULOGIC;
      DO24                             : out    STD_ULOGIC;
      DO25                             : out    STD_ULOGIC;
      DO26                             : out    STD_ULOGIC;
      DO27                             : out    STD_ULOGIC;
      DO28                             : out    STD_ULOGIC;
      DO29                             : out    STD_ULOGIC;
      DO30                             : out    STD_ULOGIC;
      DO31                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX2_RX32 : entity is FALSE;
end RAMBFIFO16KA_WX2_RX32;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX2_RX32 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(1 downto 0);
      signal DO             : std_logic_vector(31 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable DO8_zd          : std_ulogic := 'X';
        variable DO9_zd          : std_ulogic := 'X';
        variable DO10_zd          : std_ulogic := 'X';
        variable DO11_zd          : std_ulogic := 'X';
        variable DO12_zd          : std_ulogic := 'X';
        variable DO13_zd          : std_ulogic := 'X';
        variable DO14_zd          : std_ulogic := 'X';
        variable DO15_zd          : std_ulogic := 'X';
        variable DO16_zd          : std_ulogic := 'X';
        variable DO17_zd          : std_ulogic := 'X';
        variable DO18_zd          : std_ulogic := 'X';
        variable DO19_zd          : std_ulogic := 'X';
        variable DO20_zd          : std_ulogic := 'X';
        variable DO21_zd          : std_ulogic := 'X';
        variable DO22_zd          : std_ulogic := 'X';
        variable DO23_zd          : std_ulogic := 'X';
        variable DO24_zd          : std_ulogic := 'X';
        variable DO25_zd          : std_ulogic := 'X';
        variable DO26_zd          : std_ulogic := 'X';
        variable DO27_zd          : std_ulogic := 'X';
        variable DO28_zd          : std_ulogic := 'X';
        variable DO29_zd          : std_ulogic := 'X';
        variable DO30_zd          : std_ulogic := 'X';
        variable DO31_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_DO8  : process
      variable DO8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO8_zd := DO(8);

    VitalPathDelay01 (
      OutSignal => DO8,
      GlitchData => O_GlitchData,
      OutSignalName => "DO8",
      OutTemp => DO8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(8);
      end process;

    VitalBehavior_DO9  : process
      variable DO9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO9_zd := DO(9);

    VitalPathDelay01 (
      OutSignal => DO9,
      GlitchData => O_GlitchData,
      OutSignalName => "DO9",
      OutTemp => DO9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(9);
      end process;

    VitalBehavior_DO10  : process
      variable DO10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO10_zd := DO(10);

    VitalPathDelay01 (
      OutSignal => DO10,
      GlitchData => O_GlitchData,
      OutSignalName => "DO10",
      OutTemp => DO10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(10);
      end process;

    VitalBehavior_DO11  : process
      variable DO11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO11_zd := DO(11);

    VitalPathDelay01 (
      OutSignal => DO11,
      GlitchData => O_GlitchData,
      OutSignalName => "DO11",
      OutTemp => DO11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(11);
      end process;

    VitalBehavior_DO12  : process
      variable DO12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO12_zd := DO(12);

    VitalPathDelay01 (
      OutSignal => DO12,
      GlitchData => O_GlitchData,
      OutSignalName => "DO12",
      OutTemp => DO12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(12);
      end process;

    VitalBehavior_DO13  : process
      variable DO13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO13_zd := DO(13);

    VitalPathDelay01 (
      OutSignal => DO13,
      GlitchData => O_GlitchData,
      OutSignalName => "DO13",
      OutTemp => DO13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(13);
      end process;

    VitalBehavior_DO14  : process
      variable DO14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO14_zd := DO(14);

    VitalPathDelay01 (
      OutSignal => DO14,
      GlitchData => O_GlitchData,
      OutSignalName => "DO14",
      OutTemp => DO14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(14);
      end process;

    VitalBehavior_DO15  : process
      variable DO15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO15_zd := DO(15);

    VitalPathDelay01 (
      OutSignal => DO15,
      GlitchData => O_GlitchData,
      OutSignalName => "DO15",
      OutTemp => DO15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(15);
      end process;

    VitalBehavior_DO16  : process
      variable DO16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO16_zd := DO(16);

    VitalPathDelay01 (
      OutSignal => DO16,
      GlitchData => O_GlitchData,
      OutSignalName => "DO16",
      OutTemp => DO16_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO16, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(16);
      end process;

    VitalBehavior_DO17  : process
      variable DO17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO17_zd := DO(17);

    VitalPathDelay01 (
      OutSignal => DO17,
      GlitchData => O_GlitchData,
      OutSignalName => "DO17",
      OutTemp => DO17_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO17, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(17);
      end process;

    VitalBehavior_DO18  : process
      variable DO18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO18_zd := DO(18);

    VitalPathDelay01 (
      OutSignal => DO18,
      GlitchData => O_GlitchData,
      OutSignalName => "DO18",
      OutTemp => DO18_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO18, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(18);
      end process;

    VitalBehavior_DO19  : process
      variable DO19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO19_zd := DO(19);

    VitalPathDelay01 (
      OutSignal => DO19,
      GlitchData => O_GlitchData,
      OutSignalName => "DO19",
      OutTemp => DO19_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO19, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(19);
      end process;

    VitalBehavior_DO20  : process
      variable DO20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO20_zd := DO(20);

    VitalPathDelay01 (
      OutSignal => DO20,
      GlitchData => O_GlitchData,
      OutSignalName => "DO20",
      OutTemp => DO20_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO20, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(20);
      end process;

    VitalBehavior_DO21  : process
      variable DO21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO21_zd := DO(21);

    VitalPathDelay01 (
      OutSignal => DO21,
      GlitchData => O_GlitchData,
      OutSignalName => "DO21",
      OutTemp => DO21_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO21, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(21);
      end process;

    VitalBehavior_DO22  : process
      variable DO22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO22_zd := DO(22);

    VitalPathDelay01 (
      OutSignal => DO22,
      GlitchData => O_GlitchData,
      OutSignalName => "DO22",
      OutTemp => DO22_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO22, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(22);
      end process;

    VitalBehavior_DO23  : process
      variable DO23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO23_zd := DO(23);

    VitalPathDelay01 (
      OutSignal => DO23,
      GlitchData => O_GlitchData,
      OutSignalName => "DO23",
      OutTemp => DO23_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO23, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(23);
      end process;

    VitalBehavior_DO24  : process
      variable DO24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO24_zd := DO(24);

    VitalPathDelay01 (
      OutSignal => DO24,
      GlitchData => O_GlitchData,
      OutSignalName => "DO24",
      OutTemp => DO24_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO24, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(24);
      end process;

    VitalBehavior_DO25  : process
      variable DO25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO25_zd := DO(25);

    VitalPathDelay01 (
      OutSignal => DO25,
      GlitchData => O_GlitchData,
      OutSignalName => "DO25",
      OutTemp => DO25_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO25, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(25);
      end process;

    VitalBehavior_DO26  : process
      variable DO26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO26_zd := DO(26);

    VitalPathDelay01 (
      OutSignal => DO26,
      GlitchData => O_GlitchData,
      OutSignalName => "DO26",
      OutTemp => DO26_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO26, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(26);
      end process;

    VitalBehavior_DO27  : process
      variable DO27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO27_zd := DO(27);

    VitalPathDelay01 (
      OutSignal => DO27,
      GlitchData => O_GlitchData,
      OutSignalName => "DO27",
      OutTemp => DO27_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO27, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(27);
      end process;

    VitalBehavior_DO28  : process
      variable DO28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO28_zd := DO(28);

    VitalPathDelay01 (
      OutSignal => DO28,
      GlitchData => O_GlitchData,
      OutSignalName => "DO28",
      OutTemp => DO28_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO28, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(28);
      end process;

    VitalBehavior_DO29  : process
      variable DO29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO29_zd := DO(29);

    VitalPathDelay01 (
      OutSignal => DO29,
      GlitchData => O_GlitchData,
      OutSignalName => "DO29",
      OutTemp => DO29_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO29, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(29);
      end process;

    VitalBehavior_DO30  : process
      variable DO30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO30_zd := DO(30);

    VitalPathDelay01 (
      OutSignal => DO30,
      GlitchData => O_GlitchData,
      OutSignalName => "DO30",
      OutTemp => DO30_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO30, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(30);
      end process;

    VitalBehavior_DO31  : process
      variable DO31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO31_zd := DO(31);

    VitalPathDelay01 (
      OutSignal => DO31,
      GlitchData => O_GlitchData,
      OutSignalName => "DO31",
      OutTemp => DO31_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO31, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(31);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 13,
        WDATA_WIDTH    => 2,
        RADDR_WIDTH    => 9,
        RDATA_WIDTH    => 32,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX2_RX32_VITAL of RAMBFIFO16KA_WX2_RX32 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX2_RX32_VITAL;

----- CELL RAMBFIFO16KA_WX1_RX32 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX1_RX32 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 16384;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO16                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO17                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO18                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO19                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO20                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO21                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO22                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO23                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO24                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO25                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO26                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO27                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO28                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO29                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO30                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO31                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO16                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO17                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO18                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO19                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO20                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO21                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO22                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO23                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO24                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO25                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO26                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO27                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO28                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO29                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO30                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO31                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      DO4                             : out    STD_ULOGIC;
      DO5                             : out    STD_ULOGIC;
      DO6                             : out    STD_ULOGIC;
      DO7                             : out    STD_ULOGIC;
      DO8                             : out    STD_ULOGIC;
      DO9                             : out    STD_ULOGIC;
      DO10                             : out    STD_ULOGIC;
      DO11                             : out    STD_ULOGIC;
      DO12                             : out    STD_ULOGIC;
      DO13                             : out    STD_ULOGIC;
      DO14                             : out    STD_ULOGIC;
      DO15                             : out    STD_ULOGIC;
      DO16                             : out    STD_ULOGIC;
      DO17                             : out    STD_ULOGIC;
      DO18                             : out    STD_ULOGIC;
      DO19                             : out    STD_ULOGIC;
      DO20                             : out    STD_ULOGIC;
      DO21                             : out    STD_ULOGIC;
      DO22                             : out    STD_ULOGIC;
      DO23                             : out    STD_ULOGIC;
      DO24                             : out    STD_ULOGIC;
      DO25                             : out    STD_ULOGIC;
      DO26                             : out    STD_ULOGIC;
      DO27                             : out    STD_ULOGIC;
      DO28                             : out    STD_ULOGIC;
      DO29                             : out    STD_ULOGIC;
      DO30                             : out    STD_ULOGIC;
      DO31                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX1_RX32 : entity is FALSE;
end RAMBFIFO16KA_WX1_RX32;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX1_RX32 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_logic_vector(0 downto 0) := (others => 'X');
      signal DI             : std_logic_vector(0 downto 0);
      signal DO             : std_logic_vector(31 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd(0), DI0, tipd_DI0);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable DO8_zd          : std_ulogic := 'X';
        variable DO9_zd          : std_ulogic := 'X';
        variable DO10_zd          : std_ulogic := 'X';
        variable DO11_zd          : std_ulogic := 'X';
        variable DO12_zd          : std_ulogic := 'X';
        variable DO13_zd          : std_ulogic := 'X';
        variable DO14_zd          : std_ulogic := 'X';
        variable DO15_zd          : std_ulogic := 'X';
        variable DO16_zd          : std_ulogic := 'X';
        variable DO17_zd          : std_ulogic := 'X';
        variable DO18_zd          : std_ulogic := 'X';
        variable DO19_zd          : std_ulogic := 'X';
        variable DO20_zd          : std_ulogic := 'X';
        variable DO21_zd          : std_ulogic := 'X';
        variable DO22_zd          : std_ulogic := 'X';
        variable DO23_zd          : std_ulogic := 'X';
        variable DO24_zd          : std_ulogic := 'X';
        variable DO25_zd          : std_ulogic := 'X';
        variable DO26_zd          : std_ulogic := 'X';
        variable DO27_zd          : std_ulogic := 'X';
        variable DO28_zd          : std_ulogic := 'X';
        variable DO29_zd          : std_ulogic := 'X';
        variable DO30_zd          : std_ulogic := 'X';
        variable DO31_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX32",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_DO8  : process
      variable DO8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO8_zd := DO(8);

    VitalPathDelay01 (
      OutSignal => DO8,
      GlitchData => O_GlitchData,
      OutSignalName => "DO8",
      OutTemp => DO8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(8);
      end process;

    VitalBehavior_DO9  : process
      variable DO9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO9_zd := DO(9);

    VitalPathDelay01 (
      OutSignal => DO9,
      GlitchData => O_GlitchData,
      OutSignalName => "DO9",
      OutTemp => DO9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(9);
      end process;

    VitalBehavior_DO10  : process
      variable DO10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO10_zd := DO(10);

    VitalPathDelay01 (
      OutSignal => DO10,
      GlitchData => O_GlitchData,
      OutSignalName => "DO10",
      OutTemp => DO10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(10);
      end process;

    VitalBehavior_DO11  : process
      variable DO11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO11_zd := DO(11);

    VitalPathDelay01 (
      OutSignal => DO11,
      GlitchData => O_GlitchData,
      OutSignalName => "DO11",
      OutTemp => DO11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(11);
      end process;

    VitalBehavior_DO12  : process
      variable DO12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO12_zd := DO(12);

    VitalPathDelay01 (
      OutSignal => DO12,
      GlitchData => O_GlitchData,
      OutSignalName => "DO12",
      OutTemp => DO12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(12);
      end process;

    VitalBehavior_DO13  : process
      variable DO13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO13_zd := DO(13);

    VitalPathDelay01 (
      OutSignal => DO13,
      GlitchData => O_GlitchData,
      OutSignalName => "DO13",
      OutTemp => DO13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(13);
      end process;

    VitalBehavior_DO14  : process
      variable DO14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO14_zd := DO(14);

    VitalPathDelay01 (
      OutSignal => DO14,
      GlitchData => O_GlitchData,
      OutSignalName => "DO14",
      OutTemp => DO14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(14);
      end process;

    VitalBehavior_DO15  : process
      variable DO15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO15_zd := DO(15);

    VitalPathDelay01 (
      OutSignal => DO15,
      GlitchData => O_GlitchData,
      OutSignalName => "DO15",
      OutTemp => DO15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(15);
      end process;

    VitalBehavior_DO16  : process
      variable DO16_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO16_zd := DO(16);

    VitalPathDelay01 (
      OutSignal => DO16,
      GlitchData => O_GlitchData,
      OutSignalName => "DO16",
      OutTemp => DO16_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO16, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO16, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(16);
      end process;

    VitalBehavior_DO17  : process
      variable DO17_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO17_zd := DO(17);

    VitalPathDelay01 (
      OutSignal => DO17,
      GlitchData => O_GlitchData,
      OutSignalName => "DO17",
      OutTemp => DO17_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO17, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO17, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(17);
      end process;

    VitalBehavior_DO18  : process
      variable DO18_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO18_zd := DO(18);

    VitalPathDelay01 (
      OutSignal => DO18,
      GlitchData => O_GlitchData,
      OutSignalName => "DO18",
      OutTemp => DO18_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO18, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO18, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(18);
      end process;

    VitalBehavior_DO19  : process
      variable DO19_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO19_zd := DO(19);

    VitalPathDelay01 (
      OutSignal => DO19,
      GlitchData => O_GlitchData,
      OutSignalName => "DO19",
      OutTemp => DO19_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO19, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO19, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(19);
      end process;

    VitalBehavior_DO20  : process
      variable DO20_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO20_zd := DO(20);

    VitalPathDelay01 (
      OutSignal => DO20,
      GlitchData => O_GlitchData,
      OutSignalName => "DO20",
      OutTemp => DO20_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO20, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO20, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(20);
      end process;

    VitalBehavior_DO21  : process
      variable DO21_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO21_zd := DO(21);

    VitalPathDelay01 (
      OutSignal => DO21,
      GlitchData => O_GlitchData,
      OutSignalName => "DO21",
      OutTemp => DO21_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO21, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO21, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(21);
      end process;

    VitalBehavior_DO22  : process
      variable DO22_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO22_zd := DO(22);

    VitalPathDelay01 (
      OutSignal => DO22,
      GlitchData => O_GlitchData,
      OutSignalName => "DO22",
      OutTemp => DO22_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO22, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO22, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(22);
      end process;

    VitalBehavior_DO23  : process
      variable DO23_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO23_zd := DO(23);

    VitalPathDelay01 (
      OutSignal => DO23,
      GlitchData => O_GlitchData,
      OutSignalName => "DO23",
      OutTemp => DO23_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO23, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO23, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(23);
      end process;

    VitalBehavior_DO24  : process
      variable DO24_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO24_zd := DO(24);

    VitalPathDelay01 (
      OutSignal => DO24,
      GlitchData => O_GlitchData,
      OutSignalName => "DO24",
      OutTemp => DO24_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO24, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO24, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(24);
      end process;

    VitalBehavior_DO25  : process
      variable DO25_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO25_zd := DO(25);

    VitalPathDelay01 (
      OutSignal => DO25,
      GlitchData => O_GlitchData,
      OutSignalName => "DO25",
      OutTemp => DO25_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO25, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO25, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(25);
      end process;

    VitalBehavior_DO26  : process
      variable DO26_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO26_zd := DO(26);

    VitalPathDelay01 (
      OutSignal => DO26,
      GlitchData => O_GlitchData,
      OutSignalName => "DO26",
      OutTemp => DO26_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO26, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO26, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(26);
      end process;

    VitalBehavior_DO27  : process
      variable DO27_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO27_zd := DO(27);

    VitalPathDelay01 (
      OutSignal => DO27,
      GlitchData => O_GlitchData,
      OutSignalName => "DO27",
      OutTemp => DO27_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO27, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO27, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(27);
      end process;

    VitalBehavior_DO28  : process
      variable DO28_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO28_zd := DO(28);

    VitalPathDelay01 (
      OutSignal => DO28,
      GlitchData => O_GlitchData,
      OutSignalName => "DO28",
      OutTemp => DO28_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO28, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO28, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(28);
      end process;

    VitalBehavior_DO29  : process
      variable DO29_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO29_zd := DO(29);

    VitalPathDelay01 (
      OutSignal => DO29,
      GlitchData => O_GlitchData,
      OutSignalName => "DO29",
      OutTemp => DO29_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO29, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO29, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(29);
      end process;

    VitalBehavior_DO30  : process
      variable DO30_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO30_zd := DO(30);

    VitalPathDelay01 (
      OutSignal => DO30,
      GlitchData => O_GlitchData,
      OutSignalName => "DO30",
      OutTemp => DO30_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO30, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO30, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(30);
      end process;

    VitalBehavior_DO31  : process
      variable DO31_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO31_zd := DO(31);

    VitalPathDelay01 (
      OutSignal => DO31,
      GlitchData => O_GlitchData,
      OutSignalName => "DO31",
      OutTemp => DO31_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO31, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO31, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(31);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 14,
        WDATA_WIDTH    => 1,
        RADDR_WIDTH    => 9,
        RDATA_WIDTH    => 32,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX1_RX32_VITAL of RAMBFIFO16KA_WX1_RX32 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX1_RX32_VITAL;

----- CELL RAMBFIFO16KA_WX8_RX16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX8_RX16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 2048;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI4_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI4_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI5_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI5_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI6_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI6_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI7_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI7_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI4                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI5                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI6                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI7                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DI4                             : in    STD_ULOGIC;
      DI5                             : in    STD_ULOGIC;
      DI6                             : in    STD_ULOGIC;
      DI7                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      DO4                             : out    STD_ULOGIC;
      DO5                             : out    STD_ULOGIC;
      DO6                             : out    STD_ULOGIC;
      DO7                             : out    STD_ULOGIC;
      DO8                             : out    STD_ULOGIC;
      DO9                             : out    STD_ULOGIC;
      DO10                             : out    STD_ULOGIC;
      DO11                             : out    STD_ULOGIC;
      DO12                             : out    STD_ULOGIC;
      DO13                             : out    STD_ULOGIC;
      DO14                             : out    STD_ULOGIC;
      DO15                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX8_RX16 : entity is FALSE;
end RAMBFIFO16KA_WX8_RX16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX8_RX16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI4_ipd       : std_ulogic := 'X';
      signal DI5_ipd       : std_ulogic := 'X';
      signal DI6_ipd       : std_ulogic := 'X';
      signal DI7_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(7 downto 0);
      signal DO             : std_logic_vector(15 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI7_ipd & DI6_ipd & DI5_ipd & DI4_ipd & DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);
        VitalWireDelay (DI4_ipd, DI4, tipd_DI4);
        VitalWireDelay (DI5_ipd, DI5, tipd_DI5);
        VitalWireDelay (DI6_ipd, DI6, tipd_DI6);
        VitalWireDelay (DI7_ipd, DI7, tipd_DI7);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI4_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI5_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI6_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI7_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI4_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI5_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI6_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI7_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable DO8_zd          : std_ulogic := 'X';
        variable DO9_zd          : std_ulogic := 'X';
        variable DO10_zd          : std_ulogic := 'X';
        variable DO11_zd          : std_ulogic := 'X';
        variable DO12_zd          : std_ulogic := 'X';
        variable DO13_zd          : std_ulogic := 'X';
        variable DO14_zd          : std_ulogic := 'X';
        variable DO15_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI4_WCLK_posedge,
          TimingData              => Tmkr_DI4_WCLK_posedge,
          TestSignal              => DI4_ipd,
          TestSignalName          => "DI4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI4_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI4_WCLK_noedge_posedge,
          HoldLow                 => thold_DI4_WCLK_noedge_posedge,
          HoldHigh                => thold_DI4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI5_WCLK_posedge,
          TimingData              => Tmkr_DI5_WCLK_posedge,
          TestSignal              => DI5_ipd,
          TestSignalName          => "DI5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI5_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI5_WCLK_noedge_posedge,
          HoldLow                 => thold_DI5_WCLK_noedge_posedge,
          HoldHigh                => thold_DI5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI6_WCLK_posedge,
          TimingData              => Tmkr_DI6_WCLK_posedge,
          TestSignal              => DI6_ipd,
          TestSignalName          => "DI6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI6_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI6_WCLK_noedge_posedge,
          HoldLow                 => thold_DI6_WCLK_noedge_posedge,
          HoldHigh                => thold_DI6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI7_WCLK_posedge,
          TimingData              => Tmkr_DI7_WCLK_posedge,
          TestSignal              => DI7_ipd,
          TestSignalName          => "DI7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI7_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI7_WCLK_noedge_posedge,
          HoldLow                 => thold_DI7_WCLK_noedge_posedge,
          HoldHigh                => thold_DI7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX8_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Tviol_DI4_WCLK_posedge or 
                 Tviol_DI5_WCLK_posedge or 
                 Tviol_DI6_WCLK_posedge or 
                 Tviol_DI7_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_DO8  : process
      variable DO8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO8_zd := DO(8);

    VitalPathDelay01 (
      OutSignal => DO8,
      GlitchData => O_GlitchData,
      OutSignalName => "DO8",
      OutTemp => DO8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(8);
      end process;

    VitalBehavior_DO9  : process
      variable DO9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO9_zd := DO(9);

    VitalPathDelay01 (
      OutSignal => DO9,
      GlitchData => O_GlitchData,
      OutSignalName => "DO9",
      OutTemp => DO9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(9);
      end process;

    VitalBehavior_DO10  : process
      variable DO10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO10_zd := DO(10);

    VitalPathDelay01 (
      OutSignal => DO10,
      GlitchData => O_GlitchData,
      OutSignalName => "DO10",
      OutTemp => DO10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(10);
      end process;

    VitalBehavior_DO11  : process
      variable DO11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO11_zd := DO(11);

    VitalPathDelay01 (
      OutSignal => DO11,
      GlitchData => O_GlitchData,
      OutSignalName => "DO11",
      OutTemp => DO11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(11);
      end process;

    VitalBehavior_DO12  : process
      variable DO12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO12_zd := DO(12);

    VitalPathDelay01 (
      OutSignal => DO12,
      GlitchData => O_GlitchData,
      OutSignalName => "DO12",
      OutTemp => DO12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(12);
      end process;

    VitalBehavior_DO13  : process
      variable DO13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO13_zd := DO(13);

    VitalPathDelay01 (
      OutSignal => DO13,
      GlitchData => O_GlitchData,
      OutSignalName => "DO13",
      OutTemp => DO13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(13);
      end process;

    VitalBehavior_DO14  : process
      variable DO14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO14_zd := DO(14);

    VitalPathDelay01 (
      OutSignal => DO14,
      GlitchData => O_GlitchData,
      OutSignalName => "DO14",
      OutTemp => DO14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(14);
      end process;

    VitalBehavior_DO15  : process
      variable DO15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO15_zd := DO(15);

    VitalPathDelay01 (
      OutSignal => DO15,
      GlitchData => O_GlitchData,
      OutSignalName => "DO15",
      OutTemp => DO15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(15);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 11,
        WDATA_WIDTH    => 8,
        RADDR_WIDTH    => 10,
        RDATA_WIDTH    => 16,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX8_RX16_VITAL of RAMBFIFO16KA_WX8_RX16 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX8_RX16_VITAL;

----- CELL RAMBFIFO16KA_WX4_RX16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX4_RX16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 4096;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      DO4                             : out    STD_ULOGIC;
      DO5                             : out    STD_ULOGIC;
      DO6                             : out    STD_ULOGIC;
      DO7                             : out    STD_ULOGIC;
      DO8                             : out    STD_ULOGIC;
      DO9                             : out    STD_ULOGIC;
      DO10                             : out    STD_ULOGIC;
      DO11                             : out    STD_ULOGIC;
      DO12                             : out    STD_ULOGIC;
      DO13                             : out    STD_ULOGIC;
      DO14                             : out    STD_ULOGIC;
      DO15                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX4_RX16 : entity is FALSE;
end RAMBFIFO16KA_WX4_RX16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX4_RX16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(3 downto 0);
      signal DO             : std_logic_vector(15 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable DO8_zd          : std_ulogic := 'X';
        variable DO9_zd          : std_ulogic := 'X';
        variable DO10_zd          : std_ulogic := 'X';
        variable DO11_zd          : std_ulogic := 'X';
        variable DO12_zd          : std_ulogic := 'X';
        variable DO13_zd          : std_ulogic := 'X';
        variable DO14_zd          : std_ulogic := 'X';
        variable DO15_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_DO8  : process
      variable DO8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO8_zd := DO(8);

    VitalPathDelay01 (
      OutSignal => DO8,
      GlitchData => O_GlitchData,
      OutSignalName => "DO8",
      OutTemp => DO8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(8);
      end process;

    VitalBehavior_DO9  : process
      variable DO9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO9_zd := DO(9);

    VitalPathDelay01 (
      OutSignal => DO9,
      GlitchData => O_GlitchData,
      OutSignalName => "DO9",
      OutTemp => DO9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(9);
      end process;

    VitalBehavior_DO10  : process
      variable DO10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO10_zd := DO(10);

    VitalPathDelay01 (
      OutSignal => DO10,
      GlitchData => O_GlitchData,
      OutSignalName => "DO10",
      OutTemp => DO10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(10);
      end process;

    VitalBehavior_DO11  : process
      variable DO11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO11_zd := DO(11);

    VitalPathDelay01 (
      OutSignal => DO11,
      GlitchData => O_GlitchData,
      OutSignalName => "DO11",
      OutTemp => DO11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(11);
      end process;

    VitalBehavior_DO12  : process
      variable DO12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO12_zd := DO(12);

    VitalPathDelay01 (
      OutSignal => DO12,
      GlitchData => O_GlitchData,
      OutSignalName => "DO12",
      OutTemp => DO12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(12);
      end process;

    VitalBehavior_DO13  : process
      variable DO13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO13_zd := DO(13);

    VitalPathDelay01 (
      OutSignal => DO13,
      GlitchData => O_GlitchData,
      OutSignalName => "DO13",
      OutTemp => DO13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(13);
      end process;

    VitalBehavior_DO14  : process
      variable DO14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO14_zd := DO(14);

    VitalPathDelay01 (
      OutSignal => DO14,
      GlitchData => O_GlitchData,
      OutSignalName => "DO14",
      OutTemp => DO14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(14);
      end process;

    VitalBehavior_DO15  : process
      variable DO15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO15_zd := DO(15);

    VitalPathDelay01 (
      OutSignal => DO15,
      GlitchData => O_GlitchData,
      OutSignalName => "DO15",
      OutTemp => DO15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(15);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 12,
        WDATA_WIDTH    => 4,
        RADDR_WIDTH    => 10,
        RDATA_WIDTH    => 16,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX4_RX16_VITAL of RAMBFIFO16KA_WX4_RX16 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX4_RX16_VITAL;

----- CELL RAMBFIFO16KA_WX2_RX16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX2_RX16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 8192;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      DO4                             : out    STD_ULOGIC;
      DO5                             : out    STD_ULOGIC;
      DO6                             : out    STD_ULOGIC;
      DO7                             : out    STD_ULOGIC;
      DO8                             : out    STD_ULOGIC;
      DO9                             : out    STD_ULOGIC;
      DO10                             : out    STD_ULOGIC;
      DO11                             : out    STD_ULOGIC;
      DO12                             : out    STD_ULOGIC;
      DO13                             : out    STD_ULOGIC;
      DO14                             : out    STD_ULOGIC;
      DO15                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX2_RX16 : entity is FALSE;
end RAMBFIFO16KA_WX2_RX16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX2_RX16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(1 downto 0);
      signal DO             : std_logic_vector(15 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable DO8_zd          : std_ulogic := 'X';
        variable DO9_zd          : std_ulogic := 'X';
        variable DO10_zd          : std_ulogic := 'X';
        variable DO11_zd          : std_ulogic := 'X';
        variable DO12_zd          : std_ulogic := 'X';
        variable DO13_zd          : std_ulogic := 'X';
        variable DO14_zd          : std_ulogic := 'X';
        variable DO15_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_DO8  : process
      variable DO8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO8_zd := DO(8);

    VitalPathDelay01 (
      OutSignal => DO8,
      GlitchData => O_GlitchData,
      OutSignalName => "DO8",
      OutTemp => DO8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(8);
      end process;

    VitalBehavior_DO9  : process
      variable DO9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO9_zd := DO(9);

    VitalPathDelay01 (
      OutSignal => DO9,
      GlitchData => O_GlitchData,
      OutSignalName => "DO9",
      OutTemp => DO9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(9);
      end process;

    VitalBehavior_DO10  : process
      variable DO10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO10_zd := DO(10);

    VitalPathDelay01 (
      OutSignal => DO10,
      GlitchData => O_GlitchData,
      OutSignalName => "DO10",
      OutTemp => DO10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(10);
      end process;

    VitalBehavior_DO11  : process
      variable DO11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO11_zd := DO(11);

    VitalPathDelay01 (
      OutSignal => DO11,
      GlitchData => O_GlitchData,
      OutSignalName => "DO11",
      OutTemp => DO11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(11);
      end process;

    VitalBehavior_DO12  : process
      variable DO12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO12_zd := DO(12);

    VitalPathDelay01 (
      OutSignal => DO12,
      GlitchData => O_GlitchData,
      OutSignalName => "DO12",
      OutTemp => DO12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(12);
      end process;

    VitalBehavior_DO13  : process
      variable DO13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO13_zd := DO(13);

    VitalPathDelay01 (
      OutSignal => DO13,
      GlitchData => O_GlitchData,
      OutSignalName => "DO13",
      OutTemp => DO13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(13);
      end process;

    VitalBehavior_DO14  : process
      variable DO14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO14_zd := DO(14);

    VitalPathDelay01 (
      OutSignal => DO14,
      GlitchData => O_GlitchData,
      OutSignalName => "DO14",
      OutTemp => DO14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(14);
      end process;

    VitalBehavior_DO15  : process
      variable DO15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO15_zd := DO(15);

    VitalPathDelay01 (
      OutSignal => DO15,
      GlitchData => O_GlitchData,
      OutSignalName => "DO15",
      OutTemp => DO15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(15);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 13,
        WDATA_WIDTH    => 2,
        RADDR_WIDTH    => 10,
        RDATA_WIDTH    => 16,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX2_RX16_VITAL of RAMBFIFO16KA_WX2_RX16 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX2_RX16_VITAL;

----- CELL RAMBFIFO16KA_WX1_RX16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX1_RX16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 16384;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO8                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO9                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO10                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO11                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO12                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO13                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO14                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO15                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      DO4                             : out    STD_ULOGIC;
      DO5                             : out    STD_ULOGIC;
      DO6                             : out    STD_ULOGIC;
      DO7                             : out    STD_ULOGIC;
      DO8                             : out    STD_ULOGIC;
      DO9                             : out    STD_ULOGIC;
      DO10                             : out    STD_ULOGIC;
      DO11                             : out    STD_ULOGIC;
      DO12                             : out    STD_ULOGIC;
      DO13                             : out    STD_ULOGIC;
      DO14                             : out    STD_ULOGIC;
      DO15                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX1_RX16 : entity is FALSE;
end RAMBFIFO16KA_WX1_RX16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX1_RX16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_logic_vector(0 downto 0) := (others => 'X');
      signal DI             : std_logic_vector(0 downto 0);
      signal DO             : std_logic_vector(15 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd(0), DI0, tipd_DI0);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable DO8_zd          : std_ulogic := 'X';
        variable DO9_zd          : std_ulogic := 'X';
        variable DO10_zd          : std_ulogic := 'X';
        variable DO11_zd          : std_ulogic := 'X';
        variable DO12_zd          : std_ulogic := 'X';
        variable DO13_zd          : std_ulogic := 'X';
        variable DO14_zd          : std_ulogic := 'X';
        variable DO15_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_DO8  : process
      variable DO8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO8_zd := DO(8);

    VitalPathDelay01 (
      OutSignal => DO8,
      GlitchData => O_GlitchData,
      OutSignalName => "DO8",
      OutTemp => DO8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(8);
      end process;

    VitalBehavior_DO9  : process
      variable DO9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO9_zd := DO(9);

    VitalPathDelay01 (
      OutSignal => DO9,
      GlitchData => O_GlitchData,
      OutSignalName => "DO9",
      OutTemp => DO9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(9);
      end process;

    VitalBehavior_DO10  : process
      variable DO10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO10_zd := DO(10);

    VitalPathDelay01 (
      OutSignal => DO10,
      GlitchData => O_GlitchData,
      OutSignalName => "DO10",
      OutTemp => DO10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(10);
      end process;

    VitalBehavior_DO11  : process
      variable DO11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO11_zd := DO(11);

    VitalPathDelay01 (
      OutSignal => DO11,
      GlitchData => O_GlitchData,
      OutSignalName => "DO11",
      OutTemp => DO11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(11);
      end process;

    VitalBehavior_DO12  : process
      variable DO12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO12_zd := DO(12);

    VitalPathDelay01 (
      OutSignal => DO12,
      GlitchData => O_GlitchData,
      OutSignalName => "DO12",
      OutTemp => DO12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(12);
      end process;

    VitalBehavior_DO13  : process
      variable DO13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO13_zd := DO(13);

    VitalPathDelay01 (
      OutSignal => DO13,
      GlitchData => O_GlitchData,
      OutSignalName => "DO13",
      OutTemp => DO13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(13);
      end process;

    VitalBehavior_DO14  : process
      variable DO14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO14_zd := DO(14);

    VitalPathDelay01 (
      OutSignal => DO14,
      GlitchData => O_GlitchData,
      OutSignalName => "DO14",
      OutTemp => DO14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(14);
      end process;

    VitalBehavior_DO15  : process
      variable DO15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO15_zd := DO(15);

    VitalPathDelay01 (
      OutSignal => DO15,
      GlitchData => O_GlitchData,
      OutSignalName => "DO15",
      OutTemp => DO15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(15);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 14,
        WDATA_WIDTH    => 1,
        RADDR_WIDTH    => 10,
        RDATA_WIDTH    => 16,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX1_RX16_VITAL of RAMBFIFO16KA_WX1_RX16 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX1_RX16_VITAL;

----- CELL RAMBFIFO16KA_WX4_RX8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX4_RX8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 4096;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI2_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI2_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI3_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI3_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI2                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI3                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DI2                             : in    STD_ULOGIC;
      DI3                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      DO4                             : out    STD_ULOGIC;
      DO5                             : out    STD_ULOGIC;
      DO6                             : out    STD_ULOGIC;
      DO7                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX4_RX8 : entity is FALSE;
end RAMBFIFO16KA_WX4_RX8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX4_RX8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI2_ipd       : std_ulogic := 'X';
      signal DI3_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(3 downto 0);
      signal DO             : std_logic_vector(7 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI3_ipd & DI2_ipd & DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);
        VitalWireDelay (DI2_ipd, DI2, tipd_DI2);
        VitalWireDelay (DI3_ipd, DI3, tipd_DI3);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI2_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI3_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI2_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI3_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI2_WCLK_posedge,
          TimingData              => Tmkr_DI2_WCLK_posedge,
          TestSignal              => DI2_ipd,
          TestSignalName          => "DI2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI2_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI2_WCLK_noedge_posedge,
          HoldLow                 => thold_DI2_WCLK_noedge_posedge,
          HoldHigh                => thold_DI2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI3_WCLK_posedge,
          TimingData              => Tmkr_DI3_WCLK_posedge,
          TestSignal              => DI3_ipd,
          TestSignalName          => "DI3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI3_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI3_WCLK_noedge_posedge,
          HoldLow                 => thold_DI3_WCLK_noedge_posedge,
          HoldHigh                => thold_DI3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX4_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Tviol_DI2_WCLK_posedge or 
                 Tviol_DI3_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 12,
        WDATA_WIDTH    => 4,
        RADDR_WIDTH    => 11,
        RDATA_WIDTH    => 8,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX4_RX8_VITAL of RAMBFIFO16KA_WX4_RX8 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX4_RX8_VITAL;

----- CELL RAMBFIFO16KA_WX2_RX8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX2_RX8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 8192;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      DO4                             : out    STD_ULOGIC;
      DO5                             : out    STD_ULOGIC;
      DO6                             : out    STD_ULOGIC;
      DO7                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX2_RX8 : entity is FALSE;
end RAMBFIFO16KA_WX2_RX8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX2_RX8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(1 downto 0);
      signal DO             : std_logic_vector(7 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 13,
        WDATA_WIDTH    => 2,
        RADDR_WIDTH    => 11,
        RDATA_WIDTH    => 8,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX2_RX8_VITAL of RAMBFIFO16KA_WX2_RX8 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX2_RX8_VITAL;

----- CELL RAMBFIFO16KA_WX1_RX8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX1_RX8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 16384;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO4                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO5                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO6                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO7                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      DO4                             : out    STD_ULOGIC;
      DO5                             : out    STD_ULOGIC;
      DO6                             : out    STD_ULOGIC;
      DO7                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX1_RX8 : entity is FALSE;
end RAMBFIFO16KA_WX1_RX8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX1_RX8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_logic_vector(0 downto 0) := (others => 'X');
      signal DI             : std_logic_vector(0 downto 0);
      signal DO             : std_logic_vector(7 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd(0), DI0, tipd_DI0);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable DO4_zd          : std_ulogic := 'X';
        variable DO5_zd          : std_ulogic := 'X';
        variable DO6_zd          : std_ulogic := 'X';
        variable DO7_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_DO4  : process
      variable DO4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO4_zd := DO(4);

    VitalPathDelay01 (
      OutSignal => DO4,
      GlitchData => O_GlitchData,
      OutSignalName => "DO4",
      OutTemp => DO4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(4);
      end process;

    VitalBehavior_DO5  : process
      variable DO5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO5_zd := DO(5);

    VitalPathDelay01 (
      OutSignal => DO5,
      GlitchData => O_GlitchData,
      OutSignalName => "DO5",
      OutTemp => DO5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(5);
      end process;

    VitalBehavior_DO6  : process
      variable DO6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO6_zd := DO(6);

    VitalPathDelay01 (
      OutSignal => DO6,
      GlitchData => O_GlitchData,
      OutSignalName => "DO6",
      OutTemp => DO6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(6);
      end process;

    VitalBehavior_DO7  : process
      variable DO7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO7_zd := DO(7);

    VitalPathDelay01 (
      OutSignal => DO7,
      GlitchData => O_GlitchData,
      OutSignalName => "DO7",
      OutTemp => DO7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(7);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 14,
        WDATA_WIDTH    => 1,
        RADDR_WIDTH    => 11,
        RDATA_WIDTH    => 8,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX1_RX8_VITAL of RAMBFIFO16KA_WX1_RX8 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX1_RX8_VITAL;

----- CELL RAMBFIFO16KA_WX2_RX4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX2_RX4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 8192;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;
      tsetup_DI1_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI1_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DI1                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DI1                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX2_RX4 : entity is FALSE;
end RAMBFIFO16KA_WX2_RX4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX2_RX4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_ulogic := 'X';
      signal DI1_ipd       : std_ulogic := 'X';
      signal DI             : std_logic_vector(1 downto 0);
      signal DO             : std_logic_vector(3 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI1_ipd & DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd, DI0, tipd_DI0);
        VitalWireDelay (DI1_ipd, DI1, tipd_DI1);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_DI1_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DI1_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI1_WCLK_posedge,
          TimingData              => Tmkr_DI1_WCLK_posedge,
          TestSignal              => DI1_ipd,
          TestSignalName          => "DI1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI1_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI1_WCLK_noedge_posedge,
          HoldLow                 => thold_DI1_WCLK_noedge_posedge,
          HoldHigh                => thold_DI1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX2_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Tviol_DI1_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 13,
        WDATA_WIDTH    => 2,
        RADDR_WIDTH    => 12,
        RDATA_WIDTH    => 4,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX2_RX4_VITAL of RAMBFIFO16KA_WX2_RX4 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX2_RX4_VITAL;

----- CELL RAMBFIFO16KA_WX1_RX4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX1_RX4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 16384;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO2                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO3                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      DO2                             : out    STD_ULOGIC;
      DO3                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX1_RX4 : entity is FALSE;
end RAMBFIFO16KA_WX1_RX4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX1_RX4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_logic_vector(0 downto 0) := (others => 'X');
      signal DI             : std_logic_vector(0 downto 0);
      signal DO             : std_logic_vector(3 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd(0), DI0, tipd_DI0);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable DO2_zd          : std_ulogic := 'X';
        variable DO3_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_DO2  : process
      variable DO2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO2_zd := DO(2);

    VitalPathDelay01 (
      OutSignal => DO2,
      GlitchData => O_GlitchData,
      OutSignalName => "DO2",
      OutTemp => DO2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(2);
      end process;

    VitalBehavior_DO3  : process
      variable DO3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO3_zd := DO(3);

    VitalPathDelay01 (
      OutSignal => DO3,
      GlitchData => O_GlitchData,
      OutSignalName => "DO3",
      OutTemp => DO3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(3);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 14,
        WDATA_WIDTH    => 1,
        RADDR_WIDTH    => 12,
        RDATA_WIDTH    => 4,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX1_RX4_VITAL of RAMBFIFO16KA_WX1_RX4 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX1_RX4_VITAL;

----- CELL RAMBFIFO16KA_WX1_RX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity RAMBFIFO16KA_WX1_RX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      FIFO_FULL_FLAG     : integer  := 16384;
      FIFO_AMFULL_FLAG   : integer  := 1;
      FIFO_AMEMPTY_FLAG  : integer  := 1;

      tpd_RCLK_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_DO0                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_DO1                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_WCLK_FULL                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_AMFULL                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tpd_RCLK_EMPTY                     :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_AMEMPTY                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);


      tsetup_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;


      tsetup_RE_RCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_RE_RCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;

      tsetup_DI0_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_DI0_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RPRST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RPRST_RCLK_posedge_posedge    :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tpw_RPRST_posedge                  :	VitalDelayType   := 2.0 ns;

      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_FULLIN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EMPTYIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RPRST                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DI0                           :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      WE                              :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      RE                              :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      FULLIN                          :	in    STD_ULOGIC;
      EMPTYIN                         :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      RPRST                           :	in    STD_ULOGIC;
      DI0                             : in    STD_ULOGIC;
      DO0                             : out    STD_ULOGIC;
      DO1                             : out    STD_ULOGIC;
      FULL                            :  out    STD_ULOGIC;
      EMPTY                           : out    STD_ULOGIC;
      AMFULL                          : out    STD_ULOGIC;
      AMEMPTY                         : out    STD_ULOGIC);

attribute VITAL_LEVEL0 of RAMBFIFO16KA_WX1_RX2 : entity is FALSE;
end RAMBFIFO16KA_WX1_RX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;

architecture VITAL of RAMBFIFO16KA_WX1_RX2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

  component SC_FIFO_V2_16K
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
  	TERMINAL_COUNT : integer  := 511; 
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        MEM_INIT_FILE  : string  := "mem_init_file"
         );
  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
        ); 
end component ;

      signal WE_ipd        : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';


      signal RE_ipd        : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';

      signal FULLIN_ipd    : std_ulogic := 'X';
      signal EMPTYIN_ipd   : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';
      signal RPRST_ipd     : std_ulogic := 'X';

      signal DI0_ipd       : std_logic_vector(0 downto 0) := (others => 'X');
      signal DI             : std_logic_vector(0 downto 0);
      signal DO             : std_logic_vector(1 downto 0);
      signal FULL_sig       : std_logic;
      signal EMPTY_sig      : std_logic;
      signal AMFULL_sig     : std_logic;
      signal AMEMPTY_sig    : std_logic;

begin

      DI <= DI0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);

        VitalWireDelay (RE_ipd, RE, tipd_RE);
        VitalWireDelay (RCLK_Ipd, RCLK, tipd_RCLK);

        VitalWireDelay (FULLIN_ipd, FULLIN, tipd_FULLIN);
        VitalWireDelay (EMPTYIN_ipd, EMPTYIN, tipd_EMPTYIN);

        VitalWireDelay (RST_ipd, RST, tipd_RST);
        VitalWireDelay (RPRST_ipd, RPRST, tipd_RPRST);

        VitalWireDelay (DI0_ipd(0), DI0, tipd_DI0);

      end block;

      --------------------
      -- FIFO Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';
        variable Tviol_RE_RCLK_posedge      : std_ulogic  := '0';

        variable Tviol_DI0_WCLK_posedge     : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';
        variable Tviol_RPRST_RCLK_posedge_posedge : std_ulogic  := '0';

        variable Tmkr_WE_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RE_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DI0_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RST_RCLK_posedge_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RPRST_RCLK_posedge_posedge : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST        : std_ulogic := '0';
        variable PInfo_RST        : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RPRST      : std_ulogic := '0';
        variable PInfo_RPRST      : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';
        variable DO0_zd          : std_ulogic := 'X';
        variable DO1_zd          : std_ulogic := 'X';
        variable FULL_zd         : std_ulogic := 'X';
        variable EMPTY_zd        : std_ulogic := 'X';
        variable AMFULL_zd       : std_ulogic := 'X';
        variable AMEMPTY_zd      : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RE_RCLK_posedge,
          TimingData              => Tmkr_RE_RCLK_posedge,
          TestSignal              => RE_ipd,
          TestSignalName          => "RE",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RE_RCLK_noedge_posedge,
          SetupLow                => tsetup_RE_RCLK_noedge_posedge,
          HoldLow                 => thold_RE_RCLK_noedge_posedge,
          HoldHigh                => thold_Re_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DI0_WCLK_posedge,
          TimingData              => Tmkr_DI0_WCLK_posedge,
          TestSignal              => DI0_ipd,
          TestSignalName          => "DI0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DI0_WCLK_noedge_posedge,
          SetupLow                => tsetup_DI0_WCLK_noedge_posedge,
          HoldLow                 => thold_DI0_WCLK_noedge_posedge,
          HoldHigh                => thold_DI0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RPRST,
          PeriodData              => PInfo_RPRST,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RPRST_posedge,
          PulseWidthLow           => tpw_RPRST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMBFIFO16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RPRST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RPRST_RCLK_posedge_posedge,
          TestSignal              => RPRST_ipd,
          TestSignalName          => "RPRST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RPRST_RCLK_posedge_posedge,
          Removal                 => thold_RPRST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMBFIFO16KA_WX1_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WE_WCLK_posedge or 
                 Tviol_RE_RCLK_posedge or 
                 Tviol_DI0_WCLK_posedge or 
                 Pviol_WCLK or Pviol_RCLK or 
                 Pviol_RST or Pviol_RPRST or 
                 Tviol_RST_RCLK_posedge_posedge or 
                 Tviol_RPRST_RCLK_posedge_posedge;

    -------------------------
    --  Functionality Section
    -------------------------

      wait on WE_ipd, WCLK_ipd, RE_ipd, RCLK_ipd, FULLIN_ipd, EMPTYIN_ipd, RST_ipd, RPRST_ipd, DI;

      end process VITALBehavior;

    VitalBehavior_DO0  : process
      variable DO0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO0_zd := DO(0);

    VitalPathDelay01 (
      OutSignal => DO0,
      GlitchData => O_GlitchData,
      OutSignalName => "DO0",
      OutTemp => DO0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(0);
      end process;

    VitalBehavior_DO1  : process
      variable DO1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      DO1_zd := DO(1);

    VitalPathDelay01 (
      OutSignal => DO1,
      GlitchData => O_GlitchData,
      OutSignalName => "DO1",
      OutTemp => DO1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_DO1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_DO1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on DO(1);
      end process;

    VitalBehavior_FULL : process
      variable FULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      FULL_zd := FULL_sig;

    VitalPathDelay01 (
      OutSignal => FULL,
      GlitchData => O_GlitchData,
      OutSignalName => "FULL",
      OutTemp => FULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_FULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on FULL_sig;
      end process;

    VitalBehavior_AMFULL : process
      variable AMFULL_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMFULL_zd := AMFULL_sig;

    VitalPathDelay01 (
      OutSignal => AMFULL,
      GlitchData => O_GlitchData,
      OutSignalName => "AMFULL",
      OutTemp => AMFULL_zd,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_AMFULL, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMFULL_sig;
      end process;

    VitalBehavior_EMPTY : process
      variable EMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      EMPTY_zd := EMPTY_sig;

    VitalPathDelay01 (
      OutSignal => EMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "EMPTY",
      OutTemp => EMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_EMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on EMPTY_sig;
      end process;

    VitalBehavior_AMEMPTY : process
      variable AMEMPTY_zd	  : std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      AMEMPTY_zd := AMEMPTY_sig;

    VitalPathDelay01 (
      OutSignal => AMEMPTY,
      GlitchData => O_GlitchData,
      OutSignalName => "AMEMPTY",
      OutTemp => AMEMPTY_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_AMEMPTY, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on AMEMPTY_sig;
      end process;

  FIFO_INST: SC_FIFO_V2_16K 
  generic map (
        WADDR_WIDTH    => 14,
        WDATA_WIDTH    => 1,
        RADDR_WIDTH    => 13,
        RDATA_WIDTH    => 2,
  	TERMINAL_COUNT => FIFO_FULL_FLAG - 1,
        ALMOST_FULL_X  => FIFO_AMFULL_FLAG,
        ALMOST_EMPTY_Y => FIFO_AMEMPTY_FLAG,
        MEM_INIT_FLAG  => 0,  
        MEM_INIT_FILE  => open)
  port map (
        WE     => WE_ipd, 
        WCLK   => WCLK_ipd,
        RST    => RST_ipd,
        RPRST  => RPRST_ipd,
        RE     => RE_ipd, 
        RCLK   => RCLK_ipd, 
        FULLIN =>  FULLIN_ipd,
        EMPTYIN => EMPTYIN_ipd,
        DI     => DI,
        FULL   => FULL_sig,
        EMPTY  => EMPTY_sig, 
        AMFULL => AMFULL_sig,
        AMEMPTY => AMEMPTY_sig, 
        DO  => DO      ); 

end VITAL;

configuration CFG_RAMBFIFO16KA_WX1_RX2_VITAL of RAMBFIFO16KA_WX1_RX2 is
   for VITAL
   end for;
end CFG_RAMBFIFO16KA_WX1_RX2_VITAL;

----- CELL RAMB16K_WX16_RX1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX16_RX1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD11_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD11_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD12_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD12_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD13_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD13_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RAD12                            :	in    STD_ULOGIC;
      RAD13                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16K_WX16_RX1 : entity is FALSE;
end RAMB16K_WX16_RX1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX16_RX1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';
      signal RAD12_ipd      : std_ulogic := 'X';
      signal RAD13_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (15 downto 0);
 	signal WAD : std_logic_vector (9 downto 0);
 	signal RAD : std_logic_vector (13 downto 0);
	signal RD  : std_logic_vector (0 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD13_ipd & RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);
        VitalWireDelay (RAD13_ipd, RAD13, tipd_RAD13);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD11_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD12_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD13_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD11_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD12_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD13_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;


        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD11_RCLK_posedge,
          TimingData              => Tmkr_RAD11_RCLK_posedge,
          TestSignal              => RAD11_ipd,
          TestSignalName          => "RAD11",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD11_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD11_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD11_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD11_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD12_RCLK_posedge,
          TimingData              => Tmkr_RAD12_RCLK_posedge,
          TestSignal              => RAD12_ipd,
          TestSignalName          => "RAD12",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD12_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD12_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD12_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD12_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD13_RCLK_posedge,
          TimingData              => Tmkr_RAD13_RCLK_posedge,
          TestSignal              => RAD13_ipd,
          TestSignalName          => "RAD13",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD13_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD13_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD13_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD13_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or
                 Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or
                 Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or
                 Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or
                 Tviol_WD15_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or
                 Tviol_RAD1_RCLK_posedge or
                 Tviol_RAD2_RCLK_posedge or
                 Tviol_RAD3_RCLK_posedge or
                 Tviol_RAD4_RCLK_posedge or
                 Tviol_RAD5_RCLK_posedge or
                 Tviol_RAD6_RCLK_posedge or
                 Tviol_RAD7_RCLK_posedge or
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RAD9_RCLK_posedge or
                 Tviol_RAD10_RCLK_posedge or
                 Tviol_RAD11_RCLK_posedge or
                 Tviol_RAD12_RCLK_posedge or
                 Tviol_RAD13_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 10,
		WDATA_WIDTH    => 16,
		RADDR_WIDTH    => 14,
		RDATA_WIDTH    => 1,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16K_WX16_RX1_VITAL of RAMB16K_WX16_RX1 is
   for VITAL
   end for;
end CFG_RAMB16K_WX16_RX1_VITAL;


----- CELL RAMB16K_WX16_RX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX16_RX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD11_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD11_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD12_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD12_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RAD12                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16K_WX16_RX2 : entity is FALSE;
end RAMB16K_WX16_RX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX16_RX2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';
      signal RAD12_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (15 downto 0);
 	signal WAD : std_logic_vector (9 downto 0);
 	signal RAD : std_logic_vector (12 downto 0);
	signal RD  : std_logic_vector (1 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD11_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD12_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD11_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD12_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;


        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD11_RCLK_posedge,
          TimingData              => Tmkr_RAD11_RCLK_posedge,
          TestSignal              => RAD11_ipd,
          TestSignalName          => "RAD11",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD11_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD11_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD11_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD11_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD12_RCLK_posedge,
          TimingData              => Tmkr_RAD12_RCLK_posedge,
          TestSignal              => RAD12_ipd,
          TestSignalName          => "RAD12",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD12_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD12_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD12_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD12_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or
                 Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or
                 Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or
                 Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or
                 Tviol_WD15_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or
                 Tviol_RAD1_RCLK_posedge or
                 Tviol_RAD2_RCLK_posedge or
                 Tviol_RAD3_RCLK_posedge or
                 Tviol_RAD4_RCLK_posedge or
                 Tviol_RAD5_RCLK_posedge or
                 Tviol_RAD6_RCLK_posedge or
                 Tviol_RAD7_RCLK_posedge or
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RAD9_RCLK_posedge or
                 Tviol_RAD10_RCLK_posedge or
                 Tviol_RAD11_RCLK_posedge or
                 Tviol_RAD12_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 10,
		WDATA_WIDTH    => 16,
		RADDR_WIDTH    => 13,
		RDATA_WIDTH    => 2,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16K_WX16_RX2_VITAL of RAMB16K_WX16_RX2 is
   for VITAL
   end for;
end CFG_RAMB16K_WX16_RX2_VITAL;


----- CELL RAMB16K_WX16_RX4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX16_RX4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD11_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD11_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC;
      RD2                            :	out    STD_ULOGIC;
      RD3                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16K_WX16_RX4 : entity is FALSE;
end RAMB16K_WX16_RX4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX16_RX4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (15 downto 0);
 	signal WAD : std_logic_vector (9 downto 0);
 	signal RAD : std_logic_vector (11 downto 0);
	signal RD  : std_logic_vector (3 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD11_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD11_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;


        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD11_RCLK_posedge,
          TimingData              => Tmkr_RAD11_RCLK_posedge,
          TestSignal              => RAD11_ipd,
          TestSignalName          => "RAD11",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD11_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD11_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD11_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD11_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or
                 Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or
                 Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or
                 Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or
                 Tviol_WD15_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or
                 Tviol_RAD1_RCLK_posedge or
                 Tviol_RAD2_RCLK_posedge or
                 Tviol_RAD3_RCLK_posedge or
                 Tviol_RAD4_RCLK_posedge or
                 Tviol_RAD5_RCLK_posedge or
                 Tviol_RAD6_RCLK_posedge or
                 Tviol_RAD7_RCLK_posedge or
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RAD9_RCLK_posedge or
                 Tviol_RAD10_RCLK_posedge or
                 Tviol_RAD11_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 10,
		WDATA_WIDTH    => 16,
		RADDR_WIDTH    => 12,
		RDATA_WIDTH    => 4,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16K_WX16_RX4_VITAL of RAMB16K_WX16_RX4 is
   for VITAL
   end for;
end CFG_RAMB16K_WX16_RX4_VITAL;


----- CELL RAMB16K_WX16_RX8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX16_RX8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD4                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD5                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD6                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD7                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC;
      RD2                            :	out    STD_ULOGIC;
      RD3                            :	out    STD_ULOGIC;
      RD4                            :	out    STD_ULOGIC;
      RD5                            :	out    STD_ULOGIC;
      RD6                            :	out    STD_ULOGIC;
      RD7                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16K_WX16_RX8 : entity is FALSE;
end RAMB16K_WX16_RX8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX16_RX8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (15 downto 0);
 	signal WAD : std_logic_vector (9 downto 0);
 	signal RAD : std_logic_vector (10 downto 0);
	signal RD  : std_logic_vector (7 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;


        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or
                 Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or
                 Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or
                 Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or
                 Tviol_WD15_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or
                 Tviol_RAD1_RCLK_posedge or
                 Tviol_RAD2_RCLK_posedge or
                 Tviol_RAD3_RCLK_posedge or
                 Tviol_RAD4_RCLK_posedge or
                 Tviol_RAD5_RCLK_posedge or
                 Tviol_RAD6_RCLK_posedge or
                 Tviol_RAD7_RCLK_posedge or
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RAD9_RCLK_posedge or
                 Tviol_RAD10_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 10,
		WDATA_WIDTH    => 16,
		RADDR_WIDTH    => 11,
		RDATA_WIDTH    => 8,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16K_WX16_RX8_VITAL of RAMB16K_WX16_RX8 is
   for VITAL
   end for;
end CFG_RAMB16K_WX16_RX8_VITAL;


----- CELL RAMB16K_WX2_RX1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX2_RX1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD11_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD11_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD12_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD12_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD13_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD13_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                            :	in    STD_ULOGIC;
      WAD11                            :	in    STD_ULOGIC;
      WAD12                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RAD12                            :	in    STD_ULOGIC;
      RAD13                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16K_WX2_RX1 : entity is FALSE;
end RAMB16K_WX2_RX1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX2_RX1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd      : std_ulogic := 'X';
      signal WAD11_ipd      : std_ulogic := 'X';
      signal WAD12_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';
      signal RAD12_ipd      : std_ulogic := 'X';
      signal RAD13_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (1 downto 0);
 	signal WAD : std_logic_vector (12 downto 0);
 	signal RAD : std_logic_vector (13 downto 0);
	signal RD  : std_logic_vector (0 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD1_ipd & WD0_ipd;
	WAD <= WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD13_ipd & RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);
        VitalWireDelay (RAD13_ipd, RAD13, tipd_RAD13);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD11_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD12_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD13_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD11_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD12_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD13_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;


        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD12_WCLK_posedge,
          TimingData              => Tmkr_WAD12_WCLK_posedge,
          TestSignal              => WAD12_ipd,
          TestSignalName          => "WAD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD11_RCLK_posedge,
          TimingData              => Tmkr_RAD11_RCLK_posedge,
          TestSignal              => RAD11_ipd,
          TestSignalName          => "RAD11",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD11_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD11_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD11_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD11_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD12_RCLK_posedge,
          TimingData              => Tmkr_RAD12_RCLK_posedge,
          TestSignal              => RAD12_ipd,
          TestSignalName          => "RAD12",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD12_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD12_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD12_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD12_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD13_RCLK_posedge,
          TimingData              => Tmkr_RAD13_RCLK_posedge,
          TestSignal              => RAD13_ipd,
          TestSignalName          => "RAD13",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD13_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD13_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD13_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD13_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WAD10_WCLK_posedge or
                 Tviol_WAD11_WCLK_posedge or
                 Tviol_WAD12_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or
                 Tviol_RAD1_RCLK_posedge or
                 Tviol_RAD2_RCLK_posedge or
                 Tviol_RAD3_RCLK_posedge or
                 Tviol_RAD4_RCLK_posedge or
                 Tviol_RAD5_RCLK_posedge or
                 Tviol_RAD6_RCLK_posedge or
                 Tviol_RAD7_RCLK_posedge or
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RAD9_RCLK_posedge or
                 Tviol_RAD10_RCLK_posedge or
                 Tviol_RAD11_RCLK_posedge or
                 Tviol_RAD12_RCLK_posedge or
                 Tviol_RAD13_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 13,
		WDATA_WIDTH    => 2,
		RADDR_WIDTH    => 14,
		RDATA_WIDTH    => 1,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16K_WX2_RX1_VITAL of RAMB16K_WX2_RX1 is
   for VITAL
   end for;
end CFG_RAMB16K_WX2_RX1_VITAL;


----- CELL RAMB16K_WX32_RX1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX32_RX1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD16_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD16_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD17_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD17_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD18_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD18_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD19_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD19_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD20_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD20_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD21_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD21_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD22_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD22_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD23_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD23_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD24_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD24_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD25_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD25_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD26_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD26_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD27_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD27_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD28_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD28_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD29_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD29_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD30_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD30_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD31_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD31_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD11_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD11_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD12_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD12_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD13_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD13_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD16                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD17                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD18                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD19                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD20                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD21                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD22                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD23                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD24                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD25                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD26                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD27                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD28                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD29                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD30                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD31                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WD16                            :	in    STD_ULOGIC;
      WD17                            :	in    STD_ULOGIC;
      WD18                            :	in    STD_ULOGIC;
      WD19                            :	in    STD_ULOGIC;
      WD20                            :	in    STD_ULOGIC;
      WD21                            :	in    STD_ULOGIC;
      WD22                            :	in    STD_ULOGIC;
      WD23                            :	in    STD_ULOGIC;
      WD24                            :	in    STD_ULOGIC;
      WD25                            :	in    STD_ULOGIC;
      WD26                            :	in    STD_ULOGIC;
      WD27                            :	in    STD_ULOGIC;
      WD28                            :	in    STD_ULOGIC;
      WD29                            :	in    STD_ULOGIC;
      WD30                            :	in    STD_ULOGIC;
      WD31                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RAD12                            :	in    STD_ULOGIC;
      RAD13                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16K_WX32_RX1 : entity is FALSE;
end RAMB16K_WX32_RX1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX32_RX1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';
      signal WD16_ipd      : std_ulogic := 'X';
      signal WD17_ipd      : std_ulogic := 'X';
      signal WD18_ipd      : std_ulogic := 'X';
      signal WD19_ipd      : std_ulogic := 'X';
      signal WD20_ipd      : std_ulogic := 'X';
      signal WD21_ipd      : std_ulogic := 'X';
      signal WD22_ipd      : std_ulogic := 'X';
      signal WD23_ipd      : std_ulogic := 'X';
      signal WD24_ipd      : std_ulogic := 'X';
      signal WD25_ipd      : std_ulogic := 'X';
      signal WD26_ipd      : std_ulogic := 'X';
      signal WD27_ipd      : std_ulogic := 'X';
      signal WD28_ipd      : std_ulogic := 'X';
      signal WD29_ipd      : std_ulogic := 'X';
      signal WD30_ipd      : std_ulogic := 'X';
      signal WD31_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';
      signal RAD12_ipd      : std_ulogic := 'X';
      signal RAD13_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (31 downto 0);
 	signal WAD : std_logic_vector (8 downto 0);
 	signal RAD : std_logic_vector (13 downto 0);
	signal RD  : std_logic_vector (0 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD31_ipd & WD30_ipd & WD29_ipd & WD28_ipd & WD27_ipd & WD26_ipd & WD25_ipd & WD24_ipd & WD23_ipd & WD22_ipd & WD21_ipd & WD20_ipd & WD19_ipd & WD18_ipd & WD17_ipd & WD16_ipd & WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD13_ipd & RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);
        VitalWireDelay (WD16_ipd, WD16, tipd_WD16);
        VitalWireDelay (WD17_ipd, WD17, tipd_WD17);
        VitalWireDelay (WD18_ipd, WD18, tipd_WD18);
        VitalWireDelay (WD19_ipd, WD19, tipd_WD19);
        VitalWireDelay (WD20_ipd, WD20, tipd_WD20);
        VitalWireDelay (WD21_ipd, WD21, tipd_WD21);
        VitalWireDelay (WD22_ipd, WD22, tipd_WD22);
        VitalWireDelay (WD23_ipd, WD23, tipd_WD23);
        VitalWireDelay (WD24_ipd, WD24, tipd_WD24);
        VitalWireDelay (WD25_ipd, WD25, tipd_WD25);
        VitalWireDelay (WD26_ipd, WD26, tipd_WD26);
        VitalWireDelay (WD27_ipd, WD27, tipd_WD27);
        VitalWireDelay (WD28_ipd, WD28, tipd_WD28);
        VitalWireDelay (WD29_ipd, WD29, tipd_WD29);
        VitalWireDelay (WD30_ipd, WD30, tipd_WD30);
        VitalWireDelay (WD31_ipd, WD31, tipd_WD31);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);
        VitalWireDelay (RAD13_ipd, RAD13, tipd_RAD13);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD16_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD17_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD18_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD19_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD20_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD21_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD22_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD23_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD24_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD25_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD26_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD27_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD28_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD29_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD30_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD31_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD11_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD12_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD13_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD16_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD17_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD18_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD19_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD20_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD21_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD22_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD23_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD24_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD25_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD26_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD27_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD28_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD29_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD30_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD31_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD11_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD12_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD13_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;


        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD16_WCLK_posedge,
          TimingData              => Tmkr_WD16_WCLK_posedge,
          TestSignal              => WD16_ipd,
          TestSignalName          => "WD16",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD16_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD16_WCLK_noedge_posedge,
          HoldLow                 => thold_WD16_WCLK_noedge_posedge,
          HoldHigh                => thold_WD16_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD17_WCLK_posedge,
          TimingData              => Tmkr_WD17_WCLK_posedge,
          TestSignal              => WD17_ipd,
          TestSignalName          => "WD17",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD17_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD17_WCLK_noedge_posedge,
          HoldLow                 => thold_WD17_WCLK_noedge_posedge,
          HoldHigh                => thold_WD17_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD18_WCLK_posedge,
          TimingData              => Tmkr_WD18_WCLK_posedge,
          TestSignal              => WD18_ipd,
          TestSignalName          => "WD18",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD18_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD18_WCLK_noedge_posedge,
          HoldLow                 => thold_WD18_WCLK_noedge_posedge,
          HoldHigh                => thold_WD18_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD19_WCLK_posedge,
          TimingData              => Tmkr_WD19_WCLK_posedge,
          TestSignal              => WD19_ipd,
          TestSignalName          => "WD19",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD19_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD19_WCLK_noedge_posedge,
          HoldLow                 => thold_WD19_WCLK_noedge_posedge,
          HoldHigh                => thold_WD19_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD20_WCLK_posedge,
          TimingData              => Tmkr_WD20_WCLK_posedge,
          TestSignal              => WD20_ipd,
          TestSignalName          => "WD20",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD20_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD20_WCLK_noedge_posedge,
          HoldLow                 => thold_WD20_WCLK_noedge_posedge,
          HoldHigh                => thold_WD20_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD21_WCLK_posedge,
          TimingData              => Tmkr_WD21_WCLK_posedge,
          TestSignal              => WD21_ipd,
          TestSignalName          => "WD21",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD21_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD21_WCLK_noedge_posedge,
          HoldLow                 => thold_WD21_WCLK_noedge_posedge,
          HoldHigh                => thold_WD21_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD22_WCLK_posedge,
          TimingData              => Tmkr_WD22_WCLK_posedge,
          TestSignal              => WD22_ipd,
          TestSignalName          => "WD22",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD22_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD22_WCLK_noedge_posedge,
          HoldLow                 => thold_WD22_WCLK_noedge_posedge,
          HoldHigh                => thold_WD22_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD23_WCLK_posedge,
          TimingData              => Tmkr_WD23_WCLK_posedge,
          TestSignal              => WD23_ipd,
          TestSignalName          => "WD23",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD23_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD23_WCLK_noedge_posedge,
          HoldLow                 => thold_WD23_WCLK_noedge_posedge,
          HoldHigh                => thold_WD23_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD24_WCLK_posedge,
          TimingData              => Tmkr_WD24_WCLK_posedge,
          TestSignal              => WD24_ipd,
          TestSignalName          => "WD24",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD24_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD24_WCLK_noedge_posedge,
          HoldLow                 => thold_WD24_WCLK_noedge_posedge,
          HoldHigh                => thold_WD24_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD25_WCLK_posedge,
          TimingData              => Tmkr_WD25_WCLK_posedge,
          TestSignal              => WD25_ipd,
          TestSignalName          => "WD25",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD25_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD25_WCLK_noedge_posedge,
          HoldLow                 => thold_WD25_WCLK_noedge_posedge,
          HoldHigh                => thold_WD25_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD26_WCLK_posedge,
          TimingData              => Tmkr_WD26_WCLK_posedge,
          TestSignal              => WD26_ipd,
          TestSignalName          => "WD26",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD26_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD26_WCLK_noedge_posedge,
          HoldLow                 => thold_WD26_WCLK_noedge_posedge,
          HoldHigh                => thold_WD26_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD27_WCLK_posedge,
          TimingData              => Tmkr_WD27_WCLK_posedge,
          TestSignal              => WD27_ipd,
          TestSignalName          => "WD27",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD27_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD27_WCLK_noedge_posedge,
          HoldLow                 => thold_WD27_WCLK_noedge_posedge,
          HoldHigh                => thold_WD27_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD28_WCLK_posedge,
          TimingData              => Tmkr_WD28_WCLK_posedge,
          TestSignal              => WD28_ipd,
          TestSignalName          => "WD28",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD28_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD28_WCLK_noedge_posedge,
          HoldLow                 => thold_WD28_WCLK_noedge_posedge,
          HoldHigh                => thold_WD28_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD29_WCLK_posedge,
          TimingData              => Tmkr_WD29_WCLK_posedge,
          TestSignal              => WD29_ipd,
          TestSignalName          => "WD29",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD29_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD29_WCLK_noedge_posedge,
          HoldLow                 => thold_WD29_WCLK_noedge_posedge,
          HoldHigh                => thold_WD29_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD30_WCLK_posedge,
          TimingData              => Tmkr_WD30_WCLK_posedge,
          TestSignal              => WD30_ipd,
          TestSignalName          => "WD30",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD30_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD30_WCLK_noedge_posedge,
          HoldLow                 => thold_WD30_WCLK_noedge_posedge,
          HoldHigh                => thold_WD30_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD31_WCLK_posedge,
          TimingData              => Tmkr_WD31_WCLK_posedge,
          TestSignal              => WD31_ipd,
          TestSignalName          => "WD31",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD31_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD31_WCLK_noedge_posedge,
          HoldLow                 => thold_WD31_WCLK_noedge_posedge,
          HoldHigh                => thold_WD31_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD11_RCLK_posedge,
          TimingData              => Tmkr_RAD11_RCLK_posedge,
          TestSignal              => RAD11_ipd,
          TestSignalName          => "RAD11",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD11_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD11_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD11_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD11_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD12_RCLK_posedge,
          TimingData              => Tmkr_RAD12_RCLK_posedge,
          TestSignal              => RAD12_ipd,
          TestSignalName          => "RAD12",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD12_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD12_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD12_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD12_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD13_RCLK_posedge,
          TimingData              => Tmkr_RAD13_RCLK_posedge,
          TestSignal              => RAD13_ipd,
          TestSignalName          => "RAD13",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD13_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD13_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD13_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD13_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or
                 Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or
                 Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or
                 Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or
                 Tviol_WD15_WCLK_posedge or
                 Tviol_WD16_WCLK_posedge or
                 Tviol_WD17_WCLK_posedge or
                 Tviol_WD18_WCLK_posedge or
                 Tviol_WD19_WCLK_posedge or
                 Tviol_WD20_WCLK_posedge or
                 Tviol_WD21_WCLK_posedge or
                 Tviol_WD22_WCLK_posedge or
                 Tviol_WD23_WCLK_posedge or
                 Tviol_WD24_WCLK_posedge or
                 Tviol_WD25_WCLK_posedge or
                 Tviol_WD26_WCLK_posedge or
                 Tviol_WD27_WCLK_posedge or
                 Tviol_WD28_WCLK_posedge or
                 Tviol_WD29_WCLK_posedge or
                 Tviol_WD30_WCLK_posedge or
                 Tviol_WD31_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or
                 Tviol_RAD1_RCLK_posedge or
                 Tviol_RAD2_RCLK_posedge or
                 Tviol_RAD3_RCLK_posedge or
                 Tviol_RAD4_RCLK_posedge or
                 Tviol_RAD5_RCLK_posedge or
                 Tviol_RAD6_RCLK_posedge or
                 Tviol_RAD7_RCLK_posedge or
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RAD9_RCLK_posedge or
                 Tviol_RAD10_RCLK_posedge or
                 Tviol_RAD11_RCLK_posedge or
                 Tviol_RAD12_RCLK_posedge or
                 Tviol_RAD13_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 9,
		WDATA_WIDTH    => 32,
		RADDR_WIDTH    => 14,
		RDATA_WIDTH    => 1,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16K_WX32_RX1_VITAL of RAMB16K_WX32_RX1 is
   for VITAL
   end for;
end CFG_RAMB16K_WX32_RX1_VITAL;


----- CELL RAMB16K_WX32_RX16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX32_RX16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD4                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD5                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD6                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD7                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD8                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD9                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD10                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD11                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD12                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD13                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD14                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD15                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD16_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD16_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD17_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD17_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD18_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD18_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD19_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD19_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD20_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD20_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD21_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD21_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD22_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD22_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD23_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD23_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD24_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD24_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD25_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD25_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD26_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD26_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD27_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD27_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD28_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD28_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD29_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD29_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD30_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD30_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD31_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD31_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD16                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD17                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD18                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD19                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD20                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD21                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD22                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD23                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD24                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD25                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD26                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD27                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD28                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD29                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD30                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD31                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WD16                            :	in    STD_ULOGIC;
      WD17                            :	in    STD_ULOGIC;
      WD18                            :	in    STD_ULOGIC;
      WD19                            :	in    STD_ULOGIC;
      WD20                            :	in    STD_ULOGIC;
      WD21                            :	in    STD_ULOGIC;
      WD22                            :	in    STD_ULOGIC;
      WD23                            :	in    STD_ULOGIC;
      WD24                            :	in    STD_ULOGIC;
      WD25                            :	in    STD_ULOGIC;
      WD26                            :	in    STD_ULOGIC;
      WD27                            :	in    STD_ULOGIC;
      WD28                            :	in    STD_ULOGIC;
      WD29                            :	in    STD_ULOGIC;
      WD30                            :	in    STD_ULOGIC;
      WD31                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC;
      RD2                            :	out    STD_ULOGIC;
      RD3                            :	out    STD_ULOGIC;
      RD4                            :	out    STD_ULOGIC;
      RD5                            :	out    STD_ULOGIC;
      RD6                            :	out    STD_ULOGIC;
      RD7                            :	out    STD_ULOGIC;
      RD8                            :	out    STD_ULOGIC;
      RD9                            :	out    STD_ULOGIC;
      RD10                            :	out    STD_ULOGIC;
      RD11                            :	out    STD_ULOGIC;
      RD12                            :	out    STD_ULOGIC;
      RD13                            :	out    STD_ULOGIC;
      RD14                            :	out    STD_ULOGIC;
      RD15                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16K_WX32_RX16 : entity is FALSE;
end RAMB16K_WX32_RX16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX32_RX16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';
      signal WD16_ipd      : std_ulogic := 'X';
      signal WD17_ipd      : std_ulogic := 'X';
      signal WD18_ipd      : std_ulogic := 'X';
      signal WD19_ipd      : std_ulogic := 'X';
      signal WD20_ipd      : std_ulogic := 'X';
      signal WD21_ipd      : std_ulogic := 'X';
      signal WD22_ipd      : std_ulogic := 'X';
      signal WD23_ipd      : std_ulogic := 'X';
      signal WD24_ipd      : std_ulogic := 'X';
      signal WD25_ipd      : std_ulogic := 'X';
      signal WD26_ipd      : std_ulogic := 'X';
      signal WD27_ipd      : std_ulogic := 'X';
      signal WD28_ipd      : std_ulogic := 'X';
      signal WD29_ipd      : std_ulogic := 'X';
      signal WD30_ipd      : std_ulogic := 'X';
      signal WD31_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (31 downto 0);
 	signal WAD : std_logic_vector (8 downto 0);
 	signal RAD : std_logic_vector (9 downto 0);
	signal RD  : std_logic_vector (15 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD31_ipd & WD30_ipd & WD29_ipd & WD28_ipd & WD27_ipd & WD26_ipd & WD25_ipd & WD24_ipd & WD23_ipd & WD22_ipd & WD21_ipd & WD20_ipd & WD19_ipd & WD18_ipd & WD17_ipd & WD16_ipd & WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);
        VitalWireDelay (WD16_ipd, WD16, tipd_WD16);
        VitalWireDelay (WD17_ipd, WD17, tipd_WD17);
        VitalWireDelay (WD18_ipd, WD18, tipd_WD18);
        VitalWireDelay (WD19_ipd, WD19, tipd_WD19);
        VitalWireDelay (WD20_ipd, WD20, tipd_WD20);
        VitalWireDelay (WD21_ipd, WD21, tipd_WD21);
        VitalWireDelay (WD22_ipd, WD22, tipd_WD22);
        VitalWireDelay (WD23_ipd, WD23, tipd_WD23);
        VitalWireDelay (WD24_ipd, WD24, tipd_WD24);
        VitalWireDelay (WD25_ipd, WD25, tipd_WD25);
        VitalWireDelay (WD26_ipd, WD26, tipd_WD26);
        VitalWireDelay (WD27_ipd, WD27, tipd_WD27);
        VitalWireDelay (WD28_ipd, WD28, tipd_WD28);
        VitalWireDelay (WD29_ipd, WD29, tipd_WD29);
        VitalWireDelay (WD30_ipd, WD30, tipd_WD30);
        VitalWireDelay (WD31_ipd, WD31, tipd_WD31);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD16_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD17_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD18_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD19_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD20_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD21_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD22_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD23_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD24_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD25_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD26_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD27_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD28_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD29_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD30_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD31_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD16_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD17_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD18_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD19_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD20_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD21_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD22_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD23_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD24_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD25_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD26_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD27_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD28_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD29_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD30_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD31_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;


        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd          : std_ulogic := 'X';
        variable RD11_zd          : std_ulogic := 'X';
        variable RD12_zd          : std_ulogic := 'X';
        variable RD13_zd          : std_ulogic := 'X';
        variable RD14_zd          : std_ulogic := 'X';
        variable RD15_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD16_WCLK_posedge,
          TimingData              => Tmkr_WD16_WCLK_posedge,
          TestSignal              => WD16_ipd,
          TestSignalName          => "WD16",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD16_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD16_WCLK_noedge_posedge,
          HoldLow                 => thold_WD16_WCLK_noedge_posedge,
          HoldHigh                => thold_WD16_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD17_WCLK_posedge,
          TimingData              => Tmkr_WD17_WCLK_posedge,
          TestSignal              => WD17_ipd,
          TestSignalName          => "WD17",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD17_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD17_WCLK_noedge_posedge,
          HoldLow                 => thold_WD17_WCLK_noedge_posedge,
          HoldHigh                => thold_WD17_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD18_WCLK_posedge,
          TimingData              => Tmkr_WD18_WCLK_posedge,
          TestSignal              => WD18_ipd,
          TestSignalName          => "WD18",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD18_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD18_WCLK_noedge_posedge,
          HoldLow                 => thold_WD18_WCLK_noedge_posedge,
          HoldHigh                => thold_WD18_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD19_WCLK_posedge,
          TimingData              => Tmkr_WD19_WCLK_posedge,
          TestSignal              => WD19_ipd,
          TestSignalName          => "WD19",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD19_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD19_WCLK_noedge_posedge,
          HoldLow                 => thold_WD19_WCLK_noedge_posedge,
          HoldHigh                => thold_WD19_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD20_WCLK_posedge,
          TimingData              => Tmkr_WD20_WCLK_posedge,
          TestSignal              => WD20_ipd,
          TestSignalName          => "WD20",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD20_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD20_WCLK_noedge_posedge,
          HoldLow                 => thold_WD20_WCLK_noedge_posedge,
          HoldHigh                => thold_WD20_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD21_WCLK_posedge,
          TimingData              => Tmkr_WD21_WCLK_posedge,
          TestSignal              => WD21_ipd,
          TestSignalName          => "WD21",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD21_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD21_WCLK_noedge_posedge,
          HoldLow                 => thold_WD21_WCLK_noedge_posedge,
          HoldHigh                => thold_WD21_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD22_WCLK_posedge,
          TimingData              => Tmkr_WD22_WCLK_posedge,
          TestSignal              => WD22_ipd,
          TestSignalName          => "WD22",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD22_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD22_WCLK_noedge_posedge,
          HoldLow                 => thold_WD22_WCLK_noedge_posedge,
          HoldHigh                => thold_WD22_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD23_WCLK_posedge,
          TimingData              => Tmkr_WD23_WCLK_posedge,
          TestSignal              => WD23_ipd,
          TestSignalName          => "WD23",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD23_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD23_WCLK_noedge_posedge,
          HoldLow                 => thold_WD23_WCLK_noedge_posedge,
          HoldHigh                => thold_WD23_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD24_WCLK_posedge,
          TimingData              => Tmkr_WD24_WCLK_posedge,
          TestSignal              => WD24_ipd,
          TestSignalName          => "WD24",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD24_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD24_WCLK_noedge_posedge,
          HoldLow                 => thold_WD24_WCLK_noedge_posedge,
          HoldHigh                => thold_WD24_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD25_WCLK_posedge,
          TimingData              => Tmkr_WD25_WCLK_posedge,
          TestSignal              => WD25_ipd,
          TestSignalName          => "WD25",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD25_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD25_WCLK_noedge_posedge,
          HoldLow                 => thold_WD25_WCLK_noedge_posedge,
          HoldHigh                => thold_WD25_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD26_WCLK_posedge,
          TimingData              => Tmkr_WD26_WCLK_posedge,
          TestSignal              => WD26_ipd,
          TestSignalName          => "WD26",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD26_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD26_WCLK_noedge_posedge,
          HoldLow                 => thold_WD26_WCLK_noedge_posedge,
          HoldHigh                => thold_WD26_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD27_WCLK_posedge,
          TimingData              => Tmkr_WD27_WCLK_posedge,
          TestSignal              => WD27_ipd,
          TestSignalName          => "WD27",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD27_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD27_WCLK_noedge_posedge,
          HoldLow                 => thold_WD27_WCLK_noedge_posedge,
          HoldHigh                => thold_WD27_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD28_WCLK_posedge,
          TimingData              => Tmkr_WD28_WCLK_posedge,
          TestSignal              => WD28_ipd,
          TestSignalName          => "WD28",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD28_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD28_WCLK_noedge_posedge,
          HoldLow                 => thold_WD28_WCLK_noedge_posedge,
          HoldHigh                => thold_WD28_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD29_WCLK_posedge,
          TimingData              => Tmkr_WD29_WCLK_posedge,
          TestSignal              => WD29_ipd,
          TestSignalName          => "WD29",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD29_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD29_WCLK_noedge_posedge,
          HoldLow                 => thold_WD29_WCLK_noedge_posedge,
          HoldHigh                => thold_WD29_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD30_WCLK_posedge,
          TimingData              => Tmkr_WD30_WCLK_posedge,
          TestSignal              => WD30_ipd,
          TestSignalName          => "WD30",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD30_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD30_WCLK_noedge_posedge,
          HoldLow                 => thold_WD30_WCLK_noedge_posedge,
          HoldHigh                => thold_WD30_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD31_WCLK_posedge,
          TimingData              => Tmkr_WD31_WCLK_posedge,
          TestSignal              => WD31_ipd,
          TestSignalName          => "WD31",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD31_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD31_WCLK_noedge_posedge,
          HoldLow                 => thold_WD31_WCLK_noedge_posedge,
          HoldHigh                => thold_WD31_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or
                 Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or
                 Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or
                 Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or
                 Tviol_WD15_WCLK_posedge or
                 Tviol_WD16_WCLK_posedge or
                 Tviol_WD17_WCLK_posedge or
                 Tviol_WD18_WCLK_posedge or
                 Tviol_WD19_WCLK_posedge or
                 Tviol_WD20_WCLK_posedge or
                 Tviol_WD21_WCLK_posedge or
                 Tviol_WD22_WCLK_posedge or
                 Tviol_WD23_WCLK_posedge or
                 Tviol_WD24_WCLK_posedge or
                 Tviol_WD25_WCLK_posedge or
                 Tviol_WD26_WCLK_posedge or
                 Tviol_WD27_WCLK_posedge or
                 Tviol_WD28_WCLK_posedge or
                 Tviol_WD29_WCLK_posedge or
                 Tviol_WD30_WCLK_posedge or
                 Tviol_WD31_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or
                 Tviol_RAD1_RCLK_posedge or
                 Tviol_RAD2_RCLK_posedge or
                 Tviol_RAD3_RCLK_posedge or
                 Tviol_RAD4_RCLK_posedge or
                 Tviol_RAD5_RCLK_posedge or
                 Tviol_RAD6_RCLK_posedge or
                 Tviol_RAD7_RCLK_posedge or
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RAD9_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD8, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD9, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD10, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD11, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD12, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD13, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD14, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD15, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;

	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 9,
		WDATA_WIDTH    => 32,
		RADDR_WIDTH    => 10,
		RDATA_WIDTH    => 16,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16K_WX32_RX16_VITAL of RAMB16K_WX32_RX16 is
   for VITAL
   end for;
end CFG_RAMB16K_WX32_RX16_VITAL;


----- CELL RAMB16K_WX32_RX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX32_RX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD16_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD16_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD17_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD17_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD18_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD18_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD19_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD19_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD20_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD20_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD21_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD21_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD22_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD22_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD23_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD23_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD24_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD24_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD25_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD25_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD26_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD26_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD27_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD27_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD28_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD28_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD29_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD29_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD30_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD30_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD31_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD31_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD11_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD11_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD12_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD12_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD16                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD17                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD18                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD19                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD20                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD21                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD22                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD23                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD24                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD25                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD26                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD27                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD28                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD29                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD30                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD31                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WD16                            :	in    STD_ULOGIC;
      WD17                            :	in    STD_ULOGIC;
      WD18                            :	in    STD_ULOGIC;
      WD19                            :	in    STD_ULOGIC;
      WD20                            :	in    STD_ULOGIC;
      WD21                            :	in    STD_ULOGIC;
      WD22                            :	in    STD_ULOGIC;
      WD23                            :	in    STD_ULOGIC;
      WD24                            :	in    STD_ULOGIC;
      WD25                            :	in    STD_ULOGIC;
      WD26                            :	in    STD_ULOGIC;
      WD27                            :	in    STD_ULOGIC;
      WD28                            :	in    STD_ULOGIC;
      WD29                            :	in    STD_ULOGIC;
      WD30                            :	in    STD_ULOGIC;
      WD31                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RAD12                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16K_WX32_RX2 : entity is FALSE;
end RAMB16K_WX32_RX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX32_RX2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';
      signal WD16_ipd      : std_ulogic := 'X';
      signal WD17_ipd      : std_ulogic := 'X';
      signal WD18_ipd      : std_ulogic := 'X';
      signal WD19_ipd      : std_ulogic := 'X';
      signal WD20_ipd      : std_ulogic := 'X';
      signal WD21_ipd      : std_ulogic := 'X';
      signal WD22_ipd      : std_ulogic := 'X';
      signal WD23_ipd      : std_ulogic := 'X';
      signal WD24_ipd      : std_ulogic := 'X';
      signal WD25_ipd      : std_ulogic := 'X';
      signal WD26_ipd      : std_ulogic := 'X';
      signal WD27_ipd      : std_ulogic := 'X';
      signal WD28_ipd      : std_ulogic := 'X';
      signal WD29_ipd      : std_ulogic := 'X';
      signal WD30_ipd      : std_ulogic := 'X';
      signal WD31_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';
      signal RAD12_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (31 downto 0);
 	signal WAD : std_logic_vector (8 downto 0);
 	signal RAD : std_logic_vector (12 downto 0);
	signal RD  : std_logic_vector (1 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD31_ipd & WD30_ipd & WD29_ipd & WD28_ipd & WD27_ipd & WD26_ipd & WD25_ipd & WD24_ipd & WD23_ipd & WD22_ipd & WD21_ipd & WD20_ipd & WD19_ipd & WD18_ipd & WD17_ipd & WD16_ipd & WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);
        VitalWireDelay (WD16_ipd, WD16, tipd_WD16);
        VitalWireDelay (WD17_ipd, WD17, tipd_WD17);
        VitalWireDelay (WD18_ipd, WD18, tipd_WD18);
        VitalWireDelay (WD19_ipd, WD19, tipd_WD19);
        VitalWireDelay (WD20_ipd, WD20, tipd_WD20);
        VitalWireDelay (WD21_ipd, WD21, tipd_WD21);
        VitalWireDelay (WD22_ipd, WD22, tipd_WD22);
        VitalWireDelay (WD23_ipd, WD23, tipd_WD23);
        VitalWireDelay (WD24_ipd, WD24, tipd_WD24);
        VitalWireDelay (WD25_ipd, WD25, tipd_WD25);
        VitalWireDelay (WD26_ipd, WD26, tipd_WD26);
        VitalWireDelay (WD27_ipd, WD27, tipd_WD27);
        VitalWireDelay (WD28_ipd, WD28, tipd_WD28);
        VitalWireDelay (WD29_ipd, WD29, tipd_WD29);
        VitalWireDelay (WD30_ipd, WD30, tipd_WD30);
        VitalWireDelay (WD31_ipd, WD31, tipd_WD31);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD16_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD17_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD18_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD19_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD20_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD21_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD22_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD23_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD24_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD25_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD26_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD27_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD28_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD29_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD30_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD31_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD11_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD12_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD16_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD17_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD18_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD19_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD20_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD21_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD22_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD23_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD24_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD25_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD26_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD27_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD28_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD29_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD30_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD31_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD11_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD12_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;


        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD16_WCLK_posedge,
          TimingData              => Tmkr_WD16_WCLK_posedge,
          TestSignal              => WD16_ipd,
          TestSignalName          => "WD16",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD16_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD16_WCLK_noedge_posedge,
          HoldLow                 => thold_WD16_WCLK_noedge_posedge,
          HoldHigh                => thold_WD16_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD17_WCLK_posedge,
          TimingData              => Tmkr_WD17_WCLK_posedge,
          TestSignal              => WD17_ipd,
          TestSignalName          => "WD17",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD17_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD17_WCLK_noedge_posedge,
          HoldLow                 => thold_WD17_WCLK_noedge_posedge,
          HoldHigh                => thold_WD17_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD18_WCLK_posedge,
          TimingData              => Tmkr_WD18_WCLK_posedge,
          TestSignal              => WD18_ipd,
          TestSignalName          => "WD18",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD18_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD18_WCLK_noedge_posedge,
          HoldLow                 => thold_WD18_WCLK_noedge_posedge,
          HoldHigh                => thold_WD18_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD19_WCLK_posedge,
          TimingData              => Tmkr_WD19_WCLK_posedge,
          TestSignal              => WD19_ipd,
          TestSignalName          => "WD19",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD19_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD19_WCLK_noedge_posedge,
          HoldLow                 => thold_WD19_WCLK_noedge_posedge,
          HoldHigh                => thold_WD19_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD20_WCLK_posedge,
          TimingData              => Tmkr_WD20_WCLK_posedge,
          TestSignal              => WD20_ipd,
          TestSignalName          => "WD20",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD20_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD20_WCLK_noedge_posedge,
          HoldLow                 => thold_WD20_WCLK_noedge_posedge,
          HoldHigh                => thold_WD20_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD21_WCLK_posedge,
          TimingData              => Tmkr_WD21_WCLK_posedge,
          TestSignal              => WD21_ipd,
          TestSignalName          => "WD21",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD21_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD21_WCLK_noedge_posedge,
          HoldLow                 => thold_WD21_WCLK_noedge_posedge,
          HoldHigh                => thold_WD21_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD22_WCLK_posedge,
          TimingData              => Tmkr_WD22_WCLK_posedge,
          TestSignal              => WD22_ipd,
          TestSignalName          => "WD22",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD22_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD22_WCLK_noedge_posedge,
          HoldLow                 => thold_WD22_WCLK_noedge_posedge,
          HoldHigh                => thold_WD22_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD23_WCLK_posedge,
          TimingData              => Tmkr_WD23_WCLK_posedge,
          TestSignal              => WD23_ipd,
          TestSignalName          => "WD23",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD23_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD23_WCLK_noedge_posedge,
          HoldLow                 => thold_WD23_WCLK_noedge_posedge,
          HoldHigh                => thold_WD23_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD24_WCLK_posedge,
          TimingData              => Tmkr_WD24_WCLK_posedge,
          TestSignal              => WD24_ipd,
          TestSignalName          => "WD24",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD24_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD24_WCLK_noedge_posedge,
          HoldLow                 => thold_WD24_WCLK_noedge_posedge,
          HoldHigh                => thold_WD24_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD25_WCLK_posedge,
          TimingData              => Tmkr_WD25_WCLK_posedge,
          TestSignal              => WD25_ipd,
          TestSignalName          => "WD25",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD25_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD25_WCLK_noedge_posedge,
          HoldLow                 => thold_WD25_WCLK_noedge_posedge,
          HoldHigh                => thold_WD25_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD26_WCLK_posedge,
          TimingData              => Tmkr_WD26_WCLK_posedge,
          TestSignal              => WD26_ipd,
          TestSignalName          => "WD26",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD26_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD26_WCLK_noedge_posedge,
          HoldLow                 => thold_WD26_WCLK_noedge_posedge,
          HoldHigh                => thold_WD26_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD27_WCLK_posedge,
          TimingData              => Tmkr_WD27_WCLK_posedge,
          TestSignal              => WD27_ipd,
          TestSignalName          => "WD27",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD27_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD27_WCLK_noedge_posedge,
          HoldLow                 => thold_WD27_WCLK_noedge_posedge,
          HoldHigh                => thold_WD27_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD28_WCLK_posedge,
          TimingData              => Tmkr_WD28_WCLK_posedge,
          TestSignal              => WD28_ipd,
          TestSignalName          => "WD28",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD28_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD28_WCLK_noedge_posedge,
          HoldLow                 => thold_WD28_WCLK_noedge_posedge,
          HoldHigh                => thold_WD28_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD29_WCLK_posedge,
          TimingData              => Tmkr_WD29_WCLK_posedge,
          TestSignal              => WD29_ipd,
          TestSignalName          => "WD29",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD29_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD29_WCLK_noedge_posedge,
          HoldLow                 => thold_WD29_WCLK_noedge_posedge,
          HoldHigh                => thold_WD29_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD30_WCLK_posedge,
          TimingData              => Tmkr_WD30_WCLK_posedge,
          TestSignal              => WD30_ipd,
          TestSignalName          => "WD30",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD30_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD30_WCLK_noedge_posedge,
          HoldLow                 => thold_WD30_WCLK_noedge_posedge,
          HoldHigh                => thold_WD30_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD31_WCLK_posedge,
          TimingData              => Tmkr_WD31_WCLK_posedge,
          TestSignal              => WD31_ipd,
          TestSignalName          => "WD31",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD31_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD31_WCLK_noedge_posedge,
          HoldLow                 => thold_WD31_WCLK_noedge_posedge,
          HoldHigh                => thold_WD31_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD11_RCLK_posedge,
          TimingData              => Tmkr_RAD11_RCLK_posedge,
          TestSignal              => RAD11_ipd,
          TestSignalName          => "RAD11",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD11_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD11_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD11_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD11_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD12_RCLK_posedge,
          TimingData              => Tmkr_RAD12_RCLK_posedge,
          TestSignal              => RAD12_ipd,
          TestSignalName          => "RAD12",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD12_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD12_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD12_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD12_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or
                 Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or
                 Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or
                 Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or
                 Tviol_WD15_WCLK_posedge or
                 Tviol_WD16_WCLK_posedge or
                 Tviol_WD17_WCLK_posedge or
                 Tviol_WD18_WCLK_posedge or
                 Tviol_WD19_WCLK_posedge or
                 Tviol_WD20_WCLK_posedge or
                 Tviol_WD21_WCLK_posedge or
                 Tviol_WD22_WCLK_posedge or
                 Tviol_WD23_WCLK_posedge or
                 Tviol_WD24_WCLK_posedge or
                 Tviol_WD25_WCLK_posedge or
                 Tviol_WD26_WCLK_posedge or
                 Tviol_WD27_WCLK_posedge or
                 Tviol_WD28_WCLK_posedge or
                 Tviol_WD29_WCLK_posedge or
                 Tviol_WD30_WCLK_posedge or
                 Tviol_WD31_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or
                 Tviol_RAD1_RCLK_posedge or
                 Tviol_RAD2_RCLK_posedge or
                 Tviol_RAD3_RCLK_posedge or
                 Tviol_RAD4_RCLK_posedge or
                 Tviol_RAD5_RCLK_posedge or
                 Tviol_RAD6_RCLK_posedge or
                 Tviol_RAD7_RCLK_posedge or
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RAD9_RCLK_posedge or
                 Tviol_RAD10_RCLK_posedge or
                 Tviol_RAD11_RCLK_posedge or
                 Tviol_RAD12_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 9,
		WDATA_WIDTH    => 32,
		RADDR_WIDTH    => 13,
		RDATA_WIDTH    => 2,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16K_WX32_RX2_VITAL of RAMB16K_WX32_RX2 is
   for VITAL
   end for;
end CFG_RAMB16K_WX32_RX2_VITAL;


----- CELL RAMB16K_WX32_RX4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX32_RX4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD16_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD16_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD17_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD17_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD18_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD18_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD19_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD19_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD20_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD20_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD21_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD21_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD22_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD22_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD23_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD23_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD24_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD24_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD25_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD25_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD26_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD26_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD27_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD27_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD28_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD28_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD29_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD29_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD30_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD30_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD31_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD31_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD11_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD11_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD16                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD17                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD18                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD19                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD20                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD21                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD22                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD23                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD24                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD25                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD26                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD27                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD28                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD29                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD30                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD31                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WD16                            :	in    STD_ULOGIC;
      WD17                            :	in    STD_ULOGIC;
      WD18                            :	in    STD_ULOGIC;
      WD19                            :	in    STD_ULOGIC;
      WD20                            :	in    STD_ULOGIC;
      WD21                            :	in    STD_ULOGIC;
      WD22                            :	in    STD_ULOGIC;
      WD23                            :	in    STD_ULOGIC;
      WD24                            :	in    STD_ULOGIC;
      WD25                            :	in    STD_ULOGIC;
      WD26                            :	in    STD_ULOGIC;
      WD27                            :	in    STD_ULOGIC;
      WD28                            :	in    STD_ULOGIC;
      WD29                            :	in    STD_ULOGIC;
      WD30                            :	in    STD_ULOGIC;
      WD31                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC;
      RD2                            :	out    STD_ULOGIC;
      RD3                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16K_WX32_RX4 : entity is FALSE;
end RAMB16K_WX32_RX4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX32_RX4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';
      signal WD16_ipd      : std_ulogic := 'X';
      signal WD17_ipd      : std_ulogic := 'X';
      signal WD18_ipd      : std_ulogic := 'X';
      signal WD19_ipd      : std_ulogic := 'X';
      signal WD20_ipd      : std_ulogic := 'X';
      signal WD21_ipd      : std_ulogic := 'X';
      signal WD22_ipd      : std_ulogic := 'X';
      signal WD23_ipd      : std_ulogic := 'X';
      signal WD24_ipd      : std_ulogic := 'X';
      signal WD25_ipd      : std_ulogic := 'X';
      signal WD26_ipd      : std_ulogic := 'X';
      signal WD27_ipd      : std_ulogic := 'X';
      signal WD28_ipd      : std_ulogic := 'X';
      signal WD29_ipd      : std_ulogic := 'X';
      signal WD30_ipd      : std_ulogic := 'X';
      signal WD31_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (31 downto 0);
 	signal WAD : std_logic_vector (8 downto 0);
 	signal RAD : std_logic_vector (11 downto 0);
	signal RD  : std_logic_vector (3 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD31_ipd & WD30_ipd & WD29_ipd & WD28_ipd & WD27_ipd & WD26_ipd & WD25_ipd & WD24_ipd & WD23_ipd & WD22_ipd & WD21_ipd & WD20_ipd & WD19_ipd & WD18_ipd & WD17_ipd & WD16_ipd & WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);
        VitalWireDelay (WD16_ipd, WD16, tipd_WD16);
        VitalWireDelay (WD17_ipd, WD17, tipd_WD17);
        VitalWireDelay (WD18_ipd, WD18, tipd_WD18);
        VitalWireDelay (WD19_ipd, WD19, tipd_WD19);
        VitalWireDelay (WD20_ipd, WD20, tipd_WD20);
        VitalWireDelay (WD21_ipd, WD21, tipd_WD21);
        VitalWireDelay (WD22_ipd, WD22, tipd_WD22);
        VitalWireDelay (WD23_ipd, WD23, tipd_WD23);
        VitalWireDelay (WD24_ipd, WD24, tipd_WD24);
        VitalWireDelay (WD25_ipd, WD25, tipd_WD25);
        VitalWireDelay (WD26_ipd, WD26, tipd_WD26);
        VitalWireDelay (WD27_ipd, WD27, tipd_WD27);
        VitalWireDelay (WD28_ipd, WD28, tipd_WD28);
        VitalWireDelay (WD29_ipd, WD29, tipd_WD29);
        VitalWireDelay (WD30_ipd, WD30, tipd_WD30);
        VitalWireDelay (WD31_ipd, WD31, tipd_WD31);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD16_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD17_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD18_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD19_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD20_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD21_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD22_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD23_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD24_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD25_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD26_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD27_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD28_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD29_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD30_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD31_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD11_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD16_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD17_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD18_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD19_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD20_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD21_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD22_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD23_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD24_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD25_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD26_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD27_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD28_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD29_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD30_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD31_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD11_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;


        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD16_WCLK_posedge,
          TimingData              => Tmkr_WD16_WCLK_posedge,
          TestSignal              => WD16_ipd,
          TestSignalName          => "WD16",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD16_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD16_WCLK_noedge_posedge,
          HoldLow                 => thold_WD16_WCLK_noedge_posedge,
          HoldHigh                => thold_WD16_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD17_WCLK_posedge,
          TimingData              => Tmkr_WD17_WCLK_posedge,
          TestSignal              => WD17_ipd,
          TestSignalName          => "WD17",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD17_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD17_WCLK_noedge_posedge,
          HoldLow                 => thold_WD17_WCLK_noedge_posedge,
          HoldHigh                => thold_WD17_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD18_WCLK_posedge,
          TimingData              => Tmkr_WD18_WCLK_posedge,
          TestSignal              => WD18_ipd,
          TestSignalName          => "WD18",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD18_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD18_WCLK_noedge_posedge,
          HoldLow                 => thold_WD18_WCLK_noedge_posedge,
          HoldHigh                => thold_WD18_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD19_WCLK_posedge,
          TimingData              => Tmkr_WD19_WCLK_posedge,
          TestSignal              => WD19_ipd,
          TestSignalName          => "WD19",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD19_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD19_WCLK_noedge_posedge,
          HoldLow                 => thold_WD19_WCLK_noedge_posedge,
          HoldHigh                => thold_WD19_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD20_WCLK_posedge,
          TimingData              => Tmkr_WD20_WCLK_posedge,
          TestSignal              => WD20_ipd,
          TestSignalName          => "WD20",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD20_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD20_WCLK_noedge_posedge,
          HoldLow                 => thold_WD20_WCLK_noedge_posedge,
          HoldHigh                => thold_WD20_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD21_WCLK_posedge,
          TimingData              => Tmkr_WD21_WCLK_posedge,
          TestSignal              => WD21_ipd,
          TestSignalName          => "WD21",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD21_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD21_WCLK_noedge_posedge,
          HoldLow                 => thold_WD21_WCLK_noedge_posedge,
          HoldHigh                => thold_WD21_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD22_WCLK_posedge,
          TimingData              => Tmkr_WD22_WCLK_posedge,
          TestSignal              => WD22_ipd,
          TestSignalName          => "WD22",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD22_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD22_WCLK_noedge_posedge,
          HoldLow                 => thold_WD22_WCLK_noedge_posedge,
          HoldHigh                => thold_WD22_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD23_WCLK_posedge,
          TimingData              => Tmkr_WD23_WCLK_posedge,
          TestSignal              => WD23_ipd,
          TestSignalName          => "WD23",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD23_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD23_WCLK_noedge_posedge,
          HoldLow                 => thold_WD23_WCLK_noedge_posedge,
          HoldHigh                => thold_WD23_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD24_WCLK_posedge,
          TimingData              => Tmkr_WD24_WCLK_posedge,
          TestSignal              => WD24_ipd,
          TestSignalName          => "WD24",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD24_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD24_WCLK_noedge_posedge,
          HoldLow                 => thold_WD24_WCLK_noedge_posedge,
          HoldHigh                => thold_WD24_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD25_WCLK_posedge,
          TimingData              => Tmkr_WD25_WCLK_posedge,
          TestSignal              => WD25_ipd,
          TestSignalName          => "WD25",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD25_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD25_WCLK_noedge_posedge,
          HoldLow                 => thold_WD25_WCLK_noedge_posedge,
          HoldHigh                => thold_WD25_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD26_WCLK_posedge,
          TimingData              => Tmkr_WD26_WCLK_posedge,
          TestSignal              => WD26_ipd,
          TestSignalName          => "WD26",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD26_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD26_WCLK_noedge_posedge,
          HoldLow                 => thold_WD26_WCLK_noedge_posedge,
          HoldHigh                => thold_WD26_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD27_WCLK_posedge,
          TimingData              => Tmkr_WD27_WCLK_posedge,
          TestSignal              => WD27_ipd,
          TestSignalName          => "WD27",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD27_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD27_WCLK_noedge_posedge,
          HoldLow                 => thold_WD27_WCLK_noedge_posedge,
          HoldHigh                => thold_WD27_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD28_WCLK_posedge,
          TimingData              => Tmkr_WD28_WCLK_posedge,
          TestSignal              => WD28_ipd,
          TestSignalName          => "WD28",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD28_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD28_WCLK_noedge_posedge,
          HoldLow                 => thold_WD28_WCLK_noedge_posedge,
          HoldHigh                => thold_WD28_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD29_WCLK_posedge,
          TimingData              => Tmkr_WD29_WCLK_posedge,
          TestSignal              => WD29_ipd,
          TestSignalName          => "WD29",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD29_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD29_WCLK_noedge_posedge,
          HoldLow                 => thold_WD29_WCLK_noedge_posedge,
          HoldHigh                => thold_WD29_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD30_WCLK_posedge,
          TimingData              => Tmkr_WD30_WCLK_posedge,
          TestSignal              => WD30_ipd,
          TestSignalName          => "WD30",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD30_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD30_WCLK_noedge_posedge,
          HoldLow                 => thold_WD30_WCLK_noedge_posedge,
          HoldHigh                => thold_WD30_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD31_WCLK_posedge,
          TimingData              => Tmkr_WD31_WCLK_posedge,
          TestSignal              => WD31_ipd,
          TestSignalName          => "WD31",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD31_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD31_WCLK_noedge_posedge,
          HoldLow                 => thold_WD31_WCLK_noedge_posedge,
          HoldHigh                => thold_WD31_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD11_RCLK_posedge,
          TimingData              => Tmkr_RAD11_RCLK_posedge,
          TestSignal              => RAD11_ipd,
          TestSignalName          => "RAD11",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD11_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD11_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD11_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD11_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or
                 Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or
                 Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or
                 Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or
                 Tviol_WD15_WCLK_posedge or
                 Tviol_WD16_WCLK_posedge or
                 Tviol_WD17_WCLK_posedge or
                 Tviol_WD18_WCLK_posedge or
                 Tviol_WD19_WCLK_posedge or
                 Tviol_WD20_WCLK_posedge or
                 Tviol_WD21_WCLK_posedge or
                 Tviol_WD22_WCLK_posedge or
                 Tviol_WD23_WCLK_posedge or
                 Tviol_WD24_WCLK_posedge or
                 Tviol_WD25_WCLK_posedge or
                 Tviol_WD26_WCLK_posedge or
                 Tviol_WD27_WCLK_posedge or
                 Tviol_WD28_WCLK_posedge or
                 Tviol_WD29_WCLK_posedge or
                 Tviol_WD30_WCLK_posedge or
                 Tviol_WD31_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or
                 Tviol_RAD1_RCLK_posedge or
                 Tviol_RAD2_RCLK_posedge or
                 Tviol_RAD3_RCLK_posedge or
                 Tviol_RAD4_RCLK_posedge or
                 Tviol_RAD5_RCLK_posedge or
                 Tviol_RAD6_RCLK_posedge or
                 Tviol_RAD7_RCLK_posedge or
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RAD9_RCLK_posedge or
                 Tviol_RAD10_RCLK_posedge or
                 Tviol_RAD11_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 9,
		WDATA_WIDTH    => 32,
		RADDR_WIDTH    => 12,
		RDATA_WIDTH    => 4,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16K_WX32_RX4_VITAL of RAMB16K_WX32_RX4 is
   for VITAL
   end for;
end CFG_RAMB16K_WX32_RX4_VITAL;


----- CELL RAMB16K_WX32_RX8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX32_RX8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD4                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD5                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD6                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD7                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD16_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD16_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD17_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD17_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD18_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD18_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD19_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD19_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD20_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD20_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD21_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD21_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD22_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD22_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD23_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD23_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD24_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD24_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD25_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD25_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD26_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD26_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD27_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD27_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD28_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD28_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD29_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD29_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD30_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD30_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD31_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD31_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD16                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD17                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD18                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD19                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD20                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD21                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD22                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD23                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD24                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD25                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD26                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD27                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD28                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD29                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD30                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD31                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WD16                            :	in    STD_ULOGIC;
      WD17                            :	in    STD_ULOGIC;
      WD18                            :	in    STD_ULOGIC;
      WD19                            :	in    STD_ULOGIC;
      WD20                            :	in    STD_ULOGIC;
      WD21                            :	in    STD_ULOGIC;
      WD22                            :	in    STD_ULOGIC;
      WD23                            :	in    STD_ULOGIC;
      WD24                            :	in    STD_ULOGIC;
      WD25                            :	in    STD_ULOGIC;
      WD26                            :	in    STD_ULOGIC;
      WD27                            :	in    STD_ULOGIC;
      WD28                            :	in    STD_ULOGIC;
      WD29                            :	in    STD_ULOGIC;
      WD30                            :	in    STD_ULOGIC;
      WD31                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC;
      RD2                            :	out    STD_ULOGIC;
      RD3                            :	out    STD_ULOGIC;
      RD4                            :	out    STD_ULOGIC;
      RD5                            :	out    STD_ULOGIC;
      RD6                            :	out    STD_ULOGIC;
      RD7                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16K_WX32_RX8 : entity is FALSE;
end RAMB16K_WX32_RX8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX32_RX8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';
      signal WD16_ipd      : std_ulogic := 'X';
      signal WD17_ipd      : std_ulogic := 'X';
      signal WD18_ipd      : std_ulogic := 'X';
      signal WD19_ipd      : std_ulogic := 'X';
      signal WD20_ipd      : std_ulogic := 'X';
      signal WD21_ipd      : std_ulogic := 'X';
      signal WD22_ipd      : std_ulogic := 'X';
      signal WD23_ipd      : std_ulogic := 'X';
      signal WD24_ipd      : std_ulogic := 'X';
      signal WD25_ipd      : std_ulogic := 'X';
      signal WD26_ipd      : std_ulogic := 'X';
      signal WD27_ipd      : std_ulogic := 'X';
      signal WD28_ipd      : std_ulogic := 'X';
      signal WD29_ipd      : std_ulogic := 'X';
      signal WD30_ipd      : std_ulogic := 'X';
      signal WD31_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (31 downto 0);
 	signal WAD : std_logic_vector (8 downto 0);
 	signal RAD : std_logic_vector (10 downto 0);
	signal RD  : std_logic_vector (7 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD31_ipd & WD30_ipd & WD29_ipd & WD28_ipd & WD27_ipd & WD26_ipd & WD25_ipd & WD24_ipd & WD23_ipd & WD22_ipd & WD21_ipd & WD20_ipd & WD19_ipd & WD18_ipd & WD17_ipd & WD16_ipd & WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);
        VitalWireDelay (WD16_ipd, WD16, tipd_WD16);
        VitalWireDelay (WD17_ipd, WD17, tipd_WD17);
        VitalWireDelay (WD18_ipd, WD18, tipd_WD18);
        VitalWireDelay (WD19_ipd, WD19, tipd_WD19);
        VitalWireDelay (WD20_ipd, WD20, tipd_WD20);
        VitalWireDelay (WD21_ipd, WD21, tipd_WD21);
        VitalWireDelay (WD22_ipd, WD22, tipd_WD22);
        VitalWireDelay (WD23_ipd, WD23, tipd_WD23);
        VitalWireDelay (WD24_ipd, WD24, tipd_WD24);
        VitalWireDelay (WD25_ipd, WD25, tipd_WD25);
        VitalWireDelay (WD26_ipd, WD26, tipd_WD26);
        VitalWireDelay (WD27_ipd, WD27, tipd_WD27);
        VitalWireDelay (WD28_ipd, WD28, tipd_WD28);
        VitalWireDelay (WD29_ipd, WD29, tipd_WD29);
        VitalWireDelay (WD30_ipd, WD30, tipd_WD30);
        VitalWireDelay (WD31_ipd, WD31, tipd_WD31);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD16_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD17_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD18_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD19_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD20_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD21_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD22_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD23_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD24_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD25_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD26_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD27_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD28_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD29_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD30_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD31_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD16_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD17_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD18_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD19_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD20_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD21_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD22_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD23_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD24_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD25_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD26_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD27_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD28_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD29_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD30_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD31_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;


        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD16_WCLK_posedge,
          TimingData              => Tmkr_WD16_WCLK_posedge,
          TestSignal              => WD16_ipd,
          TestSignalName          => "WD16",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD16_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD16_WCLK_noedge_posedge,
          HoldLow                 => thold_WD16_WCLK_noedge_posedge,
          HoldHigh                => thold_WD16_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD17_WCLK_posedge,
          TimingData              => Tmkr_WD17_WCLK_posedge,
          TestSignal              => WD17_ipd,
          TestSignalName          => "WD17",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD17_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD17_WCLK_noedge_posedge,
          HoldLow                 => thold_WD17_WCLK_noedge_posedge,
          HoldHigh                => thold_WD17_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD18_WCLK_posedge,
          TimingData              => Tmkr_WD18_WCLK_posedge,
          TestSignal              => WD18_ipd,
          TestSignalName          => "WD18",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD18_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD18_WCLK_noedge_posedge,
          HoldLow                 => thold_WD18_WCLK_noedge_posedge,
          HoldHigh                => thold_WD18_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD19_WCLK_posedge,
          TimingData              => Tmkr_WD19_WCLK_posedge,
          TestSignal              => WD19_ipd,
          TestSignalName          => "WD19",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD19_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD19_WCLK_noedge_posedge,
          HoldLow                 => thold_WD19_WCLK_noedge_posedge,
          HoldHigh                => thold_WD19_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD20_WCLK_posedge,
          TimingData              => Tmkr_WD20_WCLK_posedge,
          TestSignal              => WD20_ipd,
          TestSignalName          => "WD20",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD20_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD20_WCLK_noedge_posedge,
          HoldLow                 => thold_WD20_WCLK_noedge_posedge,
          HoldHigh                => thold_WD20_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD21_WCLK_posedge,
          TimingData              => Tmkr_WD21_WCLK_posedge,
          TestSignal              => WD21_ipd,
          TestSignalName          => "WD21",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD21_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD21_WCLK_noedge_posedge,
          HoldLow                 => thold_WD21_WCLK_noedge_posedge,
          HoldHigh                => thold_WD21_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD22_WCLK_posedge,
          TimingData              => Tmkr_WD22_WCLK_posedge,
          TestSignal              => WD22_ipd,
          TestSignalName          => "WD22",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD22_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD22_WCLK_noedge_posedge,
          HoldLow                 => thold_WD22_WCLK_noedge_posedge,
          HoldHigh                => thold_WD22_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD23_WCLK_posedge,
          TimingData              => Tmkr_WD23_WCLK_posedge,
          TestSignal              => WD23_ipd,
          TestSignalName          => "WD23",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD23_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD23_WCLK_noedge_posedge,
          HoldLow                 => thold_WD23_WCLK_noedge_posedge,
          HoldHigh                => thold_WD23_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD24_WCLK_posedge,
          TimingData              => Tmkr_WD24_WCLK_posedge,
          TestSignal              => WD24_ipd,
          TestSignalName          => "WD24",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD24_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD24_WCLK_noedge_posedge,
          HoldLow                 => thold_WD24_WCLK_noedge_posedge,
          HoldHigh                => thold_WD24_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD25_WCLK_posedge,
          TimingData              => Tmkr_WD25_WCLK_posedge,
          TestSignal              => WD25_ipd,
          TestSignalName          => "WD25",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD25_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD25_WCLK_noedge_posedge,
          HoldLow                 => thold_WD25_WCLK_noedge_posedge,
          HoldHigh                => thold_WD25_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD26_WCLK_posedge,
          TimingData              => Tmkr_WD26_WCLK_posedge,
          TestSignal              => WD26_ipd,
          TestSignalName          => "WD26",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD26_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD26_WCLK_noedge_posedge,
          HoldLow                 => thold_WD26_WCLK_noedge_posedge,
          HoldHigh                => thold_WD26_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD27_WCLK_posedge,
          TimingData              => Tmkr_WD27_WCLK_posedge,
          TestSignal              => WD27_ipd,
          TestSignalName          => "WD27",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD27_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD27_WCLK_noedge_posedge,
          HoldLow                 => thold_WD27_WCLK_noedge_posedge,
          HoldHigh                => thold_WD27_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD28_WCLK_posedge,
          TimingData              => Tmkr_WD28_WCLK_posedge,
          TestSignal              => WD28_ipd,
          TestSignalName          => "WD28",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD28_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD28_WCLK_noedge_posedge,
          HoldLow                 => thold_WD28_WCLK_noedge_posedge,
          HoldHigh                => thold_WD28_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD29_WCLK_posedge,
          TimingData              => Tmkr_WD29_WCLK_posedge,
          TestSignal              => WD29_ipd,
          TestSignalName          => "WD29",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD29_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD29_WCLK_noedge_posedge,
          HoldLow                 => thold_WD29_WCLK_noedge_posedge,
          HoldHigh                => thold_WD29_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD30_WCLK_posedge,
          TimingData              => Tmkr_WD30_WCLK_posedge,
          TestSignal              => WD30_ipd,
          TestSignalName          => "WD30",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD30_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD30_WCLK_noedge_posedge,
          HoldLow                 => thold_WD30_WCLK_noedge_posedge,
          HoldHigh                => thold_WD30_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD31_WCLK_posedge,
          TimingData              => Tmkr_WD31_WCLK_posedge,
          TestSignal              => WD31_ipd,
          TestSignalName          => "WD31",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD31_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD31_WCLK_noedge_posedge,
          HoldLow                 => thold_WD31_WCLK_noedge_posedge,
          HoldHigh                => thold_WD31_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or
                 Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or
                 Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or
                 Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or
                 Tviol_WD15_WCLK_posedge or
                 Tviol_WD16_WCLK_posedge or
                 Tviol_WD17_WCLK_posedge or
                 Tviol_WD18_WCLK_posedge or
                 Tviol_WD19_WCLK_posedge or
                 Tviol_WD20_WCLK_posedge or
                 Tviol_WD21_WCLK_posedge or
                 Tviol_WD22_WCLK_posedge or
                 Tviol_WD23_WCLK_posedge or
                 Tviol_WD24_WCLK_posedge or
                 Tviol_WD25_WCLK_posedge or
                 Tviol_WD26_WCLK_posedge or
                 Tviol_WD27_WCLK_posedge or
                 Tviol_WD28_WCLK_posedge or
                 Tviol_WD29_WCLK_posedge or
                 Tviol_WD30_WCLK_posedge or
                 Tviol_WD31_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or
                 Tviol_RAD1_RCLK_posedge or
                 Tviol_RAD2_RCLK_posedge or
                 Tviol_RAD3_RCLK_posedge or
                 Tviol_RAD4_RCLK_posedge or
                 Tviol_RAD5_RCLK_posedge or
                 Tviol_RAD6_RCLK_posedge or
                 Tviol_RAD7_RCLK_posedge or
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RAD9_RCLK_posedge or
                 Tviol_RAD10_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD4, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD5, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD6, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD7, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 9,
		WDATA_WIDTH    => 32,
		RADDR_WIDTH    => 11,
		RDATA_WIDTH    => 8,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16K_WX32_RX8_VITAL of RAMB16K_WX32_RX8 is
   for VITAL
   end for;
end CFG_RAMB16K_WX32_RX8_VITAL;


----- CELL RAMB16K_WX4_RX1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX4_RX1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD11_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD11_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD12_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD12_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD13_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD13_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                            :	in    STD_ULOGIC;
      WAD11                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RAD12                            :	in    STD_ULOGIC;
      RAD13                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16K_WX4_RX1 : entity is FALSE;
end RAMB16K_WX4_RX1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX4_RX1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd      : std_ulogic := 'X';
      signal WAD11_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';
      signal RAD12_ipd      : std_ulogic := 'X';
      signal RAD13_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (3 downto 0);
 	signal WAD : std_logic_vector (11 downto 0);
 	signal RAD : std_logic_vector (13 downto 0);
	signal RD  : std_logic_vector (0 downto 0);
      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);

begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD13_ipd & RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);
        VitalWireDelay (RAD13_ipd, RAD13, tipd_RAD13);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD11_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD12_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD13_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD11_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD12_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD13_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;


        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD11_RCLK_posedge,
          TimingData              => Tmkr_RAD11_RCLK_posedge,
          TestSignal              => RAD11_ipd,
          TestSignalName          => "RAD11",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD11_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD11_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD11_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD11_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD12_RCLK_posedge,
          TimingData              => Tmkr_RAD12_RCLK_posedge,
          TestSignal              => RAD12_ipd,
          TestSignalName          => "RAD12",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD12_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD12_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD12_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD12_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD13_RCLK_posedge,
          TimingData              => Tmkr_RAD13_RCLK_posedge,
          TestSignal              => RAD13_ipd,
          TestSignalName          => "RAD13",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD13_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD13_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD13_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD13_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WAD10_WCLK_posedge or
                 Tviol_WAD11_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or
                 Tviol_RAD1_RCLK_posedge or
                 Tviol_RAD2_RCLK_posedge or
                 Tviol_RAD3_RCLK_posedge or
                 Tviol_RAD4_RCLK_posedge or
                 Tviol_RAD5_RCLK_posedge or
                 Tviol_RAD6_RCLK_posedge or
                 Tviol_RAD7_RCLK_posedge or
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RAD9_RCLK_posedge or
                 Tviol_RAD10_RCLK_posedge or
                 Tviol_RAD11_RCLK_posedge or
                 Tviol_RAD12_RCLK_posedge or
                 Tviol_RAD13_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 12,
		WDATA_WIDTH    => 4,
		RADDR_WIDTH    => 14,
		RDATA_WIDTH    => 1,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16K_WX4_RX1_VITAL of RAMB16K_WX4_RX1 is
   for VITAL
   end for;
end CFG_RAMB16K_WX4_RX1_VITAL;


----- CELL RAMB16K_WX4_RX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX4_RX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD11_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD11_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD12_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD12_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                            :	in    STD_ULOGIC;
      WAD11                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RAD12                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16K_WX4_RX2 : entity is FALSE;
end RAMB16K_WX4_RX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX4_RX2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd      : std_ulogic := 'X';
      signal WAD11_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';
      signal RAD12_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (3 downto 0);
 	signal WAD : std_logic_vector (11 downto 0);
 	signal RAD : std_logic_vector (12 downto 0);
	signal RD  : std_logic_vector (1 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD11_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD12_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD11_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD12_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;


        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD11_RCLK_posedge,
          TimingData              => Tmkr_RAD11_RCLK_posedge,
          TestSignal              => RAD11_ipd,
          TestSignalName          => "RAD11",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD11_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD11_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD11_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD11_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD12_RCLK_posedge,
          TimingData              => Tmkr_RAD12_RCLK_posedge,
          TestSignal              => RAD12_ipd,
          TestSignalName          => "RAD12",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD12_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD12_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD12_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD12_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WAD10_WCLK_posedge or
                 Tviol_WAD11_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or
                 Tviol_RAD1_RCLK_posedge or
                 Tviol_RAD2_RCLK_posedge or
                 Tviol_RAD3_RCLK_posedge or
                 Tviol_RAD4_RCLK_posedge or
                 Tviol_RAD5_RCLK_posedge or
                 Tviol_RAD6_RCLK_posedge or
                 Tviol_RAD7_RCLK_posedge or
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RAD9_RCLK_posedge or
                 Tviol_RAD10_RCLK_posedge or
                 Tviol_RAD11_RCLK_posedge or
                 Tviol_RAD12_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 12,
		WDATA_WIDTH    => 4,
		RADDR_WIDTH    => 13,
		RDATA_WIDTH    => 2,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16K_WX4_RX2_VITAL of RAMB16K_WX4_RX2 is
   for VITAL
   end for;
end CFG_RAMB16K_WX4_RX2_VITAL;


----- CELL RAMB16K_WX8_RX1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX8_RX1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD11_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD11_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD12_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD12_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD13_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD13_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RAD12                            :	in    STD_ULOGIC;
      RAD13                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16K_WX8_RX1 : entity is FALSE;
end RAMB16K_WX8_RX1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX8_RX1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';
      signal RAD12_ipd      : std_ulogic := 'X';
      signal RAD13_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (7 downto 0);
 	signal WAD : std_logic_vector (10 downto 0);
 	signal RAD : std_logic_vector (13 downto 0);
	signal RD  : std_logic_vector (0 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD13_ipd & RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);
        VitalWireDelay (RAD13_ipd, RAD13, tipd_RAD13);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD11_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD12_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD13_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD11_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD12_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD13_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;


        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD11_RCLK_posedge,
          TimingData              => Tmkr_RAD11_RCLK_posedge,
          TestSignal              => RAD11_ipd,
          TestSignalName          => "RAD11",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD11_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD11_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD11_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD11_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD12_RCLK_posedge,
          TimingData              => Tmkr_RAD12_RCLK_posedge,
          TestSignal              => RAD12_ipd,
          TestSignalName          => "RAD12",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD12_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD12_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD12_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD12_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD13_RCLK_posedge,
          TimingData              => Tmkr_RAD13_RCLK_posedge,
          TestSignal              => RAD13_ipd,
          TestSignalName          => "RAD13",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD13_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD13_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD13_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD13_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WAD10_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or
                 Tviol_RAD1_RCLK_posedge or
                 Tviol_RAD2_RCLK_posedge or
                 Tviol_RAD3_RCLK_posedge or
                 Tviol_RAD4_RCLK_posedge or
                 Tviol_RAD5_RCLK_posedge or
                 Tviol_RAD6_RCLK_posedge or
                 Tviol_RAD7_RCLK_posedge or
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RAD9_RCLK_posedge or
                 Tviol_RAD10_RCLK_posedge or
                 Tviol_RAD11_RCLK_posedge or
                 Tviol_RAD12_RCLK_posedge or
                 Tviol_RAD13_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 11,
		WDATA_WIDTH    => 8,
		RADDR_WIDTH    => 14,
		RDATA_WIDTH    => 1,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16K_WX8_RX1_VITAL of RAMB16K_WX8_RX1 is
   for VITAL
   end for;
end CFG_RAMB16K_WX8_RX1_VITAL;


----- CELL RAMB16K_WX8_RX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX8_RX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD11_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD11_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD12_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD12_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RAD12                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16K_WX8_RX2 : entity is FALSE;
end RAMB16K_WX8_RX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX8_RX2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';
      signal RAD12_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (7 downto 0);
 	signal WAD : std_logic_vector (10 downto 0);
 	signal RAD : std_logic_vector (12 downto 0);
	signal RD  : std_logic_vector (1 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD11_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD12_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD11_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD12_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;


        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD11_RCLK_posedge,
          TimingData              => Tmkr_RAD11_RCLK_posedge,
          TestSignal              => RAD11_ipd,
          TestSignalName          => "RAD11",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD11_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD11_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD11_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD11_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD12_RCLK_posedge,
          TimingData              => Tmkr_RAD12_RCLK_posedge,
          TestSignal              => RAD12_ipd,
          TestSignalName          => "RAD12",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD12_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD12_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD12_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD12_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WAD10_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or
                 Tviol_RAD1_RCLK_posedge or
                 Tviol_RAD2_RCLK_posedge or
                 Tviol_RAD3_RCLK_posedge or
                 Tviol_RAD4_RCLK_posedge or
                 Tviol_RAD5_RCLK_posedge or
                 Tviol_RAD6_RCLK_posedge or
                 Tviol_RAD7_RCLK_posedge or
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RAD9_RCLK_posedge or
                 Tviol_RAD10_RCLK_posedge or
                 Tviol_RAD11_RCLK_posedge or
                 Tviol_RAD12_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 11,
		WDATA_WIDTH    => 8,
		RADDR_WIDTH    => 13,
		RDATA_WIDTH    => 2,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16K_WX8_RX2_VITAL of RAMB16K_WX8_RX2 is
   for VITAL
   end for;
end CFG_RAMB16K_WX8_RX2_VITAL;


----- CELL RAMB16K_WX8_RX4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16K_WX8_RX4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RCLK_RD0                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD1                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD2                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RCLK_RD3                     :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_RCEN_RCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_RCEN_RCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_RAD0_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD0_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD1_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD1_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD2_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD2_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD3_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD3_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD4_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD4_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD5_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD5_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD6_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD6_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD7_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD7_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD8_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD8_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD9_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD9_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD10_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD10_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_RAD11_RCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_RAD11_RCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      trecovery_RST_RCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_RCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;
      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RCEN                            :	in    STD_ULOGIC;
      RCLK                            :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC;
      RD2                            :	out    STD_ULOGIC;
      RD3                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16K_WX8_RX4 : entity is FALSE;
end RAMB16K_WX8_RX4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16K_WX8_RX4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAM_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RCLK : in  STD_LOGIC;
		RCEN : in  STD_LOGIC;
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RCEN_ipd      : std_ulogic := 'X';
      signal RCLK_ipd      : std_ulogic := 'X';
      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (7 downto 0);
 	signal WAD : std_logic_vector (10 downto 0);
 	signal RAD : std_logic_vector (11 downto 0);
	signal RD  : std_logic_vector (3 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RCEN_ipd, RCEN, tipd_RCEN);
        VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_RCEN_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RAD0_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD1_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD2_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD3_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD4_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD5_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD6_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD7_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD8_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD9_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD10_RCLK_posedge    : std_ulogic  := '0';
        variable Tviol_RAD11_RCLK_posedge    : std_ulogic  := '0';

        variable Tviol_RST_RCLK_posedge_posedge   : std_ulogic  := '0';

        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RCEN_RCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_RAD0_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD1_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD2_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD3_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD4_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD5_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD6_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD7_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD8_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD9_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD10_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_RAD11_RCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;


        variable Tmkr_RST_RCLK_posedge_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RCLK       : std_ulogic := '0';
        variable PInfo_RCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RCEN_RCLK_posedge,
          TimingData              => Tmkr_RCEN_RCLK_posedge,
          TestSignal              => RCEN_ipd,
          TestSignalName          => "RCEN",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RCEN_RCLK_noedge_posedge,
          SetupLow                => tsetup_RCEN_RCLK_noedge_posedge,
          HoldLow                 => thold_RCEN_RCLK_noedge_posedge,
          HoldHigh                => thold_RCEN_RCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalRecoveryRemovalCheck (
          Violation               => Tviol_RST_RCLK_posedge_posedge,
          TimingData              => Tmkr_RST_RCLK_posedge_posedge,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName          => "RCLK",
          RefDelay                => 0 ns,
          Recovery                => trecovery_RST_RCLK_posedge_posedge,
          Removal                 => thold_RST_RCLK_posedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RCLK,
          PeriodData              => PInfo_RCLK,
          TestSignal              => RCLK_ipd,
          TestSignalName          => "RCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RCLK_posedge,
          PulseWidthLow           => tpw_RCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD0_RCLK_posedge,
          TimingData              => Tmkr_RAD0_RCLK_posedge,
          TestSignal              => RAD0_ipd,
          TestSignalName          => "RAD0",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD0_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD0_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD0_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD0_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD1_RCLK_posedge,
          TimingData              => Tmkr_RAD1_RCLK_posedge,
          TestSignal              => RAD1_ipd,
          TestSignalName          => "RAD1",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD1_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD1_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD1_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD1_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD2_RCLK_posedge,
          TimingData              => Tmkr_RAD2_RCLK_posedge,
          TestSignal              => RAD2_ipd,
          TestSignalName          => "RAD2",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD2_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD2_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD2_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD2_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD3_RCLK_posedge,
          TimingData              => Tmkr_RAD3_RCLK_posedge,
          TestSignal              => RAD3_ipd,
          TestSignalName          => "RAD3",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD3_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD3_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD3_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD3_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD4_RCLK_posedge,
          TimingData              => Tmkr_RAD4_RCLK_posedge,
          TestSignal              => RAD4_ipd,
          TestSignalName          => "RAD4",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD4_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD4_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD4_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD4_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD5_RCLK_posedge,
          TimingData              => Tmkr_RAD5_RCLK_posedge,
          TestSignal              => RAD5_ipd,
          TestSignalName          => "RAD5",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD5_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD5_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD5_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD5_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD6_RCLK_posedge,
          TimingData              => Tmkr_RAD6_RCLK_posedge,
          TestSignal              => RAD6_ipd,
          TestSignalName          => "RAD6",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD6_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD6_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD6_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD6_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD7_RCLK_posedge,
          TimingData              => Tmkr_RAD7_RCLK_posedge,
          TestSignal              => RAD7_ipd,
          TestSignalName          => "RAD7",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD7_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD7_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD7_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD7_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD8_RCLK_posedge,
          TimingData              => Tmkr_RAD8_RCLK_posedge,
          TestSignal              => RAD8_ipd,
          TestSignalName          => "RAD8",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD8_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD8_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD8_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD8_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD9_RCLK_posedge,
          TimingData              => Tmkr_RAD9_RCLK_posedge,
          TestSignal              => RAD9_ipd,
          TestSignalName          => "RAD9",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD9_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD9_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD9_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD9_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD10_RCLK_posedge,
          TimingData              => Tmkr_RAD10_RCLK_posedge,
          TestSignal              => RAD10_ipd,
          TestSignalName          => "RAD10",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD10_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD10_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD10_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD10_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_RAD11_RCLK_posedge,
          TimingData              => Tmkr_RAD11_RCLK_posedge,
          TestSignal              => RAD11_ipd,
          TestSignalName          => "RAD11",
          TestDelay               => 0 ns,
          RefSignal               => RCLK_ipd,
          RefSignalName           => "RCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_RAD11_RCLK_noedge_posedge,
          SetupLow                => tsetup_RAD11_RCLK_noedge_posedge,
          HoldLow                 => thold_RAD11_RCLK_noedge_posedge,
          HoldHigh                => thold_RAD11_RCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16K_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WAD10_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_RAD0_RCLK_posedge or
                 Tviol_RAD1_RCLK_posedge or
                 Tviol_RAD2_RCLK_posedge or
                 Tviol_RAD3_RCLK_posedge or
                 Tviol_RAD4_RCLK_posedge or
                 Tviol_RAD5_RCLK_posedge or
                 Tviol_RAD6_RCLK_posedge or
                 Tviol_RAD7_RCLK_posedge or
                 Tviol_RAD8_RCLK_posedge or
                 Tviol_RAD9_RCLK_posedge or
                 Tviol_RAD10_RCLK_posedge or
                 Tviol_RAD11_RCLK_posedge or
                 Tviol_RST_RCLK_posedge_posedge or 
                 Pviol_WCLK or Pviol_RCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RCLK_ipd, RCEN_ipd, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD0, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD1, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD2, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (0 => (RCLK_ipd'last_event, tpd_RCLK_RD3, TRUE),
                1 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

	PDPRAM_INST: SC_PDPRAM_16K
	   generic map (
		WADDR_WIDTH    => 11,
		WDATA_WIDTH    => 8,
		RADDR_WIDTH    => 12,
		RDATA_WIDTH    => 4,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RCLK => RCLK_ipd,
		RCEN => RCEN_ipd,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16K_WX8_RX4_VITAL of RAMB16K_WX8_RX4 is
   for VITAL
   end for;
end CFG_RAMB16K_WX8_RX4_VITAL;


----- CELL RAMB16KA_WX16_RX1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16KA_WX16_RX1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD12_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD13_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

     
      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RAD12                            :	in    STD_ULOGIC;
      RAD13                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16KA_WX16_RX1 : entity is FALSE;
end RAMB16KA_WX16_RX1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX16_RX1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';
      signal RAD12_ipd      : std_ulogic := 'X';
      signal RAD13_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (15 downto 0);
 	signal WAD : std_logic_vector (9 downto 0);
 	signal RAD : std_logic_vector (13 downto 0);
	signal RD  : std_logic_vector (0 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD13_ipd & RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);
        VitalWireDelay (RAD13_ipd, RAD13, tipd_RAD13);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';

 
        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

      
        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or
                 Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or
                 Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or
                 Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or
                 Tviol_WD15_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD0, TRUE),
               12 => (RAD12_ipd'last_event, tpd_RAD12_RD0, TRUE),
               13 => (RAD13_ipd'last_event, tpd_RAD13_RD0, TRUE),
               14 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 10,
		WDATA_WIDTH    => 16,
		RADDR_WIDTH    => 14,
		RDATA_WIDTH    => 1,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16KA_WX16_RX1_VITAL of RAMB16KA_WX16_RX1 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX16_RX1_VITAL;


----- CELL RAMB16KA_WX16_RX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16KA_WX16_RX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD12_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD12_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

     
      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RAD12                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16KA_WX16_RX2 : entity is FALSE;
end RAMB16KA_WX16_RX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX16_RX2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';
      signal RAD12_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (15 downto 0);
 	signal WAD : std_logic_vector (9 downto 0);
 	signal RAD : std_logic_vector (12 downto 0);
	signal RD  : std_logic_vector (1 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';

 
        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

      
        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or
                 Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or
                 Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or
                 Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or
                 Tviol_WD15_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD0, TRUE),
               12 => (RAD12_ipd'last_event, tpd_RAD12_RD0, TRUE),
               13 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD1, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD1, TRUE),
               12 => (RAD12_ipd'last_event, tpd_RAD12_RD1, TRUE),
               13 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 10,
		WDATA_WIDTH    => 16,
		RADDR_WIDTH    => 13,
		RDATA_WIDTH    => 2,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16KA_WX16_RX2_VITAL of RAMB16KA_WX16_RX2 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX16_RX2_VITAL;


----- CELL RAMB16KA_WX16_RX4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16KA_WX16_RX4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

     
      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC;
      RD2                            :	out    STD_ULOGIC;
      RD3                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16KA_WX16_RX4 : entity is FALSE;
end RAMB16KA_WX16_RX4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX16_RX4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (15 downto 0);
 	signal WAD : std_logic_vector (9 downto 0);
 	signal RAD : std_logic_vector (11 downto 0);
	signal RD  : std_logic_vector (3 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';

 
        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

      
        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or
                 Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or
                 Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or
                 Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or
                 Tviol_WD15_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD0, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD1, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD1, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD2, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD2, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD2, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD3, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD3, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD3, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 10,
		WDATA_WIDTH    => 16,
		RADDR_WIDTH    => 12,
		RDATA_WIDTH    => 4,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16KA_WX16_RX4_VITAL of RAMB16KA_WX16_RX4 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX16_RX4_VITAL;


----- CELL RAMB16KA_WX16_RX8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16KA_WX16_RX8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

     
      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC;
      RD2                            :	out    STD_ULOGIC;
      RD3                            :	out    STD_ULOGIC;
      RD4                            :	out    STD_ULOGIC;
      RD5                            :	out    STD_ULOGIC;
      RD6                            :	out    STD_ULOGIC;
      RD7                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16KA_WX16_RX8 : entity is FALSE;
end RAMB16KA_WX16_RX8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX16_RX8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (15 downto 0);
 	signal WAD : std_logic_vector (9 downto 0);
 	signal RAD : std_logic_vector (10 downto 0);
	signal RD  : std_logic_vector (7 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';

 
        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

      
        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX16_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or
                 Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or
                 Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or
                 Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or
                 Tviol_WD15_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD1, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD2, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD2, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD3, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD3, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD4, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD4, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD4, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD4, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD4, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD4, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD4, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD4, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD4, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD4, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD4, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD5, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD5, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD5, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD5, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD5, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD5, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD5, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD5, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD5, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD5, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD5, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD6, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD6, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD6, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD6, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD6, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD6, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD6, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD6, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD6, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD6, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD6, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD7, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD7, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD7, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD7, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD7, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD7, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD7, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD7, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD7, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD7, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD7, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 10,
		WDATA_WIDTH    => 16,
		RADDR_WIDTH    => 11,
		RDATA_WIDTH    => 8,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16KA_WX16_RX8_VITAL of RAMB16KA_WX16_RX8 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX16_RX8_VITAL;


----- CELL RAMB16KA_WX2_RX1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16KA_WX2_RX1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD12_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD13_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD12_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

     
      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                            :	in    STD_ULOGIC;
      WAD11                            :	in    STD_ULOGIC;
      WAD12                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RAD12                            :	in    STD_ULOGIC;
      RAD13                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16KA_WX2_RX1 : entity is FALSE;
end RAMB16KA_WX2_RX1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX2_RX1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd      : std_ulogic := 'X';
      signal WAD11_ipd      : std_ulogic := 'X';
      signal WAD12_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';
      signal RAD12_ipd      : std_ulogic := 'X';
      signal RAD13_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (1 downto 0);
 	signal WAD : std_logic_vector (12 downto 0);
 	signal RAD : std_logic_vector (13 downto 0);
	signal RD  : std_logic_vector (0 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD1_ipd & WD0_ipd;
	WAD <= WAD12_ipd & WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD13_ipd & RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);
        VitalWireDelay (WAD12_ipd, WAD12, tipd_WAD12);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);
        VitalWireDelay (RAD13_ipd, RAD13, tipd_RAD13);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD12_WCLK_posedge    : std_ulogic  := '0';

 
        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

      
        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD12_WCLK_posedge,
          TimingData              => Tmkr_WAD12_WCLK_posedge,
          TestSignal              => WAD12_ipd,
          TestSignalName          => "WAD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX2_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WAD10_WCLK_posedge or
                 Tviol_WAD11_WCLK_posedge or
                 Tviol_WAD12_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD0, TRUE),
               12 => (RAD12_ipd'last_event, tpd_RAD12_RD0, TRUE),
               13 => (RAD13_ipd'last_event, tpd_RAD13_RD0, TRUE),
               14 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 13,
		WDATA_WIDTH    => 2,
		RADDR_WIDTH    => 14,
		RDATA_WIDTH    => 1,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16KA_WX2_RX1_VITAL of RAMB16KA_WX2_RX1 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX2_RX1_VITAL;


----- CELL RAMB16KA_WX32_RX1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16KA_WX32_RX1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD12_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD13_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD16_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD16_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD17_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD17_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD18_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD18_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD19_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD19_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD20_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD20_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD21_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD21_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD22_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD22_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD23_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD23_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD24_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD24_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD25_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD25_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD26_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD26_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD27_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD27_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD28_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD28_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD29_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD29_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD30_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD30_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD31_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD31_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

     
      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD16                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD17                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD18                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD19                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD20                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD21                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD22                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD23                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD24                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD25                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD26                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD27                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD28                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD29                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD30                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD31                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WD16                            :	in    STD_ULOGIC;
      WD17                            :	in    STD_ULOGIC;
      WD18                            :	in    STD_ULOGIC;
      WD19                            :	in    STD_ULOGIC;
      WD20                            :	in    STD_ULOGIC;
      WD21                            :	in    STD_ULOGIC;
      WD22                            :	in    STD_ULOGIC;
      WD23                            :	in    STD_ULOGIC;
      WD24                            :	in    STD_ULOGIC;
      WD25                            :	in    STD_ULOGIC;
      WD26                            :	in    STD_ULOGIC;
      WD27                            :	in    STD_ULOGIC;
      WD28                            :	in    STD_ULOGIC;
      WD29                            :	in    STD_ULOGIC;
      WD30                            :	in    STD_ULOGIC;
      WD31                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RAD12                            :	in    STD_ULOGIC;
      RAD13                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16KA_WX32_RX1 : entity is FALSE;
end RAMB16KA_WX32_RX1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX32_RX1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';
      signal WD16_ipd      : std_ulogic := 'X';
      signal WD17_ipd      : std_ulogic := 'X';
      signal WD18_ipd      : std_ulogic := 'X';
      signal WD19_ipd      : std_ulogic := 'X';
      signal WD20_ipd      : std_ulogic := 'X';
      signal WD21_ipd      : std_ulogic := 'X';
      signal WD22_ipd      : std_ulogic := 'X';
      signal WD23_ipd      : std_ulogic := 'X';
      signal WD24_ipd      : std_ulogic := 'X';
      signal WD25_ipd      : std_ulogic := 'X';
      signal WD26_ipd      : std_ulogic := 'X';
      signal WD27_ipd      : std_ulogic := 'X';
      signal WD28_ipd      : std_ulogic := 'X';
      signal WD29_ipd      : std_ulogic := 'X';
      signal WD30_ipd      : std_ulogic := 'X';
      signal WD31_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';
      signal RAD12_ipd      : std_ulogic := 'X';
      signal RAD13_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (31 downto 0);
 	signal WAD : std_logic_vector (8 downto 0);
 	signal RAD : std_logic_vector (13 downto 0);
	signal RD  : std_logic_vector (0 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD31_ipd & WD30_ipd & WD29_ipd & WD28_ipd & WD27_ipd & WD26_ipd & WD25_ipd & WD24_ipd & WD23_ipd & WD22_ipd & WD21_ipd & WD20_ipd & WD19_ipd & WD18_ipd & WD17_ipd & WD16_ipd & WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD13_ipd & RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);
        VitalWireDelay (WD16_ipd, WD16, tipd_WD16);
        VitalWireDelay (WD17_ipd, WD17, tipd_WD17);
        VitalWireDelay (WD18_ipd, WD18, tipd_WD18);
        VitalWireDelay (WD19_ipd, WD19, tipd_WD19);
        VitalWireDelay (WD20_ipd, WD20, tipd_WD20);
        VitalWireDelay (WD21_ipd, WD21, tipd_WD21);
        VitalWireDelay (WD22_ipd, WD22, tipd_WD22);
        VitalWireDelay (WD23_ipd, WD23, tipd_WD23);
        VitalWireDelay (WD24_ipd, WD24, tipd_WD24);
        VitalWireDelay (WD25_ipd, WD25, tipd_WD25);
        VitalWireDelay (WD26_ipd, WD26, tipd_WD26);
        VitalWireDelay (WD27_ipd, WD27, tipd_WD27);
        VitalWireDelay (WD28_ipd, WD28, tipd_WD28);
        VitalWireDelay (WD29_ipd, WD29, tipd_WD29);
        VitalWireDelay (WD30_ipd, WD30, tipd_WD30);
        VitalWireDelay (WD31_ipd, WD31, tipd_WD31);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);
        VitalWireDelay (RAD13_ipd, RAD13, tipd_RAD13);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD16_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD17_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD18_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD19_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD20_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD21_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD22_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD23_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD24_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD25_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD26_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD27_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD28_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD29_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD30_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD31_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';

 
        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD16_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD17_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD18_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD19_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD20_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD21_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD22_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD23_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD24_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD25_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD26_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD27_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD28_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD29_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD30_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD31_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

      
        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD16_WCLK_posedge,
          TimingData              => Tmkr_WD16_WCLK_posedge,
          TestSignal              => WD16_ipd,
          TestSignalName          => "WD16",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD16_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD16_WCLK_noedge_posedge,
          HoldLow                 => thold_WD16_WCLK_noedge_posedge,
          HoldHigh                => thold_WD16_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD17_WCLK_posedge,
          TimingData              => Tmkr_WD17_WCLK_posedge,
          TestSignal              => WD17_ipd,
          TestSignalName          => "WD17",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD17_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD17_WCLK_noedge_posedge,
          HoldLow                 => thold_WD17_WCLK_noedge_posedge,
          HoldHigh                => thold_WD17_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD18_WCLK_posedge,
          TimingData              => Tmkr_WD18_WCLK_posedge,
          TestSignal              => WD18_ipd,
          TestSignalName          => "WD18",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD18_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD18_WCLK_noedge_posedge,
          HoldLow                 => thold_WD18_WCLK_noedge_posedge,
          HoldHigh                => thold_WD18_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD19_WCLK_posedge,
          TimingData              => Tmkr_WD19_WCLK_posedge,
          TestSignal              => WD19_ipd,
          TestSignalName          => "WD19",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD19_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD19_WCLK_noedge_posedge,
          HoldLow                 => thold_WD19_WCLK_noedge_posedge,
          HoldHigh                => thold_WD19_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD20_WCLK_posedge,
          TimingData              => Tmkr_WD20_WCLK_posedge,
          TestSignal              => WD20_ipd,
          TestSignalName          => "WD20",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD20_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD20_WCLK_noedge_posedge,
          HoldLow                 => thold_WD20_WCLK_noedge_posedge,
          HoldHigh                => thold_WD20_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD21_WCLK_posedge,
          TimingData              => Tmkr_WD21_WCLK_posedge,
          TestSignal              => WD21_ipd,
          TestSignalName          => "WD21",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD21_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD21_WCLK_noedge_posedge,
          HoldLow                 => thold_WD21_WCLK_noedge_posedge,
          HoldHigh                => thold_WD21_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD22_WCLK_posedge,
          TimingData              => Tmkr_WD22_WCLK_posedge,
          TestSignal              => WD22_ipd,
          TestSignalName          => "WD22",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD22_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD22_WCLK_noedge_posedge,
          HoldLow                 => thold_WD22_WCLK_noedge_posedge,
          HoldHigh                => thold_WD22_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD23_WCLK_posedge,
          TimingData              => Tmkr_WD23_WCLK_posedge,
          TestSignal              => WD23_ipd,
          TestSignalName          => "WD23",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD23_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD23_WCLK_noedge_posedge,
          HoldLow                 => thold_WD23_WCLK_noedge_posedge,
          HoldHigh                => thold_WD23_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD24_WCLK_posedge,
          TimingData              => Tmkr_WD24_WCLK_posedge,
          TestSignal              => WD24_ipd,
          TestSignalName          => "WD24",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD24_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD24_WCLK_noedge_posedge,
          HoldLow                 => thold_WD24_WCLK_noedge_posedge,
          HoldHigh                => thold_WD24_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD25_WCLK_posedge,
          TimingData              => Tmkr_WD25_WCLK_posedge,
          TestSignal              => WD25_ipd,
          TestSignalName          => "WD25",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD25_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD25_WCLK_noedge_posedge,
          HoldLow                 => thold_WD25_WCLK_noedge_posedge,
          HoldHigh                => thold_WD25_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD26_WCLK_posedge,
          TimingData              => Tmkr_WD26_WCLK_posedge,
          TestSignal              => WD26_ipd,
          TestSignalName          => "WD26",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD26_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD26_WCLK_noedge_posedge,
          HoldLow                 => thold_WD26_WCLK_noedge_posedge,
          HoldHigh                => thold_WD26_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD27_WCLK_posedge,
          TimingData              => Tmkr_WD27_WCLK_posedge,
          TestSignal              => WD27_ipd,
          TestSignalName          => "WD27",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD27_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD27_WCLK_noedge_posedge,
          HoldLow                 => thold_WD27_WCLK_noedge_posedge,
          HoldHigh                => thold_WD27_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD28_WCLK_posedge,
          TimingData              => Tmkr_WD28_WCLK_posedge,
          TestSignal              => WD28_ipd,
          TestSignalName          => "WD28",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD28_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD28_WCLK_noedge_posedge,
          HoldLow                 => thold_WD28_WCLK_noedge_posedge,
          HoldHigh                => thold_WD28_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD29_WCLK_posedge,
          TimingData              => Tmkr_WD29_WCLK_posedge,
          TestSignal              => WD29_ipd,
          TestSignalName          => "WD29",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD29_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD29_WCLK_noedge_posedge,
          HoldLow                 => thold_WD29_WCLK_noedge_posedge,
          HoldHigh                => thold_WD29_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD30_WCLK_posedge,
          TimingData              => Tmkr_WD30_WCLK_posedge,
          TestSignal              => WD30_ipd,
          TestSignalName          => "WD30",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD30_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD30_WCLK_noedge_posedge,
          HoldLow                 => thold_WD30_WCLK_noedge_posedge,
          HoldHigh                => thold_WD30_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD31_WCLK_posedge,
          TimingData              => Tmkr_WD31_WCLK_posedge,
          TestSignal              => WD31_ipd,
          TestSignalName          => "WD31",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD31_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD31_WCLK_noedge_posedge,
          HoldLow                 => thold_WD31_WCLK_noedge_posedge,
          HoldHigh                => thold_WD31_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or
                 Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or
                 Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or
                 Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or
                 Tviol_WD15_WCLK_posedge or
                 Tviol_WD16_WCLK_posedge or
                 Tviol_WD17_WCLK_posedge or
                 Tviol_WD18_WCLK_posedge or
                 Tviol_WD19_WCLK_posedge or
                 Tviol_WD20_WCLK_posedge or
                 Tviol_WD21_WCLK_posedge or
                 Tviol_WD22_WCLK_posedge or
                 Tviol_WD23_WCLK_posedge or
                 Tviol_WD24_WCLK_posedge or
                 Tviol_WD25_WCLK_posedge or
                 Tviol_WD26_WCLK_posedge or
                 Tviol_WD27_WCLK_posedge or
                 Tviol_WD28_WCLK_posedge or
                 Tviol_WD29_WCLK_posedge or
                 Tviol_WD30_WCLK_posedge or
                 Tviol_WD31_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD0, TRUE),
               12 => (RAD12_ipd'last_event, tpd_RAD12_RD0, TRUE),
               13 => (RAD13_ipd'last_event, tpd_RAD13_RD0, TRUE),
               14 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 9,
		WDATA_WIDTH    => 32,
		RADDR_WIDTH    => 14,
		RDATA_WIDTH    => 1,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16KA_WX32_RX1_VITAL of RAMB16KA_WX32_RX1 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX32_RX1_VITAL;


----- CELL RAMB16KA_WX32_RX16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16KA_WX32_RX16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD8                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD9                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD10                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD11                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD12                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD13                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD14                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD15                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD8                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD8                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD8                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD8                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD8                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD8                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD8                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD8                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD8                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD8                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD9                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD9                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD9                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD9                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD9                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD9                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD9                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD9                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD9                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD9                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD10                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD10                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD10                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD10                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD10                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD10                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD10                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD10                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD10                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD10                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD11                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD11                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD11                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD11                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD11                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD11                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD11                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD11                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD11                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD11                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD12                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD12                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD12                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD12                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD12                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD12                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD12                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD12                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD12                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD12                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD13                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD13                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD13                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD13                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD13                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD13                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD13                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD13                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD13                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD13                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD14                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD14                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD14                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD14                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD14                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD14                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD14                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD14                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD14                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD14                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD15                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD15                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD15                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD15                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD15                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD15                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD15                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD15                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD15                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD15                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD16_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD16_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD17_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD17_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD18_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD18_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD19_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD19_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD20_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD20_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD21_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD21_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD22_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD22_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD23_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD23_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD24_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD24_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD25_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD25_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD26_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD26_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD27_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD27_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD28_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD28_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD29_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD29_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD30_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD30_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD31_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD31_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

     
      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD16                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD17                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD18                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD19                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD20                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD21                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD22                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD23                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD24                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD25                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD26                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD27                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD28                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD29                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD30                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD31                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WD16                            :	in    STD_ULOGIC;
      WD17                            :	in    STD_ULOGIC;
      WD18                            :	in    STD_ULOGIC;
      WD19                            :	in    STD_ULOGIC;
      WD20                            :	in    STD_ULOGIC;
      WD21                            :	in    STD_ULOGIC;
      WD22                            :	in    STD_ULOGIC;
      WD23                            :	in    STD_ULOGIC;
      WD24                            :	in    STD_ULOGIC;
      WD25                            :	in    STD_ULOGIC;
      WD26                            :	in    STD_ULOGIC;
      WD27                            :	in    STD_ULOGIC;
      WD28                            :	in    STD_ULOGIC;
      WD29                            :	in    STD_ULOGIC;
      WD30                            :	in    STD_ULOGIC;
      WD31                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC;
      RD2                            :	out    STD_ULOGIC;
      RD3                            :	out    STD_ULOGIC;
      RD4                            :	out    STD_ULOGIC;
      RD5                            :	out    STD_ULOGIC;
      RD6                            :	out    STD_ULOGIC;
      RD7                            :	out    STD_ULOGIC;
      RD8                            :	out    STD_ULOGIC;
      RD9                            :	out    STD_ULOGIC;
      RD10                            :	out    STD_ULOGIC;
      RD11                            :	out    STD_ULOGIC;
      RD12                            :	out    STD_ULOGIC;
      RD13                            :	out    STD_ULOGIC;
      RD14                            :	out    STD_ULOGIC;
      RD15                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16KA_WX32_RX16 : entity is FALSE;
end RAMB16KA_WX32_RX16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX32_RX16 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';
      signal WD16_ipd      : std_ulogic := 'X';
      signal WD17_ipd      : std_ulogic := 'X';
      signal WD18_ipd      : std_ulogic := 'X';
      signal WD19_ipd      : std_ulogic := 'X';
      signal WD20_ipd      : std_ulogic := 'X';
      signal WD21_ipd      : std_ulogic := 'X';
      signal WD22_ipd      : std_ulogic := 'X';
      signal WD23_ipd      : std_ulogic := 'X';
      signal WD24_ipd      : std_ulogic := 'X';
      signal WD25_ipd      : std_ulogic := 'X';
      signal WD26_ipd      : std_ulogic := 'X';
      signal WD27_ipd      : std_ulogic := 'X';
      signal WD28_ipd      : std_ulogic := 'X';
      signal WD29_ipd      : std_ulogic := 'X';
      signal WD30_ipd      : std_ulogic := 'X';
      signal WD31_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (31 downto 0);
 	signal WAD : std_logic_vector (8 downto 0);
 	signal RAD : std_logic_vector (9 downto 0);
	signal RD  : std_logic_vector (15 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD31_ipd & WD30_ipd & WD29_ipd & WD28_ipd & WD27_ipd & WD26_ipd & WD25_ipd & WD24_ipd & WD23_ipd & WD22_ipd & WD21_ipd & WD20_ipd & WD19_ipd & WD18_ipd & WD17_ipd & WD16_ipd & WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);
        VitalWireDelay (WD16_ipd, WD16, tipd_WD16);
        VitalWireDelay (WD17_ipd, WD17, tipd_WD17);
        VitalWireDelay (WD18_ipd, WD18, tipd_WD18);
        VitalWireDelay (WD19_ipd, WD19, tipd_WD19);
        VitalWireDelay (WD20_ipd, WD20, tipd_WD20);
        VitalWireDelay (WD21_ipd, WD21, tipd_WD21);
        VitalWireDelay (WD22_ipd, WD22, tipd_WD22);
        VitalWireDelay (WD23_ipd, WD23, tipd_WD23);
        VitalWireDelay (WD24_ipd, WD24, tipd_WD24);
        VitalWireDelay (WD25_ipd, WD25, tipd_WD25);
        VitalWireDelay (WD26_ipd, WD26, tipd_WD26);
        VitalWireDelay (WD27_ipd, WD27, tipd_WD27);
        VitalWireDelay (WD28_ipd, WD28, tipd_WD28);
        VitalWireDelay (WD29_ipd, WD29, tipd_WD29);
        VitalWireDelay (WD30_ipd, WD30, tipd_WD30);
        VitalWireDelay (WD31_ipd, WD31, tipd_WD31);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD16_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD17_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD18_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD19_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD20_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD21_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD22_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD23_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD24_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD25_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD26_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD27_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD28_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD29_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD30_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD31_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';

 
        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD16_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD17_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD18_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD19_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD20_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD21_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD22_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD23_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD24_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD25_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD26_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD27_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD28_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD29_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD30_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD31_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

      
        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable RD8_zd          : std_ulogic := 'X';
        variable RD9_zd          : std_ulogic := 'X';
        variable RD10_zd          : std_ulogic := 'X';
        variable RD11_zd          : std_ulogic := 'X';
        variable RD12_zd          : std_ulogic := 'X';
        variable RD13_zd          : std_ulogic := 'X';
        variable RD14_zd          : std_ulogic := 'X';
        variable RD15_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD16_WCLK_posedge,
          TimingData              => Tmkr_WD16_WCLK_posedge,
          TestSignal              => WD16_ipd,
          TestSignalName          => "WD16",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD16_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD16_WCLK_noedge_posedge,
          HoldLow                 => thold_WD16_WCLK_noedge_posedge,
          HoldHigh                => thold_WD16_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD17_WCLK_posedge,
          TimingData              => Tmkr_WD17_WCLK_posedge,
          TestSignal              => WD17_ipd,
          TestSignalName          => "WD17",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD17_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD17_WCLK_noedge_posedge,
          HoldLow                 => thold_WD17_WCLK_noedge_posedge,
          HoldHigh                => thold_WD17_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD18_WCLK_posedge,
          TimingData              => Tmkr_WD18_WCLK_posedge,
          TestSignal              => WD18_ipd,
          TestSignalName          => "WD18",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD18_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD18_WCLK_noedge_posedge,
          HoldLow                 => thold_WD18_WCLK_noedge_posedge,
          HoldHigh                => thold_WD18_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD19_WCLK_posedge,
          TimingData              => Tmkr_WD19_WCLK_posedge,
          TestSignal              => WD19_ipd,
          TestSignalName          => "WD19",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD19_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD19_WCLK_noedge_posedge,
          HoldLow                 => thold_WD19_WCLK_noedge_posedge,
          HoldHigh                => thold_WD19_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD20_WCLK_posedge,
          TimingData              => Tmkr_WD20_WCLK_posedge,
          TestSignal              => WD20_ipd,
          TestSignalName          => "WD20",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD20_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD20_WCLK_noedge_posedge,
          HoldLow                 => thold_WD20_WCLK_noedge_posedge,
          HoldHigh                => thold_WD20_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD21_WCLK_posedge,
          TimingData              => Tmkr_WD21_WCLK_posedge,
          TestSignal              => WD21_ipd,
          TestSignalName          => "WD21",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD21_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD21_WCLK_noedge_posedge,
          HoldLow                 => thold_WD21_WCLK_noedge_posedge,
          HoldHigh                => thold_WD21_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD22_WCLK_posedge,
          TimingData              => Tmkr_WD22_WCLK_posedge,
          TestSignal              => WD22_ipd,
          TestSignalName          => "WD22",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD22_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD22_WCLK_noedge_posedge,
          HoldLow                 => thold_WD22_WCLK_noedge_posedge,
          HoldHigh                => thold_WD22_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD23_WCLK_posedge,
          TimingData              => Tmkr_WD23_WCLK_posedge,
          TestSignal              => WD23_ipd,
          TestSignalName          => "WD23",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD23_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD23_WCLK_noedge_posedge,
          HoldLow                 => thold_WD23_WCLK_noedge_posedge,
          HoldHigh                => thold_WD23_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD24_WCLK_posedge,
          TimingData              => Tmkr_WD24_WCLK_posedge,
          TestSignal              => WD24_ipd,
          TestSignalName          => "WD24",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD24_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD24_WCLK_noedge_posedge,
          HoldLow                 => thold_WD24_WCLK_noedge_posedge,
          HoldHigh                => thold_WD24_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD25_WCLK_posedge,
          TimingData              => Tmkr_WD25_WCLK_posedge,
          TestSignal              => WD25_ipd,
          TestSignalName          => "WD25",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD25_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD25_WCLK_noedge_posedge,
          HoldLow                 => thold_WD25_WCLK_noedge_posedge,
          HoldHigh                => thold_WD25_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD26_WCLK_posedge,
          TimingData              => Tmkr_WD26_WCLK_posedge,
          TestSignal              => WD26_ipd,
          TestSignalName          => "WD26",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD26_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD26_WCLK_noedge_posedge,
          HoldLow                 => thold_WD26_WCLK_noedge_posedge,
          HoldHigh                => thold_WD26_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD27_WCLK_posedge,
          TimingData              => Tmkr_WD27_WCLK_posedge,
          TestSignal              => WD27_ipd,
          TestSignalName          => "WD27",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD27_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD27_WCLK_noedge_posedge,
          HoldLow                 => thold_WD27_WCLK_noedge_posedge,
          HoldHigh                => thold_WD27_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD28_WCLK_posedge,
          TimingData              => Tmkr_WD28_WCLK_posedge,
          TestSignal              => WD28_ipd,
          TestSignalName          => "WD28",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD28_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD28_WCLK_noedge_posedge,
          HoldLow                 => thold_WD28_WCLK_noedge_posedge,
          HoldHigh                => thold_WD28_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD29_WCLK_posedge,
          TimingData              => Tmkr_WD29_WCLK_posedge,
          TestSignal              => WD29_ipd,
          TestSignalName          => "WD29",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD29_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD29_WCLK_noedge_posedge,
          HoldLow                 => thold_WD29_WCLK_noedge_posedge,
          HoldHigh                => thold_WD29_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD30_WCLK_posedge,
          TimingData              => Tmkr_WD30_WCLK_posedge,
          TestSignal              => WD30_ipd,
          TestSignalName          => "WD30",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD30_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD30_WCLK_noedge_posedge,
          HoldLow                 => thold_WD30_WCLK_noedge_posedge,
          HoldHigh                => thold_WD30_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD31_WCLK_posedge,
          TimingData              => Tmkr_WD31_WCLK_posedge,
          TestSignal              => WD31_ipd,
          TestSignalName          => "WD31",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD31_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD31_WCLK_noedge_posedge,
          HoldLow                 => thold_WD31_WCLK_noedge_posedge,
          HoldHigh                => thold_WD31_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX16",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or
                 Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or
                 Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or
                 Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or
                 Tviol_WD15_WCLK_posedge or
                 Tviol_WD16_WCLK_posedge or
                 Tviol_WD17_WCLK_posedge or
                 Tviol_WD18_WCLK_posedge or
                 Tviol_WD19_WCLK_posedge or
                 Tviol_WD20_WCLK_posedge or
                 Tviol_WD21_WCLK_posedge or
                 Tviol_WD22_WCLK_posedge or
                 Tviol_WD23_WCLK_posedge or
                 Tviol_WD24_WCLK_posedge or
                 Tviol_WD25_WCLK_posedge or
                 Tviol_WD26_WCLK_posedge or
                 Tviol_WD27_WCLK_posedge or
                 Tviol_WD28_WCLK_posedge or
                 Tviol_WD29_WCLK_posedge or
                 Tviol_WD30_WCLK_posedge or
                 Tviol_WD31_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD2, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD3, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD4, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD4, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD4, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD4, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD4, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD4, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD4, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD4, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD4, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD4, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD5, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD5, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD5, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD5, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD5, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD5, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD5, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD5, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD5, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD5, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD6, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD6, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD6, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD6, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD6, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD6, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD6, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD6, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD6, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD6, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD7, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD7, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD7, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD7, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD7, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD7, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD7, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD7, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD7, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD7, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

    VitalBehavior_RD8  : process
      variable RD8_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD8_zd := RD(8);

    VitalPathDelay01 (
      OutSignal => RD8,
      GlitchData => O_GlitchData,
      OutSignalName => "RD8",
      OutTemp => RD8_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD8, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD8, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD8, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD8, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD8, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD8, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD8, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD8, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD8, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD8, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD8, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(8);
      end process;

    VitalBehavior_RD9  : process
      variable RD9_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD9_zd := RD(9);

    VitalPathDelay01 (
      OutSignal => RD9,
      GlitchData => O_GlitchData,
      OutSignalName => "RD9",
      OutTemp => RD9_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD9, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD9, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD9, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD9, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD9, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD9, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD9, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD9, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD9, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD9, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD9, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(9);
      end process;

    VitalBehavior_RD10  : process
      variable RD10_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD10_zd := RD(10);

    VitalPathDelay01 (
      OutSignal => RD10,
      GlitchData => O_GlitchData,
      OutSignalName => "RD10",
      OutTemp => RD10_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD10, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD10, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD10, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD10, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD10, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD10, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD10, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD10, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD10, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD10, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD10, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(10);
      end process;

    VitalBehavior_RD11  : process
      variable RD11_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD11_zd := RD(11);

    VitalPathDelay01 (
      OutSignal => RD11,
      GlitchData => O_GlitchData,
      OutSignalName => "RD11",
      OutTemp => RD11_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD11, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD11, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD11, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD11, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD11, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD11, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD11, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD11, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD11, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD11, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD11, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(11);
      end process;

    VitalBehavior_RD12  : process
      variable RD12_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD12_zd := RD(12);

    VitalPathDelay01 (
      OutSignal => RD12,
      GlitchData => O_GlitchData,
      OutSignalName => "RD12",
      OutTemp => RD12_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD12, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD12, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD12, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD12, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD12, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD12, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD12, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD12, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD12, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD12, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD12, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(12);
      end process;

    VitalBehavior_RD13  : process
      variable RD13_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD13_zd := RD(13);

    VitalPathDelay01 (
      OutSignal => RD13,
      GlitchData => O_GlitchData,
      OutSignalName => "RD13",
      OutTemp => RD13_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD13, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD13, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD13, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD13, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD13, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD13, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD13, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD13, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD13, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD13, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD13, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(13);
      end process;

    VitalBehavior_RD14  : process
      variable RD14_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD14_zd := RD(14);

    VitalPathDelay01 (
      OutSignal => RD14,
      GlitchData => O_GlitchData,
      OutSignalName => "RD14",
      OutTemp => RD14_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD14, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD14, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD14, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD14, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD14, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD14, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD14, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD14, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD14, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD14, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD14, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(14);
      end process;

    VitalBehavior_RD15  : process
      variable RD15_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD15_zd := RD(15);

    VitalPathDelay01 (
      OutSignal => RD15,
      GlitchData => O_GlitchData,
      OutSignalName => "RD15",
      OutTemp => RD15_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD15, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD15, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD15, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD15, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD15, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD15, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD15, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD15, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD15, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD15, TRUE),
               10 => (RST_ipd'last_event, tpd_RST_RD15, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(15);
      end process;

	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 9,
		WDATA_WIDTH    => 32,
		RADDR_WIDTH    => 10,
		RDATA_WIDTH    => 16,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16KA_WX32_RX16_VITAL of RAMB16KA_WX32_RX16 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX32_RX16_VITAL;


----- CELL RAMB16KA_WX32_RX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16KA_WX32_RX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD12_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD12_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD16_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD16_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD17_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD17_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD18_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD18_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD19_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD19_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD20_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD20_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD21_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD21_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD22_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD22_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD23_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD23_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD24_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD24_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD25_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD25_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD26_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD26_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD27_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD27_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD28_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD28_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD29_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD29_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD30_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD30_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD31_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD31_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

     
      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD16                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD17                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD18                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD19                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD20                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD21                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD22                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD23                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD24                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD25                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD26                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD27                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD28                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD29                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD30                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD31                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WD16                            :	in    STD_ULOGIC;
      WD17                            :	in    STD_ULOGIC;
      WD18                            :	in    STD_ULOGIC;
      WD19                            :	in    STD_ULOGIC;
      WD20                            :	in    STD_ULOGIC;
      WD21                            :	in    STD_ULOGIC;
      WD22                            :	in    STD_ULOGIC;
      WD23                            :	in    STD_ULOGIC;
      WD24                            :	in    STD_ULOGIC;
      WD25                            :	in    STD_ULOGIC;
      WD26                            :	in    STD_ULOGIC;
      WD27                            :	in    STD_ULOGIC;
      WD28                            :	in    STD_ULOGIC;
      WD29                            :	in    STD_ULOGIC;
      WD30                            :	in    STD_ULOGIC;
      WD31                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RAD12                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16KA_WX32_RX2 : entity is FALSE;
end RAMB16KA_WX32_RX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX32_RX2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';
      signal WD16_ipd      : std_ulogic := 'X';
      signal WD17_ipd      : std_ulogic := 'X';
      signal WD18_ipd      : std_ulogic := 'X';
      signal WD19_ipd      : std_ulogic := 'X';
      signal WD20_ipd      : std_ulogic := 'X';
      signal WD21_ipd      : std_ulogic := 'X';
      signal WD22_ipd      : std_ulogic := 'X';
      signal WD23_ipd      : std_ulogic := 'X';
      signal WD24_ipd      : std_ulogic := 'X';
      signal WD25_ipd      : std_ulogic := 'X';
      signal WD26_ipd      : std_ulogic := 'X';
      signal WD27_ipd      : std_ulogic := 'X';
      signal WD28_ipd      : std_ulogic := 'X';
      signal WD29_ipd      : std_ulogic := 'X';
      signal WD30_ipd      : std_ulogic := 'X';
      signal WD31_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';
      signal RAD12_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (31 downto 0);
 	signal WAD : std_logic_vector (8 downto 0);
 	signal RAD : std_logic_vector (12 downto 0);
	signal RD  : std_logic_vector (1 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD31_ipd & WD30_ipd & WD29_ipd & WD28_ipd & WD27_ipd & WD26_ipd & WD25_ipd & WD24_ipd & WD23_ipd & WD22_ipd & WD21_ipd & WD20_ipd & WD19_ipd & WD18_ipd & WD17_ipd & WD16_ipd & WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);
        VitalWireDelay (WD16_ipd, WD16, tipd_WD16);
        VitalWireDelay (WD17_ipd, WD17, tipd_WD17);
        VitalWireDelay (WD18_ipd, WD18, tipd_WD18);
        VitalWireDelay (WD19_ipd, WD19, tipd_WD19);
        VitalWireDelay (WD20_ipd, WD20, tipd_WD20);
        VitalWireDelay (WD21_ipd, WD21, tipd_WD21);
        VitalWireDelay (WD22_ipd, WD22, tipd_WD22);
        VitalWireDelay (WD23_ipd, WD23, tipd_WD23);
        VitalWireDelay (WD24_ipd, WD24, tipd_WD24);
        VitalWireDelay (WD25_ipd, WD25, tipd_WD25);
        VitalWireDelay (WD26_ipd, WD26, tipd_WD26);
        VitalWireDelay (WD27_ipd, WD27, tipd_WD27);
        VitalWireDelay (WD28_ipd, WD28, tipd_WD28);
        VitalWireDelay (WD29_ipd, WD29, tipd_WD29);
        VitalWireDelay (WD30_ipd, WD30, tipd_WD30);
        VitalWireDelay (WD31_ipd, WD31, tipd_WD31);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD16_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD17_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD18_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD19_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD20_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD21_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD22_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD23_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD24_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD25_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD26_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD27_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD28_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD29_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD30_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD31_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';

 
        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD16_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD17_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD18_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD19_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD20_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD21_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD22_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD23_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD24_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD25_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD26_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD27_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD28_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD29_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD30_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD31_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

      
        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD16_WCLK_posedge,
          TimingData              => Tmkr_WD16_WCLK_posedge,
          TestSignal              => WD16_ipd,
          TestSignalName          => "WD16",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD16_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD16_WCLK_noedge_posedge,
          HoldLow                 => thold_WD16_WCLK_noedge_posedge,
          HoldHigh                => thold_WD16_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD17_WCLK_posedge,
          TimingData              => Tmkr_WD17_WCLK_posedge,
          TestSignal              => WD17_ipd,
          TestSignalName          => "WD17",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD17_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD17_WCLK_noedge_posedge,
          HoldLow                 => thold_WD17_WCLK_noedge_posedge,
          HoldHigh                => thold_WD17_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD18_WCLK_posedge,
          TimingData              => Tmkr_WD18_WCLK_posedge,
          TestSignal              => WD18_ipd,
          TestSignalName          => "WD18",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD18_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD18_WCLK_noedge_posedge,
          HoldLow                 => thold_WD18_WCLK_noedge_posedge,
          HoldHigh                => thold_WD18_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD19_WCLK_posedge,
          TimingData              => Tmkr_WD19_WCLK_posedge,
          TestSignal              => WD19_ipd,
          TestSignalName          => "WD19",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD19_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD19_WCLK_noedge_posedge,
          HoldLow                 => thold_WD19_WCLK_noedge_posedge,
          HoldHigh                => thold_WD19_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD20_WCLK_posedge,
          TimingData              => Tmkr_WD20_WCLK_posedge,
          TestSignal              => WD20_ipd,
          TestSignalName          => "WD20",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD20_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD20_WCLK_noedge_posedge,
          HoldLow                 => thold_WD20_WCLK_noedge_posedge,
          HoldHigh                => thold_WD20_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD21_WCLK_posedge,
          TimingData              => Tmkr_WD21_WCLK_posedge,
          TestSignal              => WD21_ipd,
          TestSignalName          => "WD21",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD21_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD21_WCLK_noedge_posedge,
          HoldLow                 => thold_WD21_WCLK_noedge_posedge,
          HoldHigh                => thold_WD21_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD22_WCLK_posedge,
          TimingData              => Tmkr_WD22_WCLK_posedge,
          TestSignal              => WD22_ipd,
          TestSignalName          => "WD22",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD22_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD22_WCLK_noedge_posedge,
          HoldLow                 => thold_WD22_WCLK_noedge_posedge,
          HoldHigh                => thold_WD22_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD23_WCLK_posedge,
          TimingData              => Tmkr_WD23_WCLK_posedge,
          TestSignal              => WD23_ipd,
          TestSignalName          => "WD23",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD23_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD23_WCLK_noedge_posedge,
          HoldLow                 => thold_WD23_WCLK_noedge_posedge,
          HoldHigh                => thold_WD23_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD24_WCLK_posedge,
          TimingData              => Tmkr_WD24_WCLK_posedge,
          TestSignal              => WD24_ipd,
          TestSignalName          => "WD24",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD24_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD24_WCLK_noedge_posedge,
          HoldLow                 => thold_WD24_WCLK_noedge_posedge,
          HoldHigh                => thold_WD24_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD25_WCLK_posedge,
          TimingData              => Tmkr_WD25_WCLK_posedge,
          TestSignal              => WD25_ipd,
          TestSignalName          => "WD25",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD25_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD25_WCLK_noedge_posedge,
          HoldLow                 => thold_WD25_WCLK_noedge_posedge,
          HoldHigh                => thold_WD25_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD26_WCLK_posedge,
          TimingData              => Tmkr_WD26_WCLK_posedge,
          TestSignal              => WD26_ipd,
          TestSignalName          => "WD26",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD26_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD26_WCLK_noedge_posedge,
          HoldLow                 => thold_WD26_WCLK_noedge_posedge,
          HoldHigh                => thold_WD26_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD27_WCLK_posedge,
          TimingData              => Tmkr_WD27_WCLK_posedge,
          TestSignal              => WD27_ipd,
          TestSignalName          => "WD27",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD27_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD27_WCLK_noedge_posedge,
          HoldLow                 => thold_WD27_WCLK_noedge_posedge,
          HoldHigh                => thold_WD27_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD28_WCLK_posedge,
          TimingData              => Tmkr_WD28_WCLK_posedge,
          TestSignal              => WD28_ipd,
          TestSignalName          => "WD28",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD28_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD28_WCLK_noedge_posedge,
          HoldLow                 => thold_WD28_WCLK_noedge_posedge,
          HoldHigh                => thold_WD28_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD29_WCLK_posedge,
          TimingData              => Tmkr_WD29_WCLK_posedge,
          TestSignal              => WD29_ipd,
          TestSignalName          => "WD29",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD29_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD29_WCLK_noedge_posedge,
          HoldLow                 => thold_WD29_WCLK_noedge_posedge,
          HoldHigh                => thold_WD29_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD30_WCLK_posedge,
          TimingData              => Tmkr_WD30_WCLK_posedge,
          TestSignal              => WD30_ipd,
          TestSignalName          => "WD30",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD30_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD30_WCLK_noedge_posedge,
          HoldLow                 => thold_WD30_WCLK_noedge_posedge,
          HoldHigh                => thold_WD30_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD31_WCLK_posedge,
          TimingData              => Tmkr_WD31_WCLK_posedge,
          TestSignal              => WD31_ipd,
          TestSignalName          => "WD31",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD31_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD31_WCLK_noedge_posedge,
          HoldLow                 => thold_WD31_WCLK_noedge_posedge,
          HoldHigh                => thold_WD31_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or
                 Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or
                 Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or
                 Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or
                 Tviol_WD15_WCLK_posedge or
                 Tviol_WD16_WCLK_posedge or
                 Tviol_WD17_WCLK_posedge or
                 Tviol_WD18_WCLK_posedge or
                 Tviol_WD19_WCLK_posedge or
                 Tviol_WD20_WCLK_posedge or
                 Tviol_WD21_WCLK_posedge or
                 Tviol_WD22_WCLK_posedge or
                 Tviol_WD23_WCLK_posedge or
                 Tviol_WD24_WCLK_posedge or
                 Tviol_WD25_WCLK_posedge or
                 Tviol_WD26_WCLK_posedge or
                 Tviol_WD27_WCLK_posedge or
                 Tviol_WD28_WCLK_posedge or
                 Tviol_WD29_WCLK_posedge or
                 Tviol_WD30_WCLK_posedge or
                 Tviol_WD31_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD0, TRUE),
               12 => (RAD12_ipd'last_event, tpd_RAD12_RD0, TRUE),
               13 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD1, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD1, TRUE),
               12 => (RAD12_ipd'last_event, tpd_RAD12_RD1, TRUE),
               13 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 9,
		WDATA_WIDTH    => 32,
		RADDR_WIDTH    => 13,
		RDATA_WIDTH    => 2,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16KA_WX32_RX2_VITAL of RAMB16KA_WX32_RX2 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX32_RX2_VITAL;


----- CELL RAMB16KA_WX32_RX4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16KA_WX32_RX4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD16_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD16_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD17_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD17_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD18_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD18_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD19_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD19_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD20_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD20_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD21_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD21_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD22_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD22_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD23_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD23_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD24_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD24_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD25_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD25_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD26_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD26_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD27_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD27_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD28_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD28_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD29_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD29_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD30_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD30_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD31_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD31_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

     
      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD16                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD17                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD18                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD19                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD20                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD21                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD22                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD23                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD24                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD25                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD26                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD27                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD28                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD29                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD30                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD31                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WD16                            :	in    STD_ULOGIC;
      WD17                            :	in    STD_ULOGIC;
      WD18                            :	in    STD_ULOGIC;
      WD19                            :	in    STD_ULOGIC;
      WD20                            :	in    STD_ULOGIC;
      WD21                            :	in    STD_ULOGIC;
      WD22                            :	in    STD_ULOGIC;
      WD23                            :	in    STD_ULOGIC;
      WD24                            :	in    STD_ULOGIC;
      WD25                            :	in    STD_ULOGIC;
      WD26                            :	in    STD_ULOGIC;
      WD27                            :	in    STD_ULOGIC;
      WD28                            :	in    STD_ULOGIC;
      WD29                            :	in    STD_ULOGIC;
      WD30                            :	in    STD_ULOGIC;
      WD31                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC;
      RD2                            :	out    STD_ULOGIC;
      RD3                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16KA_WX32_RX4 : entity is FALSE;
end RAMB16KA_WX32_RX4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX32_RX4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';
      signal WD16_ipd      : std_ulogic := 'X';
      signal WD17_ipd      : std_ulogic := 'X';
      signal WD18_ipd      : std_ulogic := 'X';
      signal WD19_ipd      : std_ulogic := 'X';
      signal WD20_ipd      : std_ulogic := 'X';
      signal WD21_ipd      : std_ulogic := 'X';
      signal WD22_ipd      : std_ulogic := 'X';
      signal WD23_ipd      : std_ulogic := 'X';
      signal WD24_ipd      : std_ulogic := 'X';
      signal WD25_ipd      : std_ulogic := 'X';
      signal WD26_ipd      : std_ulogic := 'X';
      signal WD27_ipd      : std_ulogic := 'X';
      signal WD28_ipd      : std_ulogic := 'X';
      signal WD29_ipd      : std_ulogic := 'X';
      signal WD30_ipd      : std_ulogic := 'X';
      signal WD31_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (31 downto 0);
 	signal WAD : std_logic_vector (8 downto 0);
 	signal RAD : std_logic_vector (11 downto 0);
	signal RD  : std_logic_vector (3 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD31_ipd & WD30_ipd & WD29_ipd & WD28_ipd & WD27_ipd & WD26_ipd & WD25_ipd & WD24_ipd & WD23_ipd & WD22_ipd & WD21_ipd & WD20_ipd & WD19_ipd & WD18_ipd & WD17_ipd & WD16_ipd & WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);
        VitalWireDelay (WD16_ipd, WD16, tipd_WD16);
        VitalWireDelay (WD17_ipd, WD17, tipd_WD17);
        VitalWireDelay (WD18_ipd, WD18, tipd_WD18);
        VitalWireDelay (WD19_ipd, WD19, tipd_WD19);
        VitalWireDelay (WD20_ipd, WD20, tipd_WD20);
        VitalWireDelay (WD21_ipd, WD21, tipd_WD21);
        VitalWireDelay (WD22_ipd, WD22, tipd_WD22);
        VitalWireDelay (WD23_ipd, WD23, tipd_WD23);
        VitalWireDelay (WD24_ipd, WD24, tipd_WD24);
        VitalWireDelay (WD25_ipd, WD25, tipd_WD25);
        VitalWireDelay (WD26_ipd, WD26, tipd_WD26);
        VitalWireDelay (WD27_ipd, WD27, tipd_WD27);
        VitalWireDelay (WD28_ipd, WD28, tipd_WD28);
        VitalWireDelay (WD29_ipd, WD29, tipd_WD29);
        VitalWireDelay (WD30_ipd, WD30, tipd_WD30);
        VitalWireDelay (WD31_ipd, WD31, tipd_WD31);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD16_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD17_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD18_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD19_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD20_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD21_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD22_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD23_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD24_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD25_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD26_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD27_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD28_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD29_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD30_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD31_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';

 
        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD16_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD17_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD18_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD19_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD20_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD21_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD22_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD23_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD24_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD25_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD26_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD27_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD28_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD29_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD30_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD31_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

      
        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD16_WCLK_posedge,
          TimingData              => Tmkr_WD16_WCLK_posedge,
          TestSignal              => WD16_ipd,
          TestSignalName          => "WD16",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD16_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD16_WCLK_noedge_posedge,
          HoldLow                 => thold_WD16_WCLK_noedge_posedge,
          HoldHigh                => thold_WD16_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD17_WCLK_posedge,
          TimingData              => Tmkr_WD17_WCLK_posedge,
          TestSignal              => WD17_ipd,
          TestSignalName          => "WD17",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD17_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD17_WCLK_noedge_posedge,
          HoldLow                 => thold_WD17_WCLK_noedge_posedge,
          HoldHigh                => thold_WD17_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD18_WCLK_posedge,
          TimingData              => Tmkr_WD18_WCLK_posedge,
          TestSignal              => WD18_ipd,
          TestSignalName          => "WD18",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD18_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD18_WCLK_noedge_posedge,
          HoldLow                 => thold_WD18_WCLK_noedge_posedge,
          HoldHigh                => thold_WD18_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD19_WCLK_posedge,
          TimingData              => Tmkr_WD19_WCLK_posedge,
          TestSignal              => WD19_ipd,
          TestSignalName          => "WD19",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD19_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD19_WCLK_noedge_posedge,
          HoldLow                 => thold_WD19_WCLK_noedge_posedge,
          HoldHigh                => thold_WD19_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD20_WCLK_posedge,
          TimingData              => Tmkr_WD20_WCLK_posedge,
          TestSignal              => WD20_ipd,
          TestSignalName          => "WD20",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD20_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD20_WCLK_noedge_posedge,
          HoldLow                 => thold_WD20_WCLK_noedge_posedge,
          HoldHigh                => thold_WD20_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD21_WCLK_posedge,
          TimingData              => Tmkr_WD21_WCLK_posedge,
          TestSignal              => WD21_ipd,
          TestSignalName          => "WD21",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD21_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD21_WCLK_noedge_posedge,
          HoldLow                 => thold_WD21_WCLK_noedge_posedge,
          HoldHigh                => thold_WD21_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD22_WCLK_posedge,
          TimingData              => Tmkr_WD22_WCLK_posedge,
          TestSignal              => WD22_ipd,
          TestSignalName          => "WD22",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD22_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD22_WCLK_noedge_posedge,
          HoldLow                 => thold_WD22_WCLK_noedge_posedge,
          HoldHigh                => thold_WD22_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD23_WCLK_posedge,
          TimingData              => Tmkr_WD23_WCLK_posedge,
          TestSignal              => WD23_ipd,
          TestSignalName          => "WD23",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD23_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD23_WCLK_noedge_posedge,
          HoldLow                 => thold_WD23_WCLK_noedge_posedge,
          HoldHigh                => thold_WD23_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD24_WCLK_posedge,
          TimingData              => Tmkr_WD24_WCLK_posedge,
          TestSignal              => WD24_ipd,
          TestSignalName          => "WD24",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD24_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD24_WCLK_noedge_posedge,
          HoldLow                 => thold_WD24_WCLK_noedge_posedge,
          HoldHigh                => thold_WD24_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD25_WCLK_posedge,
          TimingData              => Tmkr_WD25_WCLK_posedge,
          TestSignal              => WD25_ipd,
          TestSignalName          => "WD25",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD25_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD25_WCLK_noedge_posedge,
          HoldLow                 => thold_WD25_WCLK_noedge_posedge,
          HoldHigh                => thold_WD25_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD26_WCLK_posedge,
          TimingData              => Tmkr_WD26_WCLK_posedge,
          TestSignal              => WD26_ipd,
          TestSignalName          => "WD26",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD26_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD26_WCLK_noedge_posedge,
          HoldLow                 => thold_WD26_WCLK_noedge_posedge,
          HoldHigh                => thold_WD26_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD27_WCLK_posedge,
          TimingData              => Tmkr_WD27_WCLK_posedge,
          TestSignal              => WD27_ipd,
          TestSignalName          => "WD27",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD27_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD27_WCLK_noedge_posedge,
          HoldLow                 => thold_WD27_WCLK_noedge_posedge,
          HoldHigh                => thold_WD27_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD28_WCLK_posedge,
          TimingData              => Tmkr_WD28_WCLK_posedge,
          TestSignal              => WD28_ipd,
          TestSignalName          => "WD28",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD28_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD28_WCLK_noedge_posedge,
          HoldLow                 => thold_WD28_WCLK_noedge_posedge,
          HoldHigh                => thold_WD28_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD29_WCLK_posedge,
          TimingData              => Tmkr_WD29_WCLK_posedge,
          TestSignal              => WD29_ipd,
          TestSignalName          => "WD29",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD29_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD29_WCLK_noedge_posedge,
          HoldLow                 => thold_WD29_WCLK_noedge_posedge,
          HoldHigh                => thold_WD29_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD30_WCLK_posedge,
          TimingData              => Tmkr_WD30_WCLK_posedge,
          TestSignal              => WD30_ipd,
          TestSignalName          => "WD30",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD30_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD30_WCLK_noedge_posedge,
          HoldLow                 => thold_WD30_WCLK_noedge_posedge,
          HoldHigh                => thold_WD30_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD31_WCLK_posedge,
          TimingData              => Tmkr_WD31_WCLK_posedge,
          TestSignal              => WD31_ipd,
          TestSignalName          => "WD31",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD31_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD31_WCLK_noedge_posedge,
          HoldLow                 => thold_WD31_WCLK_noedge_posedge,
          HoldHigh                => thold_WD31_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or
                 Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or
                 Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or
                 Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or
                 Tviol_WD15_WCLK_posedge or
                 Tviol_WD16_WCLK_posedge or
                 Tviol_WD17_WCLK_posedge or
                 Tviol_WD18_WCLK_posedge or
                 Tviol_WD19_WCLK_posedge or
                 Tviol_WD20_WCLK_posedge or
                 Tviol_WD21_WCLK_posedge or
                 Tviol_WD22_WCLK_posedge or
                 Tviol_WD23_WCLK_posedge or
                 Tviol_WD24_WCLK_posedge or
                 Tviol_WD25_WCLK_posedge or
                 Tviol_WD26_WCLK_posedge or
                 Tviol_WD27_WCLK_posedge or
                 Tviol_WD28_WCLK_posedge or
                 Tviol_WD29_WCLK_posedge or
                 Tviol_WD30_WCLK_posedge or
                 Tviol_WD31_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD0, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD1, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD1, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD2, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD2, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD2, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD3, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD3, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD3, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 9,
		WDATA_WIDTH    => 32,
		RADDR_WIDTH    => 12,
		RDATA_WIDTH    => 4,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16KA_WX32_RX4_VITAL of RAMB16KA_WX32_RX4 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX32_RX4_VITAL;


----- CELL RAMB16KA_WX32_RX8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16KA_WX32_RX8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD4                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD5                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD6                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD7                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD4                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD5                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD6                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD7                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD8_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD9_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD10_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD11_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD12_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD12_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD13_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD13_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD14_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD14_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD15_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD15_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD16_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD16_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD17_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD17_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD18_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD18_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD19_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD19_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD20_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD20_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD21_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD21_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD22_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD22_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD23_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD23_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD24_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD24_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD25_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD25_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD26_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD26_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD27_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD27_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD28_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD28_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD29_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD29_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD30_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD30_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD31_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD31_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

     
      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD14                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD15                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD16                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD17                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD18                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD19                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD20                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD21                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD22                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD23                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD24                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD25                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD26                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD27                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD28                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD29                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD30                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD31                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WD8                            :	in    STD_ULOGIC;
      WD9                            :	in    STD_ULOGIC;
      WD10                            :	in    STD_ULOGIC;
      WD11                            :	in    STD_ULOGIC;
      WD12                            :	in    STD_ULOGIC;
      WD13                            :	in    STD_ULOGIC;
      WD14                            :	in    STD_ULOGIC;
      WD15                            :	in    STD_ULOGIC;
      WD16                            :	in    STD_ULOGIC;
      WD17                            :	in    STD_ULOGIC;
      WD18                            :	in    STD_ULOGIC;
      WD19                            :	in    STD_ULOGIC;
      WD20                            :	in    STD_ULOGIC;
      WD21                            :	in    STD_ULOGIC;
      WD22                            :	in    STD_ULOGIC;
      WD23                            :	in    STD_ULOGIC;
      WD24                            :	in    STD_ULOGIC;
      WD25                            :	in    STD_ULOGIC;
      WD26                            :	in    STD_ULOGIC;
      WD27                            :	in    STD_ULOGIC;
      WD28                            :	in    STD_ULOGIC;
      WD29                            :	in    STD_ULOGIC;
      WD30                            :	in    STD_ULOGIC;
      WD31                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC;
      RD2                            :	out    STD_ULOGIC;
      RD3                            :	out    STD_ULOGIC;
      RD4                            :	out    STD_ULOGIC;
      RD5                            :	out    STD_ULOGIC;
      RD6                            :	out    STD_ULOGIC;
      RD7                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16KA_WX32_RX8 : entity is FALSE;
end RAMB16KA_WX32_RX8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX32_RX8 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';
      signal WD8_ipd      : std_ulogic := 'X';
      signal WD9_ipd      : std_ulogic := 'X';
      signal WD10_ipd      : std_ulogic := 'X';
      signal WD11_ipd      : std_ulogic := 'X';
      signal WD12_ipd      : std_ulogic := 'X';
      signal WD13_ipd      : std_ulogic := 'X';
      signal WD14_ipd      : std_ulogic := 'X';
      signal WD15_ipd      : std_ulogic := 'X';
      signal WD16_ipd      : std_ulogic := 'X';
      signal WD17_ipd      : std_ulogic := 'X';
      signal WD18_ipd      : std_ulogic := 'X';
      signal WD19_ipd      : std_ulogic := 'X';
      signal WD20_ipd      : std_ulogic := 'X';
      signal WD21_ipd      : std_ulogic := 'X';
      signal WD22_ipd      : std_ulogic := 'X';
      signal WD23_ipd      : std_ulogic := 'X';
      signal WD24_ipd      : std_ulogic := 'X';
      signal WD25_ipd      : std_ulogic := 'X';
      signal WD26_ipd      : std_ulogic := 'X';
      signal WD27_ipd      : std_ulogic := 'X';
      signal WD28_ipd      : std_ulogic := 'X';
      signal WD29_ipd      : std_ulogic := 'X';
      signal WD30_ipd      : std_ulogic := 'X';
      signal WD31_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (31 downto 0);
 	signal WAD : std_logic_vector (8 downto 0);
 	signal RAD : std_logic_vector (10 downto 0);
	signal RD  : std_logic_vector (7 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD31_ipd & WD30_ipd & WD29_ipd & WD28_ipd & WD27_ipd & WD26_ipd & WD25_ipd & WD24_ipd & WD23_ipd & WD22_ipd & WD21_ipd & WD20_ipd & WD19_ipd & WD18_ipd & WD17_ipd & WD16_ipd & WD15_ipd & WD14_ipd & WD13_ipd & WD12_ipd & WD11_ipd & WD10_ipd & WD9_ipd & WD8_ipd & WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);
        VitalWireDelay (WD8_ipd, WD8, tipd_WD8);
        VitalWireDelay (WD9_ipd, WD9, tipd_WD9);
        VitalWireDelay (WD10_ipd, WD10, tipd_WD10);
        VitalWireDelay (WD11_ipd, WD11, tipd_WD11);
        VitalWireDelay (WD12_ipd, WD12, tipd_WD12);
        VitalWireDelay (WD13_ipd, WD13, tipd_WD13);
        VitalWireDelay (WD14_ipd, WD14, tipd_WD14);
        VitalWireDelay (WD15_ipd, WD15, tipd_WD15);
        VitalWireDelay (WD16_ipd, WD16, tipd_WD16);
        VitalWireDelay (WD17_ipd, WD17, tipd_WD17);
        VitalWireDelay (WD18_ipd, WD18, tipd_WD18);
        VitalWireDelay (WD19_ipd, WD19, tipd_WD19);
        VitalWireDelay (WD20_ipd, WD20, tipd_WD20);
        VitalWireDelay (WD21_ipd, WD21, tipd_WD21);
        VitalWireDelay (WD22_ipd, WD22, tipd_WD22);
        VitalWireDelay (WD23_ipd, WD23, tipd_WD23);
        VitalWireDelay (WD24_ipd, WD24, tipd_WD24);
        VitalWireDelay (WD25_ipd, WD25, tipd_WD25);
        VitalWireDelay (WD26_ipd, WD26, tipd_WD26);
        VitalWireDelay (WD27_ipd, WD27, tipd_WD27);
        VitalWireDelay (WD28_ipd, WD28, tipd_WD28);
        VitalWireDelay (WD29_ipd, WD29, tipd_WD29);
        VitalWireDelay (WD30_ipd, WD30, tipd_WD30);
        VitalWireDelay (WD31_ipd, WD31, tipd_WD31);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD11_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD12_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD13_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD14_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD15_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD16_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD17_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD18_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD19_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD20_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD21_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD22_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD23_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD24_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD25_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD26_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD27_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD28_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD29_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD30_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD31_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';

 
        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD12_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD13_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD14_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD15_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD16_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD17_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD18_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD19_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD20_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD21_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD22_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD23_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD24_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD25_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD26_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD27_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD28_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD29_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD30_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD31_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

      
        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable RD4_zd          : std_ulogic := 'X';
        variable RD5_zd          : std_ulogic := 'X';
        variable RD6_zd          : std_ulogic := 'X';
        variable RD7_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD8_WCLK_posedge,
          TimingData              => Tmkr_WD8_WCLK_posedge,
          TestSignal              => WD8_ipd,
          TestSignalName          => "WD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD9_WCLK_posedge,
          TimingData              => Tmkr_WD9_WCLK_posedge,
          TestSignal              => WD9_ipd,
          TestSignalName          => "WD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD10_WCLK_posedge,
          TimingData              => Tmkr_WD10_WCLK_posedge,
          TestSignal              => WD10_ipd,
          TestSignalName          => "WD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD11_WCLK_posedge,
          TimingData              => Tmkr_WD11_WCLK_posedge,
          TestSignal              => WD11_ipd,
          TestSignalName          => "WD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD12_WCLK_posedge,
          TimingData              => Tmkr_WD12_WCLK_posedge,
          TestSignal              => WD12_ipd,
          TestSignalName          => "WD12",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD12_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD12_WCLK_noedge_posedge,
          HoldLow                 => thold_WD12_WCLK_noedge_posedge,
          HoldHigh                => thold_WD12_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD13_WCLK_posedge,
          TimingData              => Tmkr_WD13_WCLK_posedge,
          TestSignal              => WD13_ipd,
          TestSignalName          => "WD13",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD13_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD13_WCLK_noedge_posedge,
          HoldLow                 => thold_WD13_WCLK_noedge_posedge,
          HoldHigh                => thold_WD13_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD14_WCLK_posedge,
          TimingData              => Tmkr_WD14_WCLK_posedge,
          TestSignal              => WD14_ipd,
          TestSignalName          => "WD14",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD14_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD14_WCLK_noedge_posedge,
          HoldLow                 => thold_WD14_WCLK_noedge_posedge,
          HoldHigh                => thold_WD14_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD15_WCLK_posedge,
          TimingData              => Tmkr_WD15_WCLK_posedge,
          TestSignal              => WD15_ipd,
          TestSignalName          => "WD15",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD15_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD15_WCLK_noedge_posedge,
          HoldLow                 => thold_WD15_WCLK_noedge_posedge,
          HoldHigh                => thold_WD15_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD16_WCLK_posedge,
          TimingData              => Tmkr_WD16_WCLK_posedge,
          TestSignal              => WD16_ipd,
          TestSignalName          => "WD16",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD16_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD16_WCLK_noedge_posedge,
          HoldLow                 => thold_WD16_WCLK_noedge_posedge,
          HoldHigh                => thold_WD16_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD17_WCLK_posedge,
          TimingData              => Tmkr_WD17_WCLK_posedge,
          TestSignal              => WD17_ipd,
          TestSignalName          => "WD17",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD17_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD17_WCLK_noedge_posedge,
          HoldLow                 => thold_WD17_WCLK_noedge_posedge,
          HoldHigh                => thold_WD17_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD18_WCLK_posedge,
          TimingData              => Tmkr_WD18_WCLK_posedge,
          TestSignal              => WD18_ipd,
          TestSignalName          => "WD18",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD18_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD18_WCLK_noedge_posedge,
          HoldLow                 => thold_WD18_WCLK_noedge_posedge,
          HoldHigh                => thold_WD18_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD19_WCLK_posedge,
          TimingData              => Tmkr_WD19_WCLK_posedge,
          TestSignal              => WD19_ipd,
          TestSignalName          => "WD19",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD19_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD19_WCLK_noedge_posedge,
          HoldLow                 => thold_WD19_WCLK_noedge_posedge,
          HoldHigh                => thold_WD19_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD20_WCLK_posedge,
          TimingData              => Tmkr_WD20_WCLK_posedge,
          TestSignal              => WD20_ipd,
          TestSignalName          => "WD20",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD20_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD20_WCLK_noedge_posedge,
          HoldLow                 => thold_WD20_WCLK_noedge_posedge,
          HoldHigh                => thold_WD20_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD21_WCLK_posedge,
          TimingData              => Tmkr_WD21_WCLK_posedge,
          TestSignal              => WD21_ipd,
          TestSignalName          => "WD21",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD21_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD21_WCLK_noedge_posedge,
          HoldLow                 => thold_WD21_WCLK_noedge_posedge,
          HoldHigh                => thold_WD21_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD22_WCLK_posedge,
          TimingData              => Tmkr_WD22_WCLK_posedge,
          TestSignal              => WD22_ipd,
          TestSignalName          => "WD22",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD22_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD22_WCLK_noedge_posedge,
          HoldLow                 => thold_WD22_WCLK_noedge_posedge,
          HoldHigh                => thold_WD22_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD23_WCLK_posedge,
          TimingData              => Tmkr_WD23_WCLK_posedge,
          TestSignal              => WD23_ipd,
          TestSignalName          => "WD23",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD23_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD23_WCLK_noedge_posedge,
          HoldLow                 => thold_WD23_WCLK_noedge_posedge,
          HoldHigh                => thold_WD23_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD24_WCLK_posedge,
          TimingData              => Tmkr_WD24_WCLK_posedge,
          TestSignal              => WD24_ipd,
          TestSignalName          => "WD24",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD24_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD24_WCLK_noedge_posedge,
          HoldLow                 => thold_WD24_WCLK_noedge_posedge,
          HoldHigh                => thold_WD24_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD25_WCLK_posedge,
          TimingData              => Tmkr_WD25_WCLK_posedge,
          TestSignal              => WD25_ipd,
          TestSignalName          => "WD25",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD25_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD25_WCLK_noedge_posedge,
          HoldLow                 => thold_WD25_WCLK_noedge_posedge,
          HoldHigh                => thold_WD25_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD26_WCLK_posedge,
          TimingData              => Tmkr_WD26_WCLK_posedge,
          TestSignal              => WD26_ipd,
          TestSignalName          => "WD26",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD26_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD26_WCLK_noedge_posedge,
          HoldLow                 => thold_WD26_WCLK_noedge_posedge,
          HoldHigh                => thold_WD26_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD27_WCLK_posedge,
          TimingData              => Tmkr_WD27_WCLK_posedge,
          TestSignal              => WD27_ipd,
          TestSignalName          => "WD27",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD27_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD27_WCLK_noedge_posedge,
          HoldLow                 => thold_WD27_WCLK_noedge_posedge,
          HoldHigh                => thold_WD27_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD28_WCLK_posedge,
          TimingData              => Tmkr_WD28_WCLK_posedge,
          TestSignal              => WD28_ipd,
          TestSignalName          => "WD28",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD28_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD28_WCLK_noedge_posedge,
          HoldLow                 => thold_WD28_WCLK_noedge_posedge,
          HoldHigh                => thold_WD28_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD29_WCLK_posedge,
          TimingData              => Tmkr_WD29_WCLK_posedge,
          TestSignal              => WD29_ipd,
          TestSignalName          => "WD29",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD29_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD29_WCLK_noedge_posedge,
          HoldLow                 => thold_WD29_WCLK_noedge_posedge,
          HoldHigh                => thold_WD29_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD30_WCLK_posedge,
          TimingData              => Tmkr_WD30_WCLK_posedge,
          TestSignal              => WD30_ipd,
          TestSignalName          => "WD30",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD30_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD30_WCLK_noedge_posedge,
          HoldLow                 => thold_WD30_WCLK_noedge_posedge,
          HoldHigh                => thold_WD30_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD31_WCLK_posedge,
          TimingData              => Tmkr_WD31_WCLK_posedge,
          TestSignal              => WD31_ipd,
          TestSignalName          => "WD31",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD31_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD31_WCLK_noedge_posedge,
          HoldLow                 => thold_WD31_WCLK_noedge_posedge,
          HoldHigh                => thold_WD31_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX32_RX8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Tviol_WD8_WCLK_posedge or
                 Tviol_WD9_WCLK_posedge or
                 Tviol_WD10_WCLK_posedge or
                 Tviol_WD11_WCLK_posedge or
                 Tviol_WD12_WCLK_posedge or
                 Tviol_WD13_WCLK_posedge or
                 Tviol_WD14_WCLK_posedge or
                 Tviol_WD15_WCLK_posedge or
                 Tviol_WD16_WCLK_posedge or
                 Tviol_WD17_WCLK_posedge or
                 Tviol_WD18_WCLK_posedge or
                 Tviol_WD19_WCLK_posedge or
                 Tviol_WD20_WCLK_posedge or
                 Tviol_WD21_WCLK_posedge or
                 Tviol_WD22_WCLK_posedge or
                 Tviol_WD23_WCLK_posedge or
                 Tviol_WD24_WCLK_posedge or
                 Tviol_WD25_WCLK_posedge or
                 Tviol_WD26_WCLK_posedge or
                 Tviol_WD27_WCLK_posedge or
                 Tviol_WD28_WCLK_posedge or
                 Tviol_WD29_WCLK_posedge or
                 Tviol_WD30_WCLK_posedge or
                 Tviol_WD31_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD1, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD2, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD2, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD3, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD3, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

    VitalBehavior_RD4  : process
      variable RD4_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD4_zd := RD(4);

    VitalPathDelay01 (
      OutSignal => RD4,
      GlitchData => O_GlitchData,
      OutSignalName => "RD4",
      OutTemp => RD4_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD4, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD4, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD4, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD4, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD4, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD4, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD4, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD4, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD4, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD4, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD4, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD4, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(4);
      end process;

    VitalBehavior_RD5  : process
      variable RD5_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD5_zd := RD(5);

    VitalPathDelay01 (
      OutSignal => RD5,
      GlitchData => O_GlitchData,
      OutSignalName => "RD5",
      OutTemp => RD5_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD5, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD5, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD5, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD5, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD5, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD5, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD5, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD5, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD5, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD5, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD5, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD5, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(5);
      end process;

    VitalBehavior_RD6  : process
      variable RD6_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD6_zd := RD(6);

    VitalPathDelay01 (
      OutSignal => RD6,
      GlitchData => O_GlitchData,
      OutSignalName => "RD6",
      OutTemp => RD6_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD6, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD6, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD6, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD6, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD6, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD6, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD6, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD6, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD6, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD6, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD6, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD6, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(6);
      end process;

    VitalBehavior_RD7  : process
      variable RD7_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD7_zd := RD(7);

    VitalPathDelay01 (
      OutSignal => RD7,
      GlitchData => O_GlitchData,
      OutSignalName => "RD7",
      OutTemp => RD7_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD7, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD7, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD7, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD7, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD7, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD7, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD7, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD7, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD7, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD7, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD7, TRUE),
               11 => (RST_ipd'last_event, tpd_RST_RD7, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(7);
      end process;

	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 9,
		WDATA_WIDTH    => 32,
		RADDR_WIDTH    => 11,
		RDATA_WIDTH    => 8,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16KA_WX32_RX8_VITAL of RAMB16KA_WX32_RX8 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX32_RX8_VITAL;


----- CELL RAMB16KA_WX4_RX1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16KA_WX4_RX1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD12_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD13_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

     
      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                            :	in    STD_ULOGIC;
      WAD11                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RAD12                            :	in    STD_ULOGIC;
      RAD13                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16KA_WX4_RX1 : entity is FALSE;
end RAMB16KA_WX4_RX1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX4_RX1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd      : std_ulogic := 'X';
      signal WAD11_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';
      signal RAD12_ipd      : std_ulogic := 'X';
      signal RAD13_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (3 downto 0);
 	signal WAD : std_logic_vector (11 downto 0);
 	signal RAD : std_logic_vector (13 downto 0);
	signal RD  : std_logic_vector (0 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD13_ipd & RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);
        VitalWireDelay (RAD13_ipd, RAD13, tipd_RAD13);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge    : std_ulogic  := '0';

 
        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

      
        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WAD10_WCLK_posedge or
                 Tviol_WAD11_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD0, TRUE),
               12 => (RAD12_ipd'last_event, tpd_RAD12_RD0, TRUE),
               13 => (RAD13_ipd'last_event, tpd_RAD13_RD0, TRUE),
               14 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 12,
		WDATA_WIDTH    => 4,
		RADDR_WIDTH    => 14,
		RDATA_WIDTH    => 1,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16KA_WX4_RX1_VITAL of RAMB16KA_WX4_RX1 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX4_RX1_VITAL;


----- CELL RAMB16KA_WX4_RX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16KA_WX4_RX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD12_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD12_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD11_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD11_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

     
      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                            :	in    STD_ULOGIC;
      WAD11                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RAD12                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16KA_WX4_RX2 : entity is FALSE;
end RAMB16KA_WX4_RX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX4_RX2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd      : std_ulogic := 'X';
      signal WAD11_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';
      signal RAD12_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (3 downto 0);
 	signal WAD : std_logic_vector (11 downto 0);
 	signal RAD : std_logic_vector (12 downto 0);
	signal RD  : std_logic_vector (1 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD11_ipd & WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);
        VitalWireDelay (WAD11_ipd, WAD11, tipd_WAD11);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD11_WCLK_posedge    : std_ulogic  := '0';

 
        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD11_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

      
        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD11_WCLK_posedge,
          TimingData              => Tmkr_WAD11_WCLK_posedge,
          TestSignal              => WAD11_ipd,
          TestSignalName          => "WAD11",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD11_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD11_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD11_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD11_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX4_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WAD10_WCLK_posedge or
                 Tviol_WAD11_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD0, TRUE),
               12 => (RAD12_ipd'last_event, tpd_RAD12_RD0, TRUE),
               13 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD1, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD1, TRUE),
               12 => (RAD12_ipd'last_event, tpd_RAD12_RD1, TRUE),
               13 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 12,
		WDATA_WIDTH    => 4,
		RADDR_WIDTH    => 13,
		RDATA_WIDTH    => 2,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16KA_WX4_RX2_VITAL of RAMB16KA_WX4_RX2 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX4_RX2_VITAL;


----- CELL RAMB16KA_WX8_RX1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16KA_WX8_RX1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD12_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD13_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

     
      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD13                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RAD12                            :	in    STD_ULOGIC;
      RAD13                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16KA_WX8_RX1 : entity is FALSE;
end RAMB16KA_WX8_RX1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX8_RX1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';
      signal RAD12_ipd      : std_ulogic := 'X';
      signal RAD13_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (7 downto 0);
 	signal WAD : std_logic_vector (10 downto 0);
 	signal RAD : std_logic_vector (13 downto 0);
	signal RD  : std_logic_vector (0 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD13_ipd & RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);
        VitalWireDelay (RAD13_ipd, RAD13, tipd_RAD13);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge    : std_ulogic  := '0';

 
        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

      
        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WAD10_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD0, TRUE),
               12 => (RAD12_ipd'last_event, tpd_RAD12_RD0, TRUE),
               13 => (RAD13_ipd'last_event, tpd_RAD13_RD0, TRUE),
               14 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 11,
		WDATA_WIDTH    => 8,
		RADDR_WIDTH    => 14,
		RDATA_WIDTH    => 1,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16KA_WX8_RX1_VITAL of RAMB16KA_WX8_RX1 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX8_RX1_VITAL;


----- CELL RAMB16KA_WX8_RX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16KA_WX8_RX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD12_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD12_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

     
      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD12                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RAD12                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16KA_WX8_RX2 : entity is FALSE;
end RAMB16KA_WX8_RX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX8_RX2 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';
      signal RAD12_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (7 downto 0);
 	signal WAD : std_logic_vector (10 downto 0);
 	signal RAD : std_logic_vector (12 downto 0);
	signal RD  : std_logic_vector (1 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD12_ipd & RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);
        VitalWireDelay (RAD12_ipd, RAD12, tipd_RAD12);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge    : std_ulogic  := '0';

 
        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

      
        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX2",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WAD10_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD0, TRUE),
               12 => (RAD12_ipd'last_event, tpd_RAD12_RD0, TRUE),
               13 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD1, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD1, TRUE),
               12 => (RAD12_ipd'last_event, tpd_RAD12_RD1, TRUE),
               13 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 11,
		WDATA_WIDTH    => 8,
		RADDR_WIDTH    => 13,
		RDATA_WIDTH    => 2,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16KA_WX8_RX2_VITAL of RAMB16KA_WX8_RX2 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX8_RX2_VITAL;


----- CELL RAMB16KA_WX8_RX4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

-- entity declaration --
entity RAMB16KA_WX8_RX4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      RAM_INIT_FILE   : string  := "";
      tpd_RST_RD0                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD1                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD2                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RST_RD3                      :  VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD0                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD1                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD2                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tpd_RAD0_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD1_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD2_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD3_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD4_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD5_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD6_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD7_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD8_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD9_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD10_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_RAD11_RD3                      :VitalDelayType01 := (0.0 ns, 0.0 ns);

      tsetup_WCEN_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCEN_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WCS1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WCS1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge      :	VitalDelayType   := 0.0 ns;

      tsetup_WD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD6_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WD7_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_WD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_WAD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD0_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD1_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD2_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD3_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD4_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD5_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD6_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD6_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD7_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD7_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD8_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD8_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD9_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD9_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WAD10_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WAD10_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

     
      tpw_WCLK_posedge                   :	VitalDelayType   := 2.0 ns;
      tpw_RST_posedge                    :	VitalDelayType   := 2.0 ns;

      trecovery_RST_WCLK_posedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_RST_WCLK_posedge_posedge     :	VitalDelayType   := 0.0 ns;

      tipd_WCEN                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WE                            :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCS1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RST                           :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_WAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_RAD0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD10                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RAD11                          :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      WCEN                            :	in    STD_ULOGIC;
      WCLK                            :	in    STD_ULOGIC;
      WCS0                            :	in    STD_ULOGIC;
      WCS1                            :	in    STD_ULOGIC;
      WE                              :	in    STD_ULOGIC;
      RST                             :	in    STD_ULOGIC;
      WD0                            :	in    STD_ULOGIC;
      WD1                            :	in    STD_ULOGIC;
      WD2                            :	in    STD_ULOGIC;
      WD3                            :	in    STD_ULOGIC;
      WD4                            :	in    STD_ULOGIC;
      WD5                            :	in    STD_ULOGIC;
      WD6                            :	in    STD_ULOGIC;
      WD7                            :	in    STD_ULOGIC;
      WAD0                            :	in    STD_ULOGIC;
      WAD1                            :	in    STD_ULOGIC;
      WAD2                            :	in    STD_ULOGIC;
      WAD3                            :	in    STD_ULOGIC;
      WAD4                            :	in    STD_ULOGIC;
      WAD5                            :	in    STD_ULOGIC;
      WAD6                            :	in    STD_ULOGIC;
      WAD7                            :	in    STD_ULOGIC;
      WAD8                            :	in    STD_ULOGIC;
      WAD9                            :	in    STD_ULOGIC;
      WAD10                            :	in    STD_ULOGIC;
      RAD0                            :	in    STD_ULOGIC;
      RAD1                            :	in    STD_ULOGIC;
      RAD2                            :	in    STD_ULOGIC;
      RAD3                            :	in    STD_ULOGIC;
      RAD4                            :	in    STD_ULOGIC;
      RAD5                            :	in    STD_ULOGIC;
      RAD6                            :	in    STD_ULOGIC;
      RAD7                            :	in    STD_ULOGIC;
      RAD8                            :	in    STD_ULOGIC;
      RAD9                            :	in    STD_ULOGIC;
      RAD10                            :	in    STD_ULOGIC;
      RAD11                            :	in    STD_ULOGIC;
      RD0                            :	out    STD_ULOGIC;
      RD1                            :	out    STD_ULOGIC;
      RD2                            :	out    STD_ULOGIC;
      RD3                            :	out    STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB16KA_WX8_RX4 : entity is FALSE;
end RAMB16KA_WX8_RX4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB16KA_WX8_RX4 is
  attribute VITAL_LEVEL0 of VITAL : architecture is FALSE;

	component SC_PDPRAMA_16K
	   generic (
		WADDR_WIDTH    : integer := 10;
		WDATA_WIDTH    : integer := 16;
		RADDR_WIDTH    : integer := 9;
		RDATA_WIDTH    : integer := 32;
		MEM_INIT_FLAG   : integer := 0;
		MEM_INIT_FILE   : string  := "dummy");
	   port (
		WCEN : in  STD_LOGIC ;
		WCLK : in  STD_LOGIC ;
		WE   : in  STD_LOGIC ;
		WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
		RST  : in  STD_LOGIC ;
		WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
		WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
		RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
		RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
		);
	end component ;

      signal WCEN_ipd      : std_ulogic := 'X';
      signal WCLK_ipd      : std_ulogic := 'X';
      signal WCS0_ipd      : std_ulogic := 'X';
      signal WCS1_ipd      : std_ulogic := 'X';
      signal WE_ipd        : std_ulogic := 'X';

      signal RST_ipd       : std_ulogic := 'X';

      signal WD0_ipd      : std_ulogic := 'X';
      signal WD1_ipd      : std_ulogic := 'X';
      signal WD2_ipd      : std_ulogic := 'X';
      signal WD3_ipd      : std_ulogic := 'X';
      signal WD4_ipd      : std_ulogic := 'X';
      signal WD5_ipd      : std_ulogic := 'X';
      signal WD6_ipd      : std_ulogic := 'X';
      signal WD7_ipd      : std_ulogic := 'X';

      signal WAD0_ipd      : std_ulogic := 'X';
      signal WAD1_ipd      : std_ulogic := 'X';
      signal WAD2_ipd      : std_ulogic := 'X';
      signal WAD3_ipd      : std_ulogic := 'X';
      signal WAD4_ipd      : std_ulogic := 'X';
      signal WAD5_ipd      : std_ulogic := 'X';
      signal WAD6_ipd      : std_ulogic := 'X';
      signal WAD7_ipd      : std_ulogic := 'X';
      signal WAD8_ipd      : std_ulogic := 'X';
      signal WAD9_ipd      : std_ulogic := 'X';
      signal WAD10_ipd      : std_ulogic := 'X';

      signal RAD0_ipd      : std_ulogic := 'X';
      signal RAD1_ipd      : std_ulogic := 'X';
      signal RAD2_ipd      : std_ulogic := 'X';
      signal RAD3_ipd      : std_ulogic := 'X';
      signal RAD4_ipd      : std_ulogic := 'X';
      signal RAD5_ipd      : std_ulogic := 'X';
      signal RAD6_ipd      : std_ulogic := 'X';
      signal RAD7_ipd      : std_ulogic := 'X';
      signal RAD8_ipd      : std_ulogic := 'X';
      signal RAD9_ipd      : std_ulogic := 'X';
      signal RAD10_ipd      : std_ulogic := 'X';
      signal RAD11_ipd      : std_ulogic := 'X';

	signal WCS : std_logic_vector (1 downto 0);
	signal WD  : std_logic_vector (7 downto 0);
 	signal WAD : std_logic_vector (10 downto 0);
 	signal RAD : std_logic_vector (11 downto 0);
	signal RD  : std_logic_vector (3 downto 0);

      CONSTANT  RAM_INIT_FLAG       :  integer := init_flag(RAM_INIT_FILE);
begin 

	WCS <= WCS1_ipd & WCS0_ipd;
	WD <= WD7_ipd & WD6_ipd & WD5_ipd & WD4_ipd & WD3_ipd & WD2_ipd & WD1_ipd & WD0_ipd;
	WAD <= WAD10_ipd & WAD9_ipd & WAD8_ipd & WAD7_ipd & WAD6_ipd & WAD5_ipd & WAD4_ipd & WAD3_ipd & WAD2_ipd & WAD1_ipd & WAD0_ipd;
	RAD <= RAD11_ipd & RAD10_ipd & RAD9_ipd & RAD8_ipd & RAD7_ipd & RAD6_ipd & RAD5_ipd & RAD4_ipd & RAD3_ipd & RAD2_ipd & RAD1_ipd & RAD0_ipd;

 ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin

        VitalWireDelay (WCEN_ipd, WCEN, tipd_WCEN);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        VitalWireDelay (WCS0_ipd, WCS0, tipd_WCS0);
        VitalWireDelay (WCS1_ipd, WCS1, tipd_WCS1);
        VitalWireDelay (WE_ipd, WE, tipd_WE);

        VitalWireDelay (RST_ipd, RST, tipd_RST);

        VitalWireDelay (WD0_ipd, WD0, tipd_WD0);
        VitalWireDelay (WD1_ipd, WD1, tipd_WD1);
        VitalWireDelay (WD2_ipd, WD2, tipd_WD2);
        VitalWireDelay (WD3_ipd, WD3, tipd_WD3);
        VitalWireDelay (WD4_ipd, WD4, tipd_WD4);
        VitalWireDelay (WD5_ipd, WD5, tipd_WD5);
        VitalWireDelay (WD6_ipd, WD6, tipd_WD6);
        VitalWireDelay (WD7_ipd, WD7, tipd_WD7);

        VitalWireDelay (WAD0_ipd, WAD0, tipd_WAD0);
        VitalWireDelay (WAD1_ipd, WAD1, tipd_WAD1);
        VitalWireDelay (WAD2_ipd, WAD2, tipd_WAD2);
        VitalWireDelay (WAD3_ipd, WAD3, tipd_WAD3);
        VitalWireDelay (WAD4_ipd, WAD4, tipd_WAD4);
        VitalWireDelay (WAD5_ipd, WAD5, tipd_WAD5);
        VitalWireDelay (WAD6_ipd, WAD6, tipd_WAD6);
        VitalWireDelay (WAD7_ipd, WAD7, tipd_WAD7);
        VitalWireDelay (WAD8_ipd, WAD8, tipd_WAD8);
        VitalWireDelay (WAD9_ipd, WAD9, tipd_WAD9);
        VitalWireDelay (WAD10_ipd, WAD10, tipd_WAD10);

        VitalWireDelay (RAD0_ipd, RAD0, tipd_RAD0);
        VitalWireDelay (RAD1_ipd, RAD1, tipd_RAD1);
        VitalWireDelay (RAD2_ipd, RAD2, tipd_RAD2);
        VitalWireDelay (RAD3_ipd, RAD3, tipd_RAD3);
        VitalWireDelay (RAD4_ipd, RAD4, tipd_RAD4);
        VitalWireDelay (RAD5_ipd, RAD5, tipd_RAD5);
        VitalWireDelay (RAD6_ipd, RAD6, tipd_RAD6);
        VitalWireDelay (RAD7_ipd, RAD7, tipd_RAD7);
        VitalWireDelay (RAD8_ipd, RAD8, tipd_RAD8);
        VitalWireDelay (RAD9_ipd, RAD9, tipd_RAD9);
        VitalWireDelay (RAD10_ipd, RAD10, tipd_RAD10);
        VitalWireDelay (RAD11_ipd, RAD11, tipd_RAD11);

      end block;

      --------------------
      --  Write Behavior
      --------------------
      VITALBehavior : process
        -- Local variables used for timing checks

        variable Tviol_WCEN_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WCS1_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WE_WCLK_posedge      : std_ulogic  := '0';

        variable Tviol_WD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WD7_WCLK_posedge    : std_ulogic  := '0';

        variable Tviol_WAD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD5_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD6_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD7_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD8_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD9_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_WAD10_WCLK_posedge    : std_ulogic  := '0';

 
        variable Tmkr_WCEN_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WCS1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_WAD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD6_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD7_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD8_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD9_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WAD10_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

      
        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RST       : std_ulogic := '0';
        variable PInfo_RST       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality
        variable Violation       : std_ulogic := '0';

        variable RD0_zd          : std_ulogic := 'X';
        variable RD1_zd          : std_ulogic := 'X';
        variable RD2_zd          : std_ulogic := 'X';
        variable RD3_zd          : std_ulogic := 'X';
        variable O_GlitchData    : VitalGlitchDataType;

    begin

    ------------------------
    --  Timing Check Section
    ------------------------

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WCEN_WCLK_posedge,
          TimingData              => Tmkr_WCEN_WCLK_posedge,
          TestSignal              => WCEN_ipd,
          TestSignalName          => "WCEN",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCEN_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCEN_WCLK_noedge_posedge,
          HoldLow                 => thold_WCEN_WCLK_noedge_posedge,
          HoldHigh                => thold_WCEN_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS0_WCLK_posedge,
          TimingData              => Tmkr_WCS0_WCLK_posedge,
          TestSignal              => WCS0_ipd,
          TestSignalName          => "WCS0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS0_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS0_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WCS1_WCLK_posedge,
          TimingData              => Tmkr_WCS1_WCLK_posedge,
          TestSignal              => WCS1_ipd,
          TestSignalName          => "WCS1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WCS1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WCS1_WCLK_noedge_posedge,
          HoldLow                 => thold_WCS1_WCLK_noedge_posedge,
          HoldHigh                => thold_WCS1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD0_WCLK_posedge,
          TimingData              => Tmkr_WD0_WCLK_posedge,
          TestSignal              => WD0_ipd,
          TestSignalName          => "WD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD1_WCLK_posedge,
          TimingData              => Tmkr_WD1_WCLK_posedge,
          TestSignal              => WD1_ipd,
          TestSignalName          => "WD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD2_WCLK_posedge,
          TimingData              => Tmkr_WD2_WCLK_posedge,
          TestSignal              => WD2_ipd,
          TestSignalName          => "WD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD3_WCLK_posedge,
          TimingData              => Tmkr_WD3_WCLK_posedge,
          TestSignal              => WD3_ipd,
          TestSignalName          => "WD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD4_WCLK_posedge,
          TimingData              => Tmkr_WD4_WCLK_posedge,
          TestSignal              => WD4_ipd,
          TestSignalName          => "WD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD5_WCLK_posedge,
          TimingData              => Tmkr_WD5_WCLK_posedge,
          TestSignal              => WD5_ipd,
          TestSignalName          => "WD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD6_WCLK_posedge,
          TimingData              => Tmkr_WD6_WCLK_posedge,
          TestSignal              => WD6_ipd,
          TestSignalName          => "WD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WD7_WCLK_posedge,
          TimingData              => Tmkr_WD7_WCLK_posedge,
          TestSignal              => WD7_ipd,
          TestSignalName          => "WD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD0_WCLK_posedge,
          TimingData              => Tmkr_WAD0_WCLK_posedge,
          TestSignal              => WAD0_ipd,
          TestSignalName          => "WAD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD0_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD0_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD0_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD1_WCLK_posedge,
          TimingData              => Tmkr_WAD1_WCLK_posedge,
          TestSignal              => WAD1_ipd,
          TestSignalName          => "WAD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD1_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD1_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD1_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD2_WCLK_posedge,
          TimingData              => Tmkr_WAD2_WCLK_posedge,
          TestSignal              => WAD2_ipd,
          TestSignalName          => "WAD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD2_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD2_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD2_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD3_WCLK_posedge,
          TimingData              => Tmkr_WAD3_WCLK_posedge,
          TestSignal              => WAD3_ipd,
          TestSignalName          => "WAD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD3_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD3_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD3_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD4_WCLK_posedge,
          TimingData              => Tmkr_WAD4_WCLK_posedge,
          TestSignal              => WAD4_ipd,
          TestSignalName          => "WAD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD4_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD4_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD4_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD5_WCLK_posedge,
          TimingData              => Tmkr_WAD5_WCLK_posedge,
          TestSignal              => WAD5_ipd,
          TestSignalName          => "WAD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD5_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD5_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD5_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD6_WCLK_posedge,
          TimingData              => Tmkr_WAD6_WCLK_posedge,
          TestSignal              => WAD6_ipd,
          TestSignalName          => "WAD6",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD6_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD6_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD6_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD6_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD7_WCLK_posedge,
          TimingData              => Tmkr_WAD7_WCLK_posedge,
          TestSignal              => WAD7_ipd,
          TestSignalName          => "WAD7",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD7_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD7_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD7_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD7_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD8_WCLK_posedge,
          TimingData              => Tmkr_WAD8_WCLK_posedge,
          TestSignal              => WAD8_ipd,
          TestSignalName          => "WAD8",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD8_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD8_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD8_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD8_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD9_WCLK_posedge,
          TimingData              => Tmkr_WAD9_WCLK_posedge,
          TestSignal              => WAD9_ipd,
          TestSignalName          => "WAD9",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD9_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD9_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD9_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD9_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WAD10_WCLK_posedge,
          TimingData              => Tmkr_WAD10_WCLK_posedge,
          TestSignal              => WAD10_ipd,
          TestSignalName          => "WAD10",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WAD10_WCLK_noedge_posedge,
          SetupLow                => tsetup_WAD10_WCLK_noedge_posedge,
          HoldLow                 => thold_WAD10_WCLK_noedge_posedge,
          HoldHigh                => thold_WAD10_WCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RST,
          PeriodData              => PInfo_RST,
          TestSignal              => RST_ipd,
          TestSignalName          => "RST",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RST_posedge,
          PulseWidthLow           => tpw_RST_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/RAMB16KA_WX8_RX4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WCEN_WCLK_posedge or 
                 Tviol_WE_WCLK_posedge or 
                 Tviol_WCS0_WCLK_posedge or 
                 Tviol_WCS1_WCLK_posedge or 
                 Tviol_WAD0_WCLK_posedge or
                 Tviol_WAD1_WCLK_posedge or
                 Tviol_WAD2_WCLK_posedge or
                 Tviol_WAD3_WCLK_posedge or
                 Tviol_WAD4_WCLK_posedge or
                 Tviol_WAD5_WCLK_posedge or
                 Tviol_WAD6_WCLK_posedge or
                 Tviol_WAD7_WCLK_posedge or
                 Tviol_WAD8_WCLK_posedge or
                 Tviol_WAD9_WCLK_posedge or
                 Tviol_WAD10_WCLK_posedge or
                 Tviol_WD0_WCLK_posedge or
                 Tviol_WD1_WCLK_posedge or
                 Tviol_WD2_WCLK_posedge or
                 Tviol_WD3_WCLK_posedge or
                 Tviol_WD4_WCLK_posedge or
                 Tviol_WD5_WCLK_posedge or
                 Tviol_WD6_WCLK_posedge or
                 Tviol_WD7_WCLK_posedge or
                 Pviol_WCLK or Pviol_RST;

    -------------------------
    --  Functionality Section
    -------------------------

wait on WCEN_ipd,WCLK_ipd, WE_ipd, WCS, RST_ipd, WD, WAD, RAD;


      end process VITALBehavior;


    VitalBehavior_RD0  : process
      variable RD0_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD0_zd := RD(0);

    VitalPathDelay01 (
      OutSignal => RD0,
      GlitchData => O_GlitchData,
      OutSignalName => "RD0",
      OutTemp => RD0_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD0, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD0, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD0, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD0, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD0, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD0, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD0, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD0, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD0, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD0, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD0, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD0, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD0, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(0);
      end process;

    VitalBehavior_RD1  : process
      variable RD1_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD1_zd := RD(1);

    VitalPathDelay01 (
      OutSignal => RD1,
      GlitchData => O_GlitchData,
      OutSignalName => "RD1",
      OutTemp => RD1_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD1, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD1, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD1, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD1, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD1, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD1, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD1, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD1, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD1, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD1, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD1, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD1, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD1, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(1);
      end process;

    VitalBehavior_RD2  : process
      variable RD2_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD2_zd := RD(2);

    VitalPathDelay01 (
      OutSignal => RD2,
      GlitchData => O_GlitchData,
      OutSignalName => "RD2",
      OutTemp => RD2_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD2, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD2, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD2, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD2, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD2, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD2, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD2, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD2, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD2, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD2, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD2, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD2, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD2, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(2);
      end process;

    VitalBehavior_RD3  : process
      variable RD3_zd		: std_ulogic := 'X';
      variable O_GlitchData     : VitalGlitchDataType;

    begin

      RD3_zd := RD(3);

    VitalPathDelay01 (
      OutSignal => RD3,
      GlitchData => O_GlitchData,
      OutSignalName => "RD3",
      OutTemp => RD3_zd,
      Paths => (
               0 => (RAD0_ipd'last_event, tpd_RAD0_RD3, TRUE),
               1 => (RAD1_ipd'last_event, tpd_RAD1_RD3, TRUE),
               2 => (RAD2_ipd'last_event, tpd_RAD2_RD3, TRUE),
               3 => (RAD3_ipd'last_event, tpd_RAD3_RD3, TRUE),
               4 => (RAD4_ipd'last_event, tpd_RAD4_RD3, TRUE),
               5 => (RAD5_ipd'last_event, tpd_RAD5_RD3, TRUE),
               6 => (RAD6_ipd'last_event, tpd_RAD6_RD3, TRUE),
               7 => (RAD7_ipd'last_event, tpd_RAD7_RD3, TRUE),
               8 => (RAD8_ipd'last_event, tpd_RAD8_RD3, TRUE),
               9 => (RAD9_ipd'last_event, tpd_RAD9_RD3, TRUE),
               10 => (RAD10_ipd'last_event, tpd_RAD10_RD3, TRUE),
               11 => (RAD11_ipd'last_event, tpd_RAD11_RD3, TRUE),
               12 => (RST_ipd'last_event, tpd_RST_RD3, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

      wait on RD(3);
      end process;

	PDPRAMA_INST: SC_PDPRAMA_16K
	   generic map (
		WADDR_WIDTH    => 11,
		WDATA_WIDTH    => 8,
		RADDR_WIDTH    => 12,
		RDATA_WIDTH    => 4,
		MEM_INIT_FLAG  => RAM_INIT_FLAG,
		MEM_INIT_FILE  => RAM_INIT_FILE)
	   port map (
		WCEN => WCEN_ipd ,
		WCLK => WCLK_ipd ,
		WE   => WE_ipd ,
		WCS  => WCS,
		RST  => RST_ipd ,
		WD   => WD,
		WAD  => WAD,
		RAD  => RAD,
		RD   => RD
		);
end VITAL;

configuration CFG_RAMB16KA_WX8_RX4_VITAL of RAMB16KA_WX8_RX4 is
   for VITAL
   end for;
end CFG_RAMB16KA_WX8_RX4_VITAL;


-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
-- CAM
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

USE ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

library lc5kmx;
use lc5kmx.components.all;

entity cam is
  generic ( lpm_type                  : string  := "Lattice_MEM";
	    module_type               : string  := "CAM";
	    module_width              : integer := 1;
	    module_numwords           : integer := 1;
	    module_widthad            : integer := 1;
            module_init_file          : string := "";
	    module_hint               : string  := "UNUSED");
   port(
      ClockEn                      :	in    STD_ULOGIC;
      WE                           :	in    STD_ULOGIC;
      Clock                        :	in    STD_ULOGIC;
      EnMask                       :	in    STD_ULOGIC;
      WrMask                       :	in    STD_ULOGIC;
      WrDC                         :	in    STD_ULOGIC;
      Reset                        :	in    STD_ULOGIC;
      WrAddress                    :	in    STD_LOGIC_VECTOR(module_widthad-1 downto 0);
      Data                         :	in    STD_LOGIC_VECTOR(module_width-1 downto 0);
      Address                      :	out   STD_LOGIC_VECTOR(module_widthad-1 downto 0);
      Match                        :	out   STD_ULOGIC;
      MulMatch                     :	out   STD_ULOGIC);

end cam;

architecture fun_simulation of cam is

	component SC_CAM_16K

	generic (
		ADDR_WIDTH    : integer :=  7;
		DATA_WIDTH    : integer := 48;
                MEM_INIT_FLAG : integer :=  0;  
	        MEM_INIT_FILE : string  := ""
		);
	port (
		CE        :  in  STD_LOGIC ;
		WE        :  in  STD_LOGIC ;
		CLK       :  in  STD_LOGIC ;
		EN_MASK   :  in  STD_LOGIC ;
		WR_MASK   :  in  STD_LOGIC ;
		WR_DC     :  in  STD_LOGIC ;
		RST       :  in  STD_LOGIC ;
		CS        :  in  STD_LOGIC_VECTOR ( 1 downto 0) ;
		WAD       :  in  STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0);
		WD        :  in  STD_LOGIC_VECTOR ( DATA_WIDTH -1 downto 0);
		CO        :  out STD_LOGIC_VECTOR ( ADDR_WIDTH -1 downto 0);
		MATCH     :  out STD_LOGIC;
		MUL_MATCH :  out STD_LOGIC
		);

	end component ;

	--signal cs : std_logic_vector ( 1 downto 0);
	signal cs0 : std_logic_vector (3 downto 0);
	signal cs_0 : std_logic_vector (1 downto 0);
	signal cs_1 : std_logic_vector (1 downto 0);
	signal cs_2 : std_logic_vector (1 downto 0);
	signal cs_3 : std_logic_vector (1 downto 0);
	signal Address_0 : std_logic_vector (6 downto 0);
	signal Address_1 : std_logic_vector (6 downto 0);
	signal Address_2 : std_logic_vector (6 downto 0);
	signal Address_3 : std_logic_vector (6 downto 0);
	signal match_address : std_logic_vector (6 downto 0);
	signal match_address_ff : std_logic_vector (6 downto 0);
	signal match_bit : std_logic;
	signal Match_0 : std_logic;
	signal Match_1 : std_logic;
	signal Match_2 : std_logic;
	signal Match_3 : std_logic;
	signal MulMatch_0 : std_logic;
	signal MulMatch_1 : std_logic;
	signal MulMatch_2 : std_logic;
	signal MulMatch_3 : std_logic;
	
        CONSTANT  module_init_flag       :  integer := init_flag(module_init_file);

begin
        --cs <= "11";

   cs_0 <= "1" & cs0(0);
   cs_1 <= "1" & cs0(1);
   cs_2 <= "1" & cs0(2);
   cs_3 <= "1" & cs0(3);
   Match <= match_bit;
   ------------------------------------------------------------------
   CAM_inst_0 : SC_CAM_16K
      generic map (
	 ADDR_WIDTH    => 7, DATA_WIDTH    => module_width,
         MEM_INIT_FILE => module_init_file, MEM_INIT_FLAG => module_init_flag )
      port map (
	 CE => ClockEn, WE => We, CLK => Clock, EN_MASK => EnMask, 
         WR_MASK => WrMask, WR_DC => WrDc, RST => Reset, CS => cs_0,
         WAD => WrAddress(6 downto 0), WD => Data, CO => Address_0,
	 MATCH => Match_0, MUL_MATCH => MulMatch_0 );
   ------------------------------------------------------------------
   CAM_inst_1  : SC_CAM_16K
      generic map (
	 ADDR_WIDTH    => 7, DATA_WIDTH    => module_width,
         MEM_INIT_FILE => module_init_file, MEM_INIT_FLAG => module_init_flag )
      port map (
	 CE => ClockEn, WE => We, CLK => Clock, EN_MASK => EnMask, 
         WR_MASK => WrMask, WR_DC => WrDc, RST => Reset, CS => cs_1,
         WAD => WrAddress(6 downto 0), WD => Data, CO => Address_1,
	 MATCH => Match_1, MUL_MATCH => MulMatch_1 );
	 
   ------------------------------------------------------------------
   CAM_inst_2 : SC_CAM_16K
      generic map (
	 ADDR_WIDTH    => 7, DATA_WIDTH    => module_width,
         MEM_INIT_FILE => module_init_file, MEM_INIT_FLAG => module_init_flag )
      port map (
	 CE => ClockEn, WE => We, CLK => Clock, EN_MASK => EnMask, 
         WR_MASK => WrMask, WR_DC => WrDc, RST => Reset, CS => cs_2,
         WAD => WrAddress(6 downto 0), WD => Data, CO => Address_2,
	 MATCH => Match_2, MUL_MATCH => MulMatch_2 );
   ------------------------------------------------------------------
   CAM_inst_3 : SC_CAM_16K
      generic map (
	 ADDR_WIDTH    => 7, DATA_WIDTH    => module_width,
         MEM_INIT_FILE => module_init_file, MEM_INIT_FLAG => module_init_flag )
      port map (
	 CE => ClockEn, WE => We, CLK => Clock, EN_MASK => EnMask, 
         WR_MASK => WrMask, WR_DC => WrDc, RST => Reset, CS => cs_3,
         WAD => WrAddress(6 downto 0), WD => Data, CO => Address_3,
	 MATCH => Match_3, MUL_MATCH => MulMatch_3 );
   ------------------------------------------------------------------
   
   ------------------------------------------------------------------
 
   process (WrAddress, Match_0, Match_1, Match_2, Match_3, 
      MulMatch_0, MulMatch_1, MulMatch_2, MulMatch_3,
      Address_0, Address_1, Address_2, Address_3,
	match_address, match_address_ff)
   begin
      ----------------------------------------
      if (module_widthad = 7) then --128
         cs0 (3 downto 0) <= "0001";
         match_bit <= Match_0;
         MulMatch <= MulMatch_0;
         match_address(6 downto 0) <= Address_0; 
         Address <= Address_0;
      ----------------------------------------
      elsif (module_widthad = 8) then --256
         cs0(0) <= not(WrAddress(module_widthad - 1));
         cs0(1) <= WrAddress(module_widthad - 1);
         cs0(3 downto 2) <= "00";
         match_bit <= Match_0 or Match_1;
         MulMatch <= MulMatch_0 or MulMatch_1 or (Match_0 and Match_1); 
         if Match_0 = '1' then 
            match_address(6 downto 0) <= Address_0; 
         elsif Match_1 = '1' then
            match_address(6 downto 0) <= Address_1;
         else 
            match_address(6 downto 0) <= "0000000";
         end if;
         if match_bit = '1' then 
           Address(6 downto 0 ) <= match_address;
         else
           Address(6 downto 0 ) <= match_address_ff;
         end if;
         Address(module_widthad - 1) <= not(Match_0) and Match_1;
      ----------------------------------------
      elsif (module_widthad = 9) then  --512 (1024 not valid)
         cs0(0) <= not(WrAddress(module_widthad-1)) and not(WrAddress(module_widthad-2));
         cs0(1) <= not(WrAddress(module_widthad-1)) and    (WrAddress(module_widthad-2));
         cs0(2) <=    (WrAddress(module_widthad-1)) and not(WrAddress(module_widthad-2));
         cs0(3) <=    (WrAddress(module_widthad-1)) and    (WrAddress(module_widthad-2));
         match_bit <= Match_0 or Match_1 or Match_2 or Match_3;
         MulMatch <= MulMatch_0 or MulMatch_1 or MulMatch_2 or MulMatch_3 or
            (Match_0 and Match_1) or (Match_0 and Match_2) or
            (Match_0 and Match_3) or (Match_1 and Match_2) or
            (Match_1 and Match_3) or (Match_2 and Match_3) ;
         if Match_0 = '1' then 
            match_address(6 downto 0) <= Address_0; 
         elsif Match_1 = '1' then
            match_address(6 downto 0) <= Address_1;
         elsif Match_2 = '1' then
            match_address(6 downto 0) <= Address_2;
         elsif Match_3 = '1' then
            match_address(6 downto 0) <= Address_3;
         else 
            match_address(6 downto 0) <= "0000000";
         end if;
         if match_bit = '1' then 
           Address(6 downto 0 ) <= match_address;
         else
           Address(6 downto 0 ) <= match_address_ff;
         end if;
         Address(module_widthad - 2) <= 
            (not(Match_0) and Match_1) or  
            (not(Match_0) and not(Match_1) and not(Match_2) and Match_3);
         Address(module_widthad - 1) <=  
            (not(Match_0) and not(Match_1) and Match_2) or  
            (not(Match_0) and not(Match_1) and not(Match_2) and Match_3);
      end if;
   end process;
   
   process (Clock, Reset)
   begin
      if (Reset = '1') then
         match_address_ff (6 downto 0 ) <= "0000000";
      elsif rising_edge(Clock) and match_bit = '1' then
         match_address_ff <= match_address;
      end if;
   end process;
         
end;

-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
-- FIFO_DC
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

entity fifo_dc is
  generic (
         lpm_type         : string  := "Lattice_MEM";
	 module_type      : string  := "FIFO_DC";
	 module_width     : integer := 1;
	 module_widthu    : integer := 1;
	 module_numwords  : integer := 2;
         module_amfull_flag : integer := 1;
         module_amempty_flag : integer := 1;
	 module_hint      : string  := "UNUSED");

  port (
	 Data          :  in  std_logic_vector (module_width-1 downto 0);
	 WrClock       :  in  std_logic;
	 WrEn          :  in  std_logic;
	 RdClock       :  in  std_logic;
	 RdEn          :  in  std_logic;
	 Reset          :  in  std_logic;
	 RPReset       :  in  std_logic;
	 Q             :  out std_logic_vector (module_width-1 downto 0);
	 Full          :  out std_logic;
	 Empty         :  out std_logic;
	 AlmostFull    :  out std_logic;
	 AlmostEmpty   :  out std_logic);

end fifo_dc;

architecture fun_simulation of fifo_dc is

  component SC_FIFO_16K_L

    generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0; 
        TERMINAL_COUNT : integer := 511; 
        MEM_INIT_FILE  : string  := "mem_init_file"

         );

    port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);

        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)

        ); 

end component;

     signal Rst, FullIn, EmptyIn : std_logic;


  begin

      Rst     <= '1';
      FullIn  <= '0';
      EmptyIn <= '1';


  SC_FIFO_inst : SC_FIFO_16K_L

    generic map (

        DEVICE_FAMILY   =>  open,
        WADDR_WIDTH     =>  module_widthu,
        WDATA_WIDTH     =>  module_width,
        RADDR_WIDTH     =>  module_widthu,
        RDATA_WIDTH     =>  module_width,
        ALMOST_FULL_X   =>  module_amfull_flag,
        ALMOST_EMPTY_Y  =>  module_amempty_flag,
        MEM_INIT_FLAG   =>  0,
        TERMINAL_COUNT  =>  module_numwords - 1,
        MEM_INIT_FILE   => open )

    port map (
        WE         => WrEn, 
        WCLK       => WrClock,
        RST        => Reset, 
        RPRST      => RPReset, 
        RE         => RdEn, 
        RCLK       => RdClock, 
        FULLIN     => FullIn, 
        EMPTYIN    => EmptyIn, 
        DI         => Data, 

        FULL       => Full, 
        EMPTY      => Empty, 
        AMFULL     => AlmostFull, 
        AMEMPTY    => AlmostEmpty, 
        DO         => Q
        ); 

end;



library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

entity fifo_dcx is
  generic (
         lpm_type          : string  := "Lattice_MEM";
	 module_type       : string  := "FIFO_DCX";
	 module_widthw     : integer := 1;
	 module_widthr     : integer := 1;
	 module_widthuw    : integer := 1;
	 module_widthur    : integer := 1;
	 module_numwordsw  : integer := 2;
	 module_numwordsr  : integer := 2;
         module_amfull_flag : integer := 1;
         module_amempty_flag : integer := 1;
	 module_hint      : string  := "UNUSED");

  port (
	 Data          :  in  std_logic_vector (module_widthw-1 downto 0);
	 WrClock       :  in  std_logic;
	 WrEn          :  in  std_logic;
	 RdClock       :  in  std_logic;
	 RdEn          :  in  std_logic;
	 Reset          :  in  std_logic;
	 RPReset       :  in  std_logic;
	 Q             :  out std_logic_vector (module_widthr-1 downto 0);
	 Full          :  out std_logic;
	 Empty         :  out std_logic;
	 AlmostFull    :  out std_logic;
	 AlmostEmpty   :  out std_logic);

end fifo_dcx;

architecture fun_simulation of fifo_dcx is

  component SC_FIFO_V2_16K

    generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0; 
        TERMINAL_COUNT : integer := 511; 
        MEM_INIT_FILE  : string  := "mem_init_file"

         );

    port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);

        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)

        ); 

end component;

     signal FullIn, EmptyIn : std_logic;


  begin

      FullIn  <= '0';
      EmptyIn <= '1';


  SC_FIFO_inst : SC_FIFO_V2_16K

    generic map (

        DEVICE_FAMILY   =>  open,
        WADDR_WIDTH     =>  module_widthuw,
        WDATA_WIDTH     =>  module_widthw,
        RADDR_WIDTH     =>  module_widthur,
        RDATA_WIDTH     =>  module_widthr,
        ALMOST_FULL_X   =>  module_amfull_flag,
        ALMOST_EMPTY_Y  =>  module_amempty_flag,
        MEM_INIT_FLAG   =>  0,
        TERMINAL_COUNT  =>  module_numwordsw - 1,
        MEM_INIT_FILE   => open )

    port map (
        WE         => WrEn, 
        WCLK       => WrClock,
        RST        => Reset, 
        RPRST      => RPReset, 
        RE         => RdEn, 
        RCLK       => RdClock, 
        FULLIN     => FullIn, 
        EMPTYIN    => EmptyIn, 
        DI         => Data, 

        FULL       => Full, 
        EMPTY      => Empty, 
        AMFULL     => AlmostFull, 
        AMEMPTY    => AlmostEmpty, 
        DO         => Q
        ); 

end;



library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;
    
entity ram_dp is
  generic( lpm_type                : string  := "Lattice_MEM";
	   module_type             : string := "RAM_DP";
	   module_widthw           : integer := 1;
	   module_widthr           : integer := 1;
	   module_numwordsw        : integer := 1;
	   module_widthadw         : integer := 1;
	   module_widthadr         : integer := 1;
   	   module_numwordsr        : integer := 1;
  	   module_indata           : string := "REGISTERED";
	   module_outdata          : string := "UNREGISTERED";
    	   module_addressw_control : string := "REGISTERED";
	   module_addressr_control : string := "REGISTERED";
	   module_hint             : string := "UNUSED";
           module_init_file        : string := "");


  port(
           Data        : in  std_logic_vector (module_widthw-1 downto 0);
           WrAddress   : in  std_logic_vector (module_widthadw-1 downto 0);
           RdAddress   : in  std_logic_vector (module_widthadr-1 downto 0);
           WrClock     : in std_logic;
           WrClockEn   : in std_logic;
           RdClock     : in std_logic;
           RdClockEn   : in std_logic;
           WE          : in std_logic;
           Reset       : in std_logic;
           Q           : out std_logic_vector (module_widthr-1 downto 0));

end ram_dp;

architecture fun_simulation of ram_dp is

component SC_PDPRAM_16K_L

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        WADDR_WIDTH    : integer := 13;
        WDATA_WIDTH    : integer := 2;
        RADDR_WIDTH    : integer := 13;
        RDATA_WIDTH    : integer := 2;
        ARRAY_SIZE     : integer := 511; 
        MEM_INIT_FLAG  : integer := 0;  
	MEM_INIT_FILE  : string  := "mem_init_file"

        );

  port (
        WCEN : in  STD_LOGIC ;
        WCLK : in  STD_LOGIC ;
        WE   : in  STD_LOGIC ;
        WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
        RCLK : in  STD_LOGIC;
        RCEN : in  STD_LOGIC;
        RST  : in  STD_LOGIC ;

        WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
        RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);  
        RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
       ); 

end component;

component SC_PDPRAMA_16K_L

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        WADDR_WIDTH    : integer := 13;
        WDATA_WIDTH    : integer := 2;
        RADDR_WIDTH    : integer := 13;
        RDATA_WIDTH    : integer := 2;
        ARRAY_SIZE     : integer := 16384;
        MEM_INIT_FLAG  : integer := 1;  
	MEM_INIT_FILE  : string  := "mem_init_file"

        );

  port (
        WCEN : in  STD_LOGIC ;
        WCLK : in  STD_LOGIC ;
        WE   : in  STD_LOGIC ;
        WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
        RST  : in  STD_LOGIC ;

        WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
        RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);  
        RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
       ); 

end component ;


     signal cs        : std_logic_vector ( 1 downto 0);
     signal Q_K       : std_logic_vector (module_widthr-1 downto 0);
     signal Q_KA      : std_logic_vector (module_widthr-1 downto 0);
     signal Q_K_reg   : std_logic_vector (module_widthr-1 downto 0);
     signal Q_KA_reg   : std_logic_vector (module_widthr-1 downto 0);
     CONSTANT  module_init_flag       :  integer := init_flag(module_init_file);

  begin

     cs <= "11";

      OutRegister : process(RdClock, Reset)
       begin
           if (Reset = '1') then 
                Q_K_reg <= (others => '0');
                Q_KA_reg <= (others => '0');
           elsif (RdClock'EVENT and RdClock = '1') then
              if (RdClockEn = '1') then
                Q_K_reg <= Q_K;
                Q_KA_reg <= Q_KA;
              elsif (RdClockEn /= '0') then
                Q_K_reg <= (others => 'X');
                Q_KA_reg <= (others => 'X');
              end if;
           end if;
       end process;

      SelectOut  : process (Q_K , Q_KA , Q_K_reg, Q_KA_reg)
        begin
              if(module_outdata = "UNREGISTERED" and module_addressr_control = "UNREGISTERED") then
                     Q <= Q_KA;
              elsif(module_outdata = "UNREGISTERED" and module_addressr_control = "REGISTERED") then 
                     Q <= Q_K;
              elsif(module_outdata = "REGISTERED" and module_addressr_control = "UNREGISTERED")  then
                     Q <= Q_KA_reg;
              elsif(module_outdata = "REGISTERED" and module_addressr_control = "REGISTERED") then
                     Q <= Q_K_reg;
              end if;
        end process;


   PDPRAM_inst : SC_PDPRAM_16K_L

  generic map(

        DEVICE_FAMILY  => open,
        WADDR_WIDTH    => module_widthadw,
        WDATA_WIDTH    => module_widthw,
        RADDR_WIDTH    => module_widthadr,
        RDATA_WIDTH    => module_widthr,
        MEM_INIT_FLAG  => module_init_flag,  
        ARRAY_SIZE     => module_numwordsw*module_widthw,
	MEM_INIT_FILE  => module_init_file)

  port map(
        WCEN =>  WrClockEn,
        WCLK =>  WrClock,
        WE   =>  WE,
        WCS  =>  cs,
        RCLK =>  RdClock,
        RCEN =>  RdClockEn,
        RST  =>  Reset,

        WD   =>  Data,
        WAD  =>  WrAddress,
        RAD  =>  RdAddress,
        RD   => Q_K 
       ); 

   PDPRAM_instA : SC_PDPRAMA_16K_L

  generic map(

        DEVICE_FAMILY  => open,
        WADDR_WIDTH    => module_widthadw,
        WDATA_WIDTH    => module_widthw,
        RADDR_WIDTH    => module_widthadr,
        RDATA_WIDTH    => module_widthr,
        MEM_INIT_FLAG  => module_init_flag,  
        ARRAY_SIZE     => module_numwordsw*module_widthw,
	MEM_INIT_FILE  => module_init_file)

  port map(
        WCEN =>  WrClockEn,
        WCLK =>  WrClock,
        WE   =>  WE,
        WCS  =>  cs,
        RST  =>  Reset,

        WD   =>  Data,
        WAD  =>  WrAddress,
        RAD  =>  RdAddress,
        RD   => Q_KA 
       ); 
end;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

entity ram_dp_true is 
generic (     lpm_type         : string := "Lattice_MEM";
              module_type      : string := "RAM_DP_TRUE";
              module_widtha    : positive;
              module_widthada  : positive;
              module_numwordsa : positive;
              module_widthb    : positive;
              module_widthadb  : positive;
              module_numwordsb : positive;
              module_indata    : string :="REGISTERED";
              module_outdata   : string :="UNREGISTERED";
              module_addressa_control   : string :="REGISTERED";
              module_addressb_control   : string :="REGISTERED";
              module_init_file        : string := "";
              module_hint      : string :="UNUSED");
      port (  
              DataInA       : in std_logic_vector(module_widtha-1 downto 0);
              AddressA      : in std_logic_vector(module_widthada-1 downto 0);
              DataInB       : in std_logic_vector(module_widthb-1 downto 0);
              AddressB      : in std_logic_vector(module_widthadb-1 downto 0);
              ClockA        : in std_logic := '0';
              ClockEnA      : in std_logic := '0';
              ClockB        : in std_logic := '0';
              ClockEnB      : in std_logic := '0';
              WrA           : in std_logic;
              WrB           : in std_logic;
              ResetA        : in std_logic;
              ResetB        : in std_logic;
              QA            : out std_logic_vector(module_widtha-1 downto 0);
              QB            : out std_logic_vector(module_widthb-1 downto 0));
end ram_dp_true;

architecture fun_simulation of ram_dp_true is

component SC_DPRAM_16K_L
  generic (
        DEVICE_FAMILY  : string  := "SuperCool";
        ADDR_WIDTH_A     : integer := 13;
        DATA_WIDTH_A     : integer := 2;
        ADDR_WIDTH_B     : integer := 14;
        DATA_WIDTH_B     : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        ARRAY_SIZE     : integer := 511; 
	MEM_INIT_FILE  : string  := "module_init_file"
        );
  port (
        CENA : in  STD_LOGIC ;
        CLKA : in  STD_LOGIC ;
        WRA  : in  STD_LOGIC ;
        CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
        RSTA : in  STD_LOGIC ;
        DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
        ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
        DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

        CENB : in  STD_LOGIC ;
        CLKB : in  STD_LOGIC ;
        WRB  : in  STD_LOGIC ;
        CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
        RSTB : in  STD_LOGIC ;
        DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
        ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
        DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
        ); 

end component;

      signal CS : std_logic_vector ( 1 downto 0);
      signal QA_int, QA_int_reg  : std_logic_vector(module_widtha-1 downto 0);
      signal QB_int, QB_int_reg  : std_logic_vector(module_widthb-1 downto 0);
      CONSTANT  module_init_flag       :  integer := init_flag(module_init_file);
begin

      CS <= "11";

      OutRegisterA : process(ClockA, ResetA)
       begin
           if(ResetA = '1') then QA_int_reg <= (others => '0');
           elsif (ClockA'EVENT and ClockA = '1') then
              if (ClockEnA = '1') then
               QA_int_reg <= QA_int;
              elsif (ClockEnA /= '0') then
               QA_int_reg <= (others => 'X');
              end if;
           end if;
       end process;

      OutRegisterB : process(ClockB, ResetB)
       begin
           if(ResetB = '1') then QB_int_reg <= (others => '0');
           elsif (ClockB'EVENT and ClockB = '1') then
              if (ClockEnB = '1') then
               QB_int_reg <= QB_int;
              elsif (ClockEnB /= '0') then
               QB_int_reg <= (others => 'X');
              end if;
           end if;
       end process;

      SelectA   : process (QA_int , QA_int_reg)
        begin
              if(module_outdata = "UNREGISTERED" and module_addressa_control = "REGISTERED") then
                     QA <= QA_int;
              elsif(module_outdata = "REGISTERED" and module_addressa_control = "REGISTERED") then
                     QA <= QA_int_reg;
              end if;
        end process;

      SelectB   : process (QB_int , QB_int_reg)
        begin
              if(module_outdata = "UNREGISTERED" and module_addressb_control = "REGISTERED") then
                     QB <= QB_int;
              elsif(module_outdata = "REGISTERED" and module_addressb_control = "REGISTERED") then
                     QB <= QB_int_reg;
              end if;
       end process;

RAM_DP_INST : SC_DPRAM_16K_L

    generic map(
         DEVICE_FAMILY  => open ,
         ADDR_WIDTH_A  => module_widthada,
         DATA_WIDTH_A  => module_widtha,
         ADDR_WIDTH_B  => module_widthadb,
         DATA_WIDTH_B  => module_widthb,
  	 MEM_INIT_FLAG => module_init_flag,  
         ARRAY_SIZE    => module_numwordsa*module_widtha,
	 MEM_INIT_FILE  => module_init_file
       )
    port map (
         CENA => ClockEnA,
         CLKA => ClockA,
         WRA  => WrA,
         CSA  => CS,
         RSTA => ResetA,
         DIA  => DataInA,
         ADA  => AddressA,
         DOA  => QA_int,

         CENB => ClockEnB,
         CLKB => ClockB,
         WRB  => WrB,
         CSB  => CS,
         RSTB => ResetB,
         DIB  => DataInB,
         ADB  => AddressB,
         DOB  => QB_int
      );
end;



library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lc5kmx;
use lc5kmx.components.all;

entity ram_dq  is
  generic( lpm_type               : string  := "Lattice_MEM";
	   module_type            : string  := "RAM_DQ";
	   module_width           : integer := 1;
	   module_numwords        : integer := 1;
	   module_widthad         : integer := 1;
  	   module_indata          : string  := "REGISTERED";
	   module_outdata         : string  := "UNREGISTERED";
	   module_address_control : string  := "REGISTERED";
           module_init_file       : string := "";
	   module_hint            : string  := "UNUSED");

  port(

           Data                : in  std_logic_vector (module_width-1 downto 0);
           Address             : in  std_logic_vector (module_widthad-1 downto 0);
           Clock               : in  std_logic;
           ClockEn             : in  std_logic;
           WE                  : in  std_logic;
           Reset               : in  std_logic;
           Q                   : out std_logic_vector (module_width-1 downto 0));
  end ram_dq;


architecture fun_simulation of ram_dq is


  component SC_SPRAM_16K_L

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        MEM_INIT_FLAG  : integer := 1; 
        ARRAY_SIZE     : integer := 511; 
	MEM_INIT_FILE  : string  := "qq.dat"

	);

  port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

end component;

component SC_SPRAMA_16K_L

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        ARRAY_SIZE     : integer := 16384;
        MEM_INIT_FLAG  : integer := 1;  
	MEM_INIT_FILE  : string  := "mem_init_file"

	);

  port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

end component ;

    signal cs   : std_logic_vector (1 downto 0);
    signal Q_K       : std_logic_vector (module_width-1 downto 0);
    signal Q_KA      : std_logic_vector (module_width-1 downto 0);
    signal Q_K_reg   : std_logic_vector (module_width-1 downto 0);
    signal Q_KA_reg   : std_logic_vector (module_width-1 downto 0);
    CONSTANT  module_init_flag       :  integer := init_flag(module_init_file);

  begin

      cs <= "11";

      OutRegister : process(Clock, Reset)
       begin
           if (Reset = '1') then 
               Q_K_reg <= (others => '0');
               Q_KA_reg <= (others => '0');
           elsif (Clock'EVENT and Clock = '1') then
              if (ClockEn = '1') then
               Q_K_reg <= Q_K;
               Q_KA_reg <= Q_KA;
              elsif (ClockEn /= '0') then
               Q_K_reg <= (others => 'X');
               Q_KA_reg <= (others => 'X');
              end if;
           end if;
       end process;

      SelectOut  : process (Q_K , Q_KA , Q_K_reg, Q_KA_reg)
        begin
              if(module_outdata = "UNREGISTERED" and module_address_control = "UNREGISTERED") then
                     Q <= Q_KA;
              elsif(module_outdata = "UNREGISTERED" and module_address_control = "REGISTERED") then
                     Q <= Q_K;
              elsif(module_outdata = "REGISTERED" and module_address_control = "UNREGISTERED") then
                     Q <= Q_KA_reg;
              elsif(module_outdata = "REGISTERED" and module_address_control = "REGISTERED") then
                     Q <= Q_K_reg;
              end if;
        end process;

  SPRAM_inst : SC_SPRAM_16K_L

  generic map (

        DEVICE_FAMILY  => open,
        ADDR_WIDTH     => module_widthad,
        DATA_WIDTH     => module_width,
        MEM_INIT_FLAG  => module_init_flag,
        ARRAY_SIZE     => module_numwords * module_width,
	MEM_INIT_FILE  => module_init_file)

  port map (
        CEN  => ClockEn, 
        CLK  => Clock, 
         WR  => WE, 
         CS  => cs,
        RST  => Reset,
         DI  => Data,
         AD  => Address,
         DO  => Q_K
       ); 

  SPRAMA_inst : SC_SPRAMA_16K_L

  generic map (

        DEVICE_FAMILY  => open,
        ADDR_WIDTH     => module_widthad,
        DATA_WIDTH     => module_width,
        MEM_INIT_FLAG  => module_init_flag,
        ARRAY_SIZE     => module_numwords * module_width,
	MEM_INIT_FILE  => module_init_file)

  port map (
        CEN  => ClockEn, 
        CLK  => Clock, 
         WR  => WE, 
         CS  => cs,
        RST  => Reset,
         DI  => Data,
         AD  => Address,
         DO  => Q_KA
       ); 
end;



library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

entity rom is
  generic ( lpm_type                  : string  := "Lattice_MEM";
	    module_type               : string  := "ROM";
	    module_width              : integer := 1;
	    module_numwords           : integer := 1;
	    module_widthad            : integer := 1;
	    module_outdata            : string  := "REGISTERED";
	    module_address_control    : string  := "UNREGISTERED";
            module_init_file        : string := "init_file";
	    module_hint               : string  := "UNUSED");
  port (
            Address       : in  std_logic_vector (module_widthad-1 downto 0);
            OutClock      : in  std_logic;
            OutClockEn    : in  std_logic;
            Reset         : in  std_logic;
            Q             : out std_logic_vector (module_width-1 downto 0));
end rom;

architecture fun_simulation of rom is

  component  SC_SPRAM_16K_L

    generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        ARRAY_SIZE     : integer := 511; 
        MEM_INIT_FLAG  : integer := 1;  
	MEM_INIT_FILE  : string  := "qq.dat"

	);

    port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

  end component;

component SC_SPRAMA_16K_L

  generic (

        DEVICE_FAMILY  : string  := "SuperCool";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        ARRAY_SIZE     : integer := 16384;
        MEM_INIT_FLAG  : integer := 1;  
	MEM_INIT_FILE  : string  := "mem_init_file"

	);

  port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

end component ;

        signal cs : std_logic_vector ( 1 downto 0);
        signal DI_sig : std_logic_vector (module_width-1 downto 0);
        signal WE_sig : std_logic;

        signal Q_K       : std_logic_vector (module_width-1 downto 0);
        signal Q_KA      : std_logic_vector (module_width-1 downto 0);
        signal Q_K_reg   : std_logic_vector (module_width-1 downto 0);
        signal Q_KA_reg   : std_logic_vector (module_width-1 downto 0);

  begin

        cs <= "11";
        WE_sig <= '0';

      OutRegister : process(OutClock, Reset)
       begin
           if (Reset = '1') then 
               Q_K_reg <= (others => '0');
               Q_KA_reg <= (others => '0');
           elsif (OutClock'EVENT and OutClock = '1') then
              if(OutClockEn = '1') then
               Q_K_reg <= Q_K;
               Q_KA_reg <= Q_KA;
              elsif(OutClockEn /= '0') then
               Q_K_reg <= (others => 'X' );
               Q_KA_reg <= (others => 'X' );
              end if;
           end if;
       end process;

      SelectOut  : process (Q_K, Q_KA, Q_K_reg, Q_KA_reg)
        begin
              if(module_outdata = "UNREGISTERED" and module_address_control = "UNREGISTERED") then
                     Q <= Q_KA;
              elsif(module_outdata = "UNREGISTERED" and module_address_control = "REGISTERED") then
                     Q <= Q_K;
              elsif(module_outdata = "REGISTERED" and module_address_control = "UNREGISTERED") then
                     Q <= Q_KA_reg;
              elsif(module_outdata = "REGISTERED" and module_address_control = "REGISTERED") then
                     Q <= Q_K_reg;
              end if;
        end process;

    SPRAM_inst :  SC_SPRAM_16K_L

      generic map(

           DEVICE_FAMILY  =>  open,
           ADDR_WIDTH     =>  module_widthad,
           DATA_WIDTH     =>  module_width, 
           MEM_INIT_FLAG  =>  1,
           ARRAY_SIZE     =>  module_numwords * module_width,
	   MEM_INIT_FILE  =>  module_init_file)

      port map(
           CEN    =>  OutClockEn,
           CLK    =>  OutClock,
           WR     =>  WE_sig,
           CS     =>  cs,
           RST    =>  Reset,
           DI     =>  DI_sig,
           AD     =>  Address,
           DO     =>  Q_K
       ); 

  SPRAMA_inst : SC_SPRAMA_16K_L

      generic map(

           DEVICE_FAMILY  =>  open,
           ADDR_WIDTH     =>  module_widthad,
           DATA_WIDTH     =>  module_width, 
           MEM_INIT_FLAG  =>  1,
           ARRAY_SIZE     =>  module_numwords * module_width,
	   MEM_INIT_FILE  =>  module_init_file)

      port map(
           CEN    =>  OutClockEn,
           CLK    =>  OutClock,
           WR     =>  WE_sig,
           CS     =>  cs,
           RST    =>  Reset,
           DI     =>  DI_sig,
           AD     =>  Address,
           DO     =>  Q_KA
       ); 
end;





